base.hh

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/*
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 * Copyright (c) 2011 Regents of the University of California
 * All rights reserved.
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#ifndef __CPU_BASE_HH__
#define __CPU_BASE_HH__
 
#include <memory>
#include <vector>
 
#include "arch/generic/interrupts.hh"
#include "base/statistics.hh"
#include "debug/Mwait.hh"
#include "mem/htm.hh"
#include "mem/port_proxy.hh"
#include "sim/clocked_object.hh"
#include "sim/eventq.hh"
#include "sim/full_system.hh"
#include "sim/insttracer.hh"
#include "sim/probe/pmu.hh"
#include "sim/probe/probe.hh"
#include "sim/signal.hh"
#include "sim/system.hh"
 
namespace gem5
{
 
class BaseCPU;
struct BaseCPUParams;
class CheckerCPU;
class ThreadContext;
 
struct AddressMonitor
{
    AddressMonitor();
    bool doMonitor(PacketPtr pkt);
 
    bool armed;
    Addr vAddr;
    Addr pAddr;
    uint64_t val;
    bool waiting;   // 0=normal, 1=mwaiting
    bool gotWakeup;
};
 
class CPUProgressEvent : public Event
{
  protected:
    Tick _interval;
    Counter lastNumInst;
    BaseCPU *cpu;
    bool _repeatEvent;
 
  public:
    CPUProgressEvent(BaseCPU *_cpu, Tick ival = 0);
 
    void process();
 
    void interval(Tick ival) { _interval = ival; }
    Tick interval() { return _interval; }
 
    void repeatEvent(bool repeat) { _repeatEvent = repeat; }
 
    virtual const char *description() const;
};
 
class BaseCPU : public ClockedObject
{
  protected:
 
    Tick instCnt;
 
    // every cpu has an id, put it in the base cpu
    // Set at initialization, only time a cpuId might change is during a
    // takeover (which should be done from within the BaseCPU anyway,
    // therefore no setCpuId() method is provided
    int _cpuId;
 
    const uint32_t _socketId;
 
    RequestorID _instRequestorId;
 
    RequestorID _dataRequestorId;
 
    uint32_t _taskId;
 
    uint32_t _pid;
 
    bool _switchedOut;
 
    const unsigned int _cacheLineSize;
 
    struct GlobalStats : public statistics::Group
    {
        GlobalStats(statistics::Group *parent);
 
        statistics::Value simInsts;
        statistics::Value simOps;
 
        statistics::Formula hostInstRate;
        statistics::Formula hostOpRate;
    };
 
    static std::unique_ptr<GlobalStats> globalStats;
 
    SignalSinkPort<bool> modelResetPort;
 
  public:
 
    virtual Port &getDataPort() = 0;
 
    virtual Port &getInstPort() = 0;
 
    int cpuId() const { return _cpuId; }
 
    uint32_t socketId() const { return _socketId; }
 
    RequestorID dataRequestorId() const { return _dataRequestorId; }
    RequestorID instRequestorId() const { return _instRequestorId; }
 
    Port &getPort(const std::string &if_name,
                  PortID idx=InvalidPortID) override;
 
    uint32_t taskId() const { return _taskId; }
    void taskId(uint32_t id) { _taskId = id; }
 
    uint32_t getPid() const { return _pid; }
    void setPid(uint32_t pid) { _pid = pid; }
 
    inline void workItemBegin() { baseStats.numWorkItemsStarted++; }
    inline void workItemEnd() { baseStats.numWorkItemsCompleted++; }
    // @todo remove me after debugging with legion done
    Tick instCount() { return instCnt; }
 
  protected:
    std::vector<BaseInterrupts*> interrupts;
 
  public:
    BaseInterrupts *
    getInterruptController(ThreadID tid)
    {
        if (interrupts.empty())
            return NULL;
 
        assert(interrupts.size() > tid);
        return interrupts[tid];
    }
 
    virtual void wakeup(ThreadID tid) = 0;
 
    void postInterrupt(ThreadID tid, int int_num, int index);
 
    void
    clearInterrupt(ThreadID tid, int int_num, int index)
    {
        interrupts[tid]->clear(int_num, index);
    }
 
    void
    clearInterrupts(ThreadID tid)
    {
        interrupts[tid]->clearAll();
    }
 
    bool
    checkInterrupts(ThreadID tid) const
    {
        return FullSystem && interrupts[tid]->checkInterrupts();
    }
 
  protected:
    std::vector<ThreadContext *> threadContexts;
 
    trace::InstTracer * tracer;
 
  public:
 
 
    static const uint32_t invldPid = std::numeric_limits<uint32_t>::max();
 
    trace::InstTracer * getTracer() { return tracer; }
 
    virtual void activateContext(ThreadID thread_num);
 
    virtual void suspendContext(ThreadID thread_num);
 
    virtual void haltContext(ThreadID thread_num);
 
    int findContext(ThreadContext *tc);
 
    virtual ThreadContext *getContext(int tn) { return threadContexts[tn]; }
 
    unsigned
    numContexts()
    {
        return static_cast<unsigned>(threadContexts.size());
    }
 
    ThreadID
    contextToThread(ContextID cid)
    {
        return static_cast<ThreadID>(cid - threadContexts[0]->contextId());
    }
 
  public:
    PARAMS(BaseCPU);
    BaseCPU(const Params &params, bool is_checker = false);
    virtual ~BaseCPU();
 
    void init() override;
    void startup() override;
    void regStats() override;
 
    void regProbePoints() override;
 
    void registerThreadContexts();
 
    // Functions to deschedule and reschedule the events to enter the
    // power gating sleep before and after checkpoiting respectively.
    void deschedulePowerGatingEvent();
    void schedulePowerGatingEvent();
 
    virtual void switchOut();
 
    virtual void takeOverFrom(BaseCPU *cpu);
 
    virtual void setReset(bool state);
 
    void flushTLBs();
 
    bool switchedOut() const { return _switchedOut; }
 
    virtual void verifyMemoryMode() const { };
 
    ThreadID numThreads;
 
    System *system;
 
    inline unsigned int cacheLineSize() const { return _cacheLineSize; }
 
    void serialize(CheckpointOut &cp) const override;
 
    void unserialize(CheckpointIn &cp) override;
 
    virtual void serializeThread(CheckpointOut &cp, ThreadID tid) const {};
 
    virtual void unserializeThread(CheckpointIn &cp, ThreadID tid) {};
 
    virtual Counter totalInsts() const = 0;
 
    virtual Counter totalOps() const = 0;
 
    void scheduleInstStop(ThreadID tid, Counter insts, std::string cause);
 
    void scheduleSimpointsInstStop(std::vector<Counter> inst_starts);
 
    void scheduleInstStopAnyThread(Counter max_insts);
 
    uint64_t getCurrentInstCount(ThreadID tid);
 
  public:
    virtual void probeInstCommit(const StaticInstPtr &inst, Addr pc);
 
   protected:
    probing::PMUUPtr pmuProbePoint(const char *name);
 
    probing::PMUUPtr ppRetiredInsts;
    probing::PMUUPtr ppRetiredInstsPC;
 
    probing::PMUUPtr ppRetiredLoads;
    probing::PMUUPtr ppRetiredStores;
 
    probing::PMUUPtr ppRetiredBranches;
 
    probing::PMUUPtr ppAllCycles;
 
    probing::PMUUPtr ppActiveCycles;
 
    ProbePointArg<bool> *ppSleeping;
    enum CPUState
    {
        CPU_STATE_ON,
        CPU_STATE_SLEEP,
        CPU_STATE_WAKEUP
    };
 
    Cycles previousCycle;
    CPUState previousState;
 
    inline void
    updateCycleCounters(CPUState state)
    {
        uint32_t delta = curCycle() - previousCycle;
 
        if (previousState == CPU_STATE_ON) {
            ppActiveCycles->notify(delta);
        }
 
        switch (state) {
          case CPU_STATE_WAKEUP:
            ppSleeping->notify(false);
            break;
          case CPU_STATE_SLEEP:
            ppSleeping->notify(true);
            break;
          default:
            break;
        }
 
        ppAllCycles->notify(delta);
 
        previousCycle = curCycle();
        previousState = state;
    }
 
    // Function tracing
  private:
    bool functionTracingEnabled;
    std::ostream *functionTraceStream;
    Addr currentFunctionStart;
    Addr currentFunctionEnd;
    Tick functionEntryTick;
    void enableFunctionTrace();
    void traceFunctionsInternal(Addr pc);
 
  private:
    static std::vector<BaseCPU *> cpuList;   
 
  public:
    void
    traceFunctions(Addr pc)
    {
        if (functionTracingEnabled)
            traceFunctionsInternal(pc);
    }
 
    static int numSimulatedCPUs() { return cpuList.size(); }
    static Counter
    numSimulatedInsts()
    {
        Counter total = 0;
 
        int size = cpuList.size();
        for (int i = 0; i < size; ++i)
            total += cpuList[i]->totalInsts();
 
        return total;
    }
 
    static Counter
    numSimulatedOps()
    {
        Counter total = 0;
 
        int size = cpuList.size();
        for (int i = 0; i < size; ++i)
            total += cpuList[i]->totalOps();
 
        return total;
    }
 
  public:
    struct BaseCPUStats : public statistics::Group
    {
        BaseCPUStats(statistics::Group *parent);
        // Number of CPU insts and ops committed at CPU core level
        statistics::Scalar numInsts;
        statistics::Scalar numOps;
        // Number of CPU cycles simulated
        statistics::Scalar numCycles;
        /* CPI/IPC for total cycle counts and macro insts */
        statistics::Formula cpi;
        statistics::Formula ipc;
        statistics::Scalar numWorkItemsStarted;
        statistics::Scalar numWorkItemsCompleted;
    } baseStats;
 
  private:
    std::vector<AddressMonitor> addressMonitor;
 
  public:
    void armMonitor(ThreadID tid, Addr address);
    bool mwait(ThreadID tid, PacketPtr pkt);
    void mwaitAtomic(ThreadID tid, ThreadContext *tc, BaseMMU *mmu);
    AddressMonitor *
    getCpuAddrMonitor(ThreadID tid)
    {
        assert(tid < numThreads);
        return &addressMonitor[tid];
    }
 
    Cycles syscallRetryLatency;
 
    virtual void
    htmSendAbortSignal(ThreadID tid, uint64_t htm_uid,
                       HtmFailureFaultCause cause)
    {
        panic("htmSendAbortSignal not implemented");
    }
 
  // Enables CPU to enter power gating on a configurable cycle count
  protected:
    void enterPwrGating();
 
    const Cycles pwrGatingLatency;
    const bool powerGatingOnIdle;
    EventFunctionWrapper enterPwrGatingEvent;
 
 
  public:
    struct FetchCPUStats : public statistics::Group
    {
        FetchCPUStats(statistics::Group *parent, int thread_id);
 
        /* Total number of instructions fetched */
        statistics::Scalar numInsts;
 
        /* Total number of operations fetched */
        statistics::Scalar numOps;
 
        /* Number of instruction fetched per cycle. */
        statistics::Formula fetchRate;
 
        /* Total number of branches fetched */
        statistics::Scalar numBranches;
 
        /* Number of branch fetches per cycle. */
        statistics::Formula branchRate;
 
        /* Number of cycles stalled due to an icache miss */
        statistics::Scalar icacheStallCycles;
 
        /* Number of times fetch was asked to suspend by Execute */
        statistics::Scalar numFetchSuspends;
 
    };
 
    struct ExecuteCPUStats: public statistics::Group
    {
        ExecuteCPUStats(statistics::Group *parent, int thread_id);
 
        /* Stat for total number of executed instructions */
        statistics::Scalar numInsts;
        /* Number of executed nops */
        statistics::Scalar numNop;
        /* Number of executed branches */
        statistics::Scalar numBranches;
        /* Stat for total number of executed load instructions */
        statistics::Scalar numLoadInsts;
        /* Number of executed store instructions */
        statistics::Formula numStoreInsts;
        /* Number of instructions executed per cycle */
        statistics::Formula instRate;
 
        /* Number of cycles stalled for D-cache responses */
        statistics::Scalar dcacheStallCycles;
 
        /* Number of condition code register file accesses */
        statistics::Scalar numCCRegReads;
        statistics::Scalar numCCRegWrites;
 
        /* number of float alu accesses */
        statistics::Scalar numFpAluAccesses;
 
        /* Number of float register file accesses */
        statistics::Scalar numFpRegReads;
        statistics::Scalar numFpRegWrites;
 
        /* Number of integer alu accesses */
        statistics::Scalar numIntAluAccesses;
 
        /* Number of integer register file accesses */
        statistics::Scalar numIntRegReads;
        statistics::Scalar numIntRegWrites;
 
        /* number of simulated memory references */
        statistics::Scalar numMemRefs;
 
        /* Number of misc register file accesses */
        statistics::Scalar numMiscRegReads;
        statistics::Scalar numMiscRegWrites;
 
        /* Number of vector alu accesses */
        statistics::Scalar numVecAluAccesses;
 
        /* Number of predicate register file accesses */
        mutable statistics::Scalar numVecPredRegReads;
        statistics::Scalar numVecPredRegWrites;
 
        /* Number of vector register file accesses */
        mutable statistics::Scalar numVecRegReads;
        statistics::Scalar numVecRegWrites;
 
        /* Number of ops discarded before committing */
        statistics::Scalar numDiscardedOps;
    };
 
    struct CommitCPUStats: public statistics::Group
    {
        CommitCPUStats(statistics::Group *parent, int thread_id);
 
        /* Number of simulated instructions committed */
        statistics::Scalar numInsts;
        statistics::Scalar numOps;
 
        /* Number of instructions committed that are not NOP or prefetches */
        statistics::Scalar numInstsNotNOP;
        statistics::Scalar numOpsNotNOP;
 
        /* CPI/IPC for total cycle counts and macro insts */
        statistics::Formula cpi;
        statistics::Formula ipc;
 
        /* Number of committed memory references. */
        statistics::Scalar numMemRefs;
 
        /* Number of float instructions */
        statistics::Scalar numFpInsts;
 
        /* Number of int instructions */
        statistics::Scalar numIntInsts;
 
        /* number of load instructions */
        statistics::Scalar numLoadInsts;
 
        /* Number of store instructions */
        statistics::Scalar numStoreInsts;
 
        /* Number of vector instructions */
        statistics::Scalar numVecInsts;
 
        /* Number of instructions committed by type (OpClass) */
        statistics::Vector committedInstType;
 
        /* number of control instructions committed by control inst type */
        statistics::Vector committedControl;
        void updateComCtrlStats(const StaticInstPtr staticInst);
 
    };
 
    std::vector<std::unique_ptr<FetchCPUStats>> fetchStats;
    std::vector<std::unique_ptr<ExecuteCPUStats>> executeStats;
    std::vector<std::unique_ptr<CommitCPUStats>> commitStats;
};
 
} // namespace gem5
 
#endif // __CPU_BASE_HH__