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gem5::ArmISA Namespace Reference

Namespaces

 cc_reg
 
 int_reg
 
 vector_element_traits
 

Classes

class  AbortFault
 
class  ArmFault
 
class  ArmFaultVals
 
class  ArmSev
 
class  ArmStaticInst
 
class  BaseISADevice
 Base class for devices that use the MiscReg interfaces. More...
 
class  BigFpMemImmOp
 
class  BigFpMemLitOp
 
class  BigFpMemPostOp
 
class  BigFpMemPreOp
 
class  BigFpMemRegOp
 
class  BranchEret64
 
class  BranchEretA64
 
class  BranchImm
 
class  BranchImm64
 
class  BranchImmCond
 
class  BranchImmCond64
 
class  BranchImmImmReg64
 
class  BranchImmReg
 
class  BranchImmReg64
 
class  BranchReg
 
class  BranchReg64
 
class  BranchRegCond
 
class  BranchRegReg
 
class  BranchRegReg64
 
class  BranchRet64
 
class  BranchRetA64
 
class  BrkPoint
 
class  CCRegClassOps
 
class  Crypto
 
class  DataAbort
 
class  DataImmOp
 
class  DataRegOp
 
class  DataRegRegOp
 
class  DataX1Reg2ImmOp
 
class  DataX1RegImmOp
 
class  DataX1RegOp
 
class  DataX2RegImmOp
 
class  DataX2RegOp
 
class  DataX3RegOp
 
class  DataXCondCompImmOp
 
class  DataXCondCompRegOp
 
class  DataXCondSelOp
 
class  DataXERegOp
 
class  DataXImmOnlyOp
 
class  DataXImmOp
 
class  DataXSRegOp
 
class  Decoder
 
class  DTLBIALL
 Data TLB Invalidate All. More...
 
class  DTLBIASID
 Data TLB Invalidate by ASID match. More...
 
class  DTLBIMVA
 Data TLB Invalidate by VA. More...
 
class  DummyISADevice
 Dummy device that prints a warning when it is accessed. More...
 
class  DumpStats
 
class  DumpStats64
 
class  EmuFreebsd
 
class  EmuLinux
 
class  FastInterrupt
 
class  FpCondCompRegOp
 
class  FpCondSelOp
 
class  FpOp
 
class  FpRegImmOp
 
class  FpRegRegImmOp
 
class  FpRegRegOp
 
class  FpRegRegRegCondOp
 
class  FpRegRegRegImmOp
 
class  FpRegRegRegOp
 
class  FpRegRegRegRegOp
 
class  FsFreebsd
 
class  FsLinux
 
class  FsWorkload
 
class  HardwareBreakpoint
 
class  HTMCheckpoint
 
class  HypervisorCall
 
class  HypervisorTrap
 
class  IllegalInstSetStateFault
 Illegal Instruction Set State fault (AArch64 only) More...
 
class  Interrupt
 
class  Interrupts
 
class  IntRegClassOps
 
class  ISA
 
class  ITLBIALL
 Instruction TLB Invalidate All. More...
 
class  ITLBIASID
 Instruction TLB Invalidate by ASID match. More...
 
class  ITLBIMVA
 Instruction TLB Invalidate by VA. More...
 
class  MacroMemOp
 Base class for microcoded integer memory instructions. More...
 
class  MacroVFPMemOp
 Base class for microcoded floating point memory instructions. More...
 
class  Memory
 
class  Memory64
 
class  MemoryAtomicPair64
 
class  MemoryDImm
 
class  MemoryDImm64
 
class  MemoryDImmEx64
 
class  MemoryDReg
 
class  MemoryEx64
 
class  MemoryExDImm
 
class  MemoryExImm
 
class  MemoryImm
 
class  MemoryImm64
 
class  MemoryLiteral64
 
class  MemoryOffset
 
class  MemoryPostIndex
 
class  MemoryPostIndex64
 
class  MemoryPreIndex
 
class  MemoryPreIndex64
 
class  MemoryRaw64
 
class  MemoryReg
 
class  MemoryReg64
 
class  MicroIntImmOp
 Microops of the form IntRegA = IntRegB op Imm. More...
 
class  MicroIntImmXOp
 
class  MicroIntMov
 Microops of the form IntRegA = IntRegB. More...
 
class  MicroIntOp
 Microops of the form IntRegA = IntRegB op IntRegC. More...
 
class  MicroIntRegOp
 Microops of the form IntRegA = IntRegB op shifted IntRegC. More...
 
class  MicroIntRegXOp
 
class  MicroMemOp
 Memory microops which use IntReg + Imm addressing. More...
 
class  MicroMemPairOp
 
class  MicroNeonMemOp
 Microops for Neon loads/stores. More...
 
class  MicroNeonMixLaneOp
 
class  MicroNeonMixLaneOp64
 
class  MicroNeonMixOp
 Microops for Neon load/store (de)interleaving. More...
 
class  MicroNeonMixOp64
 Microops for AArch64 NEON load/store (de)interleaving. More...
 
class  MicroOp
 Base class for Memory microops. More...
 
class  MicroOpX
 
class  MicroSetPCCPSR
 Microops of the form PC = IntRegA CPSR = IntRegB. More...
 
class  MightBeMicro
 
class  MightBeMicro64
 
class  MiscRegClassOps
 
struct  MiscRegLUTEntry
 MiscReg metadata. More...
 
class  MiscRegLUTEntryInitializer
 Metadata table accessible via the value of the register. More...
 
struct  MiscRegNum32
 
struct  MiscRegNum64
 
class  MMU
 
class  Mult3
 Base class for multipy instructions using three registers. More...
 
class  Mult4
 Base class for multipy instructions using four registers. More...
 
struct  PageTableOps
 
class  PairMemOp
 Base class for pair load/store instructions. More...
 
class  PCAlignmentFault
 PC alignment fault (AArch64 only) More...
 
class  PMU
 Model of an ARM PMU version 3. More...
 
class  PredImmOp
 Base class for predicated immediate operations. More...
 
class  PredIntOp
 Base class for predicated integer operations. More...
 
class  PredMacroOp
 Base class for predicated macro-operations. More...
 
class  PredMicroop
 Base class for predicated micro-operations. More...
 
class  PredOp
 Base class for predicated integer operations. More...
 
class  PrefetchAbort
 
struct  PTE
 
struct  RegABI32
 
struct  RegABI64
 
class  RemoteGDB
 
class  Reset
 
class  RfeOp
 
class  SecureMonitorCall
 
class  SecureMonitorTrap
 
class  SelfDebug
 
class  SEWorkload
 
class  SkipFunc
 
class  SkipFuncLinux32
 
class  SkipFuncLinux64
 
class  SmeAddOp
 
class  SmeAddVlOp
 
class  SmeLd1xSt1xOp
 
class  SmeLdrStrOp
 
class  SmeMovExtractOp
 
class  SmeMovInsertOp
 
class  SmeOPOp
 
class  SmeRdsvlOp
 
class  SmeZeroOp
 
class  SoftwareBreakpoint
 Software Breakpoint (AArch64 only) More...
 
class  SoftwareStep
 
class  SoftwareStepFault
 
class  SPAlignmentFault
 Stack pointer alignment fault (AArch64 only) More...
 
class  SrsOp
 
class  StackTrace
 
class  Stage2LookUp
 
class  SupervisorCall
 
class  SupervisorTrap
 
class  SveAdrOp
 ADR. More...
 
class  SveBinConstrPredOp
 Binary, constructive, predicated SVE instruction. More...
 
class  SveBinDestrPredOp
 Binary, destructive, predicated (merging) SVE instruction. More...
 
class  SveBinIdxUnpredOp
 Binary, unpredicated SVE instruction. More...
 
class  SveBinImmIdxUnpredOp
 Binary with immediate index, destructive, unpredicated SVE instruction. More...
 
class  SveBinImmPredOp
 Binary with immediate, destructive, predicated (merging) SVE instruction. More...
 
class  SveBinImmUnpredConstrOp
 Binary with immediate, destructive, unpredicated SVE instruction. More...
 
class  SveBinImmUnpredDestrOp
 SVE vector - immediate binary operation. More...
 
class  SveBinUnpredOp
 Binary, unpredicated SVE instruction with indexed operand. More...
 
class  SveBinWideImmUnpredOp
 Binary with wide immediate, destructive, unpredicated SVE instruction. More...
 
class  SveClampOp
 
class  SveCmpImmOp
 SVE compare-with-immediate instructions, predicated (zeroing). More...
 
class  SveCmpOp
 SVE compare instructions, predicated (zeroing). More...
 
class  SveComplexIdxOp
 SVE Complex Instructions (indexed) More...
 
class  SveComplexOp
 SVE Complex Instructions (vectors) More...
 
class  SveCompTermOp
 Compare and terminate loop SVE instruction. More...
 
class  SveContigMemSI
 
class  SveContigMemSS
 
class  SveDotProdIdxOp
 SVE dot product instruction (indexed) More...
 
class  SveDotProdOp
 SVE dot product instruction (vectors) More...
 
class  SveElemCountOp
 Element count SVE instruction. More...
 
class  SveIndexedMemSV
 
class  SveIndexedMemVI
 
class  SveIndexIIOp
 Index generation instruction, immediate operands. More...
 
class  SveIndexIROp
 
class  SveIndexRIOp
 
class  SveIndexRROp
 
class  SveIntCmpImmOp
 Integer compare with immediate SVE instruction. More...
 
class  SveIntCmpOp
 Integer compare SVE instruction. More...
 
class  SveLdStructSI
 
class  SveLdStructSS
 
class  SveMemPredFillSpill
 
class  SveMemVecFillSpill
 
class  SveOrdReducOp
 SVE ordered reductions. More...
 
class  SvePartBrkOp
 Partition break SVE instruction. More...
 
class  SvePartBrkPropOp
 Partition break with propagation SVE instruction. More...
 
class  SvePredBinPermOp
 Predicate binary permute instruction. More...
 
class  SvePredCountOp
 
class  SvePredCountPredOp
 
class  SvePredLogicalOp
 Predicate logical instruction. More...
 
class  SvePredTestOp
 SVE predicate test. More...
 
class  SvePredUnaryWImplicitDstOp
 SVE unary predicate instructions with implicit destination operand. More...
 
class  SvePredUnaryWImplicitSrcOp
 SVE unary predicate instructions with implicit source operand. More...
 
class  SvePredUnaryWImplicitSrcPredOp
 SVE unary predicate instructions, predicated, with implicit source operand. More...
 
class  SvePselOp
 Psel predicate selection SVE instruction. More...
 
class  SvePtrueOp
 PTRUE, PTRUES. More...
 
class  SveReducOp
 SVE reductions. More...
 
class  SveSelectOp
 Scalar element select SVE instruction. More...
 
class  SveStStructSI
 
class  SveStStructSS
 
class  SveTblOp
 SVE table lookup/permute using vector of element indices (TBL) More...
 
class  SveTerImmUnpredOp
 Ternary with immediate, destructive, unpredicated SVE instruction. More...
 
class  SveTerPredOp
 Ternary, destructive, predicated (merging) SVE instruction. More...
 
class  SveTerUnpredOp
 Ternary, destructive, unpredicated SVE instruction. More...
 
class  SveUnaryPredOp
 Unary, constructive, predicated (merging) SVE instruction. More...
 
class  SveUnaryPredPredOp
 SVE unary operation on predicate (predicated) More...
 
class  SveUnarySca2VecUnpredOp
 Unary unpredicated scalar to vector instruction. More...
 
class  SveUnaryUnpredOp
 Unary, constructive, unpredicated SVE instruction. More...
 
class  SveUnaryWideImmPredOp
 Unary with wide immediate, constructive, predicated SVE instruction. More...
 
class  SveUnaryWideImmUnpredOp
 Unary with wide immediate, constructive, unpredicated SVE instruction. More...
 
class  SveUnpackOp
 SVE unpack and widen predicate. More...
 
class  SveWhileOp
 While predicate generation SVE instruction. More...
 
class  SveWImplicitSrcDstOp
 SVE unary predicate instructions with implicit destination operand. More...
 
class  SyscallTable32
 
class  SyscallTable64
 
class  SysDC64
 
class  SystemError
 System error (AArch64 only) More...
 
class  TableWalker
 
class  TLB
 
struct  TlbEntry
 
class  TLBIALL
 TLB Invalidate All. More...
 
class  TLBIALLEL
 Implementaton of AArch64 TLBI ALLE(1,2,3)(IS) instructions. More...
 
class  TLBIALLN
 TLB Invalidate All, Non-Secure. More...
 
class  TLBIASID
 TLB Invalidate by ASID match. More...
 
class  TLBIIPA
 TLB Invalidate by Intermediate Physical Address. More...
 
class  TLBIMVA
 TLB Invalidate by VA. More...
 
class  TLBIMVAA
 TLB Invalidate by VA, All ASID. More...
 
class  TLBIOp
 
class  TLBIVMALL
 Implementaton of AArch64 TLBI VMALLE1(IS)/VMALLS112E1(IS) instructions. More...
 
class  TlbTestInterface
 
class  UndefinedInstruction
 
struct  V7LPageTableOps
 
struct  V8PageTableOps16k
 
struct  V8PageTableOps4k
 
struct  V8PageTableOps64k
 
class  VfpMacroOp
 
class  VirtualDataAbort
 
class  VirtualFastInterrupt
 
class  VirtualInterrupt
 
class  VldMultOp
 Base classes for microcoded integer memory instructions. More...
 
class  VldMultOp64
 Base classes for microcoded AArch64 NEON memory instructions. More...
 
class  VldSingleOp
 
class  VldSingleOp64
 
struct  VReg
 128-bit NEON vector register. More...
 
class  VstMultOp
 Base class for microcoded integer memory instructions. More...
 
class  VstMultOp64
 
class  VstSingleOp
 
class  VstSingleOp64
 
class  Watchpoint
 
class  WatchPoint
 

Typedefs

typedef Addr FaultOffset
 
typedef uint64_t XReg
 
typedef int VfpSavedState
 
using MatRegContainer = gem5::MatStore< MaxSmeVecLenInBytes, MaxSmeVecLenInBytes >
 
template<typename ElemType >
using MatTile = gem5::Tile< ElemType, MatRegContainer >
 
template<typename ElemType >
using MatTileRow = gem5::HorizontalSlice< ElemType, MatRegContainer, true >
 
template<typename ElemType >
using MatTileCol = gem5::VerticalSlice< ElemType, MatRegContainer, true >
 
template<typename ElemType >
using MatRow = gem5::HorizontalSlice< ElemType, MatRegContainer, false >
 
template<typename ElemType >
using MatCol = gem5::VerticalSlice< ElemType, MatRegContainer, false >
 
using VecElem = uint32_t
 
using VecRegContainer = gem5::VecRegContainer< NumVecElemPerVecReg *sizeof(VecElem)>
 
using VecPredReg = gem5::VecPredRegT< VecElem, NumVecElemPerVecReg, false, false >
 
using ConstVecPredReg = gem5::VecPredRegT< VecElem, NumVecElemPerVecReg, false, true >
 
using VecPredRegContainer = VecPredReg::Container
 
typedef uint32_t MachInst
 
typedef uint16_t vmid_t
 
typedef int RegContextParam
 
typedef int RegContextVal
 

Enumerations

enum  FPRounding {
  FPRounding_TIEEVEN = 0, FPRounding_POSINF = 1, FPRounding_NEGINF = 2, FPRounding_ZERO = 3,
  FPRounding_TIEAWAY = 4, FPRounding_ODD = 5
}
 
enum  FpDataType { FpDataType::Fp16, FpDataType::Fp32, FpDataType::Fp64 }
 Floating point data types. More...
 
enum  SvePredType { SvePredType::NONE, SvePredType::MERGE, SvePredType::ZERO, SvePredType::SELECT }
 
enum  VfpMicroMode { VfpNotAMicroop, VfpMicroop, VfpFirstMicroop, VfpLastMicroop }
 
enum  FeExceptionBit {
  FeDivByZero = FE_DIVBYZERO, FeInexact = FE_INEXACT, FeInvalid = FE_INVALID, FeOverflow = FE_OVERFLOW,
  FeUnderflow = FE_UNDERFLOW, FeAllExceptions = FE_ALL_EXCEPT
}
 
enum  FeRoundingMode { FeRoundDown = FE_DOWNWARD, FeRoundNearest = FE_TONEAREST, FeRoundZero = FE_TOWARDZERO, FeRoundUpward = FE_UPWARD }
 
enum  VfpRoundingMode {
  VfpRoundNearest = 0, VfpRoundUpward = 1, VfpRoundDown = 2, VfpRoundZero = 3,
  VfpRoundAway = 4
}
 
enum  InterruptTypes {
  INT_RST, INT_ABT, INT_IRQ, INT_FIQ,
  INT_SEV, INT_VIRT_IRQ, INT_VIRT_FIQ, NumInterruptTypes
}
 
enum  GrainSize { Grain4KB = 12, Grain16KB = 14, Grain64KB = 16, ReservedGrain = 0 }
 
enum  ConditionCode {
  COND_EQ = 0, COND_NE, COND_CS, COND_CC,
  COND_MI, COND_PL, COND_VS, COND_VC,
  COND_HI, COND_LS, COND_GE, COND_LT,
  COND_GT, COND_LE, COND_AL, COND_UC
}
 
enum  MiscRegIndex {
  MISCREG_CPSR = 0, MISCREG_SPSR, MISCREG_SPSR_FIQ, MISCREG_SPSR_IRQ,
  MISCREG_SPSR_SVC, MISCREG_SPSR_MON, MISCREG_SPSR_ABT, MISCREG_SPSR_HYP,
  MISCREG_SPSR_UND, MISCREG_ELR_HYP, MISCREG_FPSID, MISCREG_FPSCR,
  MISCREG_MVFR1, MISCREG_MVFR0, MISCREG_FPEXC, MISCREG_CPSR_MODE,
  MISCREG_CPSR_Q, MISCREG_FPSCR_EXC, MISCREG_FPSCR_QC, MISCREG_LOCKADDR,
  MISCREG_LOCKFLAG, MISCREG_PRRR_MAIR0, MISCREG_PRRR_MAIR0_NS, MISCREG_PRRR_MAIR0_S,
  MISCREG_NMRR_MAIR1, MISCREG_NMRR_MAIR1_NS, MISCREG_NMRR_MAIR1_S, MISCREG_PMXEVTYPER_PMCCFILTR,
  MISCREG_SEV_MAILBOX, MISCREG_TLBINEEDSYNC, MISCREG_DBGDIDR, MISCREG_DBGDSCRint,
  MISCREG_DBGDCCINT, MISCREG_DBGDTRTXint, MISCREG_DBGDTRRXint, MISCREG_DBGWFAR,
  MISCREG_DBGVCR, MISCREG_DBGDTRRXext, MISCREG_DBGDSCRext, MISCREG_DBGDTRTXext,
  MISCREG_DBGOSECCR, MISCREG_DBGBVR0, MISCREG_DBGBVR1, MISCREG_DBGBVR2,
  MISCREG_DBGBVR3, MISCREG_DBGBVR4, MISCREG_DBGBVR5, MISCREG_DBGBVR6,
  MISCREG_DBGBVR7, MISCREG_DBGBVR8, MISCREG_DBGBVR9, MISCREG_DBGBVR10,
  MISCREG_DBGBVR11, MISCREG_DBGBVR12, MISCREG_DBGBVR13, MISCREG_DBGBVR14,
  MISCREG_DBGBVR15, MISCREG_DBGBCR0, MISCREG_DBGBCR1, MISCREG_DBGBCR2,
  MISCREG_DBGBCR3, MISCREG_DBGBCR4, MISCREG_DBGBCR5, MISCREG_DBGBCR6,
  MISCREG_DBGBCR7, MISCREG_DBGBCR8, MISCREG_DBGBCR9, MISCREG_DBGBCR10,
  MISCREG_DBGBCR11, MISCREG_DBGBCR12, MISCREG_DBGBCR13, MISCREG_DBGBCR14,
  MISCREG_DBGBCR15, MISCREG_DBGWVR0, MISCREG_DBGWVR1, MISCREG_DBGWVR2,
  MISCREG_DBGWVR3, MISCREG_DBGWVR4, MISCREG_DBGWVR5, MISCREG_DBGWVR6,
  MISCREG_DBGWVR7, MISCREG_DBGWVR8, MISCREG_DBGWVR9, MISCREG_DBGWVR10,
  MISCREG_DBGWVR11, MISCREG_DBGWVR12, MISCREG_DBGWVR13, MISCREG_DBGWVR14,
  MISCREG_DBGWVR15, MISCREG_DBGWCR0, MISCREG_DBGWCR1, MISCREG_DBGWCR2,
  MISCREG_DBGWCR3, MISCREG_DBGWCR4, MISCREG_DBGWCR5, MISCREG_DBGWCR6,
  MISCREG_DBGWCR7, MISCREG_DBGWCR8, MISCREG_DBGWCR9, MISCREG_DBGWCR10,
  MISCREG_DBGWCR11, MISCREG_DBGWCR12, MISCREG_DBGWCR13, MISCREG_DBGWCR14,
  MISCREG_DBGWCR15, MISCREG_DBGDRAR, MISCREG_DBGBXVR0, MISCREG_DBGBXVR1,
  MISCREG_DBGBXVR2, MISCREG_DBGBXVR3, MISCREG_DBGBXVR4, MISCREG_DBGBXVR5,
  MISCREG_DBGBXVR6, MISCREG_DBGBXVR7, MISCREG_DBGBXVR8, MISCREG_DBGBXVR9,
  MISCREG_DBGBXVR10, MISCREG_DBGBXVR11, MISCREG_DBGBXVR12, MISCREG_DBGBXVR13,
  MISCREG_DBGBXVR14, MISCREG_DBGBXVR15, MISCREG_DBGOSLAR, MISCREG_DBGOSLSR,
  MISCREG_DBGOSDLR, MISCREG_DBGPRCR, MISCREG_DBGDSAR, MISCREG_DBGCLAIMSET,
  MISCREG_DBGCLAIMCLR, MISCREG_DBGAUTHSTATUS, MISCREG_DBGDEVID2, MISCREG_DBGDEVID1,
  MISCREG_DBGDEVID0, MISCREG_TEECR, MISCREG_JIDR, MISCREG_TEEHBR,
  MISCREG_JOSCR, MISCREG_JMCR, MISCREG_MIDR, MISCREG_CTR,
  MISCREG_TCMTR, MISCREG_TLBTR, MISCREG_MPIDR, MISCREG_REVIDR,
  MISCREG_ID_PFR0, MISCREG_ID_PFR1, MISCREG_ID_DFR0, MISCREG_ID_AFR0,
  MISCREG_ID_MMFR0, MISCREG_ID_MMFR1, MISCREG_ID_MMFR2, MISCREG_ID_MMFR3,
  MISCREG_ID_MMFR4, MISCREG_ID_ISAR0, MISCREG_ID_ISAR1, MISCREG_ID_ISAR2,
  MISCREG_ID_ISAR3, MISCREG_ID_ISAR4, MISCREG_ID_ISAR5, MISCREG_ID_ISAR6,
  MISCREG_CCSIDR, MISCREG_CLIDR, MISCREG_AIDR, MISCREG_CSSELR,
  MISCREG_CSSELR_NS, MISCREG_CSSELR_S, MISCREG_VPIDR, MISCREG_VMPIDR,
  MISCREG_SCTLR, MISCREG_SCTLR_NS, MISCREG_SCTLR_S, MISCREG_ACTLR,
  MISCREG_ACTLR_NS, MISCREG_ACTLR_S, MISCREG_CPACR, MISCREG_SDCR,
  MISCREG_SCR, MISCREG_SDER, MISCREG_NSACR, MISCREG_HSCTLR,
  MISCREG_HACTLR, MISCREG_HCR, MISCREG_HCR2, MISCREG_HDCR,
  MISCREG_HCPTR, MISCREG_HSTR, MISCREG_HACR, MISCREG_TTBR0,
  MISCREG_TTBR0_NS, MISCREG_TTBR0_S, MISCREG_TTBR1, MISCREG_TTBR1_NS,
  MISCREG_TTBR1_S, MISCREG_TTBCR, MISCREG_TTBCR_NS, MISCREG_TTBCR_S,
  MISCREG_HTCR, MISCREG_VTCR, MISCREG_DACR, MISCREG_DACR_NS,
  MISCREG_DACR_S, MISCREG_DFSR, MISCREG_DFSR_NS, MISCREG_DFSR_S,
  MISCREG_IFSR, MISCREG_IFSR_NS, MISCREG_IFSR_S, MISCREG_ADFSR,
  MISCREG_ADFSR_NS, MISCREG_ADFSR_S, MISCREG_AIFSR, MISCREG_AIFSR_NS,
  MISCREG_AIFSR_S, MISCREG_HADFSR, MISCREG_HAIFSR, MISCREG_HSR,
  MISCREG_DFAR, MISCREG_DFAR_NS, MISCREG_DFAR_S, MISCREG_IFAR,
  MISCREG_IFAR_NS, MISCREG_IFAR_S, MISCREG_HDFAR, MISCREG_HIFAR,
  MISCREG_HPFAR, MISCREG_ICIALLUIS, MISCREG_BPIALLIS, MISCREG_PAR,
  MISCREG_PAR_NS, MISCREG_PAR_S, MISCREG_ICIALLU, MISCREG_ICIMVAU,
  MISCREG_CP15ISB, MISCREG_BPIALL, MISCREG_BPIMVA, MISCREG_DCIMVAC,
  MISCREG_DCISW, MISCREG_ATS1CPR, MISCREG_ATS1CPW, MISCREG_ATS1CUR,
  MISCREG_ATS1CUW, MISCREG_ATS12NSOPR, MISCREG_ATS12NSOPW, MISCREG_ATS12NSOUR,
  MISCREG_ATS12NSOUW, MISCREG_DCCMVAC, MISCREG_DCCSW, MISCREG_CP15DSB,
  MISCREG_CP15DMB, MISCREG_DCCMVAU, MISCREG_DCCIMVAC, MISCREG_DCCISW,
  MISCREG_ATS1HR, MISCREG_ATS1HW, MISCREG_TLBIALLIS, MISCREG_TLBIMVAIS,
  MISCREG_TLBIASIDIS, MISCREG_TLBIMVAAIS, MISCREG_TLBIMVALIS, MISCREG_TLBIMVAALIS,
  MISCREG_ITLBIALL, MISCREG_ITLBIMVA, MISCREG_ITLBIASID, MISCREG_DTLBIALL,
  MISCREG_DTLBIMVA, MISCREG_DTLBIASID, MISCREG_TLBIALL, MISCREG_TLBIMVA,
  MISCREG_TLBIASID, MISCREG_TLBIMVAA, MISCREG_TLBIMVAL, MISCREG_TLBIMVAAL,
  MISCREG_TLBIIPAS2IS, MISCREG_TLBIIPAS2LIS, MISCREG_TLBIALLHIS, MISCREG_TLBIMVAHIS,
  MISCREG_TLBIALLNSNHIS, MISCREG_TLBIMVALHIS, MISCREG_TLBIIPAS2, MISCREG_TLBIIPAS2L,
  MISCREG_TLBIALLH, MISCREG_TLBIMVAH, MISCREG_TLBIALLNSNH, MISCREG_TLBIMVALH,
  MISCREG_PMCR, MISCREG_PMCNTENSET, MISCREG_PMCNTENCLR, MISCREG_PMOVSR,
  MISCREG_PMSWINC, MISCREG_PMSELR, MISCREG_PMCEID0, MISCREG_PMCEID1,
  MISCREG_PMCCNTR, MISCREG_PMXEVTYPER, MISCREG_PMCCFILTR, MISCREG_PMXEVCNTR,
  MISCREG_PMUSERENR, MISCREG_PMINTENSET, MISCREG_PMINTENCLR, MISCREG_PMOVSSET,
  MISCREG_L2CTLR, MISCREG_L2ECTLR, MISCREG_PRRR, MISCREG_PRRR_NS,
  MISCREG_PRRR_S, MISCREG_MAIR0, MISCREG_MAIR0_NS, MISCREG_MAIR0_S,
  MISCREG_NMRR, MISCREG_NMRR_NS, MISCREG_NMRR_S, MISCREG_MAIR1,
  MISCREG_MAIR1_NS, MISCREG_MAIR1_S, MISCREG_AMAIR0, MISCREG_AMAIR0_NS,
  MISCREG_AMAIR0_S, MISCREG_AMAIR1, MISCREG_AMAIR1_NS, MISCREG_AMAIR1_S,
  MISCREG_HMAIR0, MISCREG_HMAIR1, MISCREG_HAMAIR0, MISCREG_HAMAIR1,
  MISCREG_VBAR, MISCREG_VBAR_NS, MISCREG_VBAR_S, MISCREG_MVBAR,
  MISCREG_RMR, MISCREG_ISR, MISCREG_HVBAR, MISCREG_FCSEIDR,
  MISCREG_CONTEXTIDR, MISCREG_CONTEXTIDR_NS, MISCREG_CONTEXTIDR_S, MISCREG_TPIDRURW,
  MISCREG_TPIDRURW_NS, MISCREG_TPIDRURW_S, MISCREG_TPIDRURO, MISCREG_TPIDRURO_NS,
  MISCREG_TPIDRURO_S, MISCREG_TPIDRPRW, MISCREG_TPIDRPRW_NS, MISCREG_TPIDRPRW_S,
  MISCREG_HTPIDR, MISCREG_CNTFRQ, MISCREG_CNTPCT, MISCREG_CNTVCT,
  MISCREG_CNTP_CTL, MISCREG_CNTP_CTL_NS, MISCREG_CNTP_CTL_S, MISCREG_CNTP_CVAL,
  MISCREG_CNTP_CVAL_NS, MISCREG_CNTP_CVAL_S, MISCREG_CNTP_TVAL, MISCREG_CNTP_TVAL_NS,
  MISCREG_CNTP_TVAL_S, MISCREG_CNTV_CTL, MISCREG_CNTV_CVAL, MISCREG_CNTV_TVAL,
  MISCREG_CNTKCTL, MISCREG_CNTHCTL, MISCREG_CNTHP_CTL, MISCREG_CNTHP_CVAL,
  MISCREG_CNTHP_TVAL, MISCREG_CNTVOFF, MISCREG_IL1DATA0, MISCREG_IL1DATA1,
  MISCREG_IL1DATA2, MISCREG_IL1DATA3, MISCREG_DL1DATA0, MISCREG_DL1DATA1,
  MISCREG_DL1DATA2, MISCREG_DL1DATA3, MISCREG_DL1DATA4, MISCREG_RAMINDEX,
  MISCREG_L2ACTLR, MISCREG_CBAR, MISCREG_HTTBR, MISCREG_VTTBR,
  MISCREG_CPUMERRSR, MISCREG_L2MERRSR, MISCREG_MDCCINT_EL1, MISCREG_OSDTRRX_EL1,
  MISCREG_MDSCR_EL1, MISCREG_OSDTRTX_EL1, MISCREG_OSECCR_EL1, MISCREG_DBGBVR0_EL1,
  MISCREG_DBGBVR1_EL1, MISCREG_DBGBVR2_EL1, MISCREG_DBGBVR3_EL1, MISCREG_DBGBVR4_EL1,
  MISCREG_DBGBVR5_EL1, MISCREG_DBGBVR6_EL1, MISCREG_DBGBVR7_EL1, MISCREG_DBGBVR8_EL1,
  MISCREG_DBGBVR9_EL1, MISCREG_DBGBVR10_EL1, MISCREG_DBGBVR11_EL1, MISCREG_DBGBVR12_EL1,
  MISCREG_DBGBVR13_EL1, MISCREG_DBGBVR14_EL1, MISCREG_DBGBVR15_EL1, MISCREG_DBGBCR0_EL1,
  MISCREG_DBGBCR1_EL1, MISCREG_DBGBCR2_EL1, MISCREG_DBGBCR3_EL1, MISCREG_DBGBCR4_EL1,
  MISCREG_DBGBCR5_EL1, MISCREG_DBGBCR6_EL1, MISCREG_DBGBCR7_EL1, MISCREG_DBGBCR8_EL1,
  MISCREG_DBGBCR9_EL1, MISCREG_DBGBCR10_EL1, MISCREG_DBGBCR11_EL1, MISCREG_DBGBCR12_EL1,
  MISCREG_DBGBCR13_EL1, MISCREG_DBGBCR14_EL1, MISCREG_DBGBCR15_EL1, MISCREG_DBGWVR0_EL1,
  MISCREG_DBGWVR1_EL1, MISCREG_DBGWVR2_EL1, MISCREG_DBGWVR3_EL1, MISCREG_DBGWVR4_EL1,
  MISCREG_DBGWVR5_EL1, MISCREG_DBGWVR6_EL1, MISCREG_DBGWVR7_EL1, MISCREG_DBGWVR8_EL1,
  MISCREG_DBGWVR9_EL1, MISCREG_DBGWVR10_EL1, MISCREG_DBGWVR11_EL1, MISCREG_DBGWVR12_EL1,
  MISCREG_DBGWVR13_EL1, MISCREG_DBGWVR14_EL1, MISCREG_DBGWVR15_EL1, MISCREG_DBGWCR0_EL1,
  MISCREG_DBGWCR1_EL1, MISCREG_DBGWCR2_EL1, MISCREG_DBGWCR3_EL1, MISCREG_DBGWCR4_EL1,
  MISCREG_DBGWCR5_EL1, MISCREG_DBGWCR6_EL1, MISCREG_DBGWCR7_EL1, MISCREG_DBGWCR8_EL1,
  MISCREG_DBGWCR9_EL1, MISCREG_DBGWCR10_EL1, MISCREG_DBGWCR11_EL1, MISCREG_DBGWCR12_EL1,
  MISCREG_DBGWCR13_EL1, MISCREG_DBGWCR14_EL1, MISCREG_DBGWCR15_EL1, MISCREG_MDCCSR_EL0,
  MISCREG_MDDTR_EL0, MISCREG_MDDTRTX_EL0, MISCREG_MDDTRRX_EL0, MISCREG_DBGVCR32_EL2,
  MISCREG_MDRAR_EL1, MISCREG_OSLAR_EL1, MISCREG_OSLSR_EL1, MISCREG_OSDLR_EL1,
  MISCREG_DBGPRCR_EL1, MISCREG_DBGCLAIMSET_EL1, MISCREG_DBGCLAIMCLR_EL1, MISCREG_DBGAUTHSTATUS_EL1,
  MISCREG_TEECR32_EL1, MISCREG_TEEHBR32_EL1, MISCREG_MIDR_EL1, MISCREG_MPIDR_EL1,
  MISCREG_REVIDR_EL1, MISCREG_ID_PFR0_EL1, MISCREG_ID_PFR1_EL1, MISCREG_ID_DFR0_EL1,
  MISCREG_ID_AFR0_EL1, MISCREG_ID_MMFR0_EL1, MISCREG_ID_MMFR1_EL1, MISCREG_ID_MMFR2_EL1,
  MISCREG_ID_MMFR3_EL1, MISCREG_ID_MMFR4_EL1, MISCREG_ID_ISAR0_EL1, MISCREG_ID_ISAR1_EL1,
  MISCREG_ID_ISAR2_EL1, MISCREG_ID_ISAR3_EL1, MISCREG_ID_ISAR4_EL1, MISCREG_ID_ISAR5_EL1,
  MISCREG_ID_ISAR6_EL1, MISCREG_MVFR0_EL1, MISCREG_MVFR1_EL1, MISCREG_MVFR2_EL1,
  MISCREG_ID_AA64PFR0_EL1, MISCREG_ID_AA64PFR1_EL1, MISCREG_ID_AA64DFR0_EL1, MISCREG_ID_AA64DFR1_EL1,
  MISCREG_ID_AA64AFR0_EL1, MISCREG_ID_AA64AFR1_EL1, MISCREG_ID_AA64ISAR0_EL1, MISCREG_ID_AA64ISAR1_EL1,
  MISCREG_ID_AA64MMFR0_EL1, MISCREG_ID_AA64MMFR1_EL1, MISCREG_CCSIDR_EL1, MISCREG_CLIDR_EL1,
  MISCREG_AIDR_EL1, MISCREG_CSSELR_EL1, MISCREG_CTR_EL0, MISCREG_DCZID_EL0,
  MISCREG_VPIDR_EL2, MISCREG_VMPIDR_EL2, MISCREG_SCTLR_EL1, MISCREG_SCTLR_EL12,
  MISCREG_ACTLR_EL1, MISCREG_CPACR_EL1, MISCREG_CPACR_EL12, MISCREG_SCTLR_EL2,
  MISCREG_ACTLR_EL2, MISCREG_HCR_EL2, MISCREG_HCRX_EL2, MISCREG_MDCR_EL2,
  MISCREG_CPTR_EL2, MISCREG_HSTR_EL2, MISCREG_HACR_EL2, MISCREG_SCTLR_EL3,
  MISCREG_ACTLR_EL3, MISCREG_SCR_EL3, MISCREG_SDER32_EL3, MISCREG_CPTR_EL3,
  MISCREG_MDCR_EL3, MISCREG_TTBR0_EL1, MISCREG_TTBR0_EL12, MISCREG_TTBR1_EL1,
  MISCREG_TTBR1_EL12, MISCREG_TCR_EL1, MISCREG_TCR_EL12, MISCREG_TTBR0_EL2,
  MISCREG_TCR_EL2, MISCREG_VTTBR_EL2, MISCREG_VTCR_EL2, MISCREG_VSTTBR_EL2,
  MISCREG_VSTCR_EL2, MISCREG_TTBR0_EL3, MISCREG_TCR_EL3, MISCREG_DACR32_EL2,
  MISCREG_SPSR_EL1, MISCREG_SPSR_EL12, MISCREG_ELR_EL1, MISCREG_ELR_EL12,
  MISCREG_SP_EL0, MISCREG_SPSEL, MISCREG_CURRENTEL, MISCREG_NZCV,
  MISCREG_DAIF, MISCREG_FPCR, MISCREG_FPSR, MISCREG_DSPSR_EL0,
  MISCREG_DLR_EL0, MISCREG_SPSR_EL2, MISCREG_ELR_EL2, MISCREG_SP_EL1,
  MISCREG_SPSR_IRQ_AA64, MISCREG_SPSR_ABT_AA64, MISCREG_SPSR_UND_AA64, MISCREG_SPSR_FIQ_AA64,
  MISCREG_SPSR_EL3, MISCREG_ELR_EL3, MISCREG_SP_EL2, MISCREG_AFSR0_EL1,
  MISCREG_AFSR0_EL12, MISCREG_AFSR1_EL1, MISCREG_AFSR1_EL12, MISCREG_ESR_EL1,
  MISCREG_ESR_EL12, MISCREG_IFSR32_EL2, MISCREG_AFSR0_EL2, MISCREG_AFSR1_EL2,
  MISCREG_ESR_EL2, MISCREG_FPEXC32_EL2, MISCREG_AFSR0_EL3, MISCREG_AFSR1_EL3,
  MISCREG_ESR_EL3, MISCREG_FAR_EL1, MISCREG_FAR_EL12, MISCREG_FAR_EL2,
  MISCREG_HPFAR_EL2, MISCREG_FAR_EL3, MISCREG_IC_IALLUIS, MISCREG_PAR_EL1,
  MISCREG_IC_IALLU, MISCREG_DC_IVAC_Xt, MISCREG_DC_ISW_Xt, MISCREG_AT_S1E1R_Xt,
  MISCREG_AT_S1E1W_Xt, MISCREG_AT_S1E0R_Xt, MISCREG_AT_S1E0W_Xt, MISCREG_DC_CSW_Xt,
  MISCREG_DC_CISW_Xt, MISCREG_DC_ZVA_Xt, MISCREG_IC_IVAU_Xt, MISCREG_DC_CVAC_Xt,
  MISCREG_DC_CVAU_Xt, MISCREG_DC_CIVAC_Xt, MISCREG_AT_S1E2R_Xt, MISCREG_AT_S1E2W_Xt,
  MISCREG_AT_S12E1R_Xt, MISCREG_AT_S12E1W_Xt, MISCREG_AT_S12E0R_Xt, MISCREG_AT_S12E0W_Xt,
  MISCREG_AT_S1E3R_Xt, MISCREG_AT_S1E3W_Xt, MISCREG_TLBI_VMALLE1IS, MISCREG_TLBI_VMALLE1OS,
  MISCREG_TLBI_VAE1IS_Xt, MISCREG_TLBI_VAE1OS_Xt, MISCREG_TLBI_ASIDE1IS_Xt, MISCREG_TLBI_ASIDE1OS_Xt,
  MISCREG_TLBI_VAAE1IS_Xt, MISCREG_TLBI_VAAE1OS_Xt, MISCREG_TLBI_VALE1IS_Xt, MISCREG_TLBI_VALE1OS_Xt,
  MISCREG_TLBI_VAALE1IS_Xt, MISCREG_TLBI_VAALE1OS_Xt, MISCREG_TLBI_VMALLE1, MISCREG_TLBI_VAE1_Xt,
  MISCREG_TLBI_ASIDE1_Xt, MISCREG_TLBI_VAAE1_Xt, MISCREG_TLBI_VALE1_Xt, MISCREG_TLBI_VAALE1_Xt,
  MISCREG_TLBI_IPAS2E1IS_Xt, MISCREG_TLBI_IPAS2E1OS_Xt, MISCREG_TLBI_IPAS2LE1IS_Xt, MISCREG_TLBI_IPAS2LE1OS_Xt,
  MISCREG_TLBI_ALLE2IS, MISCREG_TLBI_ALLE2OS, MISCREG_TLBI_VAE2IS_Xt, MISCREG_TLBI_VAE2OS_Xt,
  MISCREG_TLBI_ALLE1IS, MISCREG_TLBI_ALLE1OS, MISCREG_TLBI_VALE2IS_Xt, MISCREG_TLBI_VALE2OS_Xt,
  MISCREG_TLBI_VMALLS12E1IS, MISCREG_TLBI_VMALLS12E1OS, MISCREG_TLBI_IPAS2E1_Xt, MISCREG_TLBI_IPAS2LE1_Xt,
  MISCREG_TLBI_ALLE2, MISCREG_TLBI_VAE2_Xt, MISCREG_TLBI_ALLE1, MISCREG_TLBI_VALE2_Xt,
  MISCREG_TLBI_VMALLS12E1, MISCREG_TLBI_ALLE3IS, MISCREG_TLBI_ALLE3OS, MISCREG_TLBI_VAE3IS_Xt,
  MISCREG_TLBI_VAE3OS_Xt, MISCREG_TLBI_VALE3IS_Xt, MISCREG_TLBI_VALE3OS_Xt, MISCREG_TLBI_ALLE3,
  MISCREG_TLBI_VAE3_Xt, MISCREG_TLBI_VALE3_Xt, MISCREG_PMINTENSET_EL1, MISCREG_PMINTENCLR_EL1,
  MISCREG_PMCR_EL0, MISCREG_PMCNTENSET_EL0, MISCREG_PMCNTENCLR_EL0, MISCREG_PMOVSCLR_EL0,
  MISCREG_PMSWINC_EL0, MISCREG_PMSELR_EL0, MISCREG_PMCEID0_EL0, MISCREG_PMCEID1_EL0,
  MISCREG_PMCCNTR_EL0, MISCREG_PMXEVTYPER_EL0, MISCREG_PMCCFILTR_EL0, MISCREG_PMXEVCNTR_EL0,
  MISCREG_PMUSERENR_EL0, MISCREG_PMOVSSET_EL0, MISCREG_MAIR_EL1, MISCREG_MAIR_EL12,
  MISCREG_AMAIR_EL1, MISCREG_AMAIR_EL12, MISCREG_MAIR_EL2, MISCREG_AMAIR_EL2,
  MISCREG_MAIR_EL3, MISCREG_AMAIR_EL3, MISCREG_L2CTLR_EL1, MISCREG_L2ECTLR_EL1,
  MISCREG_VBAR_EL1, MISCREG_VBAR_EL12, MISCREG_RVBAR_EL1, MISCREG_ISR_EL1,
  MISCREG_VBAR_EL2, MISCREG_RVBAR_EL2, MISCREG_VBAR_EL3, MISCREG_RVBAR_EL3,
  MISCREG_RMR_EL3, MISCREG_CONTEXTIDR_EL1, MISCREG_CONTEXTIDR_EL12, MISCREG_TPIDR_EL1,
  MISCREG_TPIDR_EL0, MISCREG_TPIDRRO_EL0, MISCREG_TPIDR_EL2, MISCREG_TPIDR_EL3,
  MISCREG_CNTFRQ_EL0, MISCREG_CNTPCT_EL0, MISCREG_CNTVCT_EL0, MISCREG_CNTP_CTL_EL0,
  MISCREG_CNTP_CVAL_EL0, MISCREG_CNTP_TVAL_EL0, MISCREG_CNTV_CTL_EL0, MISCREG_CNTV_CVAL_EL0,
  MISCREG_CNTV_TVAL_EL0, MISCREG_CNTP_CTL_EL02, MISCREG_CNTP_CVAL_EL02, MISCREG_CNTP_TVAL_EL02,
  MISCREG_CNTV_CTL_EL02, MISCREG_CNTV_CVAL_EL02, MISCREG_CNTV_TVAL_EL02, MISCREG_CNTKCTL_EL1,
  MISCREG_CNTKCTL_EL12, MISCREG_CNTPS_CTL_EL1, MISCREG_CNTPS_CVAL_EL1, MISCREG_CNTPS_TVAL_EL1,
  MISCREG_CNTHCTL_EL2, MISCREG_CNTHP_CTL_EL2, MISCREG_CNTHP_CVAL_EL2, MISCREG_CNTHP_TVAL_EL2,
  MISCREG_CNTHPS_CTL_EL2, MISCREG_CNTHPS_CVAL_EL2, MISCREG_CNTHPS_TVAL_EL2, MISCREG_CNTHV_CTL_EL2,
  MISCREG_CNTHV_CVAL_EL2, MISCREG_CNTHV_TVAL_EL2, MISCREG_CNTHVS_CTL_EL2, MISCREG_CNTHVS_CVAL_EL2,
  MISCREG_CNTHVS_TVAL_EL2, MISCREG_CNTVOFF_EL2, MISCREG_PMEVCNTR0_EL0, MISCREG_PMEVCNTR1_EL0,
  MISCREG_PMEVCNTR2_EL0, MISCREG_PMEVCNTR3_EL0, MISCREG_PMEVCNTR4_EL0, MISCREG_PMEVCNTR5_EL0,
  MISCREG_PMEVTYPER0_EL0, MISCREG_PMEVTYPER1_EL0, MISCREG_PMEVTYPER2_EL0, MISCREG_PMEVTYPER3_EL0,
  MISCREG_PMEVTYPER4_EL0, MISCREG_PMEVTYPER5_EL0, MISCREG_IL1DATA0_EL1, MISCREG_IL1DATA1_EL1,
  MISCREG_IL1DATA2_EL1, MISCREG_IL1DATA3_EL1, MISCREG_DL1DATA0_EL1, MISCREG_DL1DATA1_EL1,
  MISCREG_DL1DATA2_EL1, MISCREG_DL1DATA3_EL1, MISCREG_DL1DATA4_EL1, MISCREG_L2ACTLR_EL1,
  MISCREG_CPUACTLR_EL1, MISCREG_CPUECTLR_EL1, MISCREG_CPUMERRSR_EL1, MISCREG_L2MERRSR_EL1,
  MISCREG_CBAR_EL1, MISCREG_CONTEXTIDR_EL2, MISCREG_TTBR1_EL2, MISCREG_ID_AA64MMFR2_EL1,
  MISCREG_APDAKeyHi_EL1, MISCREG_APDAKeyLo_EL1, MISCREG_APDBKeyHi_EL1, MISCREG_APDBKeyLo_EL1,
  MISCREG_APGAKeyHi_EL1, MISCREG_APGAKeyLo_EL1, MISCREG_APIAKeyHi_EL1, MISCREG_APIAKeyLo_EL1,
  MISCREG_APIBKeyHi_EL1, MISCREG_APIBKeyLo_EL1, MISCREG_ICC_PMR_EL1, MISCREG_ICC_IAR0_EL1,
  MISCREG_ICC_EOIR0_EL1, MISCREG_ICC_HPPIR0_EL1, MISCREG_ICC_BPR0_EL1, MISCREG_ICC_AP0R0_EL1,
  MISCREG_ICC_AP0R1_EL1, MISCREG_ICC_AP0R2_EL1, MISCREG_ICC_AP0R3_EL1, MISCREG_ICC_AP1R0_EL1,
  MISCREG_ICC_AP1R0_EL1_NS, MISCREG_ICC_AP1R0_EL1_S, MISCREG_ICC_AP1R1_EL1, MISCREG_ICC_AP1R1_EL1_NS,
  MISCREG_ICC_AP1R1_EL1_S, MISCREG_ICC_AP1R2_EL1, MISCREG_ICC_AP1R2_EL1_NS, MISCREG_ICC_AP1R2_EL1_S,
  MISCREG_ICC_AP1R3_EL1, MISCREG_ICC_AP1R3_EL1_NS, MISCREG_ICC_AP1R3_EL1_S, MISCREG_ICC_DIR_EL1,
  MISCREG_ICC_RPR_EL1, MISCREG_ICC_SGI1R_EL1, MISCREG_ICC_ASGI1R_EL1, MISCREG_ICC_SGI0R_EL1,
  MISCREG_ICC_IAR1_EL1, MISCREG_ICC_EOIR1_EL1, MISCREG_ICC_HPPIR1_EL1, MISCREG_ICC_BPR1_EL1,
  MISCREG_ICC_BPR1_EL1_NS, MISCREG_ICC_BPR1_EL1_S, MISCREG_ICC_CTLR_EL1, MISCREG_ICC_CTLR_EL1_NS,
  MISCREG_ICC_CTLR_EL1_S, MISCREG_ICC_SRE_EL1, MISCREG_ICC_SRE_EL1_NS, MISCREG_ICC_SRE_EL1_S,
  MISCREG_ICC_IGRPEN0_EL1, MISCREG_ICC_IGRPEN1_EL1, MISCREG_ICC_IGRPEN1_EL1_NS, MISCREG_ICC_IGRPEN1_EL1_S,
  MISCREG_ICC_SRE_EL2, MISCREG_ICC_CTLR_EL3, MISCREG_ICC_SRE_EL3, MISCREG_ICC_IGRPEN1_EL3,
  MISCREG_ICH_AP0R0_EL2, MISCREG_ICH_AP0R1_EL2, MISCREG_ICH_AP0R2_EL2, MISCREG_ICH_AP0R3_EL2,
  MISCREG_ICH_AP1R0_EL2, MISCREG_ICH_AP1R1_EL2, MISCREG_ICH_AP1R2_EL2, MISCREG_ICH_AP1R3_EL2,
  MISCREG_ICH_HCR_EL2, MISCREG_ICH_VTR_EL2, MISCREG_ICH_MISR_EL2, MISCREG_ICH_EISR_EL2,
  MISCREG_ICH_ELRSR_EL2, MISCREG_ICH_VMCR_EL2, MISCREG_ICH_LR0_EL2, MISCREG_ICH_LR1_EL2,
  MISCREG_ICH_LR2_EL2, MISCREG_ICH_LR3_EL2, MISCREG_ICH_LR4_EL2, MISCREG_ICH_LR5_EL2,
  MISCREG_ICH_LR6_EL2, MISCREG_ICH_LR7_EL2, MISCREG_ICH_LR8_EL2, MISCREG_ICH_LR9_EL2,
  MISCREG_ICH_LR10_EL2, MISCREG_ICH_LR11_EL2, MISCREG_ICH_LR12_EL2, MISCREG_ICH_LR13_EL2,
  MISCREG_ICH_LR14_EL2, MISCREG_ICH_LR15_EL2, MISCREG_ICV_PMR_EL1, MISCREG_ICV_IAR0_EL1,
  MISCREG_ICV_EOIR0_EL1, MISCREG_ICV_HPPIR0_EL1, MISCREG_ICV_BPR0_EL1, MISCREG_ICV_AP0R0_EL1,
  MISCREG_ICV_AP0R1_EL1, MISCREG_ICV_AP0R2_EL1, MISCREG_ICV_AP0R3_EL1, MISCREG_ICV_AP1R0_EL1,
  MISCREG_ICV_AP1R0_EL1_NS, MISCREG_ICV_AP1R0_EL1_S, MISCREG_ICV_AP1R1_EL1, MISCREG_ICV_AP1R1_EL1_NS,
  MISCREG_ICV_AP1R1_EL1_S, MISCREG_ICV_AP1R2_EL1, MISCREG_ICV_AP1R2_EL1_NS, MISCREG_ICV_AP1R2_EL1_S,
  MISCREG_ICV_AP1R3_EL1, MISCREG_ICV_AP1R3_EL1_NS, MISCREG_ICV_AP1R3_EL1_S, MISCREG_ICV_DIR_EL1,
  MISCREG_ICV_RPR_EL1, MISCREG_ICV_SGI1R_EL1, MISCREG_ICV_ASGI1R_EL1, MISCREG_ICV_SGI0R_EL1,
  MISCREG_ICV_IAR1_EL1, MISCREG_ICV_EOIR1_EL1, MISCREG_ICV_HPPIR1_EL1, MISCREG_ICV_BPR1_EL1,
  MISCREG_ICV_BPR1_EL1_NS, MISCREG_ICV_BPR1_EL1_S, MISCREG_ICV_CTLR_EL1, MISCREG_ICV_CTLR_EL1_NS,
  MISCREG_ICV_CTLR_EL1_S, MISCREG_ICV_SRE_EL1, MISCREG_ICV_SRE_EL1_NS, MISCREG_ICV_SRE_EL1_S,
  MISCREG_ICV_IGRPEN0_EL1, MISCREG_ICV_IGRPEN1_EL1, MISCREG_ICV_IGRPEN1_EL1_NS, MISCREG_ICV_IGRPEN1_EL1_S,
  MISCREG_ICC_AP0R0, MISCREG_ICC_AP0R1, MISCREG_ICC_AP0R2, MISCREG_ICC_AP0R3,
  MISCREG_ICC_AP1R0, MISCREG_ICC_AP1R0_NS, MISCREG_ICC_AP1R0_S, MISCREG_ICC_AP1R1,
  MISCREG_ICC_AP1R1_NS, MISCREG_ICC_AP1R1_S, MISCREG_ICC_AP1R2, MISCREG_ICC_AP1R2_NS,
  MISCREG_ICC_AP1R2_S, MISCREG_ICC_AP1R3, MISCREG_ICC_AP1R3_NS, MISCREG_ICC_AP1R3_S,
  MISCREG_ICC_ASGI1R, MISCREG_ICC_BPR0, MISCREG_ICC_BPR1, MISCREG_ICC_BPR1_NS,
  MISCREG_ICC_BPR1_S, MISCREG_ICC_CTLR, MISCREG_ICC_CTLR_NS, MISCREG_ICC_CTLR_S,
  MISCREG_ICC_DIR, MISCREG_ICC_EOIR0, MISCREG_ICC_EOIR1, MISCREG_ICC_HPPIR0,
  MISCREG_ICC_HPPIR1, MISCREG_ICC_HSRE, MISCREG_ICC_IAR0, MISCREG_ICC_IAR1,
  MISCREG_ICC_IGRPEN0, MISCREG_ICC_IGRPEN1, MISCREG_ICC_IGRPEN1_NS, MISCREG_ICC_IGRPEN1_S,
  MISCREG_ICC_MCTLR, MISCREG_ICC_MGRPEN1, MISCREG_ICC_MSRE, MISCREG_ICC_PMR,
  MISCREG_ICC_RPR, MISCREG_ICC_SGI0R, MISCREG_ICC_SGI1R, MISCREG_ICC_SRE,
  MISCREG_ICC_SRE_NS, MISCREG_ICC_SRE_S, MISCREG_ICH_AP0R0, MISCREG_ICH_AP0R1,
  MISCREG_ICH_AP0R2, MISCREG_ICH_AP0R3, MISCREG_ICH_AP1R0, MISCREG_ICH_AP1R1,
  MISCREG_ICH_AP1R2, MISCREG_ICH_AP1R3, MISCREG_ICH_HCR, MISCREG_ICH_VTR,
  MISCREG_ICH_MISR, MISCREG_ICH_EISR, MISCREG_ICH_ELRSR, MISCREG_ICH_VMCR,
  MISCREG_ICH_LR0, MISCREG_ICH_LR1, MISCREG_ICH_LR2, MISCREG_ICH_LR3,
  MISCREG_ICH_LR4, MISCREG_ICH_LR5, MISCREG_ICH_LR6, MISCREG_ICH_LR7,
  MISCREG_ICH_LR8, MISCREG_ICH_LR9, MISCREG_ICH_LR10, MISCREG_ICH_LR11,
  MISCREG_ICH_LR12, MISCREG_ICH_LR13, MISCREG_ICH_LR14, MISCREG_ICH_LR15,
  MISCREG_ICH_LRC0, MISCREG_ICH_LRC1, MISCREG_ICH_LRC2, MISCREG_ICH_LRC3,
  MISCREG_ICH_LRC4, MISCREG_ICH_LRC5, MISCREG_ICH_LRC6, MISCREG_ICH_LRC7,
  MISCREG_ICH_LRC8, MISCREG_ICH_LRC9, MISCREG_ICH_LRC10, MISCREG_ICH_LRC11,
  MISCREG_ICH_LRC12, MISCREG_ICH_LRC13, MISCREG_ICH_LRC14, MISCREG_ICH_LRC15,
  MISCREG_ID_AA64ZFR0_EL1, MISCREG_ZCR_EL3, MISCREG_ZCR_EL2, MISCREG_ZCR_EL12,
  MISCREG_ZCR_EL1, MISCREG_ID_AA64SMFR0_EL1, MISCREG_SVCR, MISCREG_SMIDR_EL1,
  MISCREG_SMPRI_EL1, MISCREG_SMPRIMAP_EL2, MISCREG_SMCR_EL3, MISCREG_SMCR_EL2,
  MISCREG_SMCR_EL12, MISCREG_SMCR_EL1, MISCREG_TPIDR2_EL0, MISCREG_MPAMSM_EL1,
  MISCREG_RNDR, MISCREG_RNDRRS, NUM_PHYS_MISCREGS, MISCREG_NOP,
  MISCREG_RAZ, MISCREG_UNKNOWN, MISCREG_IMPDEF_UNIMPL, MISCREG_ERRIDR_EL1,
  MISCREG_ERRSELR_EL1, MISCREG_ERXFR_EL1, MISCREG_ERXCTLR_EL1, MISCREG_ERXSTATUS_EL1,
  MISCREG_ERXADDR_EL1, MISCREG_ERXMISC0_EL1, MISCREG_ERXMISC1_EL1, MISCREG_DISR_EL1,
  MISCREG_VSESR_EL2, MISCREG_VDISR_EL2, MISCREG_HFGRTR_EL2, MISCREG_HFGWTR_EL2,
  MISCREG_PAN, MISCREG_UAO, NUM_MISCREGS
}
 
enum  MiscRegInfo {
  MISCREG_IMPLEMENTED, MISCREG_UNVERIFIABLE, MISCREG_UNSERIALIZE, MISCREG_WARN_NOT_FAIL,
  MISCREG_MUTEX, MISCREG_BANKED, MISCREG_BANKED64, MISCREG_BANKED_CHILD,
  MISCREG_USR_NS_RD, MISCREG_USR_NS_WR, MISCREG_USR_S_RD, MISCREG_USR_S_WR,
  MISCREG_PRI_NS_RD, MISCREG_PRI_NS_WR, MISCREG_PRI_S_RD, MISCREG_PRI_S_WR,
  MISCREG_HYP_NS_RD, MISCREG_HYP_NS_WR, MISCREG_HYP_S_RD, MISCREG_HYP_S_WR,
  MISCREG_MON_NS0_RD, MISCREG_MON_NS0_WR, MISCREG_MON_NS1_RD, MISCREG_MON_NS1_WR,
  NUM_MISCREG_INFOS
}
 
enum  ArmExtendType {
  UXTB = 0, UXTH = 1, UXTW = 2, UXTX = 3,
  SXTB = 4, SXTH = 5, SXTW = 6, SXTX = 7
}
 
enum  ConvertType {
  SINGLE_TO_DOUBLE, SINGLE_TO_WORD, SINGLE_TO_LONG, DOUBLE_TO_SINGLE,
  DOUBLE_TO_WORD, DOUBLE_TO_LONG, LONG_TO_SINGLE, LONG_TO_DOUBLE,
  LONG_TO_WORD, LONG_TO_PS, WORD_TO_SINGLE, WORD_TO_DOUBLE,
  WORD_TO_LONG, WORD_TO_PS, PL_TO_SINGLE, PU_TO_SINGLE
}
 
enum  RoundMode { RND_ZERO, RND_DOWN, RND_UP, RND_NEAREST }
 
enum  ExceptionLevel { EL0 = 0, EL1, EL2, EL3 }
 
enum  OperatingMode {
  MODE_EL0T = 0x0, MODE_EL1T = 0x4, MODE_EL1H = 0x5, MODE_EL2T = 0x8,
  MODE_EL2H = 0x9, MODE_EL3T = 0xC, MODE_EL3H = 0xD, MODE_USER = 16,
  MODE_FIQ = 17, MODE_IRQ = 18, MODE_SVC = 19, MODE_MON = 22,
  MODE_ABORT = 23, MODE_HYP = 26, MODE_UNDEFINED = 27, MODE_SYSTEM = 31,
  MODE_MAXMODE = MODE_SYSTEM
}
 
enum  ExceptionClass {
  ExceptionClass::INVALID = -1, ExceptionClass::UNKNOWN = 0x0, ExceptionClass::TRAPPED_WFI_WFE = 0x1, ExceptionClass::TRAPPED_CP15_MCR_MRC = 0x3,
  ExceptionClass::TRAPPED_CP15_MCRR_MRRC = 0x4, ExceptionClass::TRAPPED_CP14_MCR_MRC = 0x5, ExceptionClass::TRAPPED_CP14_LDC_STC = 0x6, ExceptionClass::TRAPPED_HCPTR = 0x7,
  ExceptionClass::TRAPPED_SIMD_FP = 0x7, ExceptionClass::TRAPPED_CP10_MRC_VMRS = 0x8, ExceptionClass::TRAPPED_PAC = 0x9, ExceptionClass::TRAPPED_BXJ = 0xA,
  ExceptionClass::TRAPPED_CP14_MCRR_MRRC = 0xC, ExceptionClass::ILLEGAL_INST = 0xE, ExceptionClass::SVC_TO_HYP = 0x11, ExceptionClass::SVC = 0x11,
  ExceptionClass::HVC = 0x12, ExceptionClass::SMC_TO_HYP = 0x13, ExceptionClass::SMC = 0x13, ExceptionClass::SVC_64 = 0x15,
  ExceptionClass::HVC_64 = 0x16, ExceptionClass::SMC_64 = 0x17, ExceptionClass::TRAPPED_MSR_MRS_64 = 0x18, ExceptionClass::TRAPPED_SVE = 0x19,
  ExceptionClass::TRAPPED_SME = 0x1D, ExceptionClass::PREFETCH_ABORT_TO_HYP = 0x20, ExceptionClass::PREFETCH_ABORT_LOWER_EL = 0x20, ExceptionClass::PREFETCH_ABORT_FROM_HYP = 0x21,
  ExceptionClass::PREFETCH_ABORT_CURR_EL = 0x21, ExceptionClass::PC_ALIGNMENT = 0x22, ExceptionClass::DATA_ABORT_TO_HYP = 0x24, ExceptionClass::DATA_ABORT_LOWER_EL = 0x24,
  ExceptionClass::DATA_ABORT_FROM_HYP = 0x25, ExceptionClass::DATA_ABORT_CURR_EL = 0x25, ExceptionClass::STACK_PTR_ALIGNMENT = 0x26, ExceptionClass::FP_EXCEPTION = 0x28,
  ExceptionClass::FP_EXCEPTION_64 = 0x2C, ExceptionClass::SERROR = 0x2F, ExceptionClass::HW_BREAKPOINT = 0x30, ExceptionClass::HW_BREAKPOINT_LOWER_EL = 0x30,
  ExceptionClass::HW_BREAKPOINT_CURR_EL = 0x31, ExceptionClass::SOFTWARE_STEP = 0x32, ExceptionClass::SOFTWARE_STEP_LOWER_EL = 0x32, ExceptionClass::SOFTWARE_STEP_CURR_EL = 0x33,
  ExceptionClass::WATCHPOINT = 0x34, ExceptionClass::WATCHPOINT_LOWER_EL = 0x34, ExceptionClass::WATCHPOINT_CURR_EL = 0x35, ExceptionClass::SOFTWARE_BREAKPOINT = 0x38,
  ExceptionClass::VECTOR_CATCH = 0x3A, ExceptionClass::SOFTWARE_BREAKPOINT_64 = 0x3C
}
 
enum  DecoderFault : std::uint8_t { OK = 0x0, UNALIGNED = 0x1, PANIC = 0x3 }
 Instruction decoder fault codes in ExtMachInst. More...
 

Functions

bool getFaultVAddr (Fault fault, Addr &va)
 Returns true if the fault passed as a first argument was triggered by a memory access, false otherwise. More...
 
static SyscallReturn issetugidFunc (SyscallDesc *desc, ThreadContext *tc)
 
static SyscallReturn sysctlFunc (SyscallDesc *desc, ThreadContext *tc, VPtr<> namep, size_t nameLen, VPtr<> oldp, VPtr<> oldlenp, VPtr<> newp, size_t newlen)
 
static uint16_t lsl16 (uint16_t x, uint32_t shift)
 
static uint16_t lsr16 (uint16_t x, uint32_t shift)
 
static uint32_t lsl32 (uint32_t x, uint32_t shift)
 
static uint32_t lsr32 (uint32_t x, uint32_t shift)
 
static uint64_t lsl64 (uint64_t x, uint32_t shift)
 
static uint64_t lsr64 (uint64_t x, uint32_t shift)
 
static void lsl128 (uint64_t *r0, uint64_t *r1, uint64_t x0, uint64_t x1, uint32_t shift)
 
static void lsr128 (uint64_t *r0, uint64_t *r1, uint64_t x0, uint64_t x1, uint32_t shift)
 
static void mul62x62 (uint64_t *x0, uint64_t *x1, uint64_t a, uint64_t b)
 
static void mul64x32 (uint64_t *x0, uint64_t *x1, uint64_t a, uint32_t b)
 
static void add128 (uint64_t *x0, uint64_t *x1, uint64_t a0, uint64_t a1, uint64_t b0, uint64_t b1)
 
static void sub128 (uint64_t *x0, uint64_t *x1, uint64_t a0, uint64_t a1, uint64_t b0, uint64_t b1)
 
static int cmp128 (uint64_t a0, uint64_t a1, uint64_t b0, uint64_t b1)
 
static uint16_t fp16_normalise (uint16_t mnt, int *exp)
 
static uint32_t fp32_normalise (uint32_t mnt, int *exp)
 
static uint64_t fp64_normalise (uint64_t mnt, int *exp)
 
static void fp128_normalise (uint64_t *mnt0, uint64_t *mnt1, int *exp)
 
static uint16_t fp16_pack (uint16_t sgn, uint16_t exp, uint16_t mnt)
 
static uint32_t fp32_pack (uint32_t sgn, uint32_t exp, uint32_t mnt)
 
static uint64_t fp64_pack (uint64_t sgn, uint64_t exp, uint64_t mnt)
 
static uint16_t fp16_zero (int sgn)
 
static uint32_t fp32_zero (int sgn)
 
static uint64_t fp64_zero (int sgn)
 
static uint16_t fp16_max_normal (int sgn)
 
static uint32_t fp32_max_normal (int sgn)
 
static uint64_t fp64_max_normal (int sgn)
 
static uint16_t fp16_infinity (int sgn)
 
static uint32_t fp32_infinity (int sgn)
 
static uint64_t fp64_infinity (int sgn)
 
static uint16_t fp16_defaultNaN ()
 
static uint32_t fp32_defaultNaN ()
 
static uint64_t fp64_defaultNaN ()
 
static void fp16_unpack (int *sgn, int *exp, uint16_t *mnt, uint16_t x, int mode, int *flags)
 
static void fp32_unpack (int *sgn, int *exp, uint32_t *mnt, uint32_t x, int mode, int *flags)
 
static void fp64_unpack (int *sgn, int *exp, uint64_t *mnt, uint64_t x, int mode, int *flags)
 
static int fp16_is_NaN (int exp, uint16_t mnt)
 
static int fp32_is_NaN (int exp, uint32_t mnt)
 
static int fp64_is_NaN (int exp, uint64_t mnt)
 
static int fp16_is_signalling_NaN (int exp, uint16_t mnt)
 
static int fp32_is_signalling_NaN (int exp, uint32_t mnt)
 
static int fp64_is_signalling_NaN (int exp, uint64_t mnt)
 
static int fp16_is_quiet_NaN (int exp, uint16_t mnt)
 
static int fp32_is_quiet_NaN (int exp, uint32_t mnt)
 
static int fp64_is_quiet_NaN (int exp, uint64_t mnt)
 
static int fp16_is_infinity (int exp, uint16_t mnt)
 
static int fp32_is_infinity (int exp, uint32_t mnt)
 
static int fp64_is_infinity (int exp, uint64_t mnt)
 
static uint16_t fp16_process_NaN (uint16_t a, int mode, int *flags)
 
static uint32_t fp32_process_NaN (uint32_t a, int mode, int *flags)
 
static uint64_t fp64_process_NaN (uint64_t a, int mode, int *flags)
 
static uint16_t fp16_process_NaNs (uint16_t a, uint16_t b, int mode, int *flags)
 
static uint32_t fp32_process_NaNs (uint32_t a, uint32_t b, int mode, int *flags)
 
static uint64_t fp64_process_NaNs (uint64_t a, uint64_t b, int mode, int *flags)
 
static uint16_t fp16_process_NaNs3 (uint16_t a, uint16_t b, uint16_t c, int mode, int *flags)
 
static uint32_t fp32_process_NaNs3 (uint32_t a, uint32_t b, uint32_t c, int mode, int *flags)
 
static uint64_t fp64_process_NaNs3 (uint64_t a, uint64_t b, uint64_t c, int mode, int *flags)
 
static uint16_t fp16_round_ (int sgn, int exp, uint16_t mnt, int rm, int mode, int *flags)
 
static uint16_t fp16_round (int sgn, int exp, uint16_t mnt, int mode, int *flags)
 
static uint32_t fp32_round_ (int sgn, int exp, uint32_t mnt, int rm, int mode, int *flags)
 
static uint32_t fp32_round (int sgn, int exp, uint32_t mnt, int mode, int *flags)
 
static uint64_t fp64_round_ (int sgn, int exp, uint64_t mnt, int rm, int mode, int *flags)
 
static uint64_t fp64_round (int sgn, int exp, uint64_t mnt, int mode, int *flags)
 
static int fp16_compare_eq (uint16_t a, uint16_t b, int mode, int *flags)
 
static int fp16_compare_ge (uint16_t a, uint16_t b, int mode, int *flags)
 
static int fp16_compare_gt (uint16_t a, uint16_t b, int mode, int *flags)
 
static int fp16_compare_un (uint16_t a, uint16_t b, int mode, int *flags)
 
static int fp32_compare_eq (uint32_t a, uint32_t b, int mode, int *flags)
 
static int fp32_compare_ge (uint32_t a, uint32_t b, int mode, int *flags)
 
static int fp32_compare_gt (uint32_t a, uint32_t b, int mode, int *flags)
 
static int fp32_compare_un (uint32_t a, uint32_t b, int mode, int *flags)
 
static int fp64_compare_eq (uint64_t a, uint64_t b, int mode, int *flags)
 
static int fp64_compare_ge (uint64_t a, uint64_t b, int mode, int *flags)
 
static int fp64_compare_gt (uint64_t a, uint64_t b, int mode, int *flags)
 
static int fp64_compare_un (uint64_t a, uint64_t b, int mode, int *flags)
 
static uint16_t fp16_add (uint16_t a, uint16_t b, int neg, int mode, int *flags)
 
static uint32_t fp32_add (uint32_t a, uint32_t b, int neg, int mode, int *flags)
 
static uint64_t fp64_add (uint64_t a, uint64_t b, int neg, int mode, int *flags)
 
static uint16_t fp16_mul (uint16_t a, uint16_t b, int mode, int *flags)
 
static uint32_t fp32_mul (uint32_t a, uint32_t b, int mode, int *flags)
 
static uint64_t fp64_mul (uint64_t a, uint64_t b, int mode, int *flags)
 
static uint16_t fp16_muladd (uint16_t a, uint16_t b, uint16_t c, int scale, int mode, int *flags)
 
static uint32_t fp32_muladd (uint32_t a, uint32_t b, uint32_t c, int scale, int mode, int *flags)
 
static uint64_t fp64_muladd (uint64_t a, uint64_t b, uint64_t c, int scale, int mode, int *flags)
 
static uint16_t fp16_div (uint16_t a, uint16_t b, int mode, int *flags)
 
static uint32_t fp32_div (uint32_t a, uint32_t b, int mode, int *flags)
 
static uint64_t fp64_div (uint64_t a, uint64_t b, int mode, int *flags)
 
static void set_fpscr0 (FPSCR &fpscr, int flags)
 
static uint16_t fp16_scale (uint16_t a, int16_t b, int mode, int *flags)
 
static uint32_t fp32_scale (uint32_t a, int32_t b, int mode, int *flags)
 
static uint64_t fp64_scale (uint64_t a, int64_t b, int mode, int *flags)
 
static uint16_t fp16_sqrt (uint16_t a, int mode, int *flags)
 
static uint32_t fp32_sqrt (uint32_t a, int mode, int *flags)
 
static uint64_t fp64_sqrt (uint64_t a, int mode, int *flags)
 
static int modeConv (FPSCR fpscr)
 
static void set_fpscr (FPSCR &fpscr, int flags)
 
template<>
bool fplibCompareEQ (uint16_t a, uint16_t b, FPSCR &fpscr)
 
template<>
bool fplibCompareGE (uint16_t a, uint16_t b, FPSCR &fpscr)
 
template<>
bool fplibCompareGT (uint16_t a, uint16_t b, FPSCR &fpscr)
 
template<>
bool fplibCompareUN (uint16_t a, uint16_t b, FPSCR &fpscr)
 
template<>
bool fplibCompareEQ (uint32_t a, uint32_t b, FPSCR &fpscr)
 
template<>
bool fplibCompareGE (uint32_t a, uint32_t b, FPSCR &fpscr)
 
template<>
bool fplibCompareGT (uint32_t a, uint32_t b, FPSCR &fpscr)
 
template<>
bool fplibCompareUN (uint32_t a, uint32_t b, FPSCR &fpscr)
 
template<>
bool fplibCompareEQ (uint64_t a, uint64_t b, FPSCR &fpscr)
 
template<>
bool fplibCompareGE (uint64_t a, uint64_t b, FPSCR &fpscr)
 
template<>
bool fplibCompareGT (uint64_t a, uint64_t b, FPSCR &fpscr)
 
template<>
bool fplibCompareUN (uint64_t a, uint64_t b, FPSCR &fpscr)
 
template<>
uint16_t fplibAbs (uint16_t op)
 
template<>
uint32_t fplibAbs (uint32_t op)
 
template<>
uint64_t fplibAbs (uint64_t op)
 
template<>
uint16_t fplibAdd (uint16_t op1, uint16_t op2, FPSCR &fpscr)
 
template<>
uint32_t fplibAdd (uint32_t op1, uint32_t op2, FPSCR &fpscr)
 
template<>
uint64_t fplibAdd (uint64_t op1, uint64_t op2, FPSCR &fpscr)
 
template<>
int fplibCompare (uint16_t op1, uint16_t op2, bool signal_nans, FPSCR &fpscr)
 
template<>
int fplibCompare (uint32_t op1, uint32_t op2, bool signal_nans, FPSCR &fpscr)
 
template<>
int fplibCompare (uint64_t op1, uint64_t op2, bool signal_nans, FPSCR &fpscr)
 
static uint16_t fp16_FPConvertNaN_32 (uint32_t op)
 
static uint16_t fp16_FPConvertNaN_64 (uint64_t op)
 
static uint32_t fp32_FPConvertNaN_16 (uint16_t op)
 
static uint32_t fp32_FPConvertNaN_64 (uint64_t op)
 
static uint64_t fp64_FPConvertNaN_16 (uint16_t op)
 
static uint64_t fp64_FPConvertNaN_32 (uint32_t op)
 
static uint16_t fp16_FPOnePointFive (int sgn)
 
static uint32_t fp32_FPOnePointFive (int sgn)
 
static uint64_t fp64_FPOnePointFive (int sgn)
 
static uint16_t fp16_FPThree (int sgn)
 
static uint32_t fp32_FPThree (int sgn)
 
static uint64_t fp64_FPThree (int sgn)
 
static uint16_t fp16_FPTwo (int sgn)
 
static uint32_t fp32_FPTwo (int sgn)
 
static uint64_t fp64_FPTwo (int sgn)
 
template<>
uint16_t fplibConvert (uint32_t op, FPRounding rounding, FPSCR &fpscr)
 
template<>
uint16_t fplibConvert (uint64_t op, FPRounding rounding, FPSCR &fpscr)
 
template<>
uint32_t fplibConvert (uint16_t op, FPRounding rounding, FPSCR &fpscr)
 
template<>
uint16_t fplibMulAdd (uint16_t addend, uint16_t op1, uint16_t op2, FPSCR &fpscr)
 
template<>
uint32_t fplibMulAdd (uint32_t addend, uint32_t op1, uint32_t op2, FPSCR &fpscr)
 
template<>
uint64_t fplibMulAdd (uint64_t addend, uint64_t op1, uint64_t op2, FPSCR &fpscr)
 
template<>
uint16_t fplibDiv (uint16_t op1, uint16_t op2, FPSCR &fpscr)
 
template<>
uint32_t fplibDiv (uint32_t op1, uint32_t op2, FPSCR &fpscr)
 
template<>
uint64_t fplibDiv (uint64_t op1, uint64_t op2, FPSCR &fpscr)
 
template<>
uint16_t fplibExpA (uint16_t op)
 
template<>
uint32_t fplibExpA (uint32_t op)
 
template<>
uint64_t fplibExpA (uint64_t op)
 
static uint16_t fp16_repack (int sgn, int exp, uint16_t mnt)
 
static uint32_t fp32_repack (int sgn, int exp, uint32_t mnt)
 
static uint64_t fp64_repack (int sgn, int exp, uint64_t mnt)
 
static void fp16_minmaxnum (uint16_t *op1, uint16_t *op2, int sgn)
 
static void fp32_minmaxnum (uint32_t *op1, uint32_t *op2, int sgn)
 
static void fp64_minmaxnum (uint64_t *op1, uint64_t *op2, int sgn)
 
template<>
uint16_t fplibMax (uint16_t op1, uint16_t op2, FPSCR &fpscr)
 
template<>
uint32_t fplibMax (uint32_t op1, uint32_t op2, FPSCR &fpscr)
 
template<>
uint64_t fplibMax (uint64_t op1, uint64_t op2, FPSCR &fpscr)
 
template<>
uint16_t fplibMaxNum (uint16_t op1, uint16_t op2, FPSCR &fpscr)
 
template<>
uint32_t fplibMaxNum (uint32_t op1, uint32_t op2, FPSCR &fpscr)
 
template<>
uint64_t fplibMaxNum (uint64_t op1, uint64_t op2, FPSCR &fpscr)
 
template<>
uint16_t fplibMin (uint16_t op1, uint16_t op2, FPSCR &fpscr)
 
template<>
uint32_t fplibMin (uint32_t op1, uint32_t op2, FPSCR &fpscr)
 
template<>
uint64_t fplibMin (uint64_t op1, uint64_t op2, FPSCR &fpscr)
 
template<>
uint16_t fplibMinNum (uint16_t op1, uint16_t op2, FPSCR &fpscr)
 
template<>
uint32_t fplibMinNum (uint32_t op1, uint32_t op2, FPSCR &fpscr)
 
template<>
uint64_t fplibMinNum (uint64_t op1, uint64_t op2, FPSCR &fpscr)
 
template<>
uint16_t fplibMul (uint16_t op1, uint16_t op2, FPSCR &fpscr)
 
template<>
uint32_t fplibMul (uint32_t op1, uint32_t op2, FPSCR &fpscr)
 
template<>
uint64_t fplibMul (uint64_t op1, uint64_t op2, FPSCR &fpscr)
 
template<>
uint16_t fplibMulX (uint16_t op1, uint16_t op2, FPSCR &fpscr)
 
template<>
uint32_t fplibMulX (uint32_t op1, uint32_t op2, FPSCR &fpscr)
 
template<>
uint64_t fplibMulX (uint64_t op1, uint64_t op2, FPSCR &fpscr)
 
template<>
uint16_t fplibNeg (uint16_t op)
 
template<>
uint32_t fplibNeg (uint32_t op)
 
template<>
uint64_t fplibNeg (uint64_t op)
 
template<>
uint16_t fplibRSqrtEstimate (uint16_t op, FPSCR &fpscr)
 
template<>
uint32_t fplibRSqrtEstimate (uint32_t op, FPSCR &fpscr)
 
template<>
uint64_t fplibRSqrtEstimate (uint64_t op, FPSCR &fpscr)
 
template<>
uint16_t fplibRSqrtStepFused (uint16_t op1, uint16_t op2, FPSCR &fpscr)
 
template<>
uint32_t fplibRSqrtStepFused (uint32_t op1, uint32_t op2, FPSCR &fpscr)
 
template<>
uint64_t fplibRSqrtStepFused (uint64_t op1, uint64_t op2, FPSCR &fpscr)
 
template<>
uint16_t fplibRecipEstimate (uint16_t op, FPSCR &fpscr)
 
template<>
uint32_t fplibRecipEstimate (uint32_t op, FPSCR &fpscr)
 
template<>
uint64_t fplibRecipEstimate (uint64_t op, FPSCR &fpscr)
 
template<>
uint16_t fplibRecipStepFused (uint16_t op1, uint16_t op2, FPSCR &fpscr)
 
template<>
uint32_t fplibRecipStepFused (uint32_t op1, uint32_t op2, FPSCR &fpscr)
 
template<>
uint64_t fplibRecipStepFused (uint64_t op1, uint64_t op2, FPSCR &fpscr)
 
template<>
uint16_t fplibRecpX (uint16_t op, FPSCR &fpscr)
 
template<>
uint32_t fplibRecpX (uint32_t op, FPSCR &fpscr)
 
template<>
uint64_t fplibRecpX (uint64_t op, FPSCR &fpscr)
 
template<>
uint16_t fplibRoundInt (uint16_t op, FPRounding rounding, bool exact, FPSCR &fpscr)
 
template<>
uint32_t fplibRoundInt (uint32_t op, FPRounding rounding, bool exact, FPSCR &fpscr)
 
template<>
uint64_t fplibRoundInt (uint64_t op, FPRounding rounding, bool exact, FPSCR &fpscr)
 
template<>
uint16_t fplibScale (uint16_t op1, uint16_t op2, FPSCR &fpscr)
 
template<>
uint32_t fplibScale (uint32_t op1, uint32_t op2, FPSCR &fpscr)
 
template<>
uint64_t fplibScale (uint64_t op1, uint64_t op2, FPSCR &fpscr)
 
template<>
uint16_t fplibSqrt (uint16_t op, FPSCR &fpscr)
 
template<>
uint32_t fplibSqrt (uint32_t op, FPSCR &fpscr)
 
template<>
uint64_t fplibSqrt (uint64_t op, FPSCR &fpscr)
 
template<>
uint16_t fplibSub (uint16_t op1, uint16_t op2, FPSCR &fpscr)
 
template<>
uint32_t fplibSub (uint32_t op1, uint32_t op2, FPSCR &fpscr)
 
template<>
uint64_t fplibSub (uint64_t op1, uint64_t op2, FPSCR &fpscr)
 
template<>
uint16_t fplibTrigMulAdd (uint8_t coeff_index, uint16_t op1, uint16_t op2, FPSCR &fpscr)
 
template<>
uint32_t fplibTrigMulAdd (uint8_t coeff_index, uint32_t op1, uint32_t op2, FPSCR &fpscr)
 
template<>
uint64_t fplibTrigMulAdd (uint8_t coeff_index, uint64_t op1, uint64_t op2, FPSCR &fpscr)
 
template<>
uint16_t fplibTrigSMul (uint16_t op1, uint16_t op2, FPSCR &fpscr)
 
template<>
uint32_t fplibTrigSMul (uint32_t op1, uint32_t op2, FPSCR &fpscr)
 
template<>
uint64_t fplibTrigSMul (uint64_t op1, uint64_t op2, FPSCR &fpscr)
 
template<>
uint16_t fplibTrigSSel (uint16_t op1, uint16_t op2, FPSCR &fpscr)
 
template<>
uint32_t fplibTrigSSel (uint32_t op1, uint32_t op2, FPSCR &fpscr)
 
template<>
uint64_t fplibTrigSSel (uint64_t op1, uint64_t op2, FPSCR &fpscr)
 
static uint64_t FPToFixed_64 (int sgn, int exp, uint64_t mnt, bool u, FPRounding rounding, int *flags)
 
static uint32_t FPToFixed_32 (int sgn, int exp, uint64_t mnt, bool u, FPRounding rounding, int *flags)
 
static uint16_t FPToFixed_16 (int sgn, int exp, uint64_t mnt, bool u, FPRounding rounding, int *flags)
 
template<>
uint16_t fplibFPToFixed (uint16_t op, int fbits, bool u, FPRounding rounding, FPSCR &fpscr)
 
template<>
uint32_t fplibFPToFixed (uint32_t op, int fbits, bool u, FPRounding rounding, FPSCR &fpscr)
 
template<>
uint32_t fplibFPToFixed (uint64_t op, int fbits, bool u, FPRounding rounding, FPSCR &fpscr)
 
uint32_t fplibFPToFixedJS (uint64_t op, FPSCR &fpscr, bool Is64, uint8_t &nz)
 Floating-point JS convert to a signed integer, with rounding to zero. More...
 
static uint16_t fp16_cvtf (uint64_t a, int fbits, int u, int mode, int *flags)
 
static uint32_t fp32_cvtf (uint64_t a, int fbits, int u, int mode, int *flags)
 
static uint64_t fp64_cvtf (uint64_t a, int fbits, int u, int mode, int *flags)
 
template<>
uint16_t fplibFixedToFP (uint64_t op, int fbits, bool u, FPRounding rounding, FPSCR &fpscr)
 Floating-point convert from fixed-point. More...
 
template<>
uint16_t fplibInfinity (int sgn)
 Floating-point value for +/- infinity. More...
 
template<>
uint16_t fplibDefaultNaN ()
 Foating-point value for default NaN. More...
 
static FPRounding FPCRRounding (FPSCR &fpscr)
 
template<class T >
T fplibAbs (T op)
 Floating-point absolute value. More...
 
template<class T >
T fplibAdd (T op1, T op2, FPSCR &fpscr)
 Floating-point add. More...
 
template<class T >
int fplibCompare (T op1, T op2, bool signal_nans, FPSCR &fpscr)
 Floating-point compare (quiet and signaling). More...
 
template<class T >
bool fplibCompareEQ (T op1, T op2, FPSCR &fpscr)
 Floating-point compare equal. More...
 
template<class T >
bool fplibCompareGE (T op1, T op2, FPSCR &fpscr)
 Floating-point compare greater than or equal. More...
 
template<class T >
bool fplibCompareGT (T op1, T op2, FPSCR &fpscr)
 Floating-point compare greater than. More...
 
template<class T >
bool fplibCompareUN (T op1, T op2, FPSCR &fpscr)
 Floating-point compare unordered. More...
 
template<class T1 , class T2 >
T2 fplibConvert (T1 op, FPRounding rounding, FPSCR &fpscr)
 Floating-point convert precision. More...
 
template<class T >
T fplibDiv (T op1, T op2, FPSCR &fpscr)
 Floating-point division. More...
 
template<class T >
T fplibExpA (T op)
 Floating-point exponential accelerator. More...
 
template<class T >
T fplibMax (T op1, T op2, FPSCR &fpscr)
 Floating-point maximum. More...
 
template<class T >
T fplibMaxNum (T op1, T op2, FPSCR &fpscr)
 Floating-point maximum number. More...
 
template<class T >
T fplibMin (T op1, T op2, FPSCR &fpscr)
 Floating-point minimum. More...
 
template<class T >
T fplibMinNum (T op1, T op2, FPSCR &fpscr)
 Floating-point minimum number. More...
 
template<class T >
T fplibMul (T op1, T op2, FPSCR &fpscr)
 Floating-point multiply. More...
 
template<class T >
T fplibMulAdd (T addend, T op1, T op2, FPSCR &fpscr)
 Floating-point multiply-add. More...
 
template<class T >
T fplibMulX (T op1, T op2, FPSCR &fpscr)
 Floating-point multiply extended. More...
 
template<class T >
T fplibNeg (T op)
 Floating-point negate. More...
 
template<class T >
T fplibRSqrtEstimate (T op, FPSCR &fpscr)
 Floating-point reciprocal square root estimate. More...
 
template<class T >
T fplibRSqrtStepFused (T op1, T op2, FPSCR &fpscr)
 Floating-point reciprocal square root step. More...
 
template<class T >
T fplibRecipEstimate (T op, FPSCR &fpscr)
 Floating-point reciprocal estimate. More...
 
template<class T >
T fplibRecipStepFused (T op1, T op2, FPSCR &fpscr)
 Floating-point reciprocal step. More...
 
template<class T >
T fplibRecpX (T op, FPSCR &fpscr)
 Floating-point reciprocal exponent. More...
 
template<class T >
T fplibRoundInt (T op, FPRounding rounding, bool exact, FPSCR &fpscr)
 Floating-point convert to integer. More...
 
template<class T >
T fplibScale (T op1, T op2, FPSCR &fpscr)
 Floating-point adjust exponent. More...
 
template<class T >
T fplibSqrt (T op, FPSCR &fpscr)
 Floating-point square root. More...
 
template<class T >
T fplibSub (T op1, T op2, FPSCR &fpscr)
 Floating-point subtract. More...
 
template<class T >
T fplibTrigMulAdd (uint8_t coeff_index, T op1, T op2, FPSCR &fpscr)
 Floating-point trigonometric multiply-add coefficient. More...
 
template<class T >
T fplibTrigSMul (T op1, T op2, FPSCR &fpscr)
 Floating-point trigonometric starting value. More...
 
template<class T >
T fplibTrigSSel (T op1, T op2, FPSCR &fpscr)
 Floating-point trigonometric select coefficient. More...
 
template<class T1 , class T2 >
T2 fplibFPToFixed (T1 op, int fbits, bool u, FPRounding rounding, FPSCR &fpscr)
 Floating-point convert to fixed-point. More...
 
static unsigned int number_of_ones (int32_t val)
 
void writeVecElem (VReg *dest, XReg src, int index, int eSize)
 Write a single NEON vector element leaving the others untouched. More...
 
XReg readVecElem (VReg src, int index, int eSize)
 Read a single NEON vector element. More...
 
static uint32_t rotate_imm (uint32_t immValue, uint32_t rotateValue)
 
static uint32_t modified_imm (uint8_t ctrlImm, uint8_t dataImm)
 
static uint64_t simd_modified_imm (bool op, uint8_t cmode, uint8_t data, bool &immValid, bool isAarch64=false)
 
static uint64_t vfp_modified_imm (uint8_t data, FpDataType dtype)
 
static FpDataType decode_fp_data_type (uint8_t encoding)
 
static uint8_t getRestoredITBits (ThreadContext *tc, CPSR spsr)
 
static bool illegalExceptionReturn (ThreadContext *tc, CPSR cpsr, CPSR spsr)
 
const char * svePredTypeToStr (SvePredType pt)
 Returns the specifier for the predication type pt as a string. More...
 
std::string sveDisasmPredCountImm (uint8_t imm)
 Returns the symbolic name associated with pattern imm for PTRUE(S) instructions. More...
 
unsigned int sveDecodePredCount (uint8_t imm, unsigned int num_elems)
 Returns the actual number of elements active for PTRUE(S) instructions. More...
 
uint64_t sveExpandFpImmAddSub (uint8_t imm, uint8_t size)
 Expand 1-bit floating-point immediate to 0.5 or 1.0 (FADD, FSUB, FSUBR). More...
 
uint64_t sveExpandFpImmMaxMin (uint8_t imm, uint8_t size)
 Expand 1-bit floating-point immediate to 0.0 or 1.0 (FMAX, FMAXNM, FMIN, FMINNM). More...
 
uint64_t sveExpandFpImmMul (uint8_t imm, uint8_t size)
 Expand 1-bit floating-point immediate to 0.5 or 2.0 (FMUL). More...
 
VfpSavedState prepFpState (uint32_t rMode)
 
void finishVfp (FPSCR &fpscr, VfpSavedState state, bool flush, FPSCR mask)
 
template<class fpType >
fpType fixDest (bool flush, bool defaultNan, fpType val, fpType op1)
 
template float fixDest< float > (bool flush, bool defaultNan, float val, float op1)
 
template double fixDest< double > (bool flush, bool defaultNan, double val, double op1)
 
template<class fpType >
fpType fixDest (bool flush, bool defaultNan, fpType val, fpType op1, fpType op2)
 
template float fixDest< float > (bool flush, bool defaultNan, float val, float op1, float op2)
 
template double fixDest< double > (bool flush, bool defaultNan, double val, double op1, double op2)
 
template<class fpType >
fpType fixDivDest (bool flush, bool defaultNan, fpType val, fpType op1, fpType op2)
 
template float fixDivDest< float > (bool flush, bool defaultNan, float val, float op1, float op2)
 
template double fixDivDest< double > (bool flush, bool defaultNan, double val, double op1, double op2)
 
float fixFpDFpSDest (FPSCR fpscr, double val)
 
double fixFpSFpDDest (FPSCR fpscr, float val)
 
static uint16_t vcvtFpFpH (FPSCR &fpscr, bool flush, bool defaultNan, uint32_t rMode, bool ahp, uint64_t opBits, bool isDouble)
 
uint16_t vcvtFpSFpH (FPSCR &fpscr, bool flush, bool defaultNan, uint32_t rMode, bool ahp, float op)
 
uint16_t vcvtFpDFpH (FPSCR &fpscr, bool flush, bool defaultNan, uint32_t rMode, bool ahp, double op)
 
static uint64_t vcvtFpHFp (FPSCR &fpscr, bool defaultNan, bool ahp, uint16_t op, bool isDouble)
 
double vcvtFpHFpD (FPSCR &fpscr, bool defaultNan, bool ahp, uint16_t op)
 
float vcvtFpHFpS (FPSCR &fpscr, bool defaultNan, bool ahp, uint16_t op)
 
float vfpUFixedToFpS (bool flush, bool defaultNan, uint64_t val, uint8_t width, uint8_t imm)
 
float vfpSFixedToFpS (bool flush, bool defaultNan, int64_t val, uint8_t width, uint8_t imm)
 
double vfpUFixedToFpD (bool flush, bool defaultNan, uint64_t val, uint8_t width, uint8_t imm)
 
double vfpSFixedToFpD (bool flush, bool defaultNan, int64_t val, uint8_t width, uint8_t imm)
 
static double recipSqrtEstimate (double a)
 
float fprSqrtEstimate (FPSCR &fpscr, float op)
 
uint32_t unsignedRSqrtEstimate (uint32_t op)
 
static double recipEstimate (double a)
 
float fpRecipEstimate (FPSCR &fpscr, float op)
 
uint32_t unsignedRecipEstimate (uint32_t op)
 
FPSCR fpStandardFPSCRValue (const FPSCR &fpscr)
 
template<class T >
static void setVfpMicroFlags (VfpMicroMode mode, T &flags)
 
static float bitsToFp (uint64_t, float)
 
static double bitsToFp (uint64_t, double)
 
static uint32_t fpToBits (float)
 
static uint64_t fpToBits (double)
 
template<class fpType >
static bool flushToZero (fpType &op)
 
template<class fpType >
static bool flushToZero (fpType &op1, fpType &op2)
 
template<class fpType >
static void vfpFlushToZero (FPSCR &fpscr, fpType &op)
 
template<class fpType >
static void vfpFlushToZero (FPSCR &fpscr, fpType &op1, fpType &op2)
 
template<class fpType >
static bool isSnan (fpType val)
 
template<class fpType >
fpType fixDest (FPSCR fpscr, fpType val, fpType op1)
 
template<class fpType >
fpType fixDest (FPSCR fpscr, fpType val, fpType op1, fpType op2)
 
template<class fpType >
fpType fixDivDest (FPSCR fpscr, fpType val, fpType op1, fpType op2)
 
static double makeDouble (uint32_t low, uint32_t high)
 
static uint32_t lowFromDouble (double val)
 
static uint32_t highFromDouble (double val)
 
static void setFPExceptions (int exceptions)
 
template<typename T >
uint64_t vfpFpToFixed (T val, bool isSigned, uint8_t width, uint8_t imm, bool useRmode=true, VfpRoundingMode roundMode=VfpRoundZero, bool aarch64=false)
 
template<typename T >
static T fpAdd (T a, T b)
 
template<typename T >
static T fpSub (T a, T b)
 
static float fpAddS (float a, float b)
 
static double fpAddD (double a, double b)
 
static float fpSubS (float a, float b)
 
static double fpSubD (double a, double b)
 
static float fpDivS (float a, float b)
 
static double fpDivD (double a, double b)
 
template<typename T >
static T fpDiv (T a, T b)
 
template<typename T >
static T fpMulX (T a, T b)
 
template<typename T >
static T fpMul (T a, T b)
 
static float fpMulS (float a, float b)
 
static double fpMulD (double a, double b)
 
template<typename T >
static T fpMulAdd (T op1, T op2, T addend)
 
template<typename T >
static T fpRIntX (T a, FPSCR &fpscr)
 
template<typename T >
static T fpMaxNum (T a, T b)
 
template<typename T >
static T fpMax (T a, T b)
 
template<typename T >
static T fpMinNum (T a, T b)
 
template<typename T >
static T fpMin (T a, T b)
 
template<typename T >
static T fpRSqrts (T a, T b)
 
template<typename T >
static T fpRecps (T a, T b)
 
static float fpRSqrtsS (float a, float b)
 
static float fpRecpsS (float a, float b)
 
template<typename T >
static T roundNEven (T a)
 
template<class XC >
static void lockedSnoopHandler (ThreadContext *tc, XC *xc, PacketPtr pkt, Addr cacheBlockMask)
 
template<class XC >
static bool lockedWriteHandler (ThreadContext *tc, XC *xc, const RequestPtr &req, Addr cacheBlockMask)
 
static SyscallReturn unameFunc32 (SyscallDesc *desc, ThreadContext *tc, VPtr< Linux::utsname > name)
 Target uname() handler. More...
 
static SyscallReturn unameFunc64 (SyscallDesc *desc, ThreadContext *tc, VPtr< Linux::utsname > name)
 Target uname() handler. More...
 
static SyscallReturn setTLSFunc32 (SyscallDesc *desc, ThreadContext *tc, uint32_t tlsPtr)
 Target set_tls() handler. More...
 
static SyscallReturn setTLSFunc64 (SyscallDesc *desc, ThreadContext *tc, uint32_t tlsPtr)
 
template<typename T >
MMU * getMMUPtr (T *tc)
 
const PageTableOps * getPageTableOps (GrainSize trans_granule)
 
bool upperAndLowerRange (ThreadContext *tc, ExceptionLevel el)
 
bool calculateTBI (ThreadContext *tc, ExceptionLevel el, uint64_t ptr, bool data)
 
int calculateBottomPACBit (ThreadContext *tc, ExceptionLevel el, bool top_bit)
 
Fault trapPACUse (ThreadContext *tc, ExceptionLevel el)
 
uint64_t addPAC (ThreadContext *tc, ExceptionLevel el, uint64_t ptr, uint64_t modifier, uint64_t k1, uint64_t k0, bool data)
 
uint64_t auth (ThreadContext *tc, ExceptionLevel el, uint64_t ptr, uint64_t modifier, uint64_t k1, uint64_t K0, bool data, uint8_t errorcode)
 
Fault authDA (ThreadContext *tc, uint64_t X, uint64_t Y, uint64_t *out)
 
Fault authDB (ThreadContext *tc, uint64_t X, uint64_t Y, uint64_t *out)
 
Fault authIA (ThreadContext *tc, uint64_t X, uint64_t Y, uint64_t *out)
 
Fault authIB (ThreadContext *tc, uint64_t X, uint64_t Y, uint64_t *out)
 
Fault addPACDA (ThreadContext *tc, uint64_t X, uint64_t Y, uint64_t *out)
 
Fault addPACDB (ThreadContext *tc, uint64_t X, uint64_t Y, uint64_t *out)
 
Fault addPACGA (ThreadContext *tc, uint64_t X, uint64_t Y, uint64_t *out)
 
Fault addPACIA (ThreadContext *tc, uint64_t X, uint64_t Y, uint64_t *out)
 
Fault addPACIB (ThreadContext *tc, uint64_t X, uint64_t Y, uint64_t *out)
 
void stripPAC (ThreadContext *tc, uint64_t A, bool data, uint64_t *out)
 
 BitUnion8 (ITSTATE) Bitfield< 7
 
 BitUnion32 (PackedIntReg) Bitfield< 31
 
 EndBitUnion (PackedIntReg) namespace int_reg
 
static const RegId & flattenIntRegModeIndex (int reg)
 
static RegIndex makeSP (RegIndex reg)
 
static bool couldBeSP (RegIndex reg)
 
static bool isSP (RegIndex reg)
 
static bool couldBeZero (RegIndex reg)
 
static bool isZero (RegIndex reg)
 
static RegIndex makeZero (RegIndex reg)
 
template<typename ElemType >
MatTile< ElemType > getTile (MatRegContainer &reg, uint8_t tile_idx)
 
template<typename ElemType >
MatTileRow< ElemType > getTileHSlice (MatRegContainer &reg, uint8_t tile_idx, uint8_t row_idx)
 
template<typename ElemType >
MatTileCol< ElemType > getTileVSlice (MatRegContainer &reg, uint8_t tile_idx, uint8_t col_idx)
 
template<typename ElemType >
MatRow< ElemType > getHSlice (MatRegContainer &reg, uint8_t row_idx)
 
template<typename ElemType >
MatCol< ElemType > getVSlice (MatRegContainer &reg, uint8_t col_idx)
 
MiscRegIndex decodeCP14Reg (unsigned crn, unsigned opc1, unsigned crm, unsigned opc2)
 
MiscRegIndex decodeCP15Reg (unsigned crn, unsigned opc1, unsigned crm, unsigned opc2)
 
MiscRegIndex decodeCP15Reg64 (unsigned crm, unsigned opc1)
 
std::tuple< bool, bool > canReadCoprocReg (MiscRegIndex reg, SCR scr, CPSR cpsr, ThreadContext *tc)
 Check for permission to read coprocessor registers. More...
 
std::tuple< bool, bool > canWriteCoprocReg (MiscRegIndex reg, SCR scr, CPSR cpsr, ThreadContext *tc)
 Check for permission to write coprocessor registers. More...
 
bool AArch32isUndefinedGenericTimer (MiscRegIndex reg, ThreadContext *tc)
 
int snsBankedIndex (MiscRegIndex reg, ThreadContext *tc)
 
int snsBankedIndex (MiscRegIndex reg, ThreadContext *tc, bool ns)
 
int snsBankedIndex64 (MiscRegIndex reg, ThreadContext *tc)
 
void preUnflattenMiscReg ()
 
int unflattenMiscReg (int reg)
 
Fault checkFaultAccessAArch64SysReg (MiscRegIndex reg, CPSR cpsr, ThreadContext *tc, const MiscRegOp64 &inst)
 
MiscRegIndex decodeAArch64SysReg (unsigned op0, unsigned op1, unsigned crn, unsigned crm, unsigned op2)
 
MiscRegIndex decodeAArch64SysReg (const MiscRegNum64 &sys_reg)
 
MiscRegNum64 encodeAArch64SysReg (MiscRegIndex misc_reg)
 
static Fault defaultFaultE2H_EL2 (const MiscRegLUTEntry &entry, ThreadContext *tc, const MiscRegOp64 &inst)
 
static Fault defaultFaultE2H_EL3 (const MiscRegLUTEntry &entry, ThreadContext *tc, const MiscRegOp64 &inst)
 
static CPSR resetCPSR (ArmSystem *system)
 
bool aarch64SysRegReadOnly (MiscRegIndex miscReg)
 
 BitUnion32 (CPSR) Bitfield< 31
 
 EndBitUnion (CPSR) BitUnion32(ISAR5) Bitfield< 31
 
 EndBitUnion (ISAR5) BitUnion32(ISAR6) Bitfield< 31
 
 EndBitUnion (ISAR6) BitUnion64(AA64DFR0) Bitfield< 43
 
 EndBitUnion (AA64DFR0) BitUnion64(AA64ISAR0) Bitfield< 63
 
 EndBitUnion (AA64ISAR0) BitUnion64(AA64ISAR1) Bitfield< 55
 
 EndBitUnion (AA64ISAR1) BitUnion64(AA64MMFR0) Bitfield< 63
 
 EndBitUnion (AA64MMFR0) BitUnion64(AA64MMFR1) Bitfield< 43
 
 EndBitUnion (AA64MMFR1) BitUnion64(AA64MMFR2) Bitfield< 63
 
 EndBitUnion (AA64MMFR2) BitUnion64(AA64PFR0) Bitfield< 63
 
 EndBitUnion (AA64PFR0) BitUnion64(AA64ZFR0) Bitfield< 59
 
 EndBitUnion (AA64ZFR0) BitUnion64(AA64SMFR0) Bitfield< 63 > fa64
 
 EndBitUnion (AA64SMFR0) BitUnion32(HDCR) Bitfield< 27 > tdcc
 
 EndBitUnion (HDCR) BitUnion32(HCPTR) Bitfield< 31 > tcpac
 
 EndBitUnion (HCPTR) BitUnion32(HSTR) Bitfield< 17 > tjdbx
 
 EndBitUnion (HSTR) BitUnion64(HCR) Bitfield< 55 > ttlbos
 
 EndBitUnion (HCR) BitUnion32(NSACR) Bitfield< 20 > nstrcdis
 
 EndBitUnion (NSACR) BitUnion64(SCR) Bitfield< 40 > trndr
 
 EndBitUnion (SCR) BitUnion64(SCTLR) Bitfield< 31 > enia
 
 EndBitUnion (SCTLR) BitUnion32(CPACR) Bitfield< 1
 
 EndBitUnion (CPACR) BitUnion32(FSR) Bitfield< 3
 
 EndBitUnion (FSR) BitUnion32(FPSCR) Bitfield< 0 > ioc
 
 EndBitUnion (FPSCR) BitUnion32(FPEXC) Bitfield< 31 > ex
 
 EndBitUnion (FPEXC) BitUnion32(MVFR0) Bitfield< 3
 
 EndBitUnion (MVFR0) BitUnion32(MVFR1) Bitfield< 3
 
 EndBitUnion (MVFR1) BitUnion64(TTBCR) Bitfield< 2
 
 EndBitUnion (TTBCR) BitUnion64(TCR) Bitfield< 5
 
 EndBitUnion (TCR) BitUnion32(HTCR) Bitfield< 2
 
 EndBitUnion (HTCR) BitUnion32(VTCR_t) Bitfield< 3
 
 EndBitUnion (VTCR_t) BitUnion32(PRRR) Bitfield< 1
 
 EndBitUnion (PRRR) BitUnion32(NMRR) Bitfield< 1
 
 EndBitUnion (NMRR) BitUnion32(CONTEXTIDR) Bitfield< 7
 
 EndBitUnion (CONTEXTIDR) BitUnion32(L2CTLR) Bitfield< 2
 
 EndBitUnion (L2CTLR) BitUnion32(CTR) Bitfield< 3
 
 EndBitUnion (CTR) BitUnion32(PMSELR) Bitfield< 4
 
 EndBitUnion (PMSELR) BitUnion64(PAR) Bitfield< 63
 
 EndBitUnion (PAR) BitUnion32(ESR) Bitfield< 31
 
 SubBitUnion (cond_iss, 24, 0) Bitfield< 24 > cv
 
 EndSubBitUnion (cond_iss) SubBitUnion(data_abort_iss
 
 EndSubBitUnion (data_abort_iss) SubBitUnion(instruction_abort_iss
 
 EndSubBitUnion (instruction_abort_iss) SubBitUnion(software_step_iss
 
 EndSubBitUnion (software_step_iss) SubBitUnion(watchpoint_iss
 
 EndSubBitUnion (watchpoint_iss) EndBitUnion(ESR) BitUnion32(CPTR) Bitfield< 31 > tcpac
 
 EndBitUnion (CPTR) BitUnion64(ZCR) Bitfield< 3
 
 EndBitUnion (ZCR) BitUnion64(SMCR) Bitfield< 63
 
 EndBitUnion (SMCR) BitUnion64(SVCR) Bitfield< 63
 
 EndBitUnion (SVCR) BitUnion64(SMIDR) Bitfield< 63
 
 EndBitUnion (SMIDR) BitUnion64(SMPRI) Bitfield< 63
 
 EndBitUnion (SMPRI) BitUnion32(OSL) Bitfield< 64
 
 EndBitUnion (OSL) BitUnion64(DBGBCR) Bitfield< 63
 
 EndBitUnion (DBGBCR) BitUnion64(DBGWCR) Bitfield< 63
 
 EndBitUnion (DBGWCR) BitUnion32(DBGDS32) Bitfield< 31 > tfo
 
 EndBitUnion (DBGDS32) BitUnion32(DBGVCR) Bitfield< 31 > nsf
 
 EndBitUnion (DBGVCR) BitUnion32(DEVID) Bitfield< 31
 
 BitUnion64 (ExtMachInst) Bitfield< 63
 
 SubBitUnion (puswl, 24, 20) Bitfield< 24 > prepost
 
 EndSubBitUnion (puswl) Bitfield< 24
 
 EndBitUnion (ExtMachInst) BitUnion32(Affinity) Bitfield< 31
 
 EndBitUnion (Affinity) enum ArmShiftType
 
 BitUnion8 (OperatingMode64) Bitfield< 0 > spX
 
 EndBitUnion (OperatingMode64) static bool inline opModeIs64(OperatingMode mode)
 
static bool opModeIsH (OperatingMode mode)
 
static bool opModeIsT (OperatingMode mode)
 
static ExceptionLevel opModeToEL (OperatingMode mode)
 
static bool unknownMode (OperatingMode mode)
 
static bool unknownMode32 (OperatingMode mode)
 
void sendEvent (ThreadContext *tc)
 Send an event (SEV) to a specific PE if there isn't already a pending event. More...
 
bool isSecure (ThreadContext *tc)
 
bool isSecureBelowEL3 (ThreadContext *tc)
 
ExceptionLevel debugTargetFrom (ThreadContext *tc, bool secure)
 
bool inAArch64 (ThreadContext *tc)
 
ExceptionLevel currEL (const ThreadContext *tc)
 Returns the current Exception Level (EL) of the provided ThreadContext. More...
 
bool longDescFormatInUse (ThreadContext *tc)
 
RegVal readMPIDR (ArmSystem *arm_sys, ThreadContext *tc)
 This helper function is either returing the value of MPIDR_EL1 (by calling getMPIDR), or it is issuing a read to VMPIDR_EL2 (as it happens in virtualized systems) More...
 
RegVal getMPIDR (ArmSystem *arm_sys, ThreadContext *tc)
 This helper function is returning the value of MPIDR_EL1. More...
 
static RegVal getAff2 (ArmSystem *arm_sys, ThreadContext *tc)
 
static RegVal getAff1 (ArmSystem *arm_sys, ThreadContext *tc)
 
static RegVal getAff0 (ArmSystem *arm_sys, ThreadContext *tc)
 
Affinity getAffinity (ArmSystem *arm_sys, ThreadContext *tc)
 Retrieves MPIDR_EL1. More...
 
bool HaveExt (ThreadContext *tc, ArmExtension ext)
 Returns true if the provided ThreadContext supports the ArmExtension passed as a second argument. More...
 
ExceptionLevel s1TranslationRegime (ThreadContext *tc, ExceptionLevel el)
 
bool IsSecureEL2Enabled (ThreadContext *tc)
 
bool EL2Enabled (ThreadContext *tc)
 
bool ELIs64 (ThreadContext *tc, ExceptionLevel el)
 
bool ELIs32 (ThreadContext *tc, ExceptionLevel el)
 
bool ELIsInHost (ThreadContext *tc, ExceptionLevel el)
 Returns true if the current exception level el is executing a Host OS or an application of a Host OS (Armv8.1 Virtualization Host Extensions). More...
 
std::pair< bool, bool > ELUsingAArch32K (ThreadContext *tc, ExceptionLevel el)
 This function checks whether selected EL provided as an argument is using the AArch32 ISA. More...
 
bool haveAArch32EL (ThreadContext *tc, ExceptionLevel el)
 
std::pair< bool, bool > ELStateUsingAArch32K (ThreadContext *tc, ExceptionLevel el, bool secure)
 
bool ELStateUsingAArch32 (ThreadContext *tc, ExceptionLevel el, bool secure)
 
bool isBigEndian64 (const ThreadContext *tc)
 
bool badMode32 (ThreadContext *tc, OperatingMode mode)
 badMode is checking if the execution mode provided as an argument is valid and implemented for AArch32 More...
 
bool badMode (ThreadContext *tc, OperatingMode mode)
 badMode is checking if the execution mode provided as an argument is valid and implemented. More...
 
int computeAddrTop (ThreadContext *tc, bool selbit, bool is_instr, TCR tcr, ExceptionLevel el)
 
Addr maskTaggedAddr (Addr addr, ThreadContext *tc, ExceptionLevel el, int topbit)
 
Addr purifyTaggedAddr (Addr addr, ThreadContext *tc, ExceptionLevel el, TCR tcr, bool isInstr)
 Removes the tag from tagged addresses if that mode is enabled. More...
 
Addr purifyTaggedAddr (Addr addr, ThreadContext *tc, ExceptionLevel el, bool is_instr)
 
Addr truncPage (Addr addr)
 
Addr roundPage (Addr addr)
 
Fault mcrMrc15Trap (const MiscRegIndex misc_reg, ExtMachInst mach_inst, ThreadContext *tc, uint32_t imm)
 
bool mcrMrc15TrapToHyp (const MiscRegIndex misc_reg, ThreadContext *tc, uint32_t iss, ExceptionClass *ec)
 
bool mcrMrc14TrapToHyp (const MiscRegIndex misc_reg, ThreadContext *tc, uint32_t iss)
 
Fault mcrrMrrc15Trap (const MiscRegIndex misc_reg, ExtMachInst mach_inst, ThreadContext *tc, uint32_t imm)
 
bool mcrrMrrc15TrapToHyp (const MiscRegIndex misc_reg, ThreadContext *tc, uint32_t iss, ExceptionClass *ec)
 
Fault AArch64AArch32SystemAccessTrap (const MiscRegIndex misc_reg, ExtMachInst mach_inst, ThreadContext *tc, uint32_t imm, ExceptionClass ec)
 
bool isAArch64AArch32SystemAccessTrapEL1 (const MiscRegIndex misc_reg, ThreadContext *tc)
 
bool isGenericTimerHypTrap (const MiscRegIndex misc_reg, ThreadContext *tc, ExceptionClass *ec)
 
bool isGenericTimerCommonEL0HypTrap (const MiscRegIndex misc_reg, ThreadContext *tc, ExceptionClass *ec)
 
bool isGenericTimerPhysHypTrap (const MiscRegIndex misc_reg, ThreadContext *tc, ExceptionClass *ec)
 
bool condGenericTimerPhysHypTrap (const MiscRegIndex misc_reg, ThreadContext *tc)
 
bool isGenericTimerSystemAccessTrapEL1 (const MiscRegIndex misc_reg, ThreadContext *tc)
 
bool condGenericTimerSystemAccessTrapEL1 (const MiscRegIndex misc_reg, ThreadContext *tc)
 
bool isAArch64AArch32SystemAccessTrapEL2 (const MiscRegIndex misc_reg, ThreadContext *tc)
 
bool isGenericTimerSystemAccessTrapEL2 (const MiscRegIndex misc_reg, ThreadContext *tc)
 
bool isGenericTimerCommonEL0SystemAccessTrapEL2 (const MiscRegIndex misc_reg, ThreadContext *tc)
 
bool isGenericTimerPhysEL0SystemAccessTrapEL2 (const MiscRegIndex misc_reg, ThreadContext *tc)
 
bool isGenericTimerPhysEL1SystemAccessTrapEL2 (const MiscRegIndex misc_reg, ThreadContext *tc)
 
bool isGenericTimerVirtSystemAccessTrapEL2 (const MiscRegIndex misc_reg, ThreadContext *tc)
 
bool condGenericTimerCommonEL0SystemAccessTrapEL2 (const MiscRegIndex misc_reg, ThreadContext *tc)
 
bool condGenericTimerCommonEL1SystemAccessTrapEL2 (const MiscRegIndex misc_reg, ThreadContext *tc)
 
bool condGenericTimerPhysEL1SystemAccessTrapEL2 (const MiscRegIndex misc_reg, ThreadContext *tc)
 
bool isGenericTimerSystemAccessTrapEL3 (const MiscRegIndex misc_reg, ThreadContext *tc)
 
bool decodeMrsMsrBankedReg (uint8_t sysM, bool r, bool &isIntReg, int &regIdx, CPSR cpsr, SCR scr, NSACR nsacr, bool checkSecurity)
 
bool isUnpriviledgeAccess (ThreadContext *tc)
 
bool SPAlignmentCheckEnabled (ThreadContext *tc)
 
int decodePhysAddrRange64 (uint8_t pa_enc)
 Returns the n. More...
 
uint8_t encodePhysAddrRange64 (int pa_size)
 Returns the encoding corresponding to the specified n. More...
 
void syncVecRegsToElems (ThreadContext *tc)
 
void syncVecElemsToRegs (ThreadContext *tc)
 
bool testPredicate (uint32_t nz, uint32_t c, uint32_t v, ConditionCode code)
 
static bool inUserMode (CPSR cpsr)
 
static bool inPrivilegedMode (CPSR cpsr)
 
ExceptionLevel currEL (CPSR cpsr)
 
static uint8_t itState (CPSR psr)
 
static uint32_t mcrMrcIssBuild (bool isRead, uint32_t crm, RegIndex rt, uint32_t crn, uint32_t opc1, uint32_t opc2)
 
static void mcrMrcIssExtract (uint32_t iss, bool &isRead, uint32_t &crm, RegIndex &rt, uint32_t &crn, uint32_t &opc1, uint32_t &opc2)
 
static uint32_t mcrrMrrcIssBuild (bool isRead, uint32_t crm, RegIndex rt, RegIndex rt2, uint32_t opc1)
 
static int decodeMrsMsrBankedIntRegIndex (uint8_t sysM, bool r)
 
ByteOrder byteOrder (const ThreadContext *tc)
 
 BitUnion64 (CNTKCTL) Bitfield< 17 > evntis
 
 EndBitUnion (CNTKCTL) BitUnion64(CNTHCTL) Bitfield< 17 > evntis
 
 EndBitUnion (CNTHCTL) BitUnion64(CNTHCTL_E2H) Bitfield< 17 > evntis
 

Variables

const uint32_t HighVecs = 0xFFFF0000
 
static SyscallDescTable< EmuFreebsd::SyscallABI32 > syscallDescs32 ({})
 
static SyscallDescTable< EmuFreebsd::SyscallABI64 > syscallDescs64
 
static const uint8_t recip_sqrt_estimate [256]
 
static SyscallTable32 syscallDescs32Low (0)
 
static SyscallTable32 syscallDescs32High (0x900000)
 
static SyscallTable64 syscallDescs64Low (0)
 
static SyscallTable64 syscallDescs64High (0x900000)
 
static SyscallDescTable< EmuLinux::SyscallABI32 > privSyscallDescs32
 
static SyscallDescTable< EmuLinux::SyscallABI64 > privSyscallDescs64
 
const Addr PageShift = 12
 
const Addr PageBytes = 1ULL << PageShift
 
const GrainSize GrainMap_tg0 []
 
const GrainSize GrainMap_tg1 []
 
const unsigned MaxPhysAddrRange = 52
 
 cond
 
Bitfield< 3, 0 > mask
 
Bitfield< 7, 2 > top6
 
Bitfield< 1, 0 > bottom2
 
static CCRegClassOps ccRegClassOps
 
constexpr RegClass ccRegClass
 
 uh1
 
Bitfield< 15, 0 > uh0
 
SignedBitfield< 31, 16 > sh1
 
SignedBitfield< 15, 0 > sh0
 
Bitfield< 31, 0 > uw
 
SignedBitfield< 31, 0 > sw
 
constexpr IntRegClassOps intRegClassOps
 
constexpr RegClass intRegClass
 
constexpr RegClass flatIntRegClass
 
constexpr size_t NumArgumentRegs = 4
 
constexpr size_t NumArgumentRegs64 = 8
 
constexpr auto & ReturnValueReg = int_reg::X0
 
constexpr auto & ReturnValueReg1 = int_reg::X1
 
constexpr auto & ArgumentReg0 = int_reg::X0
 
constexpr auto & ArgumentReg1 = int_reg::X1
 
constexpr auto & ArgumentReg2 = int_reg::X2
 
constexpr auto & FramePointerReg = int_reg::X11
 
constexpr auto & StackPointerReg = int_reg::Sp
 
constexpr auto & ReturnAddressReg = int_reg::Lr
 
constexpr auto & SyscallNumReg = ReturnValueReg
 
constexpr auto & SyscallPseudoReturnReg = ReturnValueReg
 
constexpr auto & SyscallSuccessReg = ReturnValueReg
 
const int NumMatrixRegs = 1
 
static TypedRegClassOps< ArmISA::MatRegContainer > matRegClassOps
 
constexpr RegClass matRegClass
 
int unflattenResultMiscReg [NUM_MISCREGS]
 If the reg is a child reg of a banked set, then the parent is the last banked one in the list. More...
 
std::vector< struct MiscRegLUTEntry > lookUpMiscReg (NUM_MISCREGS)
 
const char *const miscRegName []
 
static MiscRegClassOps miscRegClassOps
 
constexpr RegClass miscRegClass
 
static const uint32_t CondCodesMask = 0xF00F0000
 
static const uint32_t CpsrMaskQ = 0x08000000
 
static const uint32_t ApsrMask = CpsrMaskQ | CondCodesMask | 0x000001D0
 
static const uint32_t CpsrMask = ApsrMask | 0x00F003DF
 
static const uint32_t FpCondCodesMask = 0xF0000000
 
static const uint32_t FpscrQcMask = 0x08000000
 
static const uint32_t FpscrAhpMask = 0x04000000
 
static const uint32_t FpscrExcMask = 0x0000009F
 
 nz
 
Bitfield< 29 > c
 
Bitfield< 28 > v
 
Bitfield< 27 > q
 
Bitfield< 26, 25 > it1
 
Bitfield< 24 > j
 
Bitfield< 23 > uao
 
Bitfield< 22 > pan
 
Bitfield< 21 > ss
 
Bitfield< 20 > il
 
Bitfield< 19, 16 > ge
 
Bitfield< 15, 10 > it2
 
Bitfield< 9 > d
 
Bitfield< 9 > e
 
Bitfield< 8 > a
 
Bitfield< 7 > i
 
Bitfield< 6 > f
 
Bitfield< 8, 6 > aif
 
Bitfield< 9, 6 > daif
 
Bitfield< 5 > t
 
Bitfield< 4 > width
 
Bitfield< 3, 2 > el
 
Bitfield< 4, 0 > mode
 
Bitfield< 0 > sp
 
 vcma
 
Bitfield< 27, 24 > rdm
 
Bitfield< 19, 16 > crc32
 
Bitfield< 15, 12 > sha2
 
Bitfield< 11, 8 > sha1
 
Bitfield< 7, 4 > aes
 
Bitfield< 3, 0 > sevl
 
 clrbhb
 
Bitfield< 27, 24 > i8mm
 
Bitfield< 23, 20 > bf16
 
Bitfield< 19, 16 > specres
 
Bitfield< 15, 12 > sb
 
Bitfield< 11, 8 > fhm
 
Bitfield< 7, 4 > dp
 
Bitfield< 3, 0 > jscvt
 
 tracefilt
 
Bitfield< 39, 36 > doublelock
 
Bitfield< 35, 32 > pmsver
 
Bitfield< 31, 28 > ctx_cmps
 
Bitfield< 23, 20 > wrps
 
Bitfield< 15, 12 > brps
 
Bitfield< 11, 8 > pmuver
 
Bitfield< 7, 4 > tracever
 
Bitfield< 3, 0 > debugver
 
 rndr
 
Bitfield< 59, 56 > tlb
 
Bitfield< 55, 52 > ts
 
Bitfield< 43, 40 > sm4
 
Bitfield< 39, 36 > sm3
 
Bitfield< 35, 32 > sha3
 
Bitfield< 27, 24 > tme
 
Bitfield< 23, 20 > atomic
 
Bitfield< 35, 32 > frintts
 
Bitfield< 31, 28 > gpi
 
Bitfield< 27, 24 > gpa
 
Bitfield< 23, 20 > lrcpc
 
Bitfield< 19, 16 > fcma
 
Bitfield< 11, 8 > api
 
Bitfield< 7, 4 > apa
 
Bitfield< 3, 0 > dpb
 
 ecv
 
Bitfield< 47, 44 > exs
 
Bitfield< 43, 40 > tgran4_2
 
Bitfield< 39, 36 > tgran64_2
 
Bitfield< 35, 32 > tgran16_2
 
Bitfield< 31, 28 > tgran4
 
Bitfield< 27, 24 > tgran64
 
Bitfield< 23, 20 > tgran16
 
Bitfield< 19, 16 > bigendEL0
 
Bitfield< 15, 12 > snsmem
 
Bitfield< 11, 8 > bigend
 
Bitfield< 7, 4 > asidbits
 
Bitfield< 3, 0 > parange
 
 hcx
 
Bitfield< 31, 28 > xnx
 
Bitfield< 27, 24 > specsei
 
Bitfield< 19, 16 > lo
 
Bitfield< 15, 12 > hpds
 
Bitfield< 11, 8 > vh
 
Bitfield< 7, 4 > vmidbits
 
Bitfield< 3, 0 > hafdbs
 
 e0pd
 
Bitfield< 59, 56 > evt
 
Bitfield< 55, 52 > bbm
 
Bitfield< 51, 48 > ttl
 
Bitfield< 43, 40 > fwb
 
Bitfield< 39, 36 > ids
 
Bitfield< 35, 32 > at
 
Bitfield< 31, 28 > st
 
Bitfield< 27, 24 > nv
 
Bitfield< 23, 20 > ccidx
 
Bitfield< 19, 16 > varange
 
Bitfield< 15, 12 > iesb
 
Bitfield< 11, 8 > lsm
 
Bitfield< 3, 0 > cnp
 
 csv3
 
Bitfield< 59, 56 > csv2
 
Bitfield< 51, 48 > dit
 
Bitfield< 47, 44 > amu
 
Bitfield< 43, 40 > mpam
 
Bitfield< 39, 36 > sel2
 
Bitfield< 35, 32 > sve
 
Bitfield< 31, 28 > ras
 
Bitfield< 27, 24 > gic
 
Bitfield< 23, 20 > advsimd
 
Bitfield< 19, 16 > fp
 
Bitfield< 15, 12 > el3
 
Bitfield< 11, 8 > el2
 
Bitfield< 7, 4 > el1
 
Bitfield< 3, 0 > el0
 
 f64mm
 
Bitfield< 55, 52 > f32mm
 
Bitfield< 27, 24 > b16b16
 
Bitfield< 19, 16 > bitPerm
 
Bitfield< 3, 0 > sveVer
 
Bitfield< 59, 56 > smEver
 
Bitfield< 55, 52 > i16i64
 
Bitfield< 48 > f64f64
 
Bitfield< 39, 36 > i8i32
 
Bitfield< 35 > f16f32
 
Bitfield< 34 > b16f32
 
Bitfield< 32 > f32f32
 
Bitfield< 11 > tdra
 
Bitfield< 10 > tdosa
 
Bitfield< 9 > tda
 
Bitfield< 8 > tde
 
Bitfield< 7 > hpme
 
Bitfield< 6 > tpm
 
Bitfield< 5 > tpmcr
 
Bitfield< 4, 0 > hpmn
 
Bitfield< 20 > tta
 
Bitfield< 15 > tase
 
Bitfield< 13 > tcp13
 
Bitfield< 12 > tcp12
 
Bitfield< 11 > tcp11
 
Bitfield< 10 > tcp10
 
Bitfield< 10 > tfp
 
Bitfield< 9 > tcp9
 
Bitfield< 8 > tcp8
 
Bitfield< 8 > tz
 
Bitfield< 7 > tcp7
 
Bitfield< 6 > tcp6
 
Bitfield< 5 > tcp5
 
Bitfield< 4 > tcp4
 
Bitfield< 3 > tcp3
 
Bitfield< 2 > tcp2
 
Bitfield< 1 > tcp1
 
Bitfield< 0 > tcp0
 
Bitfield< 16 > ttee
 
Bitfield< 15 > t15
 
Bitfield< 13 > t13
 
Bitfield< 12 > t12
 
Bitfield< 11 > t11
 
Bitfield< 10 > t10
 
Bitfield< 9 > t9
 
Bitfield< 8 > t8
 
Bitfield< 7 > t7
 
Bitfield< 6 > t6
 
Bitfield< 5 > t5
 
Bitfield< 4 > t4
 
Bitfield< 3 > t3
 
Bitfield< 2 > t2
 
Bitfield< 1 > t1
 
Bitfield< 0 > t0
 
Bitfield< 54 > ttlbis
 
Bitfield< 52 > tocu
 
Bitfield< 50 > ticab
 
Bitfield< 49 > tid4
 
Bitfield< 47 > fien
 
Bitfield< 45 > nv2
 
Bitfield< 43 > nv1
 
Bitfield< 40 > apk
 
Bitfield< 38 > miocnce
 
Bitfield< 37 > tea
 
Bitfield< 36 > terr
 
Bitfield< 35 > tlor
 
Bitfield< 34 > e2h
 
Bitfield< 33 > id
 
Bitfield< 32 > cd
 
Bitfield< 31 > rw
 
Bitfield< 30 > trvm
 
Bitfield< 29 > hcd
 
Bitfield< 28 > tdz
 
Bitfield< 27 > tge
 
Bitfield< 26 > tvm
 
Bitfield< 25 > ttlb
 
Bitfield< 24 > tpu
 
Bitfield< 23 > tpc
 
Bitfield< 22 > tsw
 
Bitfield< 21 > tac
 
Bitfield< 21 > tacr
 
Bitfield< 20 > tidcp
 
Bitfield< 19 > tsc
 
Bitfield< 18 > tid3
 
Bitfield< 17 > tid2
 
Bitfield< 16 > tid1
 
Bitfield< 15 > tid0
 
Bitfield< 14 > twe
 
Bitfield< 13 > twi
 
Bitfield< 12 > dc
 
Bitfield< 11, 10 > bsu
 
Bitfield< 9 > fb
 
Bitfield< 8 > va
 
Bitfield< 8 > vse
 
Bitfield< 7 > vi
 
Bitfield< 6 > vf
 
Bitfield< 5 > amo
 
Bitfield< 4 > imo
 
Bitfield< 3 > fmo
 
Bitfield< 2 > ptw
 
Bitfield< 1 > swio
 
Bitfield< 0 > vm
 
Bitfield< 19 > rfr
 
Bitfield< 15 > nsasedis
 
Bitfield< 14 > nsd32dis
 
Bitfield< 13 > cp13
 
Bitfield< 12 > cp12
 
Bitfield< 11 > cp11
 
Bitfield< 10 > cp10
 
Bitfield< 9 > cp9
 
Bitfield< 8 > cp8
 
Bitfield< 7 > cp7
 
Bitfield< 6 > cp6
 
Bitfield< 5 > cp5
 
Bitfield< 4 > cp4
 
Bitfield< 3 > cp3
 
Bitfield< 2 > cp2
 
Bitfield< 1 > cp1
 
Bitfield< 0 > cp0
 
Bitfield< 38 > hxen
 
Bitfield< 20 > nmea
 
Bitfield< 19 > ease
 
Bitfield< 18 > eel2
 
Bitfield< 15 > teer
 
Bitfield< 9 > sif
 
Bitfield< 8 > hce
 
Bitfield< 7 > scd
 
Bitfield< 7 > smd
 
Bitfield< 6 > nEt
 
Bitfield< 5 > aw
 
Bitfield< 4 > fw
 
Bitfield< 3 > ea
 
Bitfield< 2 > fiq
 
Bitfield< 1 > irq
 
Bitfield< 0 > ns
 
Bitfield< 30 > enib
 
Bitfield< 30 > te
 
Bitfield< 29 > afe
 
Bitfield< 28 > tre
 
Bitfield< 27 > nmfi
 
Bitfield< 27 > enda
 
Bitfield< 26 > uci
 
Bitfield< 25 > ee
 
Bitfield< 24 > e0e
 
Bitfield< 23 > span
 
Bitfield< 23 > xp
 
Bitfield< 22 > u
 
Bitfield< 21 > fi
 
Bitfield< 20 > uwxn
 
Bitfield< 19 > dz
 
Bitfield< 19 > wxn
 
Bitfield< 18 > ntwe
 
Bitfield< 18 > rao2
 
Bitfield< 16 > ntwi
 
Bitfield< 16 > rao3
 
Bitfield< 15 > uct
 
Bitfield< 14 > rr
 
Bitfield< 14 > dze
 
Bitfield< 13 > endb
 
Bitfield< 11 > z
 
Bitfield< 9, 8 > rs
 
Bitfield< 9 > uma
 
Bitfield< 8 > sed
 
Bitfield< 7 > b
 
Bitfield< 7 > itd
 
Bitfield< 6, 3 > rao4
 
Bitfield< 6 > thee
 
Bitfield< 5 > cp15ben
 
Bitfield< 4 > sa0
 
Bitfield< 3 > sa
 
Bitfield< 0 > m
 
Bitfield< 17, 16 > zen
 
Bitfield< 21, 20 > fpen
 
Bitfield< 25, 24 > smen
 
Bitfield< 29, 28 > rsvd
 
Bitfield< 30 > d32dis
 
Bitfield< 31 > asedis
 
 fsLow
 
Bitfield< 5, 0 > status
 
Bitfield< 7, 4 > domain
 
Bitfield< 9 > lpae
 
Bitfield< 10 > fsHigh
 
Bitfield< 11 > wnr
 
Bitfield< 12 > ext
 
Bitfield< 13 > cm
 
Bitfield< 1 > dzc
 
Bitfield< 2 > ofc
 
Bitfield< 3 > ufc
 
Bitfield< 4 > ixc
 
Bitfield< 7 > idc
 
Bitfield< 8 > ioe
 
Bitfield< 10 > ofe
 
Bitfield< 11 > ufe
 
Bitfield< 12 > ixe
 
Bitfield< 15 > ide
 
Bitfield< 18, 16 > len
 
Bitfield< 19 > fz16
 
Bitfield< 21, 20 > stride
 
Bitfield< 23, 22 > rMode
 
Bitfield< 24 > fz
 
Bitfield< 25 > dn
 
Bitfield< 26 > ahp
 
Bitfield< 27 > qc
 
Bitfield< 31 > n
 
Bitfield< 30 > en
 
Bitfield< 29, 0 > subArchDefined
 
 advSimdRegisters
 
Bitfield< 7, 4 > singlePrecision
 
Bitfield< 11, 8 > doublePrecision
 
Bitfield< 15, 12 > vfpExceptionTrapping
 
Bitfield< 19, 16 > divide
 
Bitfield< 23, 20 > squareRoot
 
Bitfield< 27, 24 > shortVectors
 
Bitfield< 31, 28 > roundingModes
 
 flushToZero
 
Bitfield< 7, 4 > defaultNaN
 
Bitfield< 11, 8 > advSimdLoadStore
 
Bitfield< 15, 12 > advSimdInteger
 
Bitfield< 19, 16 > advSimdSinglePrecision
 
Bitfield< 23, 20 > advSimdHalfPrecision
 
Bitfield< 27, 24 > vfpHalfPrecision
 
Bitfield< 31, 28 > raz
 
Bitfield< 4 > pd0
 
Bitfield< 5 > pd1
 
Bitfield< 2, 0 > t0sz
 
Bitfield< 6 > t2e
 
Bitfield< 7 > epd0
 
Bitfield< 9, 8 > irgn0
 
Bitfield< 11, 10 > orgn0
 
Bitfield< 14 > tg0
 
Bitfield< 18, 16 > t1sz
 
Bitfield< 22 > a1
 
Bitfield< 23 > epd1
 
Bitfield< 25, 24 > irgn1
 
Bitfield< 27, 26 > orgn1
 
Bitfield< 30 > tg1
 
Bitfield< 34, 32 > ips
 
Bitfield< 36 > as
 
Bitfield< 37 > tbi0
 
Bitfield< 38 > tbi1
 
Bitfield< 31 > eae
 
Bitfield< 18, 16 > ps
 
Bitfield< 20 > tbi
 
Bitfield< 41 > hpd0
 
Bitfield< 42 > hpd1
 
Bitfield< 24 > hpd
 
Bitfield< 29 > tbid
 
Bitfield< 39 > ha
 
Bitfield< 40 > hd
 
Bitfield< 51 > tbid0
 
Bitfield< 52 > tbid1
 
Bitfield< 4 > s
 
Bitfield< 5, 0 > t0sz64
 
Bitfield< 7, 6 > sl0
 
Bitfield< 19 > vs
 
 tr0
 
Bitfield< 3, 2 > tr1
 
Bitfield< 5, 4 > tr2
 
Bitfield< 7, 6 > tr3
 
Bitfield< 9, 8 > tr4
 
Bitfield< 11, 10 > tr5
 
Bitfield< 13, 12 > tr6
 
Bitfield< 15, 14 > tr7
 
Bitfield< 16 > ds0
 
Bitfield< 17 > ds1
 
Bitfield< 18 > ns0
 
Bitfield< 19 > ns1
 
Bitfield< 24 > nos0
 
Bitfield< 25 > nos1
 
Bitfield< 26 > nos2
 
Bitfield< 27 > nos3
 
Bitfield< 28 > nos4
 
Bitfield< 29 > nos5
 
Bitfield< 30 > nos6
 
Bitfield< 31 > nos7
 
 ir0
 
Bitfield< 3, 2 > ir1
 
Bitfield< 5, 4 > ir2
 
Bitfield< 7, 6 > ir3
 
Bitfield< 9, 8 > ir4
 
Bitfield< 11, 10 > ir5
 
Bitfield< 13, 12 > ir6
 
Bitfield< 15, 14 > ir7
 
Bitfield< 17, 16 > or0
 
Bitfield< 19, 18 > or1
 
Bitfield< 21, 20 > or2
 
Bitfield< 23, 22 > or3
 
Bitfield< 25, 24 > or4
 
Bitfield< 27, 26 > or5
 
Bitfield< 29, 28 > or6
 
Bitfield< 31, 30 > or7
 
 asid
 
Bitfield< 31, 8 > procid
 
 sataRAMLatency
 
Bitfield< 4, 3 > reserved_4_3
 
Bitfield< 5 > dataRAMSetup
 
Bitfield< 8, 6 > tagRAMLatency
 
Bitfield< 9 > tagRAMSetup
 
Bitfield< 11, 10 > dataRAMSlice
 
Bitfield< 12 > tagRAMSlice
 
Bitfield< 20, 13 > reserved_20_13
 
Bitfield< 21 > eccandParityEnable
 
Bitfield< 22 > reserved_22
 
Bitfield< 23 > interptCtrlPresent
 
Bitfield< 25, 24 > numCPUs
 
Bitfield< 30, 26 > reserved_30_26
 
Bitfield< 31 > l2rstDISABLE_monitor
 
 iCacheLineSize
 
Bitfield< 13, 4 > raz_13_4
 
Bitfield< 15, 14 > l1IndexPolicy
 
Bitfield< 19, 16 > dCacheLineSize
 
Bitfield< 23, 20 > erg
 
Bitfield< 27, 24 > cwg
 
Bitfield< 28 > raz_28
 
Bitfield< 31, 29 > format
 
 sel
 
 attr
 
Bitfield< 39, 12 > pa
 
Bitfield< 8, 7 > sh
 
Bitfield< 6, 1 > fst
 
Bitfield< 6 > fs5
 
Bitfield< 5, 1 > fs4_0
 
 ec
 
Bitfield< 24, 0 > iss
 
Bitfield< 24 > isv
 
Bitfield< 23, 22 > sas
 
Bitfield< 21 > sse
 
Bitfield< 20, 16 > srt
 
Bitfield< 15 > sf
 
Bitfield< 14 > ar
 
Bitfield< 13 > vncr
 
Bitfield< 10 > fnv
 
Bitfield< 7 > s1ptw
 
Bitfield< 5, 0 > dfsc
 
Bitfield< 12, 11 > set
 
Bitfield< 5, 0 > ifsc
 
Bitfield< 6 > ex
 
Bitfield< 30 > tam
 
Bitfield< 28 > tta_e2h
 
Bitfield< 13, 13 > res1_13_el2
 
Bitfield< 12, 12 > res1_12_el2
 
Bitfield< 12 > esm
 
Bitfield< 12 > tsm
 
Bitfield< 9 > res1_9_el2
 
Bitfield< 8 > res1_8_el2
 
Bitfield< 8 > ez
 
Bitfield< 7, 0 > res1_7_0_el2
 
 res0_63_32
 
Bitfield< 31, 31 > fa64
 
Bitfield< 30, 9 > res0_30_9
 
Bitfield< 8, 4 > razwi_8_4
 
 res0_63_2
 
Bitfield< 1, 1 > za
 
Bitfield< 0, 0 > sm
 
Bitfield< 31, 24 > implementer
 
Bitfield< 23, 16 > revision
 
Bitfield< 15, 15 > smps
 
Bitfield< 14, 12 > res0_14_12
 
Bitfield< 11, 0 > affinity
 
 res0_63_4
 
Bitfield< 3, 0 > priority
 
 res0
 
Bitfield< 3 > oslm_3
 
Bitfield< 2 > nTT
 
Bitfield< 1 > oslk
 
Bitfield< 0 > oslm_0
 
 res0_2
 
Bitfield< 23, 20 > bt
 
Bitfield< 19, 16 > lbn
 
Bitfield< 15, 14 > ssc
 
Bitfield< 13 > hmc
 
Bitfield< 12, 9 > res0_1
 
Bitfield< 8, 5 > bas
 
Bitfield< 4, 3 > res0_0
 
Bitfield< 2, 1 > pmc
 
Bitfield< 20 > wt
 
Bitfield< 4, 3 > lsv
 
Bitfield< 2, 1 > pac
 
Bitfield< 30 > rxfull
 
Bitfield< 29 > txfull
 
Bitfield< 28 > res0_5
 
Bitfield< 27 > rxo
 
Bitfield< 26 > txu
 
Bitfield< 25, 24 > res0_4
 
Bitfield< 23, 22 > intdis
 
Bitfield< 20 > res0_3
 
Bitfield< 19 > sc2
 
Bitfield< 17 > spniddis
 
Bitfield< 16 > spiddis
 
Bitfield< 15 > mdbgen
 
Bitfield< 14 > hde
 
Bitfield< 13 > res0_
 
Bitfield< 12 > udccdis
 
Bitfield< 12 > tdcc
 
Bitfield< 6 > err
 
Bitfield< 5, 2 > moe
 
Bitfield< 30 > nsi
 
Bitfield< 28 > nsd
 
Bitfield< 27 > nsp
 
Bitfield< 26 > nss
 
Bitfield< 25 > nsu
 
Bitfield< 15 > mf
 
Bitfield< 14 > mi
 
Bitfield< 12 > md
 
Bitfield< 11 > mp
 
Bitfield< 10 > ms
 
Bitfield< 6 > si
 
Bitfield< 4 > sd
 
Bitfield< 1 > su
 
 cidmask
 
Bitfield< 27, 24 > auxregs
 
Bitfield< 19, 16 > virtextns
 
Bitfield< 15, 12 > vectorcatch
 
Bitfield< 11, 8 > bpaddremask
 
Bitfield< 7, 4 > wpaddrmask
 
Bitfield< 3, 0 > pcsample
 
constexpr unsigned NumVecElemPerNeonVecReg = 4
 
constexpr unsigned NumVecElemPerVecReg = MaxSveVecLenInWords
 
const int NumFloatV7ArchRegs = 64
 
const int NumVecV7ArchRegs = 16
 
const int NumVecV8ArchRegs = 32
 
const int NumVecSpecialRegs = 8
 
const int NumVecIntrlvRegs = 4
 
const int NumVecRegs = NumVecV8ArchRegs + NumVecSpecialRegs + NumVecIntrlvRegs
 
const int NumVecPredRegs = 18
 
const int VecSpecialElem = NumVecV8ArchRegs * NumVecElemPerNeonVecReg
 
const int INTRLVREG0 = NumVecV8ArchRegs + NumVecSpecialRegs
 
const int INTRLVREG1 = INTRLVREG0 + 1
 
const int INTRLVREG2 = INTRLVREG0 + 2
 
const int INTRLVREG3 = INTRLVREG0 + 3
 
const int VECREG_UREG0 = 32
 
const int PREDREG_FFR = 16
 
const int PREDREG_UREG0 = 17
 
static VecElemRegClassOps< RegVal > vecRegElemClassOps (NumVecElemPerVecReg)
 
static TypedRegClassOps< ArmISA::VecRegContainer > vecRegClassOps
 
static TypedRegClassOps< ArmISA::VecPredRegContainer > vecPredRegClassOps
 
constexpr RegClass vecRegClass
 
constexpr RegClass vecElemClass
 
constexpr RegClass vecPredRegClass
 
 decoderFault
 
Bitfield< 61 > illegalExecution
 
Bitfield< 60 > debugStep
 
Bitfield< 59, 56 > sveLen
 
Bitfield< 55, 48 > itstate
 
Bitfield< 55, 52 > itstateCond
 
Bitfield< 51, 48 > itstateMask
 
Bitfield< 41, 40 > fpscrStride
 
Bitfield< 39, 37 > fpscrLen
 
Bitfield< 36 > thumb
 
Bitfield< 35 > bigThumb
 
Bitfield< 34 > aarch64
 
Bitfield< 33 > sevenAndFour
 
Bitfield< 32 > isMisc
 
uint32_t instBits
 
Bitfield< 27, 25 > encoding
 
Bitfield< 25 > useImm
 
Bitfield< 24, 21 > opcode
 
Bitfield< 24, 20 > mediaOpcode
 
Bitfield< 24 > opcode24
 
Bitfield< 24, 23 > opcode24_23
 
Bitfield< 23, 20 > opcode23_20
 
Bitfield< 23, 21 > opcode23_21
 
Bitfield< 20 > opcode20
 
Bitfield< 22 > opcode22
 
Bitfield< 19, 16 > opcode19_16
 
Bitfield< 19 > opcode19
 
Bitfield< 18 > opcode18
 
Bitfield< 15, 12 > opcode15_12
 
Bitfield< 15 > opcode15
 
Bitfield< 7, 4 > miscOpcode
 
Bitfield< 7, 5 > opc2
 
Bitfield< 7 > opcode7
 
Bitfield< 6 > opcode6
 
Bitfield< 4 > opcode4
 
Bitfield< 31, 28 > condCode
 
Bitfield< 20 > sField
 
Bitfield< 19, 16 > rn
 
Bitfield< 15, 12 > rd
 
Bitfield< 15, 12 > rt
 
Bitfield< 11, 7 > shiftSize
 
Bitfield< 6, 5 > shift
 
Bitfield< 3, 0 > rm
 
Bitfield< 23 > up
 
Bitfield< 22 > psruser
 
Bitfield< 21 > writeback
 
Bitfield< 20 > loadOp
 
 pubwl
 
Bitfield< 7, 0 > imm
 
Bitfield< 11, 8 > rotate
 
Bitfield< 11, 0 > immed11_0
 
Bitfield< 7, 0 > immed7_0
 
Bitfield< 11, 8 > immedHi11_8
 
Bitfield< 3, 0 > immedLo3_0
 
Bitfield< 15, 0 > regList
 
Bitfield< 23, 0 > offset
 
Bitfield< 23, 0 > immed23_0
 
Bitfield< 11, 8 > cpNum
 
Bitfield< 18, 16 > fn
 
Bitfield< 14, 12 > fd
 
Bitfield< 3 > fpRegImm
 
Bitfield< 3, 0 > fm
 
Bitfield< 2, 0 > fpImm
 
Bitfield< 24, 20 > punwl
 
Bitfield< 15, 8 > m5Func
 
Bitfield< 15, 13 > topcode15_13
 
Bitfield< 13, 11 > topcode13_11
 
Bitfield< 12, 11 > topcode12_11
 
Bitfield< 12, 10 > topcode12_10
 
Bitfield< 11, 9 > topcode11_9
 
Bitfield< 11, 8 > topcode11_8
 
Bitfield< 10, 9 > topcode10_9
 
Bitfield< 10, 8 > topcode10_8
 
Bitfield< 9, 6 > topcode9_6
 
Bitfield< 7 > topcode7
 
Bitfield< 7, 6 > topcode7_6
 
Bitfield< 7, 5 > topcode7_5
 
Bitfield< 7, 4 > topcode7_4
 
Bitfield< 3, 0 > topcode3_0
 
Bitfield< 28, 27 > htopcode12_11
 
Bitfield< 26, 25 > htopcode10_9
 
Bitfield< 25 > htopcode9
 
Bitfield< 25, 24 > htopcode9_8
 
Bitfield< 25, 21 > htopcode9_5
 
Bitfield< 25, 20 > htopcode9_4
 
Bitfield< 24 > htopcode8
 
Bitfield< 24, 23 > htopcode8_7
 
Bitfield< 24, 22 > htopcode8_6
 
Bitfield< 24, 21 > htopcode8_5
 
Bitfield< 23 > htopcode7
 
Bitfield< 23, 21 > htopcode7_5
 
Bitfield< 22 > htopcode6
 
Bitfield< 22, 21 > htopcode6_5
 
Bitfield< 21, 20 > htopcode5_4
 
Bitfield< 20 > htopcode4
 
Bitfield< 19, 16 > htrn
 
Bitfield< 20 > hts
 
Bitfield< 15 > ltopcode15
 
Bitfield< 11, 8 > ltopcode11_8
 
Bitfield< 7, 6 > ltopcode7_6
 
Bitfield< 7, 4 > ltopcode7_4
 
Bitfield< 4 > ltopcode4
 
Bitfield< 11, 8 > ltrd
 
Bitfield< 11, 8 > ltcoproc
 
 aff3
 
Bitfield< 23, 16 > aff2
 
Bitfield< 15, 8 > aff1
 
Bitfield< 7, 0 > aff0
 
constexpr unsigned MaxSveVecLenInBits = 2048
 
constexpr unsigned MaxSveVecLenInBytes = MaxSveVecLenInBits >> 3
 
constexpr unsigned MaxSveVecLenInWords = MaxSveVecLenInBits >> 5
 
constexpr unsigned MaxSveVecLenInDWords = MaxSveVecLenInBits >> 6
 
constexpr unsigned VecRegSizeBytes = MaxSveVecLenInBytes
 
constexpr unsigned VecPredRegSizeBits = MaxSveVecLenInBytes
 
constexpr unsigned MaxSmeVecLenInBits = 2048
 
constexpr unsigned MaxSmeVecLenInBytes = MaxSmeVecLenInBits >> 3
 
constexpr unsigned MaxSmeVecLenInWords = MaxSmeVecLenInBits >> 5
 
constexpr unsigned MaxSmeVecLenInDWords = MaxSmeVecLenInBits >> 6
 
Bitfield< 9 > el0pten
 
Bitfield< 8 > el0vten
 
Bitfield< 7, 4 > evnti
 
Bitfield< 3 > evntdir
 
Bitfield< 2 > evnten
 
Bitfield< 1 > el0vcten
 
Bitfield< 0 > el0pcten
 
Bitfield< 16 > el1nvvct
 
Bitfield< 15 > el1nvpct
 
Bitfield< 14 > el1tvct
 
Bitfield< 13 > el1tvt
 
Bitfield< 1 > el1pcen
 
Bitfield< 0 > el1pcten
 
Bitfield< 11 > el1pten
 

Typedef Documentation

◆ ConstVecPredReg

using gem5::ArmISA::ConstVecPredReg = typedef gem5::VecPredRegT<VecElem, NumVecElemPerVecReg, false, true>

Definition at line 70 of file vec.hh.

◆ FaultOffset

typedef Addr gem5::ArmISA::FaultOffset

Definition at line 60 of file faults.hh.

◆ MachInst

typedef uint32_t gem5::ArmISA::MachInst

Definition at line 55 of file types.hh.

◆ MatCol

template<typename ElemType >
using gem5::ArmISA::MatCol = typedef gem5::VerticalSlice<ElemType, MatRegContainer, false>

Definition at line 85 of file mat.hh.

◆ MatRegContainer

using gem5::ArmISA::MatRegContainer = typedef gem5::MatStore<MaxSmeVecLenInBytes, MaxSmeVecLenInBytes>

Definition at line 61 of file mat.hh.

◆ MatRow

template<typename ElemType >
using gem5::ArmISA::MatRow = typedef gem5::HorizontalSlice<ElemType, MatRegContainer, false>

Definition at line 80 of file mat.hh.

◆ MatTile

template<typename ElemType >
using gem5::ArmISA::MatTile = typedef gem5::Tile<ElemType, MatRegContainer>

Definition at line 65 of file mat.hh.

◆ MatTileCol

template<typename ElemType >
using gem5::ArmISA::MatTileCol = typedef gem5::VerticalSlice<ElemType, MatRegContainer, true>

Definition at line 75 of file mat.hh.

◆ MatTileRow

template<typename ElemType >
using gem5::ArmISA::MatTileRow = typedef gem5::HorizontalSlice<ElemType, MatRegContainer, true>

Definition at line 70 of file mat.hh.

◆ RegContextParam

typedef int gem5::ArmISA::RegContextParam

Definition at line 234 of file types.hh.

◆ RegContextVal

typedef int gem5::ArmISA::RegContextVal

Definition at line 235 of file types.hh.

◆ VecElem

using gem5::ArmISA::VecElem = typedef uint32_t

Definition at line 63 of file vec.hh.

◆ VecPredReg

using gem5::ArmISA::VecPredReg = typedef gem5::VecPredRegT<VecElem, NumVecElemPerVecReg, false, false>

Definition at line 68 of file vec.hh.

◆ VecPredRegContainer

using gem5::ArmISA::VecPredRegContainer = typedef VecPredReg::Container

Definition at line 71 of file vec.hh.

◆ VecRegContainer

using gem5::ArmISA::VecRegContainer = typedef gem5::VecRegContainer<NumVecElemPerVecReg * sizeof(VecElem)>

Definition at line 65 of file vec.hh.

◆ VfpSavedState

typedef int gem5::ArmISA::VfpSavedState

Definition at line 217 of file vfp.hh.

◆ vmid_t

typedef uint16_t gem5::ArmISA::vmid_t

Definition at line 57 of file types.hh.

◆ XReg

typedef uint64_t gem5::ArmISA::XReg

Definition at line 53 of file neon64_mem.hh.

Enumeration Type Documentation

◆ ArmExtendType

enum gem5::ArmISA::ArmExtendType
Enumerator
UXTB 
UXTH 
UXTW 
UXTX 
SXTB 
SXTH 
SXTW 
SXTX 

Definition at line 222 of file types.hh.

◆ ConditionCode

enum gem5::ArmISA::ConditionCode
Enumerator
COND_EQ 
COND_NE 
COND_CS 
COND_CC 
COND_MI 
COND_PL 
COND_VS 
COND_VC 
COND_HI 
COND_LS 
COND_GE 
COND_LT 
COND_GT 
COND_LE 
COND_AL 
COND_UC 

Definition at line 103 of file cc.hh.

◆ ConvertType

enum gem5::ArmISA::ConvertType
Enumerator
SINGLE_TO_DOUBLE 
SINGLE_TO_WORD 
SINGLE_TO_LONG 
DOUBLE_TO_SINGLE 
DOUBLE_TO_WORD 
DOUBLE_TO_LONG 
LONG_TO_SINGLE 
LONG_TO_DOUBLE 
LONG_TO_WORD 
LONG_TO_PS 
WORD_TO_SINGLE 
WORD_TO_DOUBLE 
WORD_TO_LONG 
WORD_TO_PS 
PL_TO_SINGLE 
PU_TO_SINGLE 

Definition at line 238 of file types.hh.

◆ DecoderFault

enum gem5::ArmISA::DecoderFault : std::uint8_t

Instruction decoder fault codes in ExtMachInst.

Enumerator
OK 

No fault.

UNALIGNED 

Unaligned instruction fault.

PANIC 

Internal gem5 error.

Definition at line 357 of file types.hh.

◆ ExceptionClass

enum gem5::ArmISA::ExceptionClass
strong
Enumerator
INVALID 
UNKNOWN 
TRAPPED_WFI_WFE 
TRAPPED_CP15_MCR_MRC 
TRAPPED_CP15_MCRR_MRRC 
TRAPPED_CP14_MCR_MRC 
TRAPPED_CP14_LDC_STC 
TRAPPED_HCPTR 
TRAPPED_SIMD_FP 
TRAPPED_CP10_MRC_VMRS 
TRAPPED_PAC 
TRAPPED_BXJ 
TRAPPED_CP14_MCRR_MRRC 
ILLEGAL_INST 
SVC_TO_HYP 
SVC 
HVC 
SMC_TO_HYP 
SMC 
SVC_64 
HVC_64 
SMC_64 
TRAPPED_MSR_MRS_64 
TRAPPED_SVE 
TRAPPED_SME 
PREFETCH_ABORT_TO_HYP 
PREFETCH_ABORT_LOWER_EL 
PREFETCH_ABORT_FROM_HYP 
PREFETCH_ABORT_CURR_EL 
PC_ALIGNMENT 
DATA_ABORT_TO_HYP 
DATA_ABORT_LOWER_EL 
DATA_ABORT_FROM_HYP 
DATA_ABORT_CURR_EL 
STACK_PTR_ALIGNMENT 
FP_EXCEPTION 
FP_EXCEPTION_64 
SERROR 
HW_BREAKPOINT 
HW_BREAKPOINT_LOWER_EL 
HW_BREAKPOINT_CURR_EL 
SOFTWARE_STEP 
SOFTWARE_STEP_LOWER_EL 
SOFTWARE_STEP_CURR_EL 
WATCHPOINT 
WATCHPOINT_LOWER_EL 
WATCHPOINT_CURR_EL 
SOFTWARE_BREAKPOINT 
VECTOR_CATCH 
SOFTWARE_BREAKPOINT_64 

Definition at line 300 of file types.hh.

◆ ExceptionLevel

enum gem5::ArmISA::ExceptionLevel
Enumerator
EL0 
EL1 
EL2 
EL3 

Definition at line 271 of file types.hh.

◆ FeExceptionBit

enum gem5::ArmISA::FeExceptionBit
Enumerator
FeDivByZero 
FeInexact 
FeInvalid 
FeOverflow 
FeUnderflow 
FeAllExceptions 

Definition at line 88 of file vfp.hh.

◆ FeRoundingMode

enum gem5::ArmISA::FeRoundingMode
Enumerator
FeRoundDown 
FeRoundNearest 
FeRoundZero 
FeRoundUpward 

Definition at line 98 of file vfp.hh.

◆ FpDataType

enum gem5::ArmISA::FpDataType
strong

Floating point data types.

Enumerator
Fp16 
Fp32 
Fp64 

Definition at line 168 of file pred_inst.hh.

◆ FPRounding

enum gem5::ArmISA::FPRounding
Enumerator
FPRounding_TIEEVEN 
FPRounding_POSINF 
FPRounding_NEGINF 
FPRounding_ZERO 
FPRounding_TIEAWAY 
FPRounding_ODD 

Definition at line 60 of file fplib.hh.

◆ GrainSize

enum gem5::ArmISA::GrainSize
Enumerator
Grain4KB 
Grain16KB 
Grain64KB 
ReservedGrain 

Definition at line 61 of file pagetable.hh.

◆ InterruptTypes

enum gem5::ArmISA::InterruptTypes
Enumerator
INT_RST 
INT_ABT 
INT_IRQ 
INT_FIQ 
INT_SEV 
INT_VIRT_IRQ 
INT_VIRT_FIQ 
NumInterruptTypes 

Definition at line 59 of file interrupts.hh.

◆ MiscRegIndex

enum gem5::ArmISA::MiscRegIndex
Enumerator
MISCREG_CPSR 
MISCREG_SPSR 
MISCREG_SPSR_FIQ 
MISCREG_SPSR_IRQ 
MISCREG_SPSR_SVC 
MISCREG_SPSR_MON 
MISCREG_SPSR_ABT 
MISCREG_SPSR_HYP 
MISCREG_SPSR_UND 
MISCREG_ELR_HYP 
MISCREG_FPSID 
MISCREG_FPSCR 
MISCREG_MVFR1 
MISCREG_MVFR0 
MISCREG_FPEXC 
MISCREG_CPSR_MODE 
MISCREG_CPSR_Q 
MISCREG_FPSCR_EXC 
MISCREG_FPSCR_QC 
MISCREG_LOCKADDR 
MISCREG_LOCKFLAG 
MISCREG_PRRR_MAIR0 
MISCREG_PRRR_MAIR0_NS 
MISCREG_PRRR_MAIR0_S 
MISCREG_NMRR_MAIR1 
MISCREG_NMRR_MAIR1_NS 
MISCREG_NMRR_MAIR1_S 
MISCREG_PMXEVTYPER_PMCCFILTR 
MISCREG_SEV_MAILBOX 
MISCREG_TLBINEEDSYNC 
MISCREG_DBGDIDR 
MISCREG_DBGDSCRint 
MISCREG_DBGDCCINT 
MISCREG_DBGDTRTXint 
MISCREG_DBGDTRRXint 
MISCREG_DBGWFAR 
MISCREG_DBGVCR 
MISCREG_DBGDTRRXext 
MISCREG_DBGDSCRext 
MISCREG_DBGDTRTXext 
MISCREG_DBGOSECCR 
MISCREG_DBGBVR0 
MISCREG_DBGBVR1 
MISCREG_DBGBVR2 
MISCREG_DBGBVR3 
MISCREG_DBGBVR4 
MISCREG_DBGBVR5 
MISCREG_DBGBVR6 
MISCREG_DBGBVR7 
MISCREG_DBGBVR8 
MISCREG_DBGBVR9 
MISCREG_DBGBVR10 
MISCREG_DBGBVR11 
MISCREG_DBGBVR12 
MISCREG_DBGBVR13 
MISCREG_DBGBVR14 
MISCREG_DBGBVR15 
MISCREG_DBGBCR0 
MISCREG_DBGBCR1 
MISCREG_DBGBCR2 
MISCREG_DBGBCR3 
MISCREG_DBGBCR4 
MISCREG_DBGBCR5 
MISCREG_DBGBCR6 
MISCREG_DBGBCR7 
MISCREG_DBGBCR8 
MISCREG_DBGBCR9 
MISCREG_DBGBCR10 
MISCREG_DBGBCR11 
MISCREG_DBGBCR12 
MISCREG_DBGBCR13 
MISCREG_DBGBCR14 
MISCREG_DBGBCR15 
MISCREG_DBGWVR0 
MISCREG_DBGWVR1 
MISCREG_DBGWVR2 
MISCREG_DBGWVR3 
MISCREG_DBGWVR4 
MISCREG_DBGWVR5 
MISCREG_DBGWVR6 
MISCREG_DBGWVR7 
MISCREG_DBGWVR8 
MISCREG_DBGWVR9 
MISCREG_DBGWVR10 
MISCREG_DBGWVR11 
MISCREG_DBGWVR12 
MISCREG_DBGWVR13 
MISCREG_DBGWVR14 
MISCREG_DBGWVR15 
MISCREG_DBGWCR0 
MISCREG_DBGWCR1 
MISCREG_DBGWCR2 
MISCREG_DBGWCR3 
MISCREG_DBGWCR4 
MISCREG_DBGWCR5 
MISCREG_DBGWCR6 
MISCREG_DBGWCR7 
MISCREG_DBGWCR8 
MISCREG_DBGWCR9 
MISCREG_DBGWCR10 
MISCREG_DBGWCR11 
MISCREG_DBGWCR12 
MISCREG_DBGWCR13 
MISCREG_DBGWCR14 
MISCREG_DBGWCR15 
MISCREG_DBGDRAR 
MISCREG_DBGBXVR0 
MISCREG_DBGBXVR1 
MISCREG_DBGBXVR2 
MISCREG_DBGBXVR3 
MISCREG_DBGBXVR4 
MISCREG_DBGBXVR5 
MISCREG_DBGBXVR6 
MISCREG_DBGBXVR7 
MISCREG_DBGBXVR8 
MISCREG_DBGBXVR9 
MISCREG_DBGBXVR10 
MISCREG_DBGBXVR11 
MISCREG_DBGBXVR12 
MISCREG_DBGBXVR13 
MISCREG_DBGBXVR14 
MISCREG_DBGBXVR15 
MISCREG_DBGOSLAR 
MISCREG_DBGOSLSR 
MISCREG_DBGOSDLR 
MISCREG_DBGPRCR 
MISCREG_DBGDSAR 
MISCREG_DBGCLAIMSET 
MISCREG_DBGCLAIMCLR 
MISCREG_DBGAUTHSTATUS 
MISCREG_DBGDEVID2 
MISCREG_DBGDEVID1 
MISCREG_DBGDEVID0 
MISCREG_TEECR 
MISCREG_JIDR 
MISCREG_TEEHBR 
MISCREG_JOSCR 
MISCREG_JMCR 
MISCREG_MIDR 
MISCREG_CTR 
MISCREG_TCMTR 
MISCREG_TLBTR 
MISCREG_MPIDR 
MISCREG_REVIDR 
MISCREG_ID_PFR0 
MISCREG_ID_PFR1 
MISCREG_ID_DFR0 
MISCREG_ID_AFR0 
MISCREG_ID_MMFR0 
MISCREG_ID_MMFR1 
MISCREG_ID_MMFR2 
MISCREG_ID_MMFR3 
MISCREG_ID_MMFR4 
MISCREG_ID_ISAR0 
MISCREG_ID_ISAR1 
MISCREG_ID_ISAR2 
MISCREG_ID_ISAR3 
MISCREG_ID_ISAR4 
MISCREG_ID_ISAR5 
MISCREG_ID_ISAR6 
MISCREG_CCSIDR 
MISCREG_CLIDR 
MISCREG_AIDR 
MISCREG_CSSELR 
MISCREG_CSSELR_NS 
MISCREG_CSSELR_S 
MISCREG_VPIDR 
MISCREG_VMPIDR 
MISCREG_SCTLR 
MISCREG_SCTLR_NS 
MISCREG_SCTLR_S 
MISCREG_ACTLR 
MISCREG_ACTLR_NS 
MISCREG_ACTLR_S 
MISCREG_CPACR 
MISCREG_SDCR 
MISCREG_SCR 
MISCREG_SDER 
MISCREG_NSACR 
MISCREG_HSCTLR 
MISCREG_HACTLR 
MISCREG_HCR 
MISCREG_HCR2 
MISCREG_HDCR 
MISCREG_HCPTR 
MISCREG_HSTR 
MISCREG_HACR 
MISCREG_TTBR0 
MISCREG_TTBR0_NS 
MISCREG_TTBR0_S 
MISCREG_TTBR1 
MISCREG_TTBR1_NS 
MISCREG_TTBR1_S 
MISCREG_TTBCR 
MISCREG_TTBCR_NS 
MISCREG_TTBCR_S 
MISCREG_HTCR 
MISCREG_VTCR 
MISCREG_DACR 
MISCREG_DACR_NS 
MISCREG_DACR_S 
MISCREG_DFSR 
MISCREG_DFSR_NS 
MISCREG_DFSR_S 
MISCREG_IFSR 
MISCREG_IFSR_NS 
MISCREG_IFSR_S 
MISCREG_ADFSR 
MISCREG_ADFSR_NS 
MISCREG_ADFSR_S 
MISCREG_AIFSR 
MISCREG_AIFSR_NS 
MISCREG_AIFSR_S 
MISCREG_HADFSR 
MISCREG_HAIFSR 
MISCREG_HSR 
MISCREG_DFAR 
MISCREG_DFAR_NS 
MISCREG_DFAR_S 
MISCREG_IFAR 
MISCREG_IFAR_NS 
MISCREG_IFAR_S 
MISCREG_HDFAR 
MISCREG_HIFAR 
MISCREG_HPFAR 
MISCREG_ICIALLUIS 
MISCREG_BPIALLIS 
MISCREG_PAR 
MISCREG_PAR_NS 
MISCREG_PAR_S 
MISCREG_ICIALLU 
MISCREG_ICIMVAU 
MISCREG_CP15ISB 
MISCREG_BPIALL 
MISCREG_BPIMVA 
MISCREG_DCIMVAC 
MISCREG_DCISW 
MISCREG_ATS1CPR 
MISCREG_ATS1CPW 
MISCREG_ATS1CUR 
MISCREG_ATS1CUW 
MISCREG_ATS12NSOPR 
MISCREG_ATS12NSOPW 
MISCREG_ATS12NSOUR 
MISCREG_ATS12NSOUW 
MISCREG_DCCMVAC 
MISCREG_DCCSW 
MISCREG_CP15DSB 
MISCREG_CP15DMB 
MISCREG_DCCMVAU 
MISCREG_DCCIMVAC 
MISCREG_DCCISW 
MISCREG_ATS1HR 
MISCREG_ATS1HW 
MISCREG_TLBIALLIS 
MISCREG_TLBIMVAIS 
MISCREG_TLBIASIDIS 
MISCREG_TLBIMVAAIS 
MISCREG_TLBIMVALIS 
MISCREG_TLBIMVAALIS 
MISCREG_ITLBIALL 
MISCREG_ITLBIMVA 
MISCREG_ITLBIASID 
MISCREG_DTLBIALL 
MISCREG_DTLBIMVA 
MISCREG_DTLBIASID 
MISCREG_TLBIALL 
MISCREG_TLBIMVA 
MISCREG_TLBIASID 
MISCREG_TLBIMVAA 
MISCREG_TLBIMVAL 
MISCREG_TLBIMVAAL 
MISCREG_TLBIIPAS2IS 
MISCREG_TLBIIPAS2LIS 
MISCREG_TLBIALLHIS 
MISCREG_TLBIMVAHIS 
MISCREG_TLBIALLNSNHIS 
MISCREG_TLBIMVALHIS 
MISCREG_TLBIIPAS2 
MISCREG_TLBIIPAS2L 
MISCREG_TLBIALLH 
MISCREG_TLBIMVAH 
MISCREG_TLBIALLNSNH 
MISCREG_TLBIMVALH 
MISCREG_PMCR 
MISCREG_PMCNTENSET 
MISCREG_PMCNTENCLR 
MISCREG_PMOVSR 
MISCREG_PMSWINC 
MISCREG_PMSELR 
MISCREG_PMCEID0 
MISCREG_PMCEID1 
MISCREG_PMCCNTR 
MISCREG_PMXEVTYPER 
MISCREG_PMCCFILTR 
MISCREG_PMXEVCNTR 
MISCREG_PMUSERENR 
MISCREG_PMINTENSET 
MISCREG_PMINTENCLR 
MISCREG_PMOVSSET 
MISCREG_L2CTLR 
MISCREG_L2ECTLR 
MISCREG_PRRR 
MISCREG_PRRR_NS 
MISCREG_PRRR_S 
MISCREG_MAIR0 
MISCREG_MAIR0_NS 
MISCREG_MAIR0_S 
MISCREG_NMRR 
MISCREG_NMRR_NS 
MISCREG_NMRR_S 
MISCREG_MAIR1 
MISCREG_MAIR1_NS 
MISCREG_MAIR1_S 
MISCREG_AMAIR0 
MISCREG_AMAIR0_NS 
MISCREG_AMAIR0_S 
MISCREG_AMAIR1 
MISCREG_AMAIR1_NS 
MISCREG_AMAIR1_S 
MISCREG_HMAIR0 
MISCREG_HMAIR1 
MISCREG_HAMAIR0 
MISCREG_HAMAIR1 
MISCREG_VBAR 
MISCREG_VBAR_NS 
MISCREG_VBAR_S 
MISCREG_MVBAR 
MISCREG_RMR 
MISCREG_ISR 
MISCREG_HVBAR 
MISCREG_FCSEIDR 
MISCREG_CONTEXTIDR 
MISCREG_CONTEXTIDR_NS 
MISCREG_CONTEXTIDR_S 
MISCREG_TPIDRURW 
MISCREG_TPIDRURW_NS 
MISCREG_TPIDRURW_S 
MISCREG_TPIDRURO 
MISCREG_TPIDRURO_NS 
MISCREG_TPIDRURO_S 
MISCREG_TPIDRPRW 
MISCREG_TPIDRPRW_NS 
MISCREG_TPIDRPRW_S 
MISCREG_HTPIDR 
MISCREG_CNTFRQ 
MISCREG_CNTPCT 
MISCREG_CNTVCT 
MISCREG_CNTP_CTL 
MISCREG_CNTP_CTL_NS 
MISCREG_CNTP_CTL_S 
MISCREG_CNTP_CVAL 
MISCREG_CNTP_CVAL_NS 
MISCREG_CNTP_CVAL_S 
MISCREG_CNTP_TVAL 
MISCREG_CNTP_TVAL_NS 
MISCREG_CNTP_TVAL_S 
MISCREG_CNTV_CTL 
MISCREG_CNTV_CVAL 
MISCREG_CNTV_TVAL 
MISCREG_CNTKCTL 
MISCREG_CNTHCTL 
MISCREG_CNTHP_CTL 
MISCREG_CNTHP_CVAL 
MISCREG_CNTHP_TVAL 
MISCREG_CNTVOFF 
MISCREG_IL1DATA0 
MISCREG_IL1DATA1 
MISCREG_IL1DATA2 
MISCREG_IL1DATA3 
MISCREG_DL1DATA0 
MISCREG_DL1DATA1 
MISCREG_DL1DATA2 
MISCREG_DL1DATA3 
MISCREG_DL1DATA4 
MISCREG_RAMINDEX 
MISCREG_L2ACTLR 
MISCREG_CBAR 
MISCREG_HTTBR 
MISCREG_VTTBR 
MISCREG_CPUMERRSR 
MISCREG_L2MERRSR 
MISCREG_MDCCINT_EL1 
MISCREG_OSDTRRX_EL1 
MISCREG_MDSCR_EL1 
MISCREG_OSDTRTX_EL1 
MISCREG_OSECCR_EL1 
MISCREG_DBGBVR0_EL1 
MISCREG_DBGBVR1_EL1 
MISCREG_DBGBVR2_EL1 
MISCREG_DBGBVR3_EL1 
MISCREG_DBGBVR4_EL1 
MISCREG_DBGBVR5_EL1 
MISCREG_DBGBVR6_EL1 
MISCREG_DBGBVR7_EL1 
MISCREG_DBGBVR8_EL1 
MISCREG_DBGBVR9_EL1 
MISCREG_DBGBVR10_EL1 
MISCREG_DBGBVR11_EL1 
MISCREG_DBGBVR12_EL1 
MISCREG_DBGBVR13_EL1 
MISCREG_DBGBVR14_EL1 
MISCREG_DBGBVR15_EL1 
MISCREG_DBGBCR0_EL1 
MISCREG_DBGBCR1_EL1 
MISCREG_DBGBCR2_EL1 
MISCREG_DBGBCR3_EL1 
MISCREG_DBGBCR4_EL1 
MISCREG_DBGBCR5_EL1 
MISCREG_DBGBCR6_EL1 
MISCREG_DBGBCR7_EL1 
MISCREG_DBGBCR8_EL1 
MISCREG_DBGBCR9_EL1 
MISCREG_DBGBCR10_EL1 
MISCREG_DBGBCR11_EL1 
MISCREG_DBGBCR12_EL1 
MISCREG_DBGBCR13_EL1 
MISCREG_DBGBCR14_EL1 
MISCREG_DBGBCR15_EL1 
MISCREG_DBGWVR0_EL1 
MISCREG_DBGWVR1_EL1 
MISCREG_DBGWVR2_EL1 
MISCREG_DBGWVR3_EL1 
MISCREG_DBGWVR4_EL1 
MISCREG_DBGWVR5_EL1 
MISCREG_DBGWVR6_EL1 
MISCREG_DBGWVR7_EL1 
MISCREG_DBGWVR8_EL1 
MISCREG_DBGWVR9_EL1 
MISCREG_DBGWVR10_EL1 
MISCREG_DBGWVR11_EL1 
MISCREG_DBGWVR12_EL1 
MISCREG_DBGWVR13_EL1 
MISCREG_DBGWVR14_EL1 
MISCREG_DBGWVR15_EL1 
MISCREG_DBGWCR0_EL1 
MISCREG_DBGWCR1_EL1 
MISCREG_DBGWCR2_EL1 
MISCREG_DBGWCR3_EL1 
MISCREG_DBGWCR4_EL1 
MISCREG_DBGWCR5_EL1 
MISCREG_DBGWCR6_EL1 
MISCREG_DBGWCR7_EL1 
MISCREG_DBGWCR8_EL1 
MISCREG_DBGWCR9_EL1 
MISCREG_DBGWCR10_EL1 
MISCREG_DBGWCR11_EL1 
MISCREG_DBGWCR12_EL1 
MISCREG_DBGWCR13_EL1 
MISCREG_DBGWCR14_EL1 
MISCREG_DBGWCR15_EL1 
MISCREG_MDCCSR_EL0 
MISCREG_MDDTR_EL0 
MISCREG_MDDTRTX_EL0 
MISCREG_MDDTRRX_EL0 
MISCREG_DBGVCR32_EL2 
MISCREG_MDRAR_EL1 
MISCREG_OSLAR_EL1 
MISCREG_OSLSR_EL1 
MISCREG_OSDLR_EL1 
MISCREG_DBGPRCR_EL1 
MISCREG_DBGCLAIMSET_EL1 
MISCREG_DBGCLAIMCLR_EL1 
MISCREG_DBGAUTHSTATUS_EL1 
MISCREG_TEECR32_EL1 
MISCREG_TEEHBR32_EL1 
MISCREG_MIDR_EL1 
MISCREG_MPIDR_EL1 
MISCREG_REVIDR_EL1 
MISCREG_ID_PFR0_EL1 
MISCREG_ID_PFR1_EL1 
MISCREG_ID_DFR0_EL1 
MISCREG_ID_AFR0_EL1 
MISCREG_ID_MMFR0_EL1 
MISCREG_ID_MMFR1_EL1 
MISCREG_ID_MMFR2_EL1 
MISCREG_ID_MMFR3_EL1 
MISCREG_ID_MMFR4_EL1 
MISCREG_ID_ISAR0_EL1 
MISCREG_ID_ISAR1_EL1 
MISCREG_ID_ISAR2_EL1 
MISCREG_ID_ISAR3_EL1 
MISCREG_ID_ISAR4_EL1 
MISCREG_ID_ISAR5_EL1 
MISCREG_ID_ISAR6_EL1 
MISCREG_MVFR0_EL1 
MISCREG_MVFR1_EL1 
MISCREG_MVFR2_EL1 
MISCREG_ID_AA64PFR0_EL1 
MISCREG_ID_AA64PFR1_EL1 
MISCREG_ID_AA64DFR0_EL1 
MISCREG_ID_AA64DFR1_EL1 
MISCREG_ID_AA64AFR0_EL1 
MISCREG_ID_AA64AFR1_EL1 
MISCREG_ID_AA64ISAR0_EL1 
MISCREG_ID_AA64ISAR1_EL1 
MISCREG_ID_AA64MMFR0_EL1 
MISCREG_ID_AA64MMFR1_EL1 
MISCREG_CCSIDR_EL1 
MISCREG_CLIDR_EL1 
MISCREG_AIDR_EL1 
MISCREG_CSSELR_EL1 
MISCREG_CTR_EL0 
MISCREG_DCZID_EL0 
MISCREG_VPIDR_EL2 
MISCREG_VMPIDR_EL2 
MISCREG_SCTLR_EL1 
MISCREG_SCTLR_EL12 
MISCREG_ACTLR_EL1 
MISCREG_CPACR_EL1 
MISCREG_CPACR_EL12 
MISCREG_SCTLR_EL2 
MISCREG_ACTLR_EL2 
MISCREG_HCR_EL2 
MISCREG_HCRX_EL2 
MISCREG_MDCR_EL2 
MISCREG_CPTR_EL2 
MISCREG_HSTR_EL2 
MISCREG_HACR_EL2 
MISCREG_SCTLR_EL3 
MISCREG_ACTLR_EL3 
MISCREG_SCR_EL3 
MISCREG_SDER32_EL3 
MISCREG_CPTR_EL3 
MISCREG_MDCR_EL3 
MISCREG_TTBR0_EL1 
MISCREG_TTBR0_EL12 
MISCREG_TTBR1_EL1 
MISCREG_TTBR1_EL12 
MISCREG_TCR_EL1 
MISCREG_TCR_EL12 
MISCREG_TTBR0_EL2 
MISCREG_TCR_EL2 
MISCREG_VTTBR_EL2 
MISCREG_VTCR_EL2 
MISCREG_VSTTBR_EL2 
MISCREG_VSTCR_EL2 
MISCREG_TTBR0_EL3 
MISCREG_TCR_EL3 
MISCREG_DACR32_EL2 
MISCREG_SPSR_EL1 
MISCREG_SPSR_EL12 
MISCREG_ELR_EL1 
MISCREG_ELR_EL12 
MISCREG_SP_EL0 
MISCREG_SPSEL 
MISCREG_CURRENTEL 
MISCREG_NZCV 
MISCREG_DAIF 
MISCREG_FPCR 
MISCREG_FPSR 
MISCREG_DSPSR_EL0 
MISCREG_DLR_EL0 
MISCREG_SPSR_EL2 
MISCREG_ELR_EL2 
MISCREG_SP_EL1 
MISCREG_SPSR_IRQ_AA64 
MISCREG_SPSR_ABT_AA64 
MISCREG_SPSR_UND_AA64 
MISCREG_SPSR_FIQ_AA64 
MISCREG_SPSR_EL3 
MISCREG_ELR_EL3 
MISCREG_SP_EL2 
MISCREG_AFSR0_EL1 
MISCREG_AFSR0_EL12 
MISCREG_AFSR1_EL1 
MISCREG_AFSR1_EL12 
MISCREG_ESR_EL1 
MISCREG_ESR_EL12 
MISCREG_IFSR32_EL2 
MISCREG_AFSR0_EL2 
MISCREG_AFSR1_EL2 
MISCREG_ESR_EL2 
MISCREG_FPEXC32_EL2 
MISCREG_AFSR0_EL3 
MISCREG_AFSR1_EL3 
MISCREG_ESR_EL3 
MISCREG_FAR_EL1 
MISCREG_FAR_EL12 
MISCREG_FAR_EL2 
MISCREG_HPFAR_EL2 
MISCREG_FAR_EL3 
MISCREG_IC_IALLUIS 
MISCREG_PAR_EL1 
MISCREG_IC_IALLU 
MISCREG_DC_IVAC_Xt 
MISCREG_DC_ISW_Xt 
MISCREG_AT_S1E1R_Xt 
MISCREG_AT_S1E1W_Xt 
MISCREG_AT_S1E0R_Xt 
MISCREG_AT_S1E0W_Xt 
MISCREG_DC_CSW_Xt 
MISCREG_DC_CISW_Xt 
MISCREG_DC_ZVA_Xt 
MISCREG_IC_IVAU_Xt 
MISCREG_DC_CVAC_Xt 
MISCREG_DC_CVAU_Xt 
MISCREG_DC_CIVAC_Xt 
MISCREG_AT_S1E2R_Xt 
MISCREG_AT_S1E2W_Xt 
MISCREG_AT_S12E1R_Xt 
MISCREG_AT_S12E1W_Xt 
MISCREG_AT_S12E0R_Xt 
MISCREG_AT_S12E0W_Xt 
MISCREG_AT_S1E3R_Xt 
MISCREG_AT_S1E3W_Xt 
MISCREG_TLBI_VMALLE1IS 
MISCREG_TLBI_VMALLE1OS 
MISCREG_TLBI_VAE1IS_Xt 
MISCREG_TLBI_VAE1OS_Xt 
MISCREG_TLBI_ASIDE1IS_Xt 
MISCREG_TLBI_ASIDE1OS_Xt 
MISCREG_TLBI_VAAE1IS_Xt 
MISCREG_TLBI_VAAE1OS_Xt 
MISCREG_TLBI_VALE1IS_Xt 
MISCREG_TLBI_VALE1OS_Xt 
MISCREG_TLBI_VAALE1IS_Xt 
MISCREG_TLBI_VAALE1OS_Xt 
MISCREG_TLBI_VMALLE1 
MISCREG_TLBI_VAE1_Xt 
MISCREG_TLBI_ASIDE1_Xt 
MISCREG_TLBI_VAAE1_Xt 
MISCREG_TLBI_VALE1_Xt 
MISCREG_TLBI_VAALE1_Xt 
MISCREG_TLBI_IPAS2E1IS_Xt 
MISCREG_TLBI_IPAS2E1OS_Xt 
MISCREG_TLBI_IPAS2LE1IS_Xt 
MISCREG_TLBI_IPAS2LE1OS_Xt 
MISCREG_TLBI_ALLE2IS 
MISCREG_TLBI_ALLE2OS 
MISCREG_TLBI_VAE2IS_Xt 
MISCREG_TLBI_VAE2OS_Xt 
MISCREG_TLBI_ALLE1IS 
MISCREG_TLBI_ALLE1OS 
MISCREG_TLBI_VALE2IS_Xt 
MISCREG_TLBI_VALE2OS_Xt 
MISCREG_TLBI_VMALLS12E1IS 
MISCREG_TLBI_VMALLS12E1OS 
MISCREG_TLBI_IPAS2E1_Xt 
MISCREG_TLBI_IPAS2LE1_Xt 
MISCREG_TLBI_ALLE2 
MISCREG_TLBI_VAE2_Xt 
MISCREG_TLBI_ALLE1 
MISCREG_TLBI_VALE2_Xt 
MISCREG_TLBI_VMALLS12E1 
MISCREG_TLBI_ALLE3IS 
MISCREG_TLBI_ALLE3OS 
MISCREG_TLBI_VAE3IS_Xt 
MISCREG_TLBI_VAE3OS_Xt 
MISCREG_TLBI_VALE3IS_Xt 
MISCREG_TLBI_VALE3OS_Xt 
MISCREG_TLBI_ALLE3 
MISCREG_TLBI_VAE3_Xt 
MISCREG_TLBI_VALE3_Xt 
MISCREG_PMINTENSET_EL1 
MISCREG_PMINTENCLR_EL1 
MISCREG_PMCR_EL0 
MISCREG_PMCNTENSET_EL0 
MISCREG_PMCNTENCLR_EL0 
MISCREG_PMOVSCLR_EL0 
MISCREG_PMSWINC_EL0 
MISCREG_PMSELR_EL0 
MISCREG_PMCEID0_EL0 
MISCREG_PMCEID1_EL0 
MISCREG_PMCCNTR_EL0 
MISCREG_PMXEVTYPER_EL0 
MISCREG_PMCCFILTR_EL0 
MISCREG_PMXEVCNTR_EL0 
MISCREG_PMUSERENR_EL0 
MISCREG_PMOVSSET_EL0 
MISCREG_MAIR_EL1 
MISCREG_MAIR_EL12 
MISCREG_AMAIR_EL1 
MISCREG_AMAIR_EL12 
MISCREG_MAIR_EL2 
MISCREG_AMAIR_EL2 
MISCREG_MAIR_EL3 
MISCREG_AMAIR_EL3 
MISCREG_L2CTLR_EL1 
MISCREG_L2ECTLR_EL1 
MISCREG_VBAR_EL1 
MISCREG_VBAR_EL12 
MISCREG_RVBAR_EL1 
MISCREG_ISR_EL1 
MISCREG_VBAR_EL2 
MISCREG_RVBAR_EL2 
MISCREG_VBAR_EL3 
MISCREG_RVBAR_EL3 
MISCREG_RMR_EL3 
MISCREG_CONTEXTIDR_EL1 
MISCREG_CONTEXTIDR_EL12 
MISCREG_TPIDR_EL1 
MISCREG_TPIDR_EL0 
MISCREG_TPIDRRO_EL0 
MISCREG_TPIDR_EL2 
MISCREG_TPIDR_EL3 
MISCREG_CNTFRQ_EL0 
MISCREG_CNTPCT_EL0 
MISCREG_CNTVCT_EL0 
MISCREG_CNTP_CTL_EL0 
MISCREG_CNTP_CVAL_EL0 
MISCREG_CNTP_TVAL_EL0 
MISCREG_CNTV_CTL_EL0 
MISCREG_CNTV_CVAL_EL0 
MISCREG_CNTV_TVAL_EL0 
MISCREG_CNTP_CTL_EL02 
MISCREG_CNTP_CVAL_EL02 
MISCREG_CNTP_TVAL_EL02 
MISCREG_CNTV_CTL_EL02 
MISCREG_CNTV_CVAL_EL02 
MISCREG_CNTV_TVAL_EL02 
MISCREG_CNTKCTL_EL1 
MISCREG_CNTKCTL_EL12 
MISCREG_CNTPS_CTL_EL1 
MISCREG_CNTPS_CVAL_EL1 
MISCREG_CNTPS_TVAL_EL1 
MISCREG_CNTHCTL_EL2 
MISCREG_CNTHP_CTL_EL2 
MISCREG_CNTHP_CVAL_EL2 
MISCREG_CNTHP_TVAL_EL2 
MISCREG_CNTHPS_CTL_EL2 
MISCREG_CNTHPS_CVAL_EL2 
MISCREG_CNTHPS_TVAL_EL2 
MISCREG_CNTHV_CTL_EL2 
MISCREG_CNTHV_CVAL_EL2 
MISCREG_CNTHV_TVAL_EL2 
MISCREG_CNTHVS_CTL_EL2 
MISCREG_CNTHVS_CVAL_EL2 
MISCREG_CNTHVS_TVAL_EL2 
MISCREG_CNTVOFF_EL2 
MISCREG_PMEVCNTR0_EL0 
MISCREG_PMEVCNTR1_EL0 
MISCREG_PMEVCNTR2_EL0 
MISCREG_PMEVCNTR3_EL0 
MISCREG_PMEVCNTR4_EL0 
MISCREG_PMEVCNTR5_EL0 
MISCREG_PMEVTYPER0_EL0 
MISCREG_PMEVTYPER1_EL0 
MISCREG_PMEVTYPER2_EL0 
MISCREG_PMEVTYPER3_EL0 
MISCREG_PMEVTYPER4_EL0 
MISCREG_PMEVTYPER5_EL0 
MISCREG_IL1DATA0_EL1 
MISCREG_IL1DATA1_EL1 
MISCREG_IL1DATA2_EL1 
MISCREG_IL1DATA3_EL1 
MISCREG_DL1DATA0_EL1 
MISCREG_DL1DATA1_EL1 
MISCREG_DL1DATA2_EL1 
MISCREG_DL1DATA3_EL1 
MISCREG_DL1DATA4_EL1 
MISCREG_L2ACTLR_EL1 
MISCREG_CPUACTLR_EL1 
MISCREG_CPUECTLR_EL1 
MISCREG_CPUMERRSR_EL1 
MISCREG_L2MERRSR_EL1 
MISCREG_CBAR_EL1 
MISCREG_CONTEXTIDR_EL2 
MISCREG_TTBR1_EL2 
MISCREG_ID_AA64MMFR2_EL1 
MISCREG_APDAKeyHi_EL1 
MISCREG_APDAKeyLo_EL1 
MISCREG_APDBKeyHi_EL1 
MISCREG_APDBKeyLo_EL1 
MISCREG_APGAKeyHi_EL1 
MISCREG_APGAKeyLo_EL1 
MISCREG_APIAKeyHi_EL1 
MISCREG_APIAKeyLo_EL1 
MISCREG_APIBKeyHi_EL1 
MISCREG_APIBKeyLo_EL1 
MISCREG_ICC_PMR_EL1 
MISCREG_ICC_IAR0_EL1 
MISCREG_ICC_EOIR0_EL1 
MISCREG_ICC_HPPIR0_EL1 
MISCREG_ICC_BPR0_EL1 
MISCREG_ICC_AP0R0_EL1 
MISCREG_ICC_AP0R1_EL1 
MISCREG_ICC_AP0R2_EL1 
MISCREG_ICC_AP0R3_EL1 
MISCREG_ICC_AP1R0_EL1 
MISCREG_ICC_AP1R0_EL1_NS 
MISCREG_ICC_AP1R0_EL1_S 
MISCREG_ICC_AP1R1_EL1 
MISCREG_ICC_AP1R1_EL1_NS 
MISCREG_ICC_AP1R1_EL1_S 
MISCREG_ICC_AP1R2_EL1 
MISCREG_ICC_AP1R2_EL1_NS 
MISCREG_ICC_AP1R2_EL1_S 
MISCREG_ICC_AP1R3_EL1 
MISCREG_ICC_AP1R3_EL1_NS 
MISCREG_ICC_AP1R3_EL1_S 
MISCREG_ICC_DIR_EL1 
MISCREG_ICC_RPR_EL1 
MISCREG_ICC_SGI1R_EL1 
MISCREG_ICC_ASGI1R_EL1 
MISCREG_ICC_SGI0R_EL1 
MISCREG_ICC_IAR1_EL1 
MISCREG_ICC_EOIR1_EL1 
MISCREG_ICC_HPPIR1_EL1 
MISCREG_ICC_BPR1_EL1 
MISCREG_ICC_BPR1_EL1_NS 
MISCREG_ICC_BPR1_EL1_S 
MISCREG_ICC_CTLR_EL1 
MISCREG_ICC_CTLR_EL1_NS 
MISCREG_ICC_CTLR_EL1_S 
MISCREG_ICC_SRE_EL1 
MISCREG_ICC_SRE_EL1_NS 
MISCREG_ICC_SRE_EL1_S 
MISCREG_ICC_IGRPEN0_EL1 
MISCREG_ICC_IGRPEN1_EL1 
MISCREG_ICC_IGRPEN1_EL1_NS 
MISCREG_ICC_IGRPEN1_EL1_S 
MISCREG_ICC_SRE_EL2 
MISCREG_ICC_CTLR_EL3 
MISCREG_ICC_SRE_EL3 
MISCREG_ICC_IGRPEN1_EL3 
MISCREG_ICH_AP0R0_EL2 
MISCREG_ICH_AP0R1_EL2 
MISCREG_ICH_AP0R2_EL2 
MISCREG_ICH_AP0R3_EL2 
MISCREG_ICH_AP1R0_EL2 
MISCREG_ICH_AP1R1_EL2 
MISCREG_ICH_AP1R2_EL2 
MISCREG_ICH_AP1R3_EL2 
MISCREG_ICH_HCR_EL2 
MISCREG_ICH_VTR_EL2 
MISCREG_ICH_MISR_EL2 
MISCREG_ICH_EISR_EL2 
MISCREG_ICH_ELRSR_EL2 
MISCREG_ICH_VMCR_EL2 
MISCREG_ICH_LR0_EL2 
MISCREG_ICH_LR1_EL2 
MISCREG_ICH_LR2_EL2 
MISCREG_ICH_LR3_EL2 
MISCREG_ICH_LR4_EL2 
MISCREG_ICH_LR5_EL2 
MISCREG_ICH_LR6_EL2 
MISCREG_ICH_LR7_EL2 
MISCREG_ICH_LR8_EL2 
MISCREG_ICH_LR9_EL2 
MISCREG_ICH_LR10_EL2 
MISCREG_ICH_LR11_EL2 
MISCREG_ICH_LR12_EL2 
MISCREG_ICH_LR13_EL2 
MISCREG_ICH_LR14_EL2 
MISCREG_ICH_LR15_EL2 
MISCREG_ICV_PMR_EL1 
MISCREG_ICV_IAR0_EL1 
MISCREG_ICV_EOIR0_EL1 
MISCREG_ICV_HPPIR0_EL1 
MISCREG_ICV_BPR0_EL1 
MISCREG_ICV_AP0R0_EL1 
MISCREG_ICV_AP0R1_EL1 
MISCREG_ICV_AP0R2_EL1 
MISCREG_ICV_AP0R3_EL1 
MISCREG_ICV_AP1R0_EL1 
MISCREG_ICV_AP1R0_EL1_NS 
MISCREG_ICV_AP1R0_EL1_S 
MISCREG_ICV_AP1R1_EL1 
MISCREG_ICV_AP1R1_EL1_NS 
MISCREG_ICV_AP1R1_EL1_S 
MISCREG_ICV_AP1R2_EL1 
MISCREG_ICV_AP1R2_EL1_NS 
MISCREG_ICV_AP1R2_EL1_S 
MISCREG_ICV_AP1R3_EL1 
MISCREG_ICV_AP1R3_EL1_NS 
MISCREG_ICV_AP1R3_EL1_S 
MISCREG_ICV_DIR_EL1 
MISCREG_ICV_RPR_EL1 
MISCREG_ICV_SGI1R_EL1 
MISCREG_ICV_ASGI1R_EL1 
MISCREG_ICV_SGI0R_EL1 
MISCREG_ICV_IAR1_EL1 
MISCREG_ICV_EOIR1_EL1 
MISCREG_ICV_HPPIR1_EL1 
MISCREG_ICV_BPR1_EL1 
MISCREG_ICV_BPR1_EL1_NS 
MISCREG_ICV_BPR1_EL1_S 
MISCREG_ICV_CTLR_EL1 
MISCREG_ICV_CTLR_EL1_NS 
MISCREG_ICV_CTLR_EL1_S 
MISCREG_ICV_SRE_EL1 
MISCREG_ICV_SRE_EL1_NS 
MISCREG_ICV_SRE_EL1_S 
MISCREG_ICV_IGRPEN0_EL1 
MISCREG_ICV_IGRPEN1_EL1 
MISCREG_ICV_IGRPEN1_EL1_NS 
MISCREG_ICV_IGRPEN1_EL1_S 
MISCREG_ICC_AP0R0 
MISCREG_ICC_AP0R1 
MISCREG_ICC_AP0R2 
MISCREG_ICC_AP0R3 
MISCREG_ICC_AP1R0 
MISCREG_ICC_AP1R0_NS 
MISCREG_ICC_AP1R0_S 
MISCREG_ICC_AP1R1 
MISCREG_ICC_AP1R1_NS 
MISCREG_ICC_AP1R1_S 
MISCREG_ICC_AP1R2 
MISCREG_ICC_AP1R2_NS 
MISCREG_ICC_AP1R2_S 
MISCREG_ICC_AP1R3 
MISCREG_ICC_AP1R3_NS 
MISCREG_ICC_AP1R3_S 
MISCREG_ICC_ASGI1R 
MISCREG_ICC_BPR0 
MISCREG_ICC_BPR1 
MISCREG_ICC_BPR1_NS 
MISCREG_ICC_BPR1_S 
MISCREG_ICC_CTLR 
MISCREG_ICC_CTLR_NS 
MISCREG_ICC_CTLR_S 
MISCREG_ICC_DIR 
MISCREG_ICC_EOIR0 
MISCREG_ICC_EOIR1 
MISCREG_ICC_HPPIR0 
MISCREG_ICC_HPPIR1 
MISCREG_ICC_HSRE 
MISCREG_ICC_IAR0 
MISCREG_ICC_IAR1 
MISCREG_ICC_IGRPEN0 
MISCREG_ICC_IGRPEN1 
MISCREG_ICC_IGRPEN1_NS 
MISCREG_ICC_IGRPEN1_S 
MISCREG_ICC_MCTLR 
MISCREG_ICC_MGRPEN1 
MISCREG_ICC_MSRE 
MISCREG_ICC_PMR 
MISCREG_ICC_RPR 
MISCREG_ICC_SGI0R 
MISCREG_ICC_SGI1R 
MISCREG_ICC_SRE 
MISCREG_ICC_SRE_NS 
MISCREG_ICC_SRE_S 
MISCREG_ICH_AP0R0 
MISCREG_ICH_AP0R1 
MISCREG_ICH_AP0R2 
MISCREG_ICH_AP0R3 
MISCREG_ICH_AP1R0 
MISCREG_ICH_AP1R1 
MISCREG_ICH_AP1R2 
MISCREG_ICH_AP1R3 
MISCREG_ICH_HCR 
MISCREG_ICH_VTR 
MISCREG_ICH_MISR 
MISCREG_ICH_EISR 
MISCREG_ICH_ELRSR 
MISCREG_ICH_VMCR 
MISCREG_ICH_LR0 
MISCREG_ICH_LR1 
MISCREG_ICH_LR2 
MISCREG_ICH_LR3 
MISCREG_ICH_LR4 
MISCREG_ICH_LR5 
MISCREG_ICH_LR6 
MISCREG_ICH_LR7 
MISCREG_ICH_LR8 
MISCREG_ICH_LR9 
MISCREG_ICH_LR10 
MISCREG_ICH_LR11 
MISCREG_ICH_LR12 
MISCREG_ICH_LR13 
MISCREG_ICH_LR14 
MISCREG_ICH_LR15 
MISCREG_ICH_LRC0 
MISCREG_ICH_LRC1 
MISCREG_ICH_LRC2 
MISCREG_ICH_LRC3 
MISCREG_ICH_LRC4 
MISCREG_ICH_LRC5 
MISCREG_ICH_LRC6 
MISCREG_ICH_LRC7 
MISCREG_ICH_LRC8 
MISCREG_ICH_LRC9 
MISCREG_ICH_LRC10 
MISCREG_ICH_LRC11 
MISCREG_ICH_LRC12 
MISCREG_ICH_LRC13 
MISCREG_ICH_LRC14 
MISCREG_ICH_LRC15 
MISCREG_ID_AA64ZFR0_EL1 
MISCREG_ZCR_EL3 
MISCREG_ZCR_EL2 
MISCREG_ZCR_EL12 
MISCREG_ZCR_EL1 
MISCREG_ID_AA64SMFR0_EL1 
MISCREG_SVCR 
MISCREG_SMIDR_EL1 
MISCREG_SMPRI_EL1 
MISCREG_SMPRIMAP_EL2 
MISCREG_SMCR_EL3 
MISCREG_SMCR_EL2 
MISCREG_SMCR_EL12 
MISCREG_SMCR_EL1 
MISCREG_TPIDR2_EL0 
MISCREG_MPAMSM_EL1 
MISCREG_RNDR 
MISCREG_RNDRRS 
NUM_PHYS_MISCREGS 
MISCREG_NOP 
MISCREG_RAZ 
MISCREG_UNKNOWN 
MISCREG_IMPDEF_UNIMPL 
MISCREG_ERRIDR_EL1 
MISCREG_ERRSELR_EL1 
MISCREG_ERXFR_EL1 
MISCREG_ERXCTLR_EL1 
MISCREG_ERXSTATUS_EL1 
MISCREG_ERXADDR_EL1 
MISCREG_ERXMISC0_EL1 
MISCREG_ERXMISC1_EL1 
MISCREG_DISR_EL1 
MISCREG_VSESR_EL2 
MISCREG_VDISR_EL2 
MISCREG_HFGRTR_EL2 
MISCREG_HFGWTR_EL2 
MISCREG_PAN 
MISCREG_UAO 
NUM_MISCREGS 

Definition at line 64 of file misc.hh.

◆ MiscRegInfo

enum gem5::ArmISA::MiscRegInfo
Enumerator
MISCREG_IMPLEMENTED 
MISCREG_UNVERIFIABLE 
MISCREG_UNSERIALIZE 
MISCREG_WARN_NOT_FAIL 
MISCREG_MUTEX 
MISCREG_BANKED 
MISCREG_BANKED64 
MISCREG_BANKED_CHILD 
MISCREG_USR_NS_RD 
MISCREG_USR_NS_WR 
MISCREG_USR_S_RD 
MISCREG_USR_S_WR 
MISCREG_PRI_NS_RD 
MISCREG_PRI_NS_WR 
MISCREG_PRI_S_RD 
MISCREG_PRI_S_WR 
MISCREG_HYP_NS_RD 
MISCREG_HYP_NS_WR 
MISCREG_HYP_S_RD 
MISCREG_HYP_S_WR 
MISCREG_MON_NS0_RD 
MISCREG_MON_NS0_WR 
MISCREG_MON_NS1_RD 
MISCREG_MON_NS1_WR 
NUM_MISCREG_INFOS 

Definition at line 1141 of file misc.hh.

◆ OperatingMode

enum gem5::ArmISA::OperatingMode
Enumerator
MODE_EL0T 
MODE_EL1T 
MODE_EL1H 
MODE_EL2T 
MODE_EL2H 
MODE_EL3T 
MODE_EL3H 
MODE_USER 
MODE_FIQ 
MODE_IRQ 
MODE_SVC 
MODE_MON 
MODE_ABORT 
MODE_HYP 
MODE_UNDEFINED 
MODE_SYSTEM 
MODE_MAXMODE 

Definition at line 279 of file types.hh.

◆ RoundMode

enum gem5::ArmISA::RoundMode
Enumerator
RND_ZERO 
RND_DOWN 
RND_UP 
RND_NEAREST 

Definition at line 263 of file types.hh.

◆ SvePredType

enum gem5::ArmISA::SvePredType
strong
Enumerator
NONE 
MERGE 
ZERO 
SELECT 

Definition at line 48 of file sve.hh.

◆ VfpMicroMode

enum gem5::ArmISA::VfpMicroMode
Enumerator
VfpNotAMicroop 
VfpMicroop 
VfpFirstMicroop 
VfpLastMicroop 

Definition at line 56 of file vfp.hh.

◆ VfpRoundingMode

enum gem5::ArmISA::VfpRoundingMode
Enumerator
VfpRoundNearest 
VfpRoundUpward 
VfpRoundDown 
VfpRoundZero 
VfpRoundAway 

Definition at line 106 of file vfp.hh.

Function Documentation

◆ AArch32isUndefinedGenericTimer()

bool gem5::ArmISA::AArch32isUndefinedGenericTimer ( MiscRegIndex  reg,
ThreadContext *  tc 
)

Definition at line 659 of file misc.cc.

References condGenericTimerSystemAccessTrapEL1(), currEL(), EL0, EL1, EL2Enabled(), ELIs32(), MISCREG_HCR_EL2, gem5::ThreadContext::readMiscReg(), and gem5::X86ISA::reg.

Referenced by canReadCoprocReg(), and canWriteCoprocReg().

◆ AArch64AArch32SystemAccessTrap()

Fault gem5::ArmISA::AArch64AArch32SystemAccessTrap ( const MiscRegIndex  misc_reg,
ExtMachInst  mach_inst,
ThreadContext *  tc,
uint32_t  imm,
ExceptionClass  ec 
)

Definition at line 777 of file utility.cc.

References currEL(), ec, EL1, EL2, EL2Enabled(), ELIs32(), imm, isAArch64AArch32SystemAccessTrapEL1(), isAArch64AArch32SystemAccessTrapEL2(), and gem5::NoFault.

Referenced by mcrMrc15Trap(), and mcrrMrrc15Trap().

◆ aarch64SysRegReadOnly()

bool gem5::ArmISA::aarch64SysRegReadOnly ( MiscRegIndex  miscReg)

◆ add128()

static void gem5::ArmISA::add128 ( uint64_t *  x0,
uint64_t *  x1,
uint64_t  a0,
uint64_t  a1,
uint64_t  b0,
uint64_t  b1 
)
inlinestatic

Definition at line 197 of file fplib.cc.

References gem5::MipsISA::a0, a1, gem5::QARMA::b0, and gem5::QARMA::b1.

Referenced by fp64_muladd().

◆ addPAC()

uint64_t gem5::ArmISA::addPAC ( ThreadContext *  tc,
ExceptionLevel  el,
uint64_t  ptr,
uint64_t  modifier,
uint64_t  k1,
uint64_t  k0,
bool  data 
)

Definition at line 135 of file pauth_helpers.cc.

References gem5::bits(), calculateBottomPACBit(), calculateTBI(), gem5::QARMA::computePAC(), data, el, EL1, EL2, gem5::ArmSystem::haveEL(), gem5::MipsISA::k0, mask, MISCREG_TCR_EL1, MISCREG_TCR_EL2, gem5::ThreadContext::readMiscReg(), s1TranslationRegime(), t, tbi, and upperAndLowerRange().

Referenced by addPACDA(), addPACDB(), addPACIA(), and addPACIB().

◆ addPACDA()

Fault gem5::ArmISA::addPACDA ( ThreadContext *  tc,
uint64_t  X,
uint64_t  Y,
uint64_t *  out 
)

Definition at line 572 of file pauth_helpers.cc.

References addPAC(), currEL(), el, EL0, EL1, EL2, EL2Enabled(), EL3, gem5::X86ISA::enable, gem5::ArmSystem::haveEL(), MISCREG_APDAKeyHi_EL1, MISCREG_APDAKeyLo_EL1, MISCREG_HCR_EL2, MISCREG_SCR_EL3, MISCREG_SCTLR_EL1, MISCREG_SCTLR_EL2, MISCREG_SCTLR_EL3, gem5::NoFault, gem5::ThreadContext::readMiscReg(), s1TranslationRegime(), sc2, trapPACUse(), gem5::X86ISA::X, and gem5::SparcISA::int_reg::Y.

◆ addPACDB()

Fault gem5::ArmISA::addPACDB ( ThreadContext *  tc,
uint64_t  X,
uint64_t  Y,
uint64_t *  out 
)

Definition at line 636 of file pauth_helpers.cc.

References addPAC(), currEL(), el, EL0, EL1, EL2, EL2Enabled(), EL3, gem5::X86ISA::enable, gem5::ArmSystem::haveEL(), MISCREG_APDBKeyHi_EL1, MISCREG_APDBKeyLo_EL1, MISCREG_HCR_EL2, MISCREG_SCR_EL3, MISCREG_SCTLR_EL1, MISCREG_SCTLR_EL2, MISCREG_SCTLR_EL3, gem5::NoFault, gem5::ThreadContext::readMiscReg(), s1TranslationRegime(), sc2, trapPACUse(), gem5::X86ISA::X, and gem5::SparcISA::int_reg::Y.

◆ addPACGA()

Fault gem5::ArmISA::addPACGA ( ThreadContext *  tc,
uint64_t  X,
uint64_t  Y,
uint64_t *  out 
)

Definition at line 697 of file pauth_helpers.cc.

References gem5::QARMA::computePAC(), currEL(), el, EL0, EL1, EL2, EL2Enabled(), EL3, gem5::ArmSystem::haveEL(), MISCREG_APGAKeyHi_EL1, MISCREG_APGAKeyLo_EL1, MISCREG_HCR_EL2, MISCREG_SCR_EL3, gem5::NoFault, gem5::ThreadContext::readMiscReg(), trapPACUse(), gem5::X86ISA::X, and gem5::SparcISA::int_reg::Y.

◆ addPACIA()

Fault gem5::ArmISA::addPACIA ( ThreadContext *  tc,
uint64_t  X,
uint64_t  Y,
uint64_t *  out 
)

Definition at line 745 of file pauth_helpers.cc.

References addPAC(), currEL(), el, EL0, EL1, EL2, EL2Enabled(), EL3, gem5::X86ISA::enable, gem5::ArmSystem::haveEL(), MISCREG_APIAKeyHi_EL1, MISCREG_APIAKeyLo_EL1, MISCREG_HCR_EL2, MISCREG_SCR_EL3, MISCREG_SCTLR_EL1, MISCREG_SCTLR_EL2, MISCREG_SCTLR_EL3, gem5::NoFault, gem5::ThreadContext::readMiscReg(), s1TranslationRegime(), sc2, trapPACUse(), gem5::X86ISA::X, and gem5::SparcISA::int_reg::Y.

◆ addPACIB()

Fault gem5::ArmISA::addPACIB ( ThreadContext *  tc,
uint64_t  X,
uint64_t  Y,
uint64_t *  out 
)

Definition at line 804 of file pauth_helpers.cc.

References addPAC(), currEL(), el, EL0, EL1, EL2, EL2Enabled(), EL3, gem5::X86ISA::enable, gem5::ArmSystem::haveEL(), MISCREG_APIBKeyHi_EL1, MISCREG_APIBKeyLo_EL1, MISCREG_HCR_EL2, MISCREG_SCR_EL3, MISCREG_SCTLR_EL1, MISCREG_SCTLR_EL2, MISCREG_SCTLR_EL3, gem5::NoFault, gem5::ThreadContext::readMiscReg(), s1TranslationRegime(), sc2, trapPACUse(), gem5::X86ISA::X, and gem5::SparcISA::int_reg::Y.

◆ auth()

uint64_t gem5::ArmISA::auth ( ThreadContext *  tc,
ExceptionLevel  el,
uint64_t  ptr,
uint64_t  modifier,
uint64_t  k1,
uint64_t  K0,
bool  data,
uint8_t  errorcode 
)

Definition at line 227 of file pauth_helpers.cc.

References gem5::bits(), calculateBottomPACBit(), calculateTBI(), gem5::QARMA::computePAC(), data, el, gem5::MipsISA::k0, mask, and tbi.

Referenced by authDA(), authDB(), authIA(), and authIB().

◆ authDA()

Fault gem5::ArmISA::authDA ( ThreadContext *  tc,
uint64_t  X,
uint64_t  Y,
uint64_t *  out 
)

Definition at line 284 of file pauth_helpers.cc.

References auth(), currEL(), el, EL0, EL1, EL2, EL2Enabled(), EL3, gem5::X86ISA::enable, gem5::ArmSystem::haveEL(), MISCREG_APDAKeyHi_EL1, MISCREG_APDAKeyLo_EL1, MISCREG_HCR_EL2, MISCREG_SCR_EL3, MISCREG_SCTLR_EL1, MISCREG_SCTLR_EL2, MISCREG_SCTLR_EL3, gem5::NoFault, gem5::ThreadContext::readMiscReg(), s1TranslationRegime(), sc2, trapPACUse(), gem5::X86ISA::X, and gem5::SparcISA::int_reg::Y.

◆ authDB()

Fault gem5::ArmISA::authDB ( ThreadContext *  tc,
uint64_t  X,
uint64_t  Y,
uint64_t *  out 
)

Definition at line 352 of file pauth_helpers.cc.

References auth(), currEL(), el, EL0, EL1, EL2, EL2Enabled(), EL3, gem5::X86ISA::enable, gem5::ArmSystem::haveEL(), MISCREG_APDBKeyHi_EL1, MISCREG_APDBKeyLo_EL1, MISCREG_HCR_EL2, MISCREG_SCR_EL3, MISCREG_SCTLR_EL1, MISCREG_SCTLR_EL2, MISCREG_SCTLR_EL3, gem5::NoFault, gem5::ThreadContext::readMiscReg(), s1TranslationRegime(), sc2, trapPACUse(), gem5::X86ISA::X, and gem5::SparcISA::int_reg::Y.

◆ authIA()

Fault gem5::ArmISA::authIA ( ThreadContext *  tc,
uint64_t  X,
uint64_t  Y,
uint64_t *  out 
)

Definition at line 422 of file pauth_helpers.cc.

References auth(), currEL(), el, EL0, EL1, EL2, EL2Enabled(), EL3, gem5::X86ISA::enable, gem5::ArmSystem::haveEL(), MISCREG_APIAKeyHi_EL1, MISCREG_APIAKeyLo_EL1, MISCREG_HCR_EL2, MISCREG_SCR_EL3, MISCREG_SCTLR_EL1, MISCREG_SCTLR_EL2, MISCREG_SCTLR_EL3, gem5::NoFault, gem5::ThreadContext::readMiscReg(), s1TranslationRegime(), sc2, trapPACUse(), gem5::X86ISA::X, and gem5::SparcISA::int_reg::Y.

◆ authIB()

Fault gem5::ArmISA::authIB ( ThreadContext *  tc,
uint64_t  X,
uint64_t  Y,
uint64_t *  out 
)

Definition at line 496 of file pauth_helpers.cc.

References auth(), currEL(), el, EL0, EL1, EL2, EL2Enabled(), EL3, gem5::X86ISA::enable, gem5::ArmSystem::haveEL(), MISCREG_APIBKeyHi_EL1, MISCREG_APIBKeyLo_EL1, MISCREG_HCR_EL2, MISCREG_SCR_EL3, MISCREG_SCTLR_EL1, MISCREG_SCTLR_EL2, MISCREG_SCTLR_EL3, gem5::NoFault, gem5::ThreadContext::readMiscReg(), s1TranslationRegime(), sc2, trapPACUse(), gem5::X86ISA::X, and gem5::SparcISA::int_reg::Y.

◆ badMode()

bool gem5::ArmISA::badMode ( ThreadContext *  tc,
OperatingMode  mode 
)

badMode is checking if the execution mode provided as an argument is valid and implemented.

Parameters
tcThreadContext
modeOperatingMode to check
Returns
false if mode is valid and implemented, true otherwise

Definition at line 397 of file utility.cc.

References gem5::ArmSystem::haveEL(), mode, opModeToEL(), and unknownMode().

Referenced by gem5::ArmISA::ArmStaticInst::cpsrWriteByInstr().

◆ badMode32()

bool gem5::ArmISA::badMode32 ( ThreadContext *  tc,
OperatingMode  mode 
)

badMode is checking if the execution mode provided as an argument is valid and implemented for AArch32

Parameters
tcThreadContext
modeOperatingMode to check
Returns
false if mode is valid and implemented, true otherwise

Definition at line 391 of file utility.cc.

References gem5::ArmSystem::haveEL(), mode, opModeToEL(), and unknownMode32().

◆ bitsToFp() [1/2]

static double gem5::ArmISA::bitsToFp ( uint64_t  bits,
double  junk 
)
inlinestatic

Definition at line 196 of file vfp.hh.

References gem5::bits(), fp, and gem5::X86ISA::val.

◆ bitsToFp() [2/2]

static float gem5::ArmISA::bitsToFp ( uint64_t  bits,
float  junk 
)
inlinestatic

Definition at line 184 of file vfp.hh.

References gem5::bits(), fp, and gem5::X86ISA::val.

Referenced by gem5::ArmISA::FpOp::binaryOp(), gem5::ArmISA::FpOp::dbl(), fixDest(), fixDivDest(), fixFpDFpSDest(), fixFpSFpDDest(), flushToZero(), fpMulAdd(), fpRecipEstimate(), fprSqrtEstimate(), makeDouble(), gem5::ArmISA::FpOp::processNans(), gem5::ArmISA::FpOp::ternaryOp(), gem5::ArmISA::FpOp::unaryOp(), unsignedRecipEstimate(), unsignedRSqrtEstimate(), vcvtFpHFpD(), and vcvtFpHFpS().

◆ BitUnion32() [1/2]

gem5::ArmISA::BitUnion32 ( CPSR  )

◆ BitUnion32() [2/2]

gem5::ArmISA::BitUnion32 ( PackedIntReg  )

◆ BitUnion64() [1/2]

gem5::ArmISA::BitUnion64 ( CNTKCTL  )

◆ BitUnion64() [2/2]

gem5::ArmISA::BitUnion64 ( ExtMachInst  )

◆ BitUnion8() [1/2]

gem5::ArmISA::BitUnion8 ( ITSTATE  )

◆ BitUnion8() [2/2]

gem5::ArmISA::BitUnion8 ( OperatingMode64  )

◆ byteOrder()

ByteOrder gem5::ArmISA::byteOrder ( const ThreadContext *  tc)
inline

Definition at line 357 of file utility.hh.

References isBigEndian64().

Referenced by gem5::PowerProcess::argsInit(), gem5::ArmSemihosting::callElapsed32(), gem5::ArmSemihosting::callElapsed64(), gem5::ArmSemihosting::callGetCmdLine(), gem5::ArmSemihosting::callHeapInfo32(), gem5::ArmSemihosting::callHeapInfo64(), gem5::clock_gettimeFunc(), gem5::copyOutStat64Buf(), gem5::copyOutStatBuf(), gem5::copyOutStatfsBuf(), gem5::ArmISA::TableWalker::doL1Descriptor(), gem5::ArmISA::TableWalker::doL2Descriptor(), gem5::ArmISA::TableWalker::doLongDescriptor(), gem5::futimesatFunc(), gem5::guest_abi::Argument< Aapcs32, Composite, typename std::enable_if_t< IsAapcs32CompositeV< Composite > > >::get(), gem5::guest_abi::Argument< Aapcs64, Composite, typename std::enable_if_t< IsAapcs64CompositeV< Composite > &&!IsAapcs64HxaV< Composite > > >::get(), gem5::getrlimitFunc(), gem5::getrusageFunc(), gem5::gettimeofdayFunc(), gem5::PowerProcess::initState(), gem5::guest_abi::Aapcs32ArgumentBase::loadFromStack(), gem5::VirtDescriptor::operator=(), gem5::prlimitFunc(), gem5::readvFunc(), gem5::guest_abi::Result< Aapcs32, Integer, typename std::enable_if_t< std::is_integral_v< Integer > &&(sizeof(Integer)==sizeof(uint64_t))> >::store(), gem5::guest_abi::Result< Aapcs32, Composite, typename std::enable_if_t< IsAapcs32CompositeV< Composite > > >::store(), gem5::guest_abi::Result< Aapcs64, Composite, typename std::enable_if_t< IsAapcs64CompositeV< Composite > &&!IsAapcs64HxaV< Composite > > >::store(), gem5::timeFunc(), gem5::timesFunc(), and gem5::writevFunc().

◆ calculateBottomPACBit()

int gem5::ArmISA::calculateBottomPACBit ( ThreadContext *  tc,
ExceptionLevel  el,
bool  top_bit 
)

Definition at line 80 of file pauth_helpers.cc.

References el, EL1, EL2, gem5::ArmSystem::haveEL(), MISCREG_ID_AA64MMFR2_EL1, MISCREG_TCR_EL1, MISCREG_TCR_EL2, MISCREG_TCR_EL3, gem5::ThreadContext::readMiscReg(), s1TranslationRegime(), and upperAndLowerRange().

Referenced by addPAC(), auth(), and stripPAC().

◆ calculateTBI()

bool gem5::ArmISA::calculateTBI ( ThreadContext *  tc,
ExceptionLevel  el,
uint64_t  ptr,
bool  data 
)

Definition at line 50 of file pauth_helpers.cc.

References gem5::bits(), data, el, EL1, EL2, EL3, MISCREG_TCR_EL1, MISCREG_TCR_EL2, MISCREG_TCR_EL3, gem5::ThreadContext::readMiscReg(), s1TranslationRegime(), tbi, and upperAndLowerRange().

Referenced by addPAC(), auth(), and stripPAC().

◆ canReadCoprocReg()

std::tuple< bool, bool > gem5::ArmISA::canReadCoprocReg ( MiscRegIndex  reg,
SCR  scr,
CPSR  cpsr,
ThreadContext *  tc 
)

Check for permission to read coprocessor registers.

Checks whether an instruction at the current program mode has permissions to read the coprocessor registers. This function returns whether the check is undefined and if not whether the read access is permitted.

Parameters
themisc reg indicating the coprocessor
theSCR
theCPSR
thethread context on the core
Returns
a tuple of booleans: can_read, undefined

Definition at line 565 of file misc.cc.

References AArch32isUndefinedGenericTimer(), lookUpMiscReg, MISCREG_BANKED, MISCREG_CNTFRQ, MISCREG_CNTVOFF, MISCREG_HYP_NS_RD, MISCREG_MON_NS0_RD, MISCREG_MON_NS1_RD, MISCREG_PRI_NS_RD, MISCREG_PRI_S_RD, MISCREG_USR_NS_RD, MISCREG_USR_S_RD, MODE_ABORT, MODE_FIQ, MODE_HYP, MODE_IRQ, MODE_MON, MODE_SVC, MODE_SYSTEM, MODE_UNDEFINED, MODE_USER, and gem5::X86ISA::reg.

◆ canWriteCoprocReg()

std::tuple< bool, bool > gem5::ArmISA::canWriteCoprocReg ( MiscRegIndex  reg,
SCR  scr,
CPSR  cpsr,
ThreadContext *  tc 
)

Check for permission to write coprocessor registers.

Checks whether an instruction at the current program mode has permissions to write the coprocessor registers. This function returns whether the check is undefined and if not whether the write access is permitted.

Parameters
themisc reg indicating the coprocessor
theSCR
theCPSR
thethread context on the core
Returns
a tuple of booleans: can_write, undefined

Definition at line 612 of file misc.cc.

References AArch32isUndefinedGenericTimer(), lookUpMiscReg, MISCREG_BANKED, MISCREG_CNTFRQ, MISCREG_CNTVOFF, MISCREG_HYP_NS_WR, MISCREG_MON_NS0_WR, MISCREG_MON_NS1_WR, MISCREG_PRI_NS_WR, MISCREG_PRI_S_WR, MISCREG_USR_NS_WR, MISCREG_USR_S_WR, MODE_ABORT, MODE_FIQ, MODE_HYP, MODE_IRQ, MODE_MON, MODE_SVC, MODE_SYSTEM, MODE_UNDEFINED, MODE_USER, and gem5::X86ISA::reg.

◆ checkFaultAccessAArch64SysReg()

Fault gem5::ArmISA::checkFaultAccessAArch64SysReg ( MiscRegIndex  reg,
CPSR  cpsr,
ThreadContext *  tc,
const MiscRegOp64 &  inst 
)

Definition at line 729 of file misc.cc.

References currEL(), lookUpMiscReg, and gem5::X86ISA::reg.

Referenced by gem5::MiscRegImplDefined64::execute().

◆ cmp128()

static int gem5::ArmISA::cmp128 ( uint64_t  a0,
uint64_t  a1,
uint64_t  b0,
uint64_t  b1 
)
inlinestatic

Definition at line 213 of file fplib.cc.

References gem5::QARMA::b0, and gem5::QARMA::b1.

Referenced by fp64_div(), fp64_muladd(), and fp64_sqrt().

◆ computeAddrTop()

int gem5::ArmISA::computeAddrTop ( ThreadContext *  tc,
bool  selbit,
bool  is_instr,
TCR  tcr,
ExceptionLevel  el 
)

Definition at line 403 of file utility.cc.

References el, EL1, EL2, EL3, ELIs32(), ELIsInHost(), HaveExt(), MISCREG_TCR_EL2, MISCREG_TCR_EL3, gem5::ThreadContext::readMiscReg(), s1TranslationRegime(), tbi, and tbid.

Referenced by gem5::ArmISA::TableWalker::processWalkAArch64(), purifyTaggedAddr(), and gem5::ArmISA::MMU::translateMmuOff().

◆ condGenericTimerCommonEL0SystemAccessTrapEL2()

bool gem5::ArmISA::condGenericTimerCommonEL0SystemAccessTrapEL2 ( const MiscRegIndex  misc_reg,
ThreadContext *  tc 
)

Definition at line 1035 of file utility.cc.

References MISCREG_CNTFRQ, MISCREG_CNTFRQ_EL0, MISCREG_CNTHCTL_EL2, MISCREG_CNTP_CTL, MISCREG_CNTP_CTL_EL0, MISCREG_CNTP_TVAL_EL0, MISCREG_CNTP_TVAL_S, MISCREG_CNTPCT, MISCREG_CNTPCT_EL0, MISCREG_CNTV_CTL, MISCREG_CNTV_CTL_EL0, MISCREG_CNTV_TVAL, MISCREG_CNTV_TVAL_EL0, MISCREG_CNTVCT, MISCREG_CNTVCT_EL0, and gem5::ThreadContext::readMiscReg().

Referenced by isGenericTimerCommonEL0SystemAccessTrapEL2().

◆ condGenericTimerCommonEL1SystemAccessTrapEL2()

bool gem5::ArmISA::condGenericTimerCommonEL1SystemAccessTrapEL2 ( const MiscRegIndex  misc_reg,
ThreadContext *  tc 
)

Definition at line 1062 of file utility.cc.

References MISCREG_CNTHCTL_EL2, MISCREG_CNTP_CTL, MISCREG_CNTP_CTL_EL0, MISCREG_CNTP_TVAL_EL0, MISCREG_CNTP_TVAL_S, MISCREG_CNTPCT, MISCREG_CNTPCT_EL0, MISCREG_CNTV_CTL, MISCREG_CNTV_CTL_EL0, MISCREG_CNTV_TVAL, MISCREG_CNTV_TVAL_EL0, MISCREG_CNTVCT, MISCREG_CNTVCT_EL0, MISCREG_HCR_EL2, MISCREG_ID_AA64MMFR0_EL1, gem5::ThreadContext::readMiscReg(), and gem5::ThreadContext::readMiscRegNoEffect().

Referenced by isGenericTimerPhysEL0SystemAccessTrapEL2(), isGenericTimerPhysEL1SystemAccessTrapEL2(), and isGenericTimerVirtSystemAccessTrapEL2().

◆ condGenericTimerPhysEL1SystemAccessTrapEL2()

bool gem5::ArmISA::condGenericTimerPhysEL1SystemAccessTrapEL2 ( const MiscRegIndex  misc_reg,
ThreadContext *  tc 
)

Definition at line 1096 of file utility.cc.

References MISCREG_CNTHCTL_EL2, and gem5::ThreadContext::readMiscReg().

Referenced by isGenericTimerPhysEL0SystemAccessTrapEL2(), and isGenericTimerPhysEL1SystemAccessTrapEL2().

◆ condGenericTimerPhysHypTrap()

bool gem5::ArmISA::condGenericTimerPhysHypTrap ( const MiscRegIndex  misc_reg,
ThreadContext *  tc 
)

Definition at line 854 of file utility.cc.

References MISCREG_CNTHCTL_EL2, MISCREG_CNTP_CTL, MISCREG_CNTP_TVAL_S, MISCREG_CNTPCT, and gem5::ThreadContext::readMiscReg().

Referenced by isGenericTimerPhysHypTrap().

◆ condGenericTimerSystemAccessTrapEL1()

bool gem5::ArmISA::condGenericTimerSystemAccessTrapEL1 ( const MiscRegIndex  misc_reg,
ThreadContext *  tc 
)

Definition at line 888 of file utility.cc.

References MISCREG_CNTFRQ, MISCREG_CNTFRQ_EL0, MISCREG_CNTKCTL_EL1, MISCREG_CNTP_CTL, MISCREG_CNTP_CTL_EL0, MISCREG_CNTP_TVAL_EL0, MISCREG_CNTP_TVAL_S, MISCREG_CNTPCT, MISCREG_CNTPCT_EL0, MISCREG_CNTV_CTL, MISCREG_CNTV_CTL_EL0, MISCREG_CNTV_TVAL, MISCREG_CNTV_TVAL_EL0, MISCREG_CNTVCT, MISCREG_CNTVCT_EL0, and gem5::ThreadContext::readMiscReg().

Referenced by AArch32isUndefinedGenericTimer(), isGenericTimerCommonEL0HypTrap(), isGenericTimerCommonEL0SystemAccessTrapEL2(), and isGenericTimerSystemAccessTrapEL1().

◆ couldBeSP()

static bool gem5::ArmISA::couldBeSP ( RegIndex  reg)
inlinestatic

Definition at line 613 of file int.hh.

References gem5::X86ISA::reg, gem5::ArmISA::int_reg::Spx, and gem5::ArmISA::int_reg::X31.

◆ couldBeZero()

static bool gem5::ArmISA::couldBeZero ( RegIndex  reg)
inlinestatic

Definition at line 625 of file int.hh.

References gem5::X86ISA::reg, gem5::ArmISA::int_reg::X31, and gem5::ArmISA::int_reg::Zero.

◆ currEL() [1/2]

ExceptionLevel gem5::ArmISA::currEL ( const ThreadContext *  tc)

Returns the current Exception Level (EL) of the provided ThreadContext.

Definition at line 124 of file utility.cc.

References MISCREG_CPSR, opModeToEL(), and gem5::ThreadContext::readMiscRegNoEffect().

Referenced by AArch32isUndefinedGenericTimer(), AArch64AArch32SystemAccessTrap(), addPACDA(), addPACDB(), addPACGA(), addPACIA(), addPACIB(), authDA(), authDB(), authIA(), authIB(), gem5::ArmISA::ArmStaticInst::checkAdvSIMDOrFPEnabled32(), checkFaultAccessAArch64SysReg(), gem5::ArmISA::ArmStaticInst::checkFPAdvSIMDEnabled64(), gem5::ArmISA::ArmStaticInst::checkFPAdvSIMDTrap64(), gem5::ArmISA::Interrupts::checkInterrupts(), gem5::ArmISA::ArmStaticInst::checkSETENDEnabled(), gem5::Gicv3CPUInterface::currEL(), ELStateUsingAArch32K(), gem5::ArmISA::Interrupts::getInterrupt(), gem5::ArmISA::ArmStaticInst::getPSTATEFromPSR(), illegalExceptionReturn(), isAArch64AArch32SystemAccessTrapEL1(), isAArch64AArch32SystemAccessTrapEL2(), isBigEndian64(), gem5::ArmISA::SelfDebug::isDebugEnabled(), isGenericTimerHypTrap(), isGenericTimerSystemAccessTrapEL2(), isGenericTimerSystemAccessTrapEL3(), isSecure(), isUnpriviledgeAccess(), mcrMrc14TrapToHyp(), mcrMrc15TrapToHyp(), mcrrMrrc15TrapToHyp(), gem5::ArmISA::TLBIALL::operator()(), readMPIDR(), gem5::ArmISA::SupervisorTrap::routeToHyp(), gem5::ArmISA::PrefetchAbort::routeToHyp(), gem5::ArmISA::SPAlignmentFault::routeToHyp(), gem5::ArmISA::SelfDebug::setAArch32(), SPAlignmentCheckEnabled(), stripPAC(), gem5::ArmISA::Interrupts::takeInt(), gem5::ArmISA::SelfDebug::testBreakPoints(), gem5::ArmISA::BrkPoint::testContextMatch(), gem5::ArmISA::BrkPoint::testVMIDMatch(), gem5::ArmISA::SelfDebug::testWatchPoints(), gem5::fastmodel::CortexA76TC::translateAddress(), gem5::ArmISA::MMU::translateMmuOff(), gem5::ArmISA::MMU::tranTypeEL(), trapPACUse(), and gem5::ArmISA::ArmStaticInst::trapWFx().

◆ currEL() [2/2]

ExceptionLevel gem5::ArmISA::currEL ( CPSR  cpsr)
inline

Definition at line 119 of file utility.hh.

References opModeToEL().

◆ debugTargetFrom()

ExceptionLevel gem5::ArmISA::debugTargetFrom ( ThreadContext *  tc,
bool  secure 
)

Definition at line 93 of file utility.cc.

References EL1, EL2, EL3, gem5::ArmSystem::haveEL(), HaveExt(), gem5::ArmSystem::highestELIs64(), MISCREG_HCR_EL2, MISCREG_MDCR_EL2, gem5::ThreadContext::readMiscReg(), and gem5::ThreadContext::readMiscRegNoEffect().

Referenced by gem5::ArmISA::SoftwareStep::debugExceptionReturnSS(), and gem5::ArmISA::SelfDebug::targetAArch32().

◆ decode_fp_data_type()

static FpDataType gem5::ArmISA::decode_fp_data_type ( uint8_t  encoding)
inlinestatic

Definition at line 201 of file pred_inst.hh.

References encoding, Fp16, Fp32, Fp64, and panic.

◆ decodeAArch64SysReg() [1/2]

MiscRegIndex gem5::ArmISA::decodeAArch64SysReg ( const MiscRegNum64 &  sys_reg)

Definition at line 2171 of file misc.cc.

References gem5::ArmISA::MiscRegNum64::crn, MISCREG_IMPDEF_UNIMPL, MISCREG_UNKNOWN, and gem5::ArmISA::MiscRegNum64::op0.

◆ decodeAArch64SysReg() [2/2]

MiscRegIndex gem5::ArmISA::decodeAArch64SysReg ( unsigned  op0,
unsigned  op1,
unsigned  crn,
unsigned  crm,
unsigned  op2 
)

Definition at line 2162 of file misc.cc.

Referenced by gem5::ArmV8KvmCPU::dump(), gem5::ArmV8KvmCPU::getSysRegMap(), and gem5::MiscRegImplDefined64::MiscRegImplDefined64().

◆ decodeCP14Reg()

MiscRegIndex gem5::ArmISA::decodeCP14Reg ( unsigned  crn,
unsigned  opc1,
unsigned  crm,
unsigned  opc2 
)

Definition at line 520 of file misc.cc.

References MISCREG_UNKNOWN, opc2, and warn.

Referenced by gem5::ArmKvmCPU::decodeCoProcReg().

◆ decodeCP15Reg()

MiscRegIndex gem5::ArmISA::decodeCP15Reg ( unsigned  crn,
unsigned  opc1,
unsigned  crm,
unsigned  opc2 
)

Definition at line 534 of file misc.cc.

References MISCREG_IMPDEF_UNIMPL, MISCREG_UNKNOWN, and opc2.

Referenced by gem5::ArmKvmCPU::decodeCoProcReg().

◆ decodeCP15Reg64()

MiscRegIndex gem5::ArmISA::decodeCP15Reg64 ( unsigned  crm,
unsigned  opc1 
)

Definition at line 553 of file misc.cc.

References MISCREG_UNKNOWN.

◆ decodeMrsMsrBankedIntRegIndex()

static int gem5::ArmISA::decodeMrsMsrBankedIntRegIndex ( uint8_t  sysM,
bool  r 
)
inlinestatic

Definition at line 335 of file utility.hh.

References decodeMrsMsrBankedReg(), gem5::VegaISA::r, and gem5::ArmISA::int_reg::Zero.

◆ decodeMrsMsrBankedReg()

bool gem5::ArmISA::decodeMrsMsrBankedReg ( uint8_t  sysM,
bool  r,
bool &  isIntReg,
int &  regIdx,
CPSR  cpsr,
SCR  scr,
NSACR  nsacr,
bool  checkSecurity 
)

Definition at line 1120 of file utility.cc.

References gem5::bits(), MISCREG_ELR_HYP, MISCREG_SPSR_ABT, MISCREG_SPSR_FIQ, MISCREG_SPSR_HYP, MISCREG_SPSR_IRQ, MISCREG_SPSR_MON, MISCREG_SPSR_SVC, MISCREG_SPSR_UND, mode, MODE_ABORT, MODE_FIQ, MODE_HYP, MODE_IRQ, MODE_MON, MODE_SVC, MODE_SYSTEM, MODE_UNDEFINED, MODE_USER, panic, gem5::VegaISA::r, and gem5::ArmISA::int_reg::regInMode().

Referenced by decodeMrsMsrBankedIntRegIndex().

◆ decodePhysAddrRange64()

int gem5::ArmISA::decodePhysAddrRange64 ( uint8_t  pa_enc)

Returns the n.

of PA bits corresponding to the specified encoding.

Definition at line 1279 of file utility.cc.

References panic.

Referenced by gem5::ArmISA::TableWalker::processWalkAArch64().

◆ defaultFaultE2H_EL2()

static Fault gem5::ArmISA::defaultFaultE2H_EL2 ( const MiscRegLUTEntry &  entry,
ThreadContext *  tc,
const MiscRegOp64 &  inst 
)
static

Definition at line 2219 of file misc.cc.

References MISCREG_HCR_EL2, gem5::NoFault, gem5::ThreadContext::readMiscRegNoEffect(), and gem5::ArmISA::ArmStaticInst::undefined().

◆ defaultFaultE2H_EL3()

static Fault gem5::ArmISA::defaultFaultE2H_EL3 ( const MiscRegLUTEntry &  entry,
ThreadContext *  tc,
const MiscRegOp64 &  inst 
)
static

Definition at line 2231 of file misc.cc.

References EL2Enabled(), MISCREG_HCR_EL2, gem5::NoFault, gem5::ThreadContext::readMiscRegNoEffect(), and gem5::ArmISA::ArmStaticInst::undefined().

◆ EL2Enabled()

bool gem5::ArmISA::EL2Enabled ( ThreadContext *  tc)

Definition at line 258 of file utility.cc.

References EL2, EL3, gem5::ArmSystem::haveEL(), IsSecureEL2Enabled(), MISCREG_SCR_EL3, ns, and gem5::ThreadContext::readMiscRegNoEffect().

Referenced by AArch32isUndefinedGenericTimer(), AArch64AArch32SystemAccessTrap(), addPACDA(), addPACDB(), addPACGA(), addPACIA(), addPACIB(), authDA(), authDB(), authIA(), authIB(), gem5::ArmISA::ArmStaticInst::checkFPAdvSIMDTrap64(), gem5::ArmISA::ArmStaticInst::checkSmeAccess(), gem5::ArmISA::ArmStaticInst::checkSmeEnabled(), gem5::ArmISA::ArmStaticInst::checkSveEnabled(), defaultFaultE2H_EL3(), isGenericTimerHypTrap(), isGenericTimerSystemAccessTrapEL1(), mcrMrc14TrapToHyp(), mcrMrc15TrapToHyp(), mcrrMrrc15TrapToHyp(), gem5::ArmISA::ArmFaultVals< FastInterrupt >::offset64(), gem5::ArmISA::TLBIALL::operator()(), gem5::ArmISA::ITLBIALL::operator()(), gem5::ArmISA::DTLBIALL::operator()(), gem5::ArmISA::TLBIVMALL::operator()(), gem5::ArmISA::TLBIASID::operator()(), gem5::ArmISA::ITLBIASID::operator()(), gem5::ArmISA::DTLBIASID::operator()(), gem5::TlbiOp64::performTlbi(), gem5::ArmISA::ISA::readMiscReg(), readMPIDR(), gem5::ArmISA::UndefinedInstruction::routeToHyp(), gem5::ArmISA::SupervisorCall::routeToHyp(), gem5::ArmISA::SupervisorTrap::routeToHyp(), gem5::ArmISA::DataAbort::routeToHyp(), gem5::ArmISA::Interrupt::routeToHyp(), gem5::ArmISA::FastInterrupt::routeToHyp(), gem5::ArmISA::PCAlignmentFault::routeToHyp(), gem5::ArmISA::SPAlignmentFault::routeToHyp(), gem5::ArmISA::SystemError::routeToHyp(), gem5::ArmISA::SoftwareBreakpoint::routeToHyp(), gem5::ArmISA::HardwareBreakpoint::routeToHyp(), gem5::ArmISA::Watchpoint::routeToHyp(), gem5::ArmISA::SoftwareStepFault::routeToHyp(), gem5::ArmISA::IllegalInstSetStateFault::routeToHyp(), gem5::ArmISA::ArmStaticInst::softwareBreakpoint32(), gem5::ArmISA::BrkPoint::test(), and gem5::ArmISA::ArmStaticInst::trapWFx().

◆ ELIs32()

bool gem5::ArmISA::ELIs32 ( ThreadContext *  tc,
ExceptionLevel  el 
)

Definition at line 273 of file utility.cc.

References el, ELUsingAArch32K(), and panic_if.

Referenced by AArch32isUndefinedGenericTimer(), AArch64AArch32SystemAccessTrap(), computeAddrTop(), gem5::ArmISA::SoftwareStep::debugExceptionReturnSS(), ELIs64(), ELIsInHost(), gem5::ArmISA::ArmStaticInst::generalExceptionsToAArch64(), isGenericTimerCommonEL0HypTrap(), isGenericTimerCommonEL0SystemAccessTrapEL2(), isGenericTimerHypTrap(), isGenericTimerSystemAccessTrapEL1(), isGenericTimerVirtSystemAccessTrapEL2(), IsSecureEL2Enabled(), gem5::ArmISA::ArmFaultVals< FastInterrupt >::offset64(), gem5::ArmISA::ISA::readMiscReg(), s1TranslationRegime(), gem5::ArmISA::SelfDebug::setAArch32(), gem5::ArmISA::ISA::setMiscReg(), gem5::ArmISA::ArmStaticInst::softwareBreakpoint32(), and gem5::ArmISA::SelfDebug::targetAArch32().

◆ ELIs64()

bool gem5::ArmISA::ELIs64 ( ThreadContext *  tc,
ExceptionLevel  el 
)

Definition at line 267 of file utility.cc.

References el, and ELIs32().

Referenced by gem5::ArmISA::ArmStaticInst::checkAdvSIMDOrFPEnabled32(), gem5::ArmISA::ArmStaticInst::checkForWFxTrap32(), gem5::ArmISA::Stage2LookUp::getTe(), gem5::ArmISA::MMU::CachedState::getVMID(), illegalExceptionReturn(), gem5::ArmISA::ArmFault::update(), gem5::ArmISA::MMU::CachedState::updateMiscReg(), and gem5::ArmISA::TableWalker::walk().

◆ ELIsInHost()

bool gem5::ArmISA::ELIsInHost ( ThreadContext *  tc,
ExceptionLevel  el 
)

Returns true if the current exception level el is executing a Host OS or an application of a Host OS (Armv8.1 Virtualization Host Extensions).

Definition at line 281 of file utility.cc.

References el, EL0, EL2, ELIs32(), gem5::ArmSystem::haveEL(), HaveExt(), isSecureBelowEL3(), IsSecureEL2Enabled(), MISCREG_HCR_EL2, and gem5::ThreadContext::readMiscReg().

Referenced by gem5::ArmISA::ArmStaticInst::checkFPAdvSIMDEnabled64(), gem5::ArmISA::ArmStaticInst::checkSmeAccess(), gem5::ArmISA::ArmStaticInst::checkSmeEnabled(), gem5::ArmISA::ArmStaticInst::checkSveEnabled(), computeAddrTop(), gem5::ArmISA::ISA::getCurSmeVecLenInBits(), gem5::ArmISA::ISA::getCurSveVecLenInBits(), maskTaggedAddr(), gem5::ArmISA::ArmFaultVals< FastInterrupt >::offset64(), gem5::ArmISA::ISA::redirectRegVHE(), s1TranslationRegime(), and gem5::ArmISA::BrkPoint::test().

◆ ELStateUsingAArch32()

bool gem5::ArmISA::ELStateUsingAArch32 ( ThreadContext *  tc,
ExceptionLevel  el,
bool  secure 
)

Definition at line 365 of file utility.cc.

References el, ELStateUsingAArch32K(), and panic_if.

Referenced by gem5::ArmISA::SelfDebug::isDebugEnabledForEL32().

◆ ELStateUsingAArch32K()

std::pair< bool, bool > gem5::ArmISA::ELStateUsingAArch32K ( ThreadContext *  tc,
ExceptionLevel  el,
bool  secure 
)

Definition at line 313 of file utility.cc.

References currEL(), el, EL0, EL1, EL2, EL3, haveAArch32EL(), gem5::ArmSystem::haveEL(), HaveExt(), gem5::ArmSystem::highestEL(), gem5::ArmSystem::highestELIs64(), MISCREG_CPSR, MISCREG_HCR_EL2, MISCREG_SCR_EL3, panic_if, and gem5::ThreadContext::readMiscReg().

Referenced by ELStateUsingAArch32(), and ELUsingAArch32K().

◆ ELUsingAArch32K()

std::pair< bool, bool > gem5::ArmISA::ELUsingAArch32K ( ThreadContext *  tc,
ExceptionLevel  el 
)

This function checks whether selected EL provided as an argument is using the AArch32 ISA.

This information might be unavailable at the current EL status: it hence returns a pair of boolean values: a first boolean, true if information is available (known), and a second one, true if EL is using AArch32, false for AArch64.

Parameters
tcThe thread context.
elThe target exception level.
Return values
knownis FALSE for EL0 if the current Exception level is not EL0 and EL1 is using AArch64, since it cannot determine the state of EL0; TRUE otherwise.
aarch32is TRUE if the specified Exception level is using AArch32; FALSE otherwise.

Definition at line 292 of file utility.cc.

References el, ELStateUsingAArch32K(), and isSecureBelowEL3().

Referenced by ELIs32(), and illegalExceptionReturn().

◆ encodeAArch64SysReg()

MiscRegNum64 gem5::ArmISA::encodeAArch64SysReg ( MiscRegIndex  misc_reg)

Definition at line 2188 of file misc.cc.

References panic.

Referenced by gem5::ArmISA::SysDC64::iss(), gem5::MiscRegRegImmOp64::iss(), gem5::RegMiscRegImmOp64::iss(), gem5::KvmKernelGicV3::readCpu(), and gem5::KvmKernelGicV3::writeCpu().

◆ encodePhysAddrRange64()

uint8_t gem5::ArmISA::encodePhysAddrRange64 ( int  pa_size)

Returns the encoding corresponding to the specified n.

of PA bits.

Definition at line 1302 of file utility.cc.

References panic.

◆ EndBitUnion() [1/53]

gem5::ArmISA::EndBitUnion ( AA64DFR0  )

◆ EndBitUnion() [2/53]

gem5::ArmISA::EndBitUnion ( AA64ISAR0  )

◆ EndBitUnion() [3/53]

gem5::ArmISA::EndBitUnion ( AA64ISAR1  )

◆ EndBitUnion() [4/53]

gem5::ArmISA::EndBitUnion ( AA64MMFR0  )

◆ EndBitUnion() [5/53]

gem5::ArmISA::EndBitUnion ( AA64MMFR1  )

◆ EndBitUnion() [6/53]

gem5::ArmISA::EndBitUnion ( AA64MMFR2  )

◆ EndBitUnion() [7/53]

gem5::ArmISA::EndBitUnion ( AA64PFR0  )

◆ EndBitUnion() [8/53]

gem5::ArmISA::EndBitUnion ( AA64SMFR0  )

◆ EndBitUnion() [9/53]

gem5::ArmISA::EndBitUnion ( AA64ZFR0  )

◆ EndBitUnion() [10/53]

gem5::ArmISA::EndBitUnion ( Affinity  )

Definition at line 210 of file types.hh.

◆ EndBitUnion() [11/53]

gem5::ArmISA::EndBitUnion ( CNTHCTL  )

◆ EndBitUnion() [12/53]

gem5::ArmISA::EndBitUnion ( CNTKCTL  )

◆ EndBitUnion() [13/53]

gem5::ArmISA::EndBitUnion ( CONTEXTIDR  )

◆ EndBitUnion() [14/53]

gem5::ArmISA::EndBitUnion ( CPACR  )

◆ EndBitUnion() [15/53]

gem5::ArmISA::EndBitUnion ( CPSR  )

◆ EndBitUnion() [16/53]

gem5::ArmISA::EndBitUnion ( CPTR  )

◆ EndBitUnion() [17/53]

gem5::ArmISA::EndBitUnion ( CTR  )

◆ EndBitUnion() [18/53]

gem5::ArmISA::EndBitUnion ( DBGBCR  )

◆ EndBitUnion() [19/53]

gem5::ArmISA::EndBitUnion ( DBGDS32  )

◆ EndBitUnion() [20/53]

gem5::ArmISA::EndBitUnion ( DBGVCR  )

◆ EndBitUnion() [21/53]

gem5::ArmISA::EndBitUnion ( DBGWCR  )

◆ EndBitUnion() [22/53]

gem5::ArmISA::EndBitUnion ( ExtMachInst  )

◆ EndBitUnion() [23/53]

gem5::ArmISA::EndBitUnion ( FPEXC  )

◆ EndBitUnion() [24/53]

gem5::ArmISA::EndBitUnion ( FPSCR  )

◆ EndBitUnion() [25/53]

gem5::ArmISA::EndBitUnion ( FSR  )

◆ EndBitUnion() [26/53]

gem5::ArmISA::EndBitUnion ( HCPTR  )

◆ EndBitUnion() [27/53]

gem5::ArmISA::EndBitUnion ( HCR  )

◆ EndBitUnion() [28/53]

gem5::ArmISA::EndBitUnion ( HDCR  )

◆ EndBitUnion() [29/53]

gem5::ArmISA::EndBitUnion ( HSTR  )

◆ EndBitUnion() [30/53]

gem5::ArmISA::EndBitUnion ( HTCR  )

◆ EndBitUnion() [31/53]

gem5::ArmISA::EndBitUnion ( ISAR5  )

◆ EndBitUnion() [32/53]

gem5::ArmISA::EndBitUnion ( ISAR6  )

◆ EndBitUnion() [33/53]

gem5::ArmISA::EndBitUnion ( L2CTLR  )

◆ EndBitUnion() [34/53]

gem5::ArmISA::EndBitUnion ( MVFR0  )

◆ EndBitUnion() [35/53]

gem5::ArmISA::EndBitUnion ( MVFR1  )

◆ EndBitUnion() [36/53]

gem5::ArmISA::EndBitUnion ( NMRR  )

◆ EndBitUnion() [37/53]

gem5::ArmISA::EndBitUnion ( NSACR  )

◆ EndBitUnion() [38/53]

gem5::ArmISA::EndBitUnion ( OperatingMode64  )

Definition at line 369 of file types.hh.

References mode.

◆ EndBitUnion() [39/53]

gem5::ArmISA::EndBitUnion ( OSL  )

◆ EndBitUnion() [40/53]

gem5::ArmISA::EndBitUnion ( PackedIntReg  )

Definition at line 65 of file int.hh.

References gem5::PowerISA::int_reg::_R0Idx, gem5::PowerISA::int_reg::_R10Idx, gem5::PowerISA::int_reg::_R11Idx, gem5::PowerISA::int_reg::_R12Idx, gem5::PowerISA::int_reg::_R13Idx, gem5::PowerISA::int_reg::_R14Idx, gem5::PowerISA::int_reg::_R15Idx, gem5::PowerISA::int_reg::_R1Idx, gem5::PowerISA::int_reg::_R2Idx, gem5::PowerISA::int_reg::_R3Idx, gem5::PowerISA::int_reg::_R4Idx, gem5::PowerISA::int_reg::_R5Idx, gem5::PowerISA::int_reg::_R6Idx, gem5::PowerISA::int_reg::_R7Idx, gem5::PowerISA::int_reg::_R8Idx, gem5::PowerISA::int_reg::_R9Idx, gem5::SparcISA::int_reg::_Ureg0Idx, gem5::RiscvISA::int_reg::_ZeroIdx, gem5::SparcISA::int_reg::NumArchRegs, and gem5::SparcISA::int_reg::NumRegs.

◆ EndBitUnion() [41/53]

gem5::ArmISA::EndBitUnion ( PAR  )

◆ EndBitUnion() [42/53]

gem5::ArmISA::EndBitUnion ( PMSELR  )

◆ EndBitUnion() [43/53]

gem5::ArmISA::EndBitUnion ( PRRR  )

◆ EndBitUnion() [44/53]

gem5::ArmISA::EndBitUnion ( SCR  )

◆ EndBitUnion() [45/53]

gem5::ArmISA::EndBitUnion ( SCTLR  )

◆ EndBitUnion() [46/53]

gem5::ArmISA::EndBitUnion ( SMCR  )

◆ EndBitUnion() [47/53]

gem5::ArmISA::EndBitUnion ( SMIDR  )

◆ EndBitUnion() [48/53]

gem5::ArmISA::EndBitUnion ( SMPRI  )

◆ EndBitUnion() [49/53]

gem5::ArmISA::EndBitUnion ( SVCR  )

◆ EndBitUnion() [50/53]

gem5::ArmISA::EndBitUnion ( TCR  )

◆ EndBitUnion() [51/53]

gem5::ArmISA::EndBitUnion ( TTBCR  )

◆ EndBitUnion() [52/53]

gem5::ArmISA::EndBitUnion ( VTCR_t  )

◆ EndBitUnion() [53/53]

gem5::ArmISA::EndBitUnion ( ZCR  )

◆ EndSubBitUnion() [1/6]

gem5::ArmISA::EndSubBitUnion ( cond_iss  )

◆ EndSubBitUnion() [2/6]

gem5::ArmISA::EndSubBitUnion ( data_abort_iss  )

◆ EndSubBitUnion() [3/6]

gem5::ArmISA::EndSubBitUnion ( instruction_abort_iss  )

◆ EndSubBitUnion() [4/6]

gem5::ArmISA::EndSubBitUnion ( puswl  )

◆ EndSubBitUnion() [5/6]

gem5::ArmISA::EndSubBitUnion ( software_step_iss  )

◆ EndSubBitUnion() [6/6]

gem5::ArmISA::EndSubBitUnion ( watchpoint_iss  )

◆ finishVfp()

void gem5::ArmISA::finishVfp ( FPSCR &  fpscr,
VfpSavedState  state,
bool  flush,
FPSCR  mask 
)

Definition at line 205 of file vfp.cc.

References FeAllExceptions, FeDivByZero, FeInexact, FeInvalid, FeOverflow, FeUnderflow, mask, and state.

Referenced by gem5::ArmISA::FpOp::binaryOp(), gem5::ArmISA::FpOp::ternaryOp(), and gem5::ArmISA::FpOp::unaryOp().

◆ fixDest() [1/4]

template<class fpType >
fpType gem5::ArmISA::fixDest ( bool  flush,
bool  defaultNan,
fpType  val,
fpType  op1 
)

Definition at line 231 of file vfp.cc.

References bitsToFp(), FeInexact, FeUnderflow, fpToBits(), and gem5::X86ISA::val.

Referenced by fixDivDest(), fixFpDFpSDest(), and fixFpSFpDDest().

◆ fixDest() [2/4]

template<class fpType >
fpType gem5::ArmISA::fixDest ( bool  flush,
bool  defaultNan,
fpType  val,
fpType  op1,
fpType  op2 
)

Definition at line 261 of file vfp.cc.

References bitsToFp(), FeInexact, FeUnderflow, fpToBits(), and gem5::X86ISA::val.

◆ fixDest() [3/4]

template<class fpType >
fpType gem5::ArmISA::fixDest ( FPSCR  fpscr,
fpType  val,
fpType  op1 
)

◆ fixDest() [4/4]

template<class fpType >
fpType gem5::ArmISA::fixDest ( FPSCR  fpscr,
fpType  val,
fpType  op1,
fpType  op2 
)

◆ fixDest< double >() [1/2]

template double gem5::ArmISA::fixDest< double > ( bool  flush,
bool  defaultNan,
double  val,
double  op1 
)

◆ fixDest< double >() [2/2]

template double gem5::ArmISA::fixDest< double > ( bool  flush,
bool  defaultNan,
double  val,
double  op1,
double  op2 
)

◆ fixDest< float >() [1/2]

template float gem5::ArmISA::fixDest< float > ( bool  flush,
bool  defaultNan,
float  val,
float  op1 
)

◆ fixDest< float >() [2/2]

template float gem5::ArmISA::fixDest< float > ( bool  flush,
bool  defaultNan,
float  val,
float  op1,
float  op2 
)

◆ fixDivDest() [1/2]

template<class fpType >
fpType gem5::ArmISA::fixDivDest ( bool  flush,
bool  defaultNan,
fpType  val,
fpType  op1,
fpType  op2 
)

Definition at line 302 of file vfp.cc.

References bitsToFp(), FeInexact, FeRoundZero, FeUnderflow, fixDest(), flushToZero, and gem5::X86ISA::val.

Referenced by vfpSFixedToFpD(), vfpSFixedToFpS(), vfpUFixedToFpD(), and vfpUFixedToFpS().

◆ fixDivDest() [2/2]

template<class fpType >
fpType gem5::ArmISA::fixDivDest ( FPSCR  fpscr,
fpType  val,
fpType  op1,
fpType  op2 
)

◆ fixDivDest< double >()

template double gem5::ArmISA::fixDivDest< double > ( bool  flush,
bool  defaultNan,
double  val,
double  op1,
double  op2 
)

◆ fixDivDest< float >()

template float gem5::ArmISA::fixDivDest< float > ( bool  flush,
bool  defaultNan,
float  val,
float  op1,
float  op2 
)

◆ fixFpDFpSDest()

float gem5::ArmISA::fixFpDFpSDest ( FPSCR  fpscr,
double  val 
)

Definition at line 337 of file vfp.cc.

References gem5::bits(), bitsToFp(), FeInexact, FeRoundZero, FeUnderflow, fixDest(), flushToZero, fpToBits(), mask, and gem5::X86ISA::val.

◆ fixFpSFpDDest()

double gem5::ArmISA::fixFpSFpDDest ( FPSCR  fpscr,
float  val 
)

Definition at line 373 of file vfp.cc.

References gem5::bits(), bitsToFp(), FeInexact, FeRoundZero, FeUnderflow, fixDest(), flushToZero, fpToBits(), mask, and gem5::X86ISA::val.

◆ flattenIntRegModeIndex()

static const RegId& gem5::ArmISA::flattenIntRegModeIndex ( int  reg)
inlinestatic

Definition at line 575 of file int.hh.

References gem5::ArmISA::int_reg::abt(), gem5::curTick(), gem5::ArmISA::int_reg::fiq(), gem5::ArmISA::int_reg::hyp(), gem5::ArmISA::int_reg::irq(), mode, MODE_ABORT, MODE_FIQ, MODE_HYP, MODE_IRQ, MODE_MON, MODE_SVC, MODE_SYSTEM, MODE_UNDEFINED, MODE_USER, gem5::ArmISA::int_reg::mon(), panic, gem5::X86ISA::reg, gem5::ArmISA::int_reg::regsPerMode, gem5::ArmISA::int_reg::svc(), gem5::ArmISA::int_reg::und(), and gem5::ArmISA::int_reg::usr().

Referenced by gem5::ArmISA::IntRegClassOps::flatten().

◆ flushToZero() [1/2]

template<class fpType >
static bool gem5::ArmISA::flushToZero ( fpType &  op)
inlinestatic

Definition at line 122 of file vfp.hh.

References bitsToFp(), fpToBits(), and gem5::X86ISA::op.

◆ flushToZero() [2/2]

template<class fpType >
static bool gem5::ArmISA::flushToZero ( fpType &  op1,
fpType &  op2 
)
inlinestatic

Definition at line 135 of file vfp.hh.

References flushToZero.

◆ fp128_normalise()

static void gem5::ArmISA::fp128_normalise ( uint64_t *  mnt0,
uint64_t *  mnt1,
int *  exp 
)
inlinestatic

Definition at line 273 of file fplib.cc.

References shift.

Referenced by fp64_mul(), and fp64_muladd().

◆ fp16_add()

static uint16_t gem5::ArmISA::fp16_add ( uint16_t  a,
uint16_t  b,
int  neg,
int  mode,
int *  flags 
)
static

Definition at line 1223 of file fplib.cc.

References a, b, flags, fp16_defaultNaN(), FP16_EXP_BITS, FP16_EXP_INF, fp16_infinity(), fp16_normalise(), fp16_process_NaNs(), fp16_round(), fp16_unpack(), fp16_zero(), FPLIB_IOC, lsl16(), lsr16(), mode, sc_dt::neg(), and gem5::VegaISA::x.

Referenced by fplibAdd(), and fplibSub().

◆ fp16_compare_eq()

static int gem5::ArmISA::fp16_compare_eq ( uint16_t  a,
uint16_t  b,
int  mode,
int *  flags 
)
static

Definition at line 959 of file fplib.cc.

References a, b, flags, fp16_is_NaN(), fp16_is_signalling_NaN(), fp16_unpack(), FPLIB_IOC, and mode.

Referenced by fplibCompareEQ().

◆ fp16_compare_ge()

static int gem5::ArmISA::fp16_compare_ge ( uint16_t  a,
uint16_t  b,
int  mode,
int *  flags 
)
static

Definition at line 978 of file fplib.cc.

References a, b, flags, fp16_is_NaN(), fp16_unpack(), FPLIB_IOC, and mode.

Referenced by fplibCompareGE().

◆ fp16_compare_gt()

static int gem5::ArmISA::fp16_compare_gt ( uint16_t  a,
uint16_t  b,
int  mode,
int *  flags 
)
static

Definition at line 1003 of file fplib.cc.

References a, b, flags, fp16_is_NaN(), fp16_unpack(), FPLIB_IOC, and mode.

Referenced by fplibCompareGT().

◆ fp16_compare_un()

static int gem5::ArmISA::fp16_compare_un ( uint16_t  a,
uint16_t  b,
int  mode,
int *  flags 
)
static

Definition at line 1028 of file fplib.cc.

References a, b, flags, fp16_is_NaN(), fp16_is_signalling_NaN(), fp16_unpack(), FPLIB_IOC, and mode.

Referenced by fplibCompareUN().

◆ fp16_cvtf()

static uint16_t gem5::ArmISA::fp16_cvtf ( uint64_t  a,
int  fbits,
int  u,
int  mode,
int *  flags 
)
static

Definition at line 4908 of file fplib.cc.

References a, flags, FP16_BITS, FP16_EXP_BIAS, fp16_round(), fp16_zero(), FP64_BITS, fp64_normalise(), mode, and u.

Referenced by fplibFixedToFP().

◆ fp16_defaultNaN()

static uint16_t gem5::ArmISA::fp16_defaultNaN ( )
inlinestatic

Definition at line 374 of file fplib.cc.

References FP16_EXP_INF, FP16_MANT_BITS, and fp16_pack().

Referenced by fp16_add(), fp16_div(), fp16_mul(), fp16_muladd(), fp16_process_NaN(), fp16_sqrt(), fplibConvert(), fplibDefaultNaN(), and fplibRSqrtEstimate().

◆ fp16_div()

static uint16_t gem5::ArmISA::fp16_div ( uint16_t  a,
uint16_t  b,
int  mode,
int *  flags 
)
static

Definition at line 1776 of file fplib.cc.

References a, b, flags, FP16_BITS, fp16_defaultNaN(), FP16_EXP_BIAS, FP16_EXP_BITS, FP16_EXP_INF, fp16_infinity(), FP16_MANT_BITS, fp16_normalise(), fp16_process_NaNs(), fp16_round(), fp16_unpack(), fp16_zero(), fp32_normalise(), FPLIB_DZC, FPLIB_IOC, mode, and gem5::VegaISA::x.

Referenced by fplibDiv().

◆ fp16_FPConvertNaN_32()

static uint16_t gem5::ArmISA::fp16_FPConvertNaN_32 ( uint32_t  op)
static

Definition at line 2524 of file fplib.cc.

References FP16_EXP_INF, FP16_MANT_BITS, fp16_pack(), FP32_BITS, FP32_MANT_BITS, and gem5::X86ISA::op.

Referenced by fplibConvert().

◆ fp16_FPConvertNaN_64()

static uint16_t gem5::ArmISA::fp16_FPConvertNaN_64 ( uint64_t  op)
static

Definition at line 2532 of file fplib.cc.

References FP16_EXP_INF, FP16_MANT_BITS, fp16_pack(), FP64_BITS, FP64_MANT_BITS, and gem5::X86ISA::op.

Referenced by fplibConvert().

◆ fp16_FPOnePointFive()

static uint16_t gem5::ArmISA::fp16_FPOnePointFive ( int  sgn)
static

Definition at line 2572 of file fplib.cc.

References FP16_EXP_BIAS, FP16_MANT_BITS, and fp16_pack().

Referenced by fplibRSqrtStepFused().

◆ fp16_FPThree()

static uint16_t gem5::ArmISA::fp16_FPThree ( int  sgn)
static

Definition at line 2590 of file fplib.cc.

References FP16_EXP_BIAS, FP16_MANT_BITS, and fp16_pack().

Referenced by fplibRSqrtStepFused().

◆ fp16_FPTwo()

static uint16_t gem5::ArmISA::fp16_FPTwo ( int  sgn)
static

Definition at line 2608 of file fplib.cc.

References FP16_EXP_BIAS, and fp16_pack().

Referenced by fplibMulX(), and fplibRecipStepFused().

◆ fp16_infinity()

static uint16_t gem5::ArmISA::fp16_infinity ( int  sgn)
inlinestatic

Definition at line 356 of file fplib.cc.

References FP16_EXP_INF, and fp16_pack().

Referenced by fp16_add(), fp16_div(), fp16_minmaxnum(), fp16_mul(), fp16_muladd(), fp16_round_(), fp16_scale(), fp16_sqrt(), fplibConvert(), fplibInfinity(), fplibMulX(), fplibRecipEstimate(), fplibRecipStepFused(), fplibRoundInt(), fplibRSqrtEstimate(), and fplibRSqrtStepFused().

◆ fp16_is_infinity()

static int gem5::ArmISA::fp16_is_infinity ( int  exp,
uint16_t  mnt 
)
inlinestatic

Definition at line 517 of file fplib.cc.

References FP16_EXP_INF, and FP16_MANT.

Referenced by fp16_muladd().

◆ fp16_is_NaN()

static int gem5::ArmISA::fp16_is_NaN ( int  exp,
uint16_t  mnt 
)
inlinestatic

Definition at line 463 of file fplib.cc.

References FP16_EXP_INF, and FP16_MANT.

Referenced by fp16_compare_eq(), fp16_compare_ge(), fp16_compare_gt(), fp16_compare_un(), fp16_is_signalling_NaN(), fp16_process_NaNs(), fp16_process_NaNs3(), fp16_scale(), fp16_sqrt(), fplibCompare(), fplibConvert(), fplibFPToFixed(), fplibRecipEstimate(), fplibRecpX(), fplibRoundInt(), fplibRSqrtEstimate(), and fplibTrigSMul().

◆ fp16_is_quiet_NaN()

static int gem5::ArmISA::fp16_is_quiet_NaN ( int  exp,
uint16_t  mnt 
)
inlinestatic

Definition at line 499 of file fplib.cc.

References FP16_EXP_INF, and FP16_MANT_BITS.

Referenced by fp16_muladd().

◆ fp16_is_signalling_NaN()

static int gem5::ArmISA::fp16_is_signalling_NaN ( int  exp,
uint16_t  mnt 
)
inlinestatic

Definition at line 481 of file fplib.cc.

References fp16_is_NaN(), and FP16_MANT_BITS.

Referenced by fp16_compare_eq(), fp16_compare_un(), fp16_process_NaNs(), fp16_process_NaNs3(), and fplibCompare().

◆ fp16_max_normal()

static uint16_t gem5::ArmISA::fp16_max_normal ( int  sgn)
inlinestatic

Definition at line 338 of file fplib.cc.

References FP16_EXP_INF, and fp16_pack().

Referenced by fp16_round_(), and fplibRecipEstimate().

◆ fp16_minmaxnum()

static void gem5::ArmISA::fp16_minmaxnum ( uint16_t *  op1,
uint16_t *  op2,
int  sgn 
)
static

Definition at line 3145 of file fplib.cc.

References fp16_infinity(), and FP16_MANT_BITS.

Referenced by fplibMaxNum(), and fplibMinNum().

◆ fp16_mul()

static uint16_t gem5::ArmISA::fp16_mul ( uint16_t  a,
uint16_t  b,
int  mode,
int *  flags 
)
static

Definition at line 1403 of file fplib.cc.

References a, b, flags, FP16_BITS, fp16_defaultNaN(), FP16_EXP_BIAS, FP16_EXP_BITS, FP16_EXP_INF, fp16_infinity(), fp16_process_NaNs(), fp16_round(), fp16_unpack(), fp16_zero(), fp32_normalise(), FPLIB_IOC, lsl32(), lsr32(), mode, and gem5::VegaISA::x.

Referenced by fplibMul(), fplibMulX(), and fplibTrigSMul().

◆ fp16_muladd()

static uint16_t gem5::ArmISA::fp16_muladd ( uint16_t  a,
uint16_t  b,
uint16_t  c,
int  scale,
int  mode,
int *  flags 
)
static

Definition at line 1514 of file fplib.cc.

References a, b, c, flags, FP16_BITS, fp16_defaultNaN(), FP16_EXP_BIAS, FP16_EXP_BITS, FP16_EXP_INF, fp16_infinity(), fp16_is_infinity(), fp16_is_quiet_NaN(), FP16_MANT_BITS, fp16_process_NaNs3(), fp16_round(), fp16_unpack(), fp16_zero(), fp32_normalise(), FPLIB_IOC, lsl32(), lsr32(), mode, gem5::X86ISA::scale, and gem5::VegaISA::x.

Referenced by fplibMulAdd(), fplibRecipStepFused(), fplibRSqrtStepFused(), and fplibTrigMulAdd().

◆ fp16_normalise()

static uint16_t gem5::ArmISA::fp16_normalise ( uint16_t  mnt,
int *  exp 
)
inlinestatic

Definition at line 219 of file fplib.cc.

References shift.

Referenced by fp16_add(), fp16_div(), fp16_scale(), fp16_sqrt(), fplibConvert(), fplibRecipEstimate(), fplibRoundInt(), and fplibRSqrtEstimate().

◆ fp16_pack()

static uint16_t gem5::ArmISA::fp16_pack ( uint16_t  sgn,
uint16_t  exp,
uint16_t  mnt 
)
inlinestatic

Definition at line 302 of file fplib.cc.

References FP16_BITS, FP16_MANT, and FP16_MANT_BITS.

Referenced by fp16_defaultNaN(), fp16_FPConvertNaN_32(), fp16_FPConvertNaN_64(), fp16_FPOnePointFive(), fp16_FPThree(), fp16_FPTwo(), fp16_infinity(), fp16_max_normal(), fp16_repack(), fp16_round_(), fp16_zero(), fplibRecipEstimate(), fplibRecpX(), fplibRoundInt(), and fplibRSqrtEstimate().

◆ fp16_process_NaN()

static uint16_t gem5::ArmISA::fp16_process_NaN ( uint16_t  a,
int  mode,
int *  flags 
)
inlinestatic

Definition at line 535 of file fplib.cc.

References a, flags, fp16_defaultNaN(), FP16_MANT_BITS, FPLIB_DN, FPLIB_IOC, and mode.

Referenced by fp16_process_NaNs(), fp16_process_NaNs3(), fp16_scale(), fp16_sqrt(), fplibRecipEstimate(), fplibRecpX(), fplibRoundInt(), and fplibRSqrtEstimate().

◆ fp16_process_NaNs()

static uint16_t gem5::ArmISA::fp16_process_NaNs ( uint16_t  a,
uint16_t  b,
int  mode,
int *  flags 
)
static

Definition at line 565 of file fplib.cc.

References a, b, flags, FP16_EXP, fp16_is_NaN(), fp16_is_signalling_NaN(), FP16_MANT, fp16_process_NaN(), and mode.

Referenced by fp16_add(), fp16_div(), fp16_mul(), fplibMax(), fplibMin(), fplibMulX(), fplibRecipStepFused(), and fplibRSqrtStepFused().

◆ fp16_process_NaNs3()

static uint16_t gem5::ArmISA::fp16_process_NaNs3 ( uint16_t  a,
uint16_t  b,
uint16_t  c,
int  mode,
int *  flags 
)
static

Definition at line 634 of file fplib.cc.

References a, b, c, flags, FP16_EXP, fp16_is_NaN(), fp16_is_signalling_NaN(), FP16_MANT, fp16_process_NaN(), and mode.

Referenced by fp16_muladd().

◆ fp16_repack()

static uint16_t gem5::ArmISA::fp16_repack ( int  sgn,
int  exp,
uint16_t  mnt 
)
static

Definition at line 3127 of file fplib.cc.

References FP16_MANT_BITS, and fp16_pack().

Referenced by fplibMax(), and fplibMin().

◆ fp16_round()

static uint16_t gem5::ArmISA::fp16_round ( int  sgn,
int  exp,
uint16_t  mnt,
int  mode,
int *  flags 
)
static

Definition at line 799 of file fplib.cc.

References flags, fp16_round_(), and mode.

Referenced by fp16_add(), fp16_cvtf(), fp16_div(), fp16_mul(), fp16_muladd(), fp16_scale(), and fp16_sqrt().

◆ fp16_round_()

static uint16_t gem5::ArmISA::fp16_round_ ( int  sgn,
int  exp,
uint16_t  mnt,
int  rm,
int  mode,
int *  flags 
)
static

Definition at line 721 of file fplib.cc.

References error, flags, FP16_EXP_BITS, FP16_EXP_INF, fp16_infinity(), FP16_MANT_BITS, fp16_max_normal(), fp16_pack(), fp16_zero(), FPLIB_AHP, FPLIB_FZ16, FPLIB_IOC, FPLIB_IXC, FPLIB_OFC, FPLIB_RM, FPLIB_RN, FPLIB_RP, FPLIB_UFC, FPRounding_ODD, FPRounding_TIEAWAY, lsl16(), lsr16(), mode, and rm.

Referenced by fp16_round(), and fplibConvert().

◆ fp16_scale()

static uint16_t gem5::ArmISA::fp16_scale ( uint16_t  a,
int16_t  b,
int  mode,
int *  flags 
)
static

Definition at line 1938 of file fplib.cc.

References a, b, flags, FP16_EXP_BITS, FP16_EXP_INF, fp16_infinity(), fp16_is_NaN(), fp16_normalise(), fp16_process_NaN(), fp16_round(), fp16_unpack(), fp16_zero(), and mode.

Referenced by fplibScale().

◆ fp16_sqrt()

static uint16_t gem5::ArmISA::fp16_sqrt ( uint16_t  a,
int  mode,
int *  flags 
)
static

Definition at line 2040 of file fplib.cc.

References a, flags, fp16_defaultNaN(), FP16_EXP_INF, fp16_infinity(), fp16_is_NaN(), fp16_normalise(), fp16_process_NaN(), fp16_round(), fp16_unpack(), fp16_zero(), FPLIB_IOC, mode, t0, t1, and gem5::VegaISA::x.

Referenced by fplibSqrt().

◆ fp16_unpack()

static void gem5::ArmISA::fp16_unpack ( int *  sgn,
int *  exp,
uint16_t *  mnt,
uint16_t  x,
int  mode,
int *  flags 
)
inlinestatic

Definition at line 392 of file fplib.cc.

References FP16_BITS, FP16_EXP, FP16_MANT, FP16_MANT_BITS, FPLIB_FZ16, mode, and gem5::VegaISA::x.

Referenced by fp16_add(), fp16_compare_eq(), fp16_compare_ge(), fp16_compare_gt(), fp16_compare_un(), fp16_div(), fp16_mul(), fp16_muladd(), fp16_scale(), fp16_sqrt(), fplibCompare(), fplibConvert(), fplibFPToFixed(), fplibMax(), fplibMin(), fplibMulX(), fplibRecipEstimate(), fplibRecipStepFused(), fplibRecpX(), fplibRoundInt(), fplibRSqrtEstimate(), fplibRSqrtStepFused(), and fplibTrigSMul().

◆ fp16_zero()

static uint16_t gem5::ArmISA::fp16_zero ( int  sgn)
inlinestatic

Definition at line 320 of file fplib.cc.

References fp16_pack().

Referenced by fp16_add(), fp16_cvtf(), fp16_div(), fp16_mul(), fp16_muladd(), fp16_round_(), fp16_scale(), fp16_sqrt(), fplibConvert(), fplibMulX(), fplibRecipEstimate(), fplibRoundInt(), and fplibRSqrtEstimate().

◆ fp32_add()

static uint32_t gem5::ArmISA::fp32_add ( uint32_t  a,
uint32_t  b,
int  neg,
int  mode,
int *  flags 
)
static

Definition at line 1283 of file fplib.cc.

References a, b, flags, fp32_defaultNaN(), FP32_EXP_BITS, FP32_EXP_INF, fp32_infinity(), fp32_normalise(), fp32_process_NaNs(), fp32_round(), fp32_unpack(), fp32_zero(), FPLIB_IOC, lsl32(), lsr32(), mode, sc_dt::neg(), and gem5::VegaISA::x.

Referenced by fplibAdd(), and fplibSub().

◆ fp32_compare_eq()

static int gem5::ArmISA::fp32_compare_eq ( uint32_t  a,
uint32_t  b,
int  mode,
int *  flags 
)
static

Definition at line 1047 of file fplib.cc.

References a, b, flags, fp32_is_NaN(), fp32_is_signalling_NaN(), fp32_unpack(), FPLIB_IOC, and mode.

Referenced by fplibCompareEQ().

◆ fp32_compare_ge()

static int gem5::ArmISA::fp32_compare_ge ( uint32_t  a,
uint32_t  b,
int  mode,
int *  flags 
)
static

Definition at line 1066 of file fplib.cc.

References a, b, flags, fp32_is_NaN(), fp32_unpack(), FPLIB_IOC, and mode.

Referenced by fplibCompareGE().

◆ fp32_compare_gt()

static int gem5::ArmISA::fp32_compare_gt ( uint32_t  a,
uint32_t  b,
int  mode,
int *  flags 
)
static

Definition at line 1091 of file fplib.cc.

References a, b, flags, fp32_is_NaN(), fp32_unpack(), FPLIB_IOC, and mode.

Referenced by fplibCompareGT().

◆ fp32_compare_un()

static int gem5::ArmISA::fp32_compare_un ( uint32_t  a,
uint32_t  b,
int  mode,
int *  flags 
)
static

Definition at line 1116 of file fplib.cc.

References a, b, flags, fp32_is_NaN(), fp32_is_signalling_NaN(), fp32_unpack(), FPLIB_IOC, and mode.

Referenced by fplibCompareUN().

◆ fp32_cvtf()

static uint32_t gem5::ArmISA::fp32_cvtf ( uint64_t  a,
int  fbits,
int  u,
int  mode,
int *  flags 
)
static

Definition at line 4928 of file fplib.cc.

References a, flags, FP32_BITS, FP32_EXP_BIAS, fp32_round(), fp32_zero(), FP64_BITS, fp64_normalise(), mode, and u.

◆ fp32_defaultNaN()

static uint32_t gem5::ArmISA::fp32_defaultNaN ( )
inlinestatic

Definition at line 380 of file fplib.cc.

References FP32_EXP_INF, FP32_MANT_BITS, and fp32_pack().

Referenced by fp32_add(), fp32_div(), fp32_mul(), fp32_muladd(), fp32_process_NaN(), fp32_sqrt(), fplibConvert(), and fplibRSqrtEstimate().

◆ fp32_div()

static uint32_t gem5::ArmISA::fp32_div ( uint32_t  a,
uint32_t  b,
int  mode,
int *  flags 
)
static

Definition at line 1818 of file fplib.cc.

References a, b, flags, FP32_BITS, fp32_defaultNaN(), FP32_EXP_BIAS, FP32_EXP_BITS, FP32_EXP_INF, fp32_infinity(), FP32_MANT_BITS, fp32_normalise(), fp32_process_NaNs(), fp32_round(), fp32_unpack(), fp32_zero(), fp64_normalise(), FPLIB_DZC, FPLIB_IOC, mode, and gem5::VegaISA::x.

Referenced by fplibDiv().

◆ fp32_FPConvertNaN_16()

static uint32_t gem5::ArmISA::fp32_FPConvertNaN_16 ( uint16_t  op)
static

Definition at line 2540 of file fplib.cc.

References FP16_BITS, FP16_MANT_BITS, FP32_EXP_INF, FP32_MANT_BITS, fp32_pack(), and gem5::X86ISA::op.

Referenced by fplibConvert().

◆ fp32_FPConvertNaN_64()

static uint32_t gem5::ArmISA::fp32_FPConvertNaN_64 ( uint64_t  op)
static

Definition at line 2548 of file fplib.cc.

References FP32_EXP_INF, FP32_MANT_BITS, fp32_pack(), FP64_BITS, FP64_MANT_BITS, and gem5::X86ISA::op.

◆ fp32_FPOnePointFive()

static uint32_t gem5::ArmISA::fp32_FPOnePointFive ( int  sgn)
static

Definition at line 2578 of file fplib.cc.

References FP32_EXP_BIAS, FP32_MANT_BITS, and fp32_pack().

Referenced by fplibRSqrtStepFused().

◆ fp32_FPThree()

static uint32_t gem5::ArmISA::fp32_FPThree ( int  sgn)
static

Definition at line 2596 of file fplib.cc.

References FP32_EXP_BIAS, FP32_MANT_BITS, and fp32_pack().

Referenced by fplibRSqrtStepFused().

◆ fp32_FPTwo()

static uint32_t gem5::ArmISA::fp32_FPTwo ( int  sgn)
static

Definition at line 2614 of file fplib.cc.

References FP32_EXP_BIAS, and fp32_pack().

Referenced by fplibMulX(), and fplibRecipStepFused().

◆ fp32_infinity()

static uint32_t gem5::ArmISA::fp32_infinity ( int  sgn)
inlinestatic

Definition at line 362 of file fplib.cc.

References FP32_EXP_INF, and fp32_pack().

Referenced by fp32_add(), fp32_div(), fp32_minmaxnum(), fp32_mul(), fp32_muladd(), fp32_round_(), fp32_scale(), fp32_sqrt(), fplibConvert(), fplibMulX(), fplibRecipEstimate(), fplibRecipStepFused(), fplibRoundInt(), fplibRSqrtEstimate(), and fplibRSqrtStepFused().

◆ fp32_is_infinity()

static int gem5::ArmISA::fp32_is_infinity ( int  exp,
uint32_t  mnt 
)
inlinestatic

Definition at line 523 of file fplib.cc.

References FP32_EXP_INF, and FP32_MANT.

Referenced by fp32_muladd().

◆ fp32_is_NaN()

static int gem5::ArmISA::fp32_is_NaN ( int  exp,
uint32_t  mnt 
)
inlinestatic

Definition at line 469 of file fplib.cc.

References FP32_EXP_INF, and FP32_MANT.

Referenced by fp32_compare_eq(), fp32_compare_ge(), fp32_compare_gt(), fp32_compare_un(), fp32_is_signalling_NaN(), fp32_process_NaNs(), fp32_process_NaNs3(), fp32_scale(), fp32_sqrt(), fplibCompare(), fplibConvert(), fplibFPToFixed(), fplibRecipEstimate(), fplibRecpX(), fplibRoundInt(), fplibRSqrtEstimate(), and fplibTrigSMul().

◆ fp32_is_quiet_NaN()

static int gem5::ArmISA::fp32_is_quiet_NaN ( int  exp,
uint32_t  mnt 
)
inlinestatic

Definition at line 505 of file fplib.cc.

References FP32_EXP_INF, and FP32_MANT_BITS.

Referenced by fp32_muladd().

◆ fp32_is_signalling_NaN()

static int gem5::ArmISA::fp32_is_signalling_NaN ( int  exp,
uint32_t  mnt 
)
inlinestatic

Definition at line 487 of file fplib.cc.

References fp32_is_NaN(), and FP32_MANT_BITS.

Referenced by fp32_compare_eq(), fp32_compare_un(), fp32_process_NaNs(), fp32_process_NaNs3(), and fplibCompare().

◆ fp32_max_normal()

static uint32_t gem5::ArmISA::fp32_max_normal ( int  sgn)
inlinestatic

Definition at line 344 of file fplib.cc.

References FP32_EXP_INF, and fp32_pack().

Referenced by fp32_round_(), and fplibRecipEstimate().

◆ fp32_minmaxnum()

static void gem5::ArmISA::fp32_minmaxnum ( uint32_t *  op1,
uint32_t *  op2,
int  sgn 
)
static

Definition at line 3157 of file fplib.cc.

References fp32_infinity(), and FP32_MANT_BITS.

Referenced by fplibMaxNum(), and fplibMinNum().

◆ fp32_mul()

static uint32_t gem5::ArmISA::fp32_mul ( uint32_t  a,
uint32_t  b,
int  mode,
int *  flags 
)
static

Definition at line 1440 of file fplib.cc.

References a, b, flags, FP32_BITS, fp32_defaultNaN(), FP32_EXP_BIAS, FP32_EXP_BITS, FP32_EXP_INF, fp32_infinity(), fp32_process_NaNs(), fp32_round(), fp32_unpack(), fp32_zero(), fp64_normalise(), FPLIB_IOC, lsl64(), lsr64(), mode, and gem5::VegaISA::x.

Referenced by fplibMul(), fplibMulX(), and fplibTrigSMul().

◆ fp32_muladd()

static uint32_t gem5::ArmISA::fp32_muladd ( uint32_t  a,
uint32_t  b,
uint32_t  c,
int  scale,
int  mode,
int *  flags 
)
static

Definition at line 1599 of file fplib.cc.

References a, b, c, flags, FP32_BITS, fp32_defaultNaN(), FP32_EXP_BIAS, FP32_EXP_BITS, FP32_EXP_INF, fp32_infinity(), fp32_is_infinity(), fp32_is_quiet_NaN(), FP32_MANT_BITS, fp32_process_NaNs3(), fp32_round(), fp32_unpack(), fp32_zero(), fp64_normalise(), FPLIB_IOC, lsl64(), lsr64(), mode, gem5::X86ISA::scale, and gem5::VegaISA::x.

Referenced by fplibMulAdd(), fplibRecipStepFused(), fplibRSqrtStepFused(), and fplibTrigMulAdd().

◆ fp32_normalise()

static uint32_t gem5::ArmISA::fp32_normalise ( uint32_t  mnt,
int *  exp 
)
inlinestatic

Definition at line 237 of file fplib.cc.

References shift.

Referenced by fp16_div(), fp16_mul(), fp16_muladd(), fp32_add(), fp32_div(), fp32_scale(), fp32_sqrt(), fplibRecipEstimate(), fplibRoundInt(), and fplibRSqrtEstimate().

◆ fp32_pack()

static uint32_t gem5::ArmISA::fp32_pack ( uint32_t  sgn,
uint32_t  exp,
uint32_t  mnt 
)
inlinestatic

Definition at line 308 of file fplib.cc.

References FP32_BITS, FP32_MANT, and FP32_MANT_BITS.

Referenced by fp32_defaultNaN(), fp32_FPConvertNaN_16(), fp32_FPConvertNaN_64(), fp32_FPOnePointFive(), fp32_FPThree(), fp32_FPTwo(), fp32_infinity(), fp32_max_normal(), fp32_repack(), fp32_round_(), fp32_zero(), fplibConvert(), fplibRecipEstimate(), fplibRecpX(), fplibRoundInt(), and fplibRSqrtEstimate().

◆ fp32_process_NaN()

static uint32_t gem5::ArmISA::fp32_process_NaN ( uint32_t  a,
int  mode,
int *  flags 
)
inlinestatic

Definition at line 545 of file fplib.cc.

References a, flags, fp32_defaultNaN(), FP32_MANT_BITS, FPLIB_DN, FPLIB_IOC, and mode.

Referenced by fp32_process_NaNs(), fp32_process_NaNs3(), fp32_scale(), fp32_sqrt(), fplibRecipEstimate(), fplibRecpX(), fplibRoundInt(), and fplibRSqrtEstimate().

◆ fp32_process_NaNs()

static uint32_t gem5::ArmISA::fp32_process_NaNs ( uint32_t  a,
uint32_t  b,
int  mode,
int *  flags 
)
static

Definition at line 588 of file fplib.cc.

References a, b, flags, FP32_EXP, fp32_is_NaN(), fp32_is_signalling_NaN(), FP32_MANT, fp32_process_NaN(), and mode.

Referenced by fp32_add(), fp32_div(), fp32_mul(), fplibMax(), fplibMin(), fplibMulX(), fplibRecipStepFused(), and fplibRSqrtStepFused().

◆ fp32_process_NaNs3()

static uint32_t gem5::ArmISA::fp32_process_NaNs3 ( uint32_t  a,
uint32_t  b,
uint32_t  c,
int  mode,
int *  flags 
)
static

Definition at line 663 of file fplib.cc.

References a, b, c, flags, FP32_EXP, fp32_is_NaN(), fp32_is_signalling_NaN(), FP32_MANT, fp32_process_NaN(), and mode.

Referenced by fp32_muladd().

◆ fp32_repack()

static uint32_t gem5::ArmISA::fp32_repack ( int  sgn,
int  exp,
uint32_t  mnt 
)
static

Definition at line 3133 of file fplib.cc.

References FP32_MANT_BITS, and fp32_pack().

Referenced by fplibMax(), and fplibMin().

◆ fp32_round()

static uint32_t gem5::ArmISA::fp32_round ( int  sgn,
int  exp,
uint32_t  mnt,
int  mode,
int *  flags 
)
static

Definition at line 876 of file fplib.cc.

References flags, fp32_round_(), and mode.

Referenced by fp32_add(), fp32_cvtf(), fp32_div(), fp32_mul(), fp32_muladd(), fp32_scale(), and fp32_sqrt().

◆ fp32_round_()

static uint32_t gem5::ArmISA::fp32_round_ ( int  sgn,
int  exp,
uint32_t  mnt,
int  rm,
int  mode,
int *  flags 
)
static

Definition at line 805 of file fplib.cc.

References error, flags, FP32_EXP_BITS, FP32_EXP_INF, fp32_infinity(), FP32_MANT_BITS, fp32_max_normal(), fp32_pack(), fp32_zero(), FPLIB_FZ, FPLIB_IXC, FPLIB_OFC, FPLIB_RM, FPLIB_RN, FPLIB_RP, FPLIB_UFC, FPRounding_ODD, FPRounding_TIEAWAY, lsl32(), lsr32(), mode, and rm.

Referenced by fp32_round().

◆ fp32_scale()

static uint32_t gem5::ArmISA::fp32_scale ( uint32_t  a,
int32_t  b,
int  mode,
int *  flags 
)
static

Definition at line 1972 of file fplib.cc.

References a, b, flags, FP32_EXP_BITS, FP32_EXP_INF, fp32_infinity(), fp32_is_NaN(), fp32_normalise(), fp32_process_NaN(), fp32_round(), fp32_unpack(), fp32_zero(), and mode.

Referenced by fplibScale().

◆ fp32_sqrt()

static uint32_t gem5::ArmISA::fp32_sqrt ( uint32_t  a,
int  mode,
int *  flags 
)
static

Definition at line 2092 of file fplib.cc.

References a, flags, fp32_defaultNaN(), FP32_EXP_INF, fp32_infinity(), fp32_is_NaN(), fp32_normalise(), fp32_process_NaN(), fp32_round(), fp32_unpack(), fp32_zero(), FPLIB_IOC, mode, t0, t1, and gem5::VegaISA::x.

Referenced by fplibSqrt().

◆ fp32_unpack()

static void gem5::ArmISA::fp32_unpack ( int *  sgn,
int *  exp,
uint32_t *  mnt,
uint32_t  x,
int  mode,
int *  flags 
)
inlinestatic

Definition at line 415 of file fplib.cc.

References flags, FP32_BITS, FP32_EXP, FP32_MANT, FP32_MANT_BITS, FPLIB_FZ, FPLIB_IDC, mode, and gem5::VegaISA::x.

Referenced by fp32_add(), fp32_compare_eq(), fp32_compare_ge(), fp32_compare_gt(), fp32_compare_un(), fp32_div(), fp32_mul(), fp32_muladd(), fp32_scale(), fp32_sqrt(), fplibCompare(), fplibConvert(), fplibFPToFixed(), fplibMax(), fplibMin(), fplibMulX(), fplibRecipEstimate(), fplibRecipStepFused(), fplibRecpX(), fplibRoundInt(), fplibRSqrtEstimate(), fplibRSqrtStepFused(), and fplibTrigSMul().

◆ fp32_zero()

static uint32_t gem5::ArmISA::fp32_zero ( int  sgn)
inlinestatic

Definition at line 326 of file fplib.cc.

References fp32_pack().

Referenced by fp32_add(), fp32_cvtf(), fp32_div(), fp32_mul(), fp32_muladd(), fp32_round_(), fp32_scale(), fp32_sqrt(), fplibConvert(), fplibMulX(), fplibRecipEstimate(), fplibRoundInt(), and fplibRSqrtEstimate().

◆ fp64_add()

static uint64_t gem5::ArmISA::fp64_add ( uint64_t  a,
uint64_t  b,
int  neg,
int  mode,
int *  flags 
)
static

Definition at line 1343 of file fplib.cc.

References a, b, flags, fp64_defaultNaN(), FP64_EXP_BITS, FP64_EXP_INF, fp64_infinity(), fp64_normalise(), fp64_process_NaNs(), fp64_round(), fp64_unpack(), fp64_zero(), FPLIB_IOC, lsl64(), lsr64(), mode, sc_dt::neg(), and gem5::VegaISA::x.

Referenced by fplibAdd(), and fplibSub().

◆ fp64_compare_eq()

static int gem5::ArmISA::fp64_compare_eq ( uint64_t  a,
uint64_t  b,
int  mode,
int *  flags 
)
static

Definition at line 1135 of file fplib.cc.

References a, b, flags, fp64_is_NaN(), fp64_is_signalling_NaN(), fp64_unpack(), FPLIB_IOC, and mode.

Referenced by fplibCompareEQ().

◆ fp64_compare_ge()

static int gem5::ArmISA::fp64_compare_ge ( uint64_t  a,
uint64_t  b,
int  mode,
int *  flags 
)
static

Definition at line 1154 of file fplib.cc.

References a, b, flags, fp64_is_NaN(), fp64_unpack(), FPLIB_IOC, and mode.

Referenced by fplibCompareGE().

◆ fp64_compare_gt()

static int gem5::ArmISA::fp64_compare_gt ( uint64_t  a,
uint64_t  b,
int  mode,
int *  flags 
)
static

Definition at line 1179 of file fplib.cc.

References a, b, flags, fp64_is_NaN(), fp64_unpack(), FPLIB_IOC, and mode.

Referenced by fplibCompareGT().

◆ fp64_compare_un()

static int gem5::ArmISA::fp64_compare_un ( uint64_t  a,
uint64_t  b,
int  mode,
int *  flags 
)
static

Definition at line 1204 of file fplib.cc.

References a, b, flags, fp64_is_NaN(), fp64_is_signalling_NaN(), fp64_unpack(), FPLIB_IOC, and mode.

Referenced by fplibCompareUN().

◆ fp64_cvtf()

static uint64_t gem5::ArmISA::fp64_cvtf ( uint64_t  a,
int  fbits,
int  u,
int  mode,
int *  flags 
)
static

Definition at line 4948 of file fplib.cc.

References a, flags, FP64_BITS, FP64_EXP_BIAS, fp64_normalise(), fp64_round(), fp64_zero(), mode, and u.

◆ fp64_defaultNaN()

static uint64_t gem5::ArmISA::fp64_defaultNaN ( )
inlinestatic

Definition at line 386 of file fplib.cc.

References FP64_EXP_INF, FP64_MANT_BITS, and fp64_pack().

Referenced by fp64_add(), fp64_div(), fp64_mul(), fp64_muladd(), fp64_process_NaN(), fp64_sqrt(), and fplibRSqrtEstimate().

◆ fp64_div()

static uint64_t gem5::ArmISA::fp64_div ( uint64_t  a,
uint64_t  b,
int  mode,
int *  flags 
)
static

Definition at line 1860 of file fplib.cc.

References a, b, c, cmp128(), flags, fp64_defaultNaN(), FP64_EXP_BIAS, FP64_EXP_INF, fp64_infinity(), fp64_normalise(), fp64_process_NaNs(), fp64_round(), fp64_unpack(), fp64_zero(), FPLIB_DZC, FPLIB_IOC, lsr128(), mode, mul62x62(), mul64x32(), sub128(), and gem5::VegaISA::x.

Referenced by fplibDiv().

◆ fp64_FPConvertNaN_16()

static uint64_t gem5::ArmISA::fp64_FPConvertNaN_16 ( uint16_t  op)
static

Definition at line 2556 of file fplib.cc.

References FP16_BITS, FP16_MANT_BITS, FP64_EXP_INF, FP64_MANT_BITS, fp64_pack(), and gem5::X86ISA::op.

◆ fp64_FPConvertNaN_32()

static uint64_t gem5::ArmISA::fp64_FPConvertNaN_32 ( uint32_t  op)
static

Definition at line 2564 of file fplib.cc.

References FP32_BITS, FP32_MANT_BITS, FP64_EXP_INF, FP64_MANT_BITS, fp64_pack(), and gem5::X86ISA::op.

◆ fp64_FPOnePointFive()

static uint64_t gem5::ArmISA::fp64_FPOnePointFive ( int  sgn)
static

Definition at line 2584 of file fplib.cc.

References FP64_EXP_BIAS, FP64_MANT_BITS, and fp64_pack().

Referenced by fplibRSqrtStepFused().

◆ fp64_FPThree()

static uint64_t gem5::ArmISA::fp64_FPThree ( int  sgn)
static

Definition at line 2602 of file fplib.cc.

References FP64_EXP_BIAS, FP64_MANT_BITS, and fp64_pack().

Referenced by fplibRSqrtStepFused().

◆ fp64_FPTwo()

static uint64_t gem5::ArmISA::fp64_FPTwo ( int  sgn)
static

Definition at line 2620 of file fplib.cc.

References FP64_EXP_BIAS, and fp64_pack().

Referenced by fplibMulX(), and fplibRecipStepFused().

◆ fp64_infinity()

static uint64_t gem5::ArmISA::fp64_infinity ( int  sgn)
inlinestatic

Definition at line 368 of file fplib.cc.

References FP64_EXP_INF, and fp64_pack().

Referenced by fp64_add(), fp64_div(), fp64_minmaxnum(), fp64_mul(), fp64_muladd(), fp64_round_(), fp64_scale(), fp64_sqrt(), fplibMulX(), fplibRecipEstimate(), fplibRecipStepFused(), fplibRoundInt(), fplibRSqrtEstimate(), and fplibRSqrtStepFused().

◆ fp64_is_infinity()

static int gem5::ArmISA::fp64_is_infinity ( int  exp,
uint64_t  mnt 
)
inlinestatic

Definition at line 529 of file fplib.cc.

References FP64_EXP_INF, and FP64_MANT.

Referenced by fp64_muladd().

◆ fp64_is_NaN()

static int gem5::ArmISA::fp64_is_NaN ( int  exp,
uint64_t  mnt 
)
inlinestatic

Definition at line 475 of file fplib.cc.

References FP64_EXP_INF, and FP64_MANT.

Referenced by fp64_compare_eq(), fp64_compare_ge(), fp64_compare_gt(), fp64_compare_un(), fp64_is_signalling_NaN(), fp64_process_NaNs(), fp64_process_NaNs3(), fp64_scale(), fp64_sqrt(), fplibCompare(), fplibConvert(), fplibFPToFixed(), fplibRecipEstimate(), fplibRecpX(), fplibRoundInt(), fplibRSqrtEstimate(), and fplibTrigSMul().

◆ fp64_is_quiet_NaN()

static int gem5::ArmISA::fp64_is_quiet_NaN ( int  exp,
uint64_t  mnt 
)
inlinestatic

Definition at line 511 of file fplib.cc.

References FP64_EXP_INF, and FP64_MANT_BITS.

Referenced by fp64_muladd().

◆ fp64_is_signalling_NaN()

static int gem5::ArmISA::fp64_is_signalling_NaN ( int  exp,
uint64_t  mnt 
)
inlinestatic

Definition at line 493 of file fplib.cc.

References fp64_is_NaN(), and FP64_MANT_BITS.

Referenced by fp64_compare_eq(), fp64_compare_un(), fp64_process_NaNs(), fp64_process_NaNs3(), and fplibCompare().

◆ fp64_max_normal()

static uint64_t gem5::ArmISA::fp64_max_normal ( int  sgn)
inlinestatic

Definition at line 350 of file fplib.cc.

References FP64_EXP_INF, and fp64_pack().

Referenced by fp64_round_(), and fplibRecipEstimate().

◆ fp64_minmaxnum()

static void gem5::ArmISA::fp64_minmaxnum ( uint64_t *  op1,
uint64_t *  op2,
int  sgn 
)
static

Definition at line 3169 of file fplib.cc.

References fp64_infinity(), and FP64_MANT_BITS.

Referenced by fplibMaxNum(), and fplibMinNum().

◆ fp64_mul()

static uint64_t gem5::ArmISA::fp64_mul ( uint64_t  a,
uint64_t  b,
int  mode,
int *  flags 
)
static

Definition at line 1477 of file fplib.cc.

References a, b, flags, fp128_normalise(), fp64_defaultNaN(), FP64_EXP_BIAS, FP64_EXP_BITS, FP64_EXP_INF, fp64_infinity(), fp64_process_NaNs(), fp64_round(), fp64_unpack(), fp64_zero(), FPLIB_IOC, mode, mul62x62(), and gem5::VegaISA::x.

Referenced by fplibMul(), fplibMulX(), and fplibTrigSMul().

◆ fp64_muladd()

static uint64_t gem5::ArmISA::fp64_muladd ( uint64_t  a,
uint64_t  b,
uint64_t  c,
int  scale,
int  mode,
int *  flags 
)
static

Definition at line 1684 of file fplib.cc.

References a, add128(), b, c, cmp128(), flags, fp128_normalise(), fp64_defaultNaN(), FP64_EXP_BIAS, FP64_EXP_BITS, FP64_EXP_INF, fp64_infinity(), fp64_is_infinity(), fp64_is_quiet_NaN(), fp64_process_NaNs3(), fp64_round(), fp64_unpack(), fp64_zero(), FPLIB_IOC, lsl128(), lsr128(), mode, mul62x62(), gem5::X86ISA::scale, sub128(), t0, t1, and gem5::VegaISA::x.

Referenced by fplibMulAdd(), fplibRecipStepFused(), fplibRSqrtStepFused(), and fplibTrigMulAdd().

◆ fp64_normalise()

static uint64_t gem5::ArmISA::fp64_normalise ( uint64_t  mnt,
int *  exp 
)
inlinestatic

Definition at line 255 of file fplib.cc.

References shift.

Referenced by fp16_cvtf(), fp32_cvtf(), fp32_div(), fp32_mul(), fp32_muladd(), fp64_add(), fp64_cvtf(), fp64_div(), fp64_scale(), fp64_sqrt(), fplibRecipEstimate(), fplibRoundInt(), and fplibRSqrtEstimate().

◆ fp64_pack()

static uint64_t gem5::ArmISA::fp64_pack ( uint64_t  sgn,
uint64_t  exp,
uint64_t  mnt 
)
inlinestatic

Definition at line 314 of file fplib.cc.

References FP64_BITS, FP64_MANT, and FP64_MANT_BITS.

Referenced by fp64_defaultNaN(), fp64_FPConvertNaN_16(), fp64_FPConvertNaN_32(), fp64_FPOnePointFive(), fp64_FPThree(), fp64_FPTwo(), fp64_infinity(), fp64_max_normal(), fp64_repack(), fp64_round_(), fp64_zero(), fplibRecipEstimate(), fplibRecpX(), fplibRoundInt(), and fplibRSqrtEstimate().

◆ fp64_process_NaN()

static uint64_t gem5::ArmISA::fp64_process_NaN ( uint64_t  a,
int  mode,
int *  flags 
)
inlinestatic

Definition at line 555 of file fplib.cc.

References a, flags, fp64_defaultNaN(), FP64_MANT_BITS, FPLIB_DN, FPLIB_IOC, and mode.

Referenced by fp64_process_NaNs(), fp64_process_NaNs3(), fp64_scale(), fp64_sqrt(), fplibRecipEstimate(), fplibRecpX(), fplibRoundInt(), and fplibRSqrtEstimate().

◆ fp64_process_NaNs()

static uint64_t gem5::ArmISA::fp64_process_NaNs ( uint64_t  a,
uint64_t  b,
int  mode,
int *  flags 
)
static

Definition at line 611 of file fplib.cc.

References a, b, flags, FP64_EXP, fp64_is_NaN(), fp64_is_signalling_NaN(), FP64_MANT, fp64_process_NaN(), and mode.

Referenced by fp64_add(), fp64_div(), fp64_mul(), fplibMax(), fplibMin(), fplibMulX(), fplibRecipStepFused(), and fplibRSqrtStepFused().

◆ fp64_process_NaNs3()

static uint64_t gem5::ArmISA::fp64_process_NaNs3 ( uint64_t  a,
uint64_t  b,
uint64_t  c,
int  mode,
int *  flags 
)
static

Definition at line 692 of file fplib.cc.

References a, b, c, flags, FP64_EXP, fp64_is_NaN(), fp64_is_signalling_NaN(), FP64_MANT, fp64_process_NaN(), and mode.

Referenced by fp64_muladd().

◆ fp64_repack()

static uint64_t gem5::ArmISA::fp64_repack ( int  sgn,
int  exp,
uint64_t  mnt 
)
static

Definition at line 3139 of file fplib.cc.

References FP64_MANT_BITS, and fp64_pack().

Referenced by fplibMax(), and fplibMin().

◆ fp64_round()

static uint64_t gem5::ArmISA::fp64_round ( int  sgn,
int  exp,
uint64_t  mnt,
int  mode,
int *  flags 
)
static

Definition at line 953 of file fplib.cc.

References flags, fp64_round_(), and mode.

Referenced by fp64_add(), fp64_cvtf(), fp64_div(), fp64_mul(), fp64_muladd(), fp64_scale(), and fp64_sqrt().

◆ fp64_round_()

static uint64_t gem5::ArmISA::fp64_round_ ( int  sgn,
int  exp,
uint64_t  mnt,
int  rm,
int  mode,
int *  flags 
)
static

Definition at line 882 of file fplib.cc.

References error, flags, FP64_EXP_BITS, FP64_EXP_INF, fp64_infinity(), FP64_MANT_BITS, fp64_max_normal(), fp64_pack(), fp64_zero(), FPLIB_FZ, FPLIB_IXC, FPLIB_OFC, FPLIB_RM, FPLIB_RN, FPLIB_RP, FPLIB_UFC, FPRounding_ODD, FPRounding_TIEAWAY, lsl64(), lsr64(), mode, and rm.

Referenced by fp64_round().

◆ fp64_scale()

static uint64_t gem5::ArmISA::fp64_scale ( uint64_t  a,
int64_t  b,
int  mode,
int *  flags 
)
static

Definition at line 2006 of file fplib.cc.

References a, b, flags, FP64_EXP_BITS, FP64_EXP_INF, fp64_infinity(), fp64_is_NaN(), fp64_normalise(), fp64_process_NaN(), fp64_round(), fp64_unpack(), fp64_zero(), and mode.

Referenced by fplibScale().

◆ fp64_sqrt()

static uint64_t gem5::ArmISA::fp64_sqrt ( uint64_t  a,
int  mode,
int *  flags 
)
static

Definition at line 2147 of file fplib.cc.

References a, c, cmp128(), flags, fp64_defaultNaN(), FP64_EXP_INF, fp64_infinity(), fp64_is_NaN(), fp64_normalise(), fp64_process_NaN(), fp64_round(), fp64_unpack(), fp64_zero(), FPLIB_IOC, lsl128(), lsr128(), mode, mul62x62(), mul64x32(), gem5::VegaISA::r, and gem5::VegaISA::x.

Referenced by fplibSqrt().

◆ fp64_unpack()

static void gem5::ArmISA::fp64_unpack ( int *  sgn,
int *  exp,
uint64_t *  mnt,
uint64_t  x,
int  mode,
int *  flags 
)
inlinestatic

Definition at line 438 of file fplib.cc.

References flags, FP64_BITS, FP64_EXP, FP64_MANT, FP64_MANT_BITS, FPLIB_FZ, FPLIB_IDC, mode, and gem5::VegaISA::x.

Referenced by fp64_add(), fp64_compare_eq(), fp64_compare_ge(), fp64_compare_gt(), fp64_compare_un(), fp64_div(), fp64_mul(), fp64_muladd(), fp64_scale(), fp64_sqrt(), fplibCompare(), fplibConvert(), fplibFPToFixed(), fplibMax(), fplibMin(), fplibMulX(), fplibRecipEstimate(), fplibRecipStepFused(), fplibRecpX(), fplibRoundInt(), fplibRSqrtEstimate(), fplibRSqrtStepFused(), and fplibTrigSMul().

◆ fp64_zero()

static uint64_t gem5::ArmISA::fp64_zero ( int  sgn)
inlinestatic

Definition at line 332 of file fplib.cc.

References fp64_pack().

Referenced by fp64_add(), fp64_cvtf(), fp64_div(), fp64_mul(), fp64_muladd(), fp64_round_(), fp64_scale(), fp64_sqrt(), fplibMulX(), fplibRecipEstimate(), and fplibRoundInt().

◆ fpAdd()

template<typename T >
static T gem5::ArmISA::fpAdd ( T  a,
T  b 
)
inlinestatic

Definition at line 482 of file vfp.hh.

References a, and b.

◆ fpAddD()

static double gem5::ArmISA::fpAddD ( double  a,
double  b 
)
inlinestatic

Definition at line 501 of file vfp.hh.

References a, and b.

◆ fpAddS()

static float gem5::ArmISA::fpAddS ( float  a,
float  b 
)
inlinestatic

Definition at line 495 of file vfp.hh.

References a, and b.

◆ FPCRRounding()

static FPRounding gem5::ArmISA::FPCRRounding ( FPSCR &  fpscr)
inlinestatic

Definition at line 71 of file fplib.hh.

Referenced by fplibRecipEstimate().

◆ fpDiv()

template<typename T >
static T gem5::ArmISA::fpDiv ( T  a,
T  b 
)
inlinestatic

Definition at line 532 of file vfp.hh.

References a, and b.

◆ fpDivD()

static double gem5::ArmISA::fpDivD ( double  a,
double  b 
)
inlinestatic

Definition at line 525 of file vfp.hh.

References a, and b.

◆ fpDivS()

static float gem5::ArmISA::fpDivS ( float  a,
float  b 
)
inlinestatic

Definition at line 519 of file vfp.hh.

References a, and b.

◆ fplibAbs() [1/4]

template<class T >
T gem5::ArmISA::fplibAbs ( T  op)

Floating-point absolute value.

◆ fplibAbs() [2/4]

template<>
uint16_t gem5::ArmISA::fplibAbs ( uint16_t  op)

Definition at line 2372 of file fplib.cc.

References FP16_BITS, and gem5::X86ISA::op.

Referenced by fplibTrigMulAdd().

◆ fplibAbs() [3/4]

template<>
uint32_t gem5::ArmISA::fplibAbs ( uint32_t  op)

Definition at line 2379 of file fplib.cc.

References FP32_BITS, and gem5::X86ISA::op.

◆ fplibAbs() [4/4]

template<>
uint64_t gem5::ArmISA::fplibAbs ( uint64_t  op)

Definition at line 2386 of file fplib.cc.

References FP64_BITS, and gem5::X86ISA::op.

◆ fplibAdd() [1/4]

template<class T >
T gem5::ArmISA::fplibAdd ( T  op1,
T  op2,
FPSCR &  fpscr 
)

Floating-point add.

◆ fplibAdd() [2/4]

template<>
uint16_t gem5::ArmISA::fplibAdd ( uint16_t  op1,
uint16_t  op2,
FPSCR &  fpscr 
)

Definition at line 2393 of file fplib.cc.

References flags, fp16_add(), modeConv(), and set_fpscr0().

◆ fplibAdd() [3/4]

template<>
uint32_t gem5::ArmISA::fplibAdd ( uint32_t  op1,
uint32_t  op2,
FPSCR &  fpscr 
)

Definition at line 2403 of file fplib.cc.

References flags, fp32_add(), modeConv(), and set_fpscr0().

◆ fplibAdd() [4/4]

template<>
uint64_t gem5::ArmISA::fplibAdd ( uint64_t  op1,
uint64_t  op2,
FPSCR &  fpscr 
)

Definition at line 2413 of file fplib.cc.

References flags, fp64_add(), modeConv(), and set_fpscr0().

◆ fplibCompare() [1/4]

template<class T >
int gem5::ArmISA::fplibCompare ( T  op1,
T  op2,
bool  signal_nans,
FPSCR &  fpscr 
)

Floating-point compare (quiet and signaling).

◆ fplibCompare() [2/4]

template<>
int gem5::ArmISA::fplibCompare ( uint16_t  op1,
uint16_t  op2,
bool  signal_nans,
FPSCR &  fpscr 
)

Definition at line 2423 of file fplib.cc.

References flags, fp16_is_NaN(), fp16_is_signalling_NaN(), fp16_unpack(), FPLIB_IOC, mode, modeConv(), and set_fpscr0().

◆ fplibCompare() [3/4]

template<>
int gem5::ArmISA::fplibCompare ( uint32_t  op1,
uint32_t  op2,
bool  signal_nans,
FPSCR &  fpscr 
)

Definition at line 2457 of file fplib.cc.

References flags, fp32_is_NaN(), fp32_is_signalling_NaN(), fp32_unpack(), FPLIB_IOC, mode, modeConv(), and set_fpscr0().

◆ fplibCompare() [4/4]

template<>
int gem5::ArmISA::fplibCompare ( uint64_t  op1,
uint64_t  op2,
bool  signal_nans,
FPSCR &  fpscr 
)

Definition at line 2491 of file fplib.cc.

References flags, fp64_is_NaN(), fp64_is_signalling_NaN(), fp64_unpack(), FPLIB_IOC, mode, modeConv(), and set_fpscr0().

◆ fplibCompareEQ() [1/4]

template<class T >
bool gem5::ArmISA::fplibCompareEQ ( T  op1,
T  op2,
FPSCR &  fpscr 
)

Floating-point compare equal.

◆ fplibCompareEQ() [2/4]

template<>
bool gem5::ArmISA::fplibCompareEQ ( uint16_t  a,
uint16_t  b,
FPSCR &  fpscr 
)

Definition at line 2252 of file fplib.cc.

References a, b, flags, fp16_compare_eq(), modeConv(), set_fpscr(), and gem5::VegaISA::x.

◆ fplibCompareEQ() [3/4]

template<>
bool gem5::ArmISA::fplibCompareEQ ( uint32_t  a,
uint32_t  b,
FPSCR &  fpscr 
)

Definition at line 2292 of file fplib.cc.

References a, b, flags, fp32_compare_eq(), modeConv(), set_fpscr(), and gem5::VegaISA::x.

◆ fplibCompareEQ() [4/4]

template<>
bool gem5::ArmISA::fplibCompareEQ ( uint64_t  a,
uint64_t  b,
FPSCR &  fpscr 
)

Definition at line 2332 of file fplib.cc.

References a, b, flags, fp64_compare_eq(), modeConv(), set_fpscr(), and gem5::VegaISA::x.

◆ fplibCompareGE() [1/4]

template<class T >
bool gem5::ArmISA::fplibCompareGE ( T  op1,
T  op2,
FPSCR &  fpscr 
)

Floating-point compare greater than or equal.

◆ fplibCompareGE() [2/4]

template<>
bool gem5::ArmISA::fplibCompareGE ( uint16_t  a,
uint16_t  b,
FPSCR &  fpscr 
)

Definition at line 2262 of file fplib.cc.

References a, b, flags, fp16_compare_ge(), modeConv(), set_fpscr(), and gem5::VegaISA::x.

◆ fplibCompareGE() [3/4]

template<>
bool gem5::ArmISA::fplibCompareGE ( uint32_t  a,
uint32_t  b,
FPSCR &  fpscr 
)

Definition at line 2302 of file fplib.cc.

References a, b, flags, fp32_compare_ge(), modeConv(), set_fpscr(), and gem5::VegaISA::x.

◆ fplibCompareGE() [4/4]

template<>
bool gem5::ArmISA::fplibCompareGE ( uint64_t  a,
uint64_t  b,
FPSCR &  fpscr 
)

Definition at line 2342 of file fplib.cc.

References a, b, flags, fp64_compare_ge(), modeConv(), set_fpscr(), and gem5::VegaISA::x.

◆ fplibCompareGT() [1/4]

template<class T >
bool gem5::ArmISA::fplibCompareGT ( T  op1,
T  op2,
FPSCR &  fpscr 
)

Floating-point compare greater than.

◆ fplibCompareGT() [2/4]

template<>
bool gem5::ArmISA::fplibCompareGT ( uint16_t  a,
uint16_t  b,
FPSCR &  fpscr 
)

Definition at line 2272 of file fplib.cc.

References a, b, flags, fp16_compare_gt(), modeConv(), set_fpscr(), and gem5::VegaISA::x.

◆ fplibCompareGT() [3/4]

template<>
bool gem5::ArmISA::fplibCompareGT ( uint32_t  a,
uint32_t  b,
FPSCR &  fpscr 
)

Definition at line 2312 of file fplib.cc.

References a, b, flags, fp32_compare_gt(), modeConv(), set_fpscr(), and gem5::VegaISA::x.

◆ fplibCompareGT() [4/4]

template<>
bool gem5::ArmISA::fplibCompareGT ( uint64_t  a,
uint64_t  b,
FPSCR &  fpscr 
)

Definition at line 2352 of file fplib.cc.

References a, b, flags, fp64_compare_gt(), modeConv(), set_fpscr(), and gem5::VegaISA::x.

◆ fplibCompareUN() [1/4]

template<class T >
bool gem5::ArmISA::fplibCompareUN ( T  op1,
T  op2,
FPSCR &  fpscr 
)

Floating-point compare unordered.

◆ fplibCompareUN() [2/4]

template<>
bool gem5::ArmISA::fplibCompareUN ( uint16_t  a,
uint16_t  b,
FPSCR &  fpscr 
)

Definition at line 2282 of file fplib.cc.

References a, b, flags, fp16_compare_un(), modeConv(), set_fpscr(), and gem5::VegaISA::x.

◆ fplibCompareUN() [3/4]

template<>
bool gem5::ArmISA::fplibCompareUN ( uint32_t  a,
uint32_t  b,
FPSCR &  fpscr 
)

Definition at line 2322 of file fplib.cc.

References a, b, flags, fp32_compare_un(), modeConv(), set_fpscr(), and gem5::VegaISA::x.

◆ fplibCompareUN() [4/4]

template<>
bool gem5::ArmISA::fplibCompareUN ( uint64_t  a,
uint64_t  b,
FPSCR &  fpscr 
)

Definition at line 2362 of file fplib.cc.

References a, b, flags, fp64_compare_un(), modeConv(), set_fpscr(), and gem5::VegaISA::x.

◆ fplibConvert() [1/4]

template<class T1 , class T2 >
T2 gem5::ArmISA::fplibConvert ( T1  op,
FPRounding  rounding,
FPSCR &  fpscr 
)

Floating-point convert precision.

◆ fplibConvert() [2/4]

template<>
uint64_t gem5::ArmISA::fplibConvert ( uint16_t  op,
FPRounding  rounding,
FPSCR &  fpscr 
)

Definition at line 2725 of file fplib.cc.

References flags, FP16_BITS, FP16_EXP_BIAS, FP16_EXP_BITS, FP16_EXP_INF, fp16_is_NaN(), FP16_MANT_BITS, fp16_normalise(), fp16_unpack(), fp32_defaultNaN(), FP32_EXP_BIAS, fp32_FPConvertNaN_16(), fp32_infinity(), FP32_MANT_BITS, fp32_pack(), fp32_zero(), FPLIB_IOC, mode, modeConv(), gem5::X86ISA::op, and set_fpscr0().

◆ fplibConvert() [3/4]

template<>
uint64_t gem5::ArmISA::fplibConvert ( uint32_t  op,
FPRounding  rounding,
FPSCR &  fpscr 
)

Definition at line 2627 of file fplib.cc.

References flags, FP16_BITS, fp16_defaultNaN(), FP16_EXP_BIAS, fp16_FPConvertNaN_32(), fp16_infinity(), fp16_round_(), fp16_zero(), FP32_EXP_BIAS, FP32_EXP_INF, fp32_is_NaN(), FP32_MANT_BITS, fp32_unpack(), FPLIB_IOC, mode, modeConv(), gem5::X86ISA::op, and set_fpscr0().

◆ fplibConvert() [4/4]

template<>
uint32_t gem5::ArmISA::fplibConvert ( uint64_t  op,
FPRounding  rounding,
FPSCR &  fpscr 
)

Definition at line 2676 of file fplib.cc.

References flags, FP16_BITS, fp16_defaultNaN(), FP16_EXP_BIAS, fp16_FPConvertNaN_64(), fp16_infinity(), fp16_round_(), fp16_zero(), FP64_EXP_BIAS, FP64_EXP_INF, fp64_is_NaN(), FP64_MANT_BITS, fp64_unpack(), FPLIB_IOC, mode, modeConv(), gem5::X86ISA::op, and set_fpscr0().

◆ fplibDefaultNaN()

template<>
uint64_t gem5::ArmISA::fplibDefaultNaN ( )

Foating-point value for default NaN.

Definition at line 5024 of file fplib.cc.

References fp16_defaultNaN().

◆ fplibDiv() [1/4]

template<class T >
T gem5::ArmISA::fplibDiv ( T  op1,
T  op2,
FPSCR &  fpscr 
)

Floating-point division.

◆ fplibDiv() [2/4]

template<>
uint16_t gem5::ArmISA::fplibDiv ( uint16_t  op1,
uint16_t  op2,
FPSCR &  fpscr 
)

Definition at line 2908 of file fplib.cc.

References flags, fp16_div(), modeConv(), and set_fpscr0().

◆ fplibDiv() [3/4]

template<>
uint32_t gem5::ArmISA::fplibDiv ( uint32_t  op1,
uint32_t  op2,
FPSCR &  fpscr 
)

Definition at line 2918 of file fplib.cc.

References flags, fp32_div(), modeConv(), and set_fpscr0().

◆ fplibDiv() [4/4]

template<>
uint64_t gem5::ArmISA::fplibDiv ( uint64_t  op1,
uint64_t  op2,
FPSCR &  fpscr 
)

Definition at line 2928 of file fplib.cc.

References flags, fp64_div(), modeConv(), and set_fpscr0().

◆ fplibExpA() [1/4]

template<class T >
T gem5::ArmISA::fplibExpA ( T  op)

Floating-point exponential accelerator.

◆ fplibExpA() [2/4]

template<>
uint16_t gem5::ArmISA::fplibExpA ( uint16_t  op)

Definition at line 2938 of file fplib.cc.

References FP16_EXP_BITS, FP16_MANT_BITS, and gem5::X86ISA::op.

◆ fplibExpA() [3/4]

template<>
uint32_t gem5::ArmISA::fplibExpA ( uint32_t  op)

Definition at line 2980 of file fplib.cc.

References FP32_EXP_BITS, FP32_MANT_BITS, and gem5::X86ISA::op.

◆ fplibExpA() [4/4]

template<>
uint64_t gem5::ArmISA::fplibExpA ( uint64_t  op)

Definition at line 3054 of file fplib.cc.

References FP64_EXP_BITS, FP64_MANT_BITS, and gem5::X86ISA::op.

◆ fplibFixedToFP()

template<>
uint64_t gem5::ArmISA::fplibFixedToFP ( uint64_t  op,
int  fbits,
bool  u,
FPRounding  rounding,
FPSCR &  fpscr 
)

Floating-point convert from fixed-point.

Definition at line 4966 of file fplib.cc.

References flags, fp16_cvtf(), gem5::X86ISA::op, set_fpscr0(), and u.

◆ fplibFPToFixed() [1/4]

template<class T1 , class T2 >
T2 gem5::ArmISA::fplibFPToFixed ( T1  op,
int  fbits,
bool  u,
FPRounding  rounding,
FPSCR &  fpscr 
)

Floating-point convert to fixed-point.

◆ fplibFPToFixed() [2/4]

template<>
uint64_t gem5::ArmISA::fplibFPToFixed ( uint16_t  op,
int  fbits,
bool  u,
FPRounding  rounding,
FPSCR &  fpscr 
)

Definition at line 4638 of file fplib.cc.

References flags, FP16_EXP_BIAS, fp16_is_NaN(), FP16_MANT_BITS, fp16_unpack(), FP64_EXP_BIAS, FP64_MANT_BITS, FPLIB_IOC, FPToFixed_16(), modeConv(), gem5::X86ISA::op, set_fpscr0(), and u.

◆ fplibFPToFixed() [3/4]

template<>
uint64_t gem5::ArmISA::fplibFPToFixed ( uint32_t  op,
int  fbits,
bool  u,
FPRounding  rounding,
FPSCR &  fpscr 
)

Definition at line 4700 of file fplib.cc.

References flags, FP32_EXP_BIAS, fp32_is_NaN(), FP32_MANT_BITS, fp32_unpack(), FP64_EXP_BIAS, FP64_MANT_BITS, FPLIB_IOC, FPToFixed_32(), modeConv(), gem5::X86ISA::op, set_fpscr0(), and u.

◆ fplibFPToFixed() [4/4]

template<>
uint64_t gem5::ArmISA::fplibFPToFixed ( uint64_t  op,
int  fbits,
bool  u,
FPRounding  rounding,
FPSCR &  fpscr 
)

Definition at line 4729 of file fplib.cc.

References flags, fp64_is_NaN(), fp64_unpack(), FPLIB_IOC, FPToFixed_32(), modeConv(), gem5::X86ISA::op, set_fpscr0(), and u.

◆ fplibFPToFixedJS()

uint32_t gem5::ArmISA::fplibFPToFixedJS ( uint64_t  op,
FPSCR &  fpscr,
bool  is64,
uint8_t &  nz 
)

Floating-point JS convert to a signed integer, with rounding to zero.

Definition at line 4755 of file fplib.cc.

References gem5::bits(), err, flags, FP32_BITS, FP64_BITS, FP64_EXP_BIAS, FP64_MANT_BITS, FPLIB_IDC, FPLIB_IOC, FPLIB_IXC, lsl64(), lsr64(), nz, gem5::X86ISA::op, and set_fpscr0().

◆ fplibInfinity()

template<>
uint64_t gem5::ArmISA::fplibInfinity ( int  sgn)

Floating-point value for +/- infinity.

Definition at line 5003 of file fplib.cc.

References fp16_infinity().

◆ fplibMax() [1/4]

template<class T >
T gem5::ArmISA::fplibMax ( T  op1,
T  op2,
FPSCR &  fpscr 
)

Floating-point maximum.

◆ fplibMax() [2/4]

template<>
uint16_t gem5::ArmISA::fplibMax ( uint16_t  op1,
uint16_t  op2,
FPSCR &  fpscr 
)

Definition at line 3182 of file fplib.cc.

References flags, fp16_process_NaNs(), fp16_repack(), fp16_unpack(), mode, modeConv(), set_fpscr0(), and gem5::VegaISA::x.

◆ fplibMax() [3/4]

template<>
uint32_t gem5::ArmISA::fplibMax ( uint32_t  op1,
uint32_t  op2,
FPSCR &  fpscr 
)

Definition at line 3205 of file fplib.cc.

References flags, fp32_process_NaNs(), fp32_repack(), fp32_unpack(), mode, modeConv(), set_fpscr0(), and gem5::VegaISA::x.

◆ fplibMax() [4/4]

template<>
uint64_t gem5::ArmISA::fplibMax ( uint64_t  op1,
uint64_t  op2,
FPSCR &  fpscr 
)

Definition at line 3228 of file fplib.cc.

References flags, fp64_process_NaNs(), fp64_repack(), fp64_unpack(), mode, modeConv(), set_fpscr0(), and gem5::VegaISA::x.

◆ fplibMaxNum() [1/4]

template<class T >
T gem5::ArmISA::fplibMaxNum ( T  op1,
T  op2,
FPSCR &  fpscr 
)

Floating-point maximum number.

◆ fplibMaxNum() [2/4]

template<>
uint16_t gem5::ArmISA::fplibMaxNum ( uint16_t  op1,
uint16_t  op2,
FPSCR &  fpscr 
)

Definition at line 3251 of file fplib.cc.

References fp16_minmaxnum().

◆ fplibMaxNum() [3/4]

template<>
uint32_t gem5::ArmISA::fplibMaxNum ( uint32_t  op1,
uint32_t  op2,
FPSCR &  fpscr 
)

Definition at line 3259 of file fplib.cc.

References fp32_minmaxnum().

◆ fplibMaxNum() [4/4]

template<>
uint64_t gem5::ArmISA::fplibMaxNum ( uint64_t  op1,
uint64_t  op2,
FPSCR &  fpscr 
)

Definition at line 3267 of file fplib.cc.

References fp64_minmaxnum().

◆ fplibMin() [1/4]

template<class T >
T gem5::ArmISA::fplibMin ( T  op1,
T  op2,
FPSCR &  fpscr 
)

Floating-point minimum.

◆ fplibMin() [2/4]

template<>
uint16_t gem5::ArmISA::fplibMin ( uint16_t  op1,
uint16_t  op2,
FPSCR &  fpscr 
)

Definition at line 3275 of file fplib.cc.

References flags, fp16_process_NaNs(), fp16_repack(), fp16_unpack(), mode, modeConv(), set_fpscr0(), and gem5::VegaISA::x.

◆ fplibMin() [3/4]

template<>
uint32_t gem5::ArmISA::fplibMin ( uint32_t  op1,
uint32_t  op2,
FPSCR &  fpscr 
)

Definition at line 3298 of file fplib.cc.

References flags, fp32_process_NaNs(), fp32_repack(), fp32_unpack(), mode, modeConv(), set_fpscr0(), and gem5::VegaISA::x.

◆ fplibMin() [4/4]

template<>
uint64_t gem5::ArmISA::fplibMin ( uint64_t  op1,
uint64_t  op2,
FPSCR &  fpscr 
)

Definition at line 3321 of file fplib.cc.

References flags, fp64_process_NaNs(), fp64_repack(), fp64_unpack(), mode, modeConv(), set_fpscr0(), and gem5::VegaISA::x.

◆ fplibMinNum() [1/4]

template<class T >
T gem5::ArmISA::fplibMinNum ( T  op1,
T  op2,
FPSCR &  fpscr 
)

Floating-point minimum number.

◆ fplibMinNum() [2/4]

template<>
uint16_t gem5::ArmISA::fplibMinNum ( uint16_t  op1,
uint16_t  op2,
FPSCR &  fpscr 
)

Definition at line 3344 of file fplib.cc.

References fp16_minmaxnum().

◆ fplibMinNum() [3/4]

template<>
uint32_t gem5::ArmISA::fplibMinNum ( uint32_t  op1,
uint32_t  op2,
FPSCR &  fpscr 
)

Definition at line 3352 of file fplib.cc.

References fp32_minmaxnum().

◆ fplibMinNum() [4/4]

template<>
uint64_t gem5::ArmISA::fplibMinNum ( uint64_t  op1,
uint64_t  op2,
FPSCR &  fpscr 
)

Definition at line 3360 of file fplib.cc.

References fp64_minmaxnum().

◆ fplibMul() [1/4]

template<class T >
T gem5::ArmISA::fplibMul ( T  op1,
T  op2,
FPSCR &  fpscr 
)

Floating-point multiply.

◆ fplibMul() [2/4]

template<>
uint16_t gem5::ArmISA::fplibMul ( uint16_t  op1,
uint16_t  op2,
FPSCR &  fpscr 
)

Definition at line 3368 of file fplib.cc.

References flags, fp16_mul(), modeConv(), and set_fpscr0().

◆ fplibMul() [3/4]

template<>
uint32_t gem5::ArmISA::fplibMul ( uint32_t  op1,
uint32_t  op2,
FPSCR &  fpscr 
)

Definition at line 3378 of file fplib.cc.

References flags, fp32_mul(), modeConv(), and set_fpscr0().

◆ fplibMul() [4/4]

template<>
uint64_t gem5::ArmISA::fplibMul ( uint64_t  op1,
uint64_t  op2,
FPSCR &  fpscr 
)

Definition at line 3388 of file fplib.cc.

References flags, fp64_mul(), modeConv(), and set_fpscr0().

◆ fplibMulAdd() [1/4]

template<class T >
T gem5::ArmISA::fplibMulAdd ( T  addend,
T  op1,
T  op2,
FPSCR &  fpscr 
)

Floating-point multiply-add.

◆ fplibMulAdd() [2/4]

template<>
uint16_t gem5::ArmISA::fplibMulAdd ( uint16_t  addend,
uint16_t  op1,
uint16_t  op2,
FPSCR &  fpscr 
)

Definition at line 2878 of file fplib.cc.

References flags, fp16_muladd(), modeConv(), and set_fpscr0().

◆ fplibMulAdd() [3/4]

template<>
uint32_t gem5::ArmISA::fplibMulAdd ( uint32_t  addend,
uint32_t  op1,
uint32_t  op2,
FPSCR &  fpscr 
)

Definition at line 2888 of file fplib.cc.

References flags, fp32_muladd(), modeConv(), and set_fpscr0().

◆ fplibMulAdd() [4/4]

template<>
uint64_t gem5::ArmISA::fplibMulAdd ( uint64_t  addend,
uint64_t  op1,
uint64_t  op2,
FPSCR &  fpscr 
)

Definition at line 2898 of file fplib.cc.

References flags, fp64_muladd(), modeConv(), and set_fpscr0().

◆ fplibMulX() [1/4]

template<class T >
T gem5::ArmISA::fplibMulX ( T  op1,
T  op2,
FPSCR &  fpscr 
)

Floating-point multiply extended.

◆ fplibMulX() [2/4]

template<>
uint16_t gem5::ArmISA::fplibMulX ( uint16_t  op1,
uint16_t  op2,
FPSCR &  fpscr 
)

Definition at line 3398 of file fplib.cc.

References flags, FP16_EXP_INF, fp16_FPTwo(), fp16_infinity(), fp16_mul(), fp16_process_NaNs(), fp16_unpack(), fp16_zero(), mode, modeConv(), and set_fpscr0().

◆ fplibMulX() [3/4]

template<>
uint32_t gem5::ArmISA::fplibMulX ( uint32_t  op1,
uint32_t  op2,
FPSCR &  fpscr 
)

Definition at line 3429 of file fplib.cc.

References flags, FP32_EXP_INF, fp32_FPTwo(), fp32_infinity(), fp32_mul(), fp32_process_NaNs(), fp32_unpack(), fp32_zero(), mode, modeConv(), and set_fpscr0().

◆ fplibMulX() [4/4]

template<>
uint64_t gem5::ArmISA::fplibMulX ( uint64_t  op1,
uint64_t  op2,
FPSCR &  fpscr 
)

Definition at line 3460 of file fplib.cc.

References flags, FP64_EXP_INF, fp64_FPTwo(), fp64_infinity(), fp64_mul(), fp64_process_NaNs(), fp64_unpack(), fp64_zero(), mode, modeConv(), and set_fpscr0().

◆ fplibNeg() [1/4]

template<class T >
T gem5::ArmISA::fplibNeg ( T  op)

Floating-point negate.

◆ fplibNeg() [2/4]

template<>
uint16_t gem5::ArmISA::fplibNeg ( uint16_t  op)

Definition at line 3491 of file fplib.cc.

References FP16_BITS, and gem5::X86ISA::op.

◆ fplibNeg() [3/4]

template<>
uint32_t gem5::ArmISA::fplibNeg ( uint32_t  op)

Definition at line 3498 of file fplib.cc.

References FP32_BITS, and gem5::X86ISA::op.

◆ fplibNeg() [4/4]

template<>
uint64_t gem5::ArmISA::fplibNeg ( uint64_t  op)

Definition at line 3505 of file fplib.cc.

References FP64_BITS, and gem5::X86ISA::op.

◆ fplibRecipEstimate() [1/4]

template<class T >
T gem5::ArmISA::fplibRecipEstimate ( T  op,
FPSCR &  fpscr 
)

Floating-point reciprocal estimate.

◆ fplibRecipEstimate() [2/4]

template<>
uint16_t gem5::ArmISA::fplibRecipEstimate ( uint16_t  op,
FPSCR &  fpscr 
)

Definition at line 3726 of file fplib.cc.

References flags, FP16_BITS, FP16_EXP_BIAS, FP16_EXP_BITS, FP16_EXP_INF, fp16_infinity(), fp16_is_NaN(), FP16_MANT_BITS, fp16_max_normal(), fp16_normalise(), fp16_pack(), fp16_process_NaN(), fp16_unpack(), fp16_zero(), FPCRRounding(), FPLIB_DZC, FPLIB_IXC, FPLIB_OFC, FPLIB_UFC, FPRounding_NEGINF, FPRounding_POSINF, FPRounding_TIEEVEN, FPRounding_ZERO, mode, modeConv(), gem5::X86ISA::op, panic, and set_fpscr0().

◆ fplibRecipEstimate() [3/4]

template<>
uint32_t gem5::ArmISA::fplibRecipEstimate ( uint32_t  op,
FPSCR &  fpscr 
)

Definition at line 3788 of file fplib.cc.

References flags, FP32_BITS, FP32_EXP_BIAS, FP32_EXP_BITS, FP32_EXP_INF, fp32_infinity(), fp32_is_NaN(), FP32_MANT_BITS, fp32_max_normal(), fp32_normalise(), fp32_pack(), fp32_process_NaN(), fp32_unpack(), fp32_zero(), FPCRRounding(), FPLIB_DZC, FPLIB_IXC, FPLIB_OFC, FPLIB_UFC, FPRounding_NEGINF, FPRounding_POSINF, FPRounding_TIEEVEN, FPRounding_ZERO, mode, modeConv(), gem5::X86ISA::op, panic, and set_fpscr0().

◆ fplibRecipEstimate() [4/4]

template<>
uint64_t gem5::ArmISA::fplibRecipEstimate ( uint64_t  op,
FPSCR &  fpscr 
)

Definition at line 3850 of file fplib.cc.

References flags, FP64_BITS, FP64_EXP_BIAS, FP64_EXP_BITS, FP64_EXP_INF, fp64_infinity(), fp64_is_NaN(), FP64_MANT_BITS, fp64_max_normal(), fp64_normalise(), fp64_pack(), fp64_process_NaN(), fp64_unpack(), fp64_zero(), FPCRRounding(), FPLIB_DZC, FPLIB_IXC, FPLIB_OFC, FPLIB_UFC, FPRounding_NEGINF, FPRounding_POSINF, FPRounding_TIEEVEN, FPRounding_ZERO, mode, modeConv(), gem5::X86ISA::op, panic, and set_fpscr0().

◆ fplibRecipStepFused() [1/4]

template<class T >
T gem5::ArmISA::fplibRecipStepFused ( T  op1,
T  op2,
FPSCR &  fpscr 
)

Floating-point reciprocal step.

◆ fplibRecipStepFused() [2/4]

template<>
uint16_t gem5::ArmISA::fplibRecipStepFused ( uint16_t  op1,
uint16_t  op2,
FPSCR &  fpscr 
)

Definition at line 3912 of file fplib.cc.

References flags, FP16_EXP_INF, fp16_FPTwo(), fp16_infinity(), fp16_muladd(), fp16_process_NaNs(), fp16_unpack(), mode, modeConv(), and set_fpscr0().

◆ fplibRecipStepFused() [3/4]

template<>
uint32_t gem5::ArmISA::fplibRecipStepFused ( uint32_t  op1,
uint32_t  op2,
FPSCR &  fpscr 
)

Definition at line 3942 of file fplib.cc.

References flags, FP32_EXP_INF, fp32_FPTwo(), fp32_infinity(), fp32_muladd(), fp32_process_NaNs(), fp32_unpack(), mode, modeConv(), and set_fpscr0().

◆ fplibRecipStepFused() [4/4]

template<>
uint64_t gem5::ArmISA::fplibRecipStepFused ( uint64_t  op1,
uint64_t  op2,
FPSCR &  fpscr 
)

Definition at line 3972 of file fplib.cc.

References flags, FP64_EXP_INF, fp64_FPTwo(), fp64_infinity(), fp64_muladd(), fp64_process_NaNs(), fp64_unpack(), mode, modeConv(), and set_fpscr0().

◆ fplibRecpX() [1/4]

template<class T >
T gem5::ArmISA::fplibRecpX ( T  op,
FPSCR &  fpscr 
)

Floating-point reciprocal exponent.

◆ fplibRecpX() [2/4]

template<>
uint16_t gem5::ArmISA::fplibRecpX ( uint16_t  op,
FPSCR &  fpscr 
)

Definition at line 4002 of file fplib.cc.

References flags, FP16_EXP_INF, fp16_is_NaN(), fp16_pack(), fp16_process_NaN(), fp16_unpack(), mode, modeConv(), gem5::X86ISA::op, and set_fpscr0().

◆ fplibRecpX() [3/4]

template<>
uint32_t gem5::ArmISA::fplibRecpX ( uint32_t  op,
FPSCR &  fpscr 
)

Definition at line 4029 of file fplib.cc.

References flags, FP32_EXP_INF, fp32_is_NaN(), fp32_pack(), fp32_process_NaN(), fp32_unpack(), mode, modeConv(), gem5::X86ISA::op, and set_fpscr0().

◆ fplibRecpX() [4/4]

template<>
uint64_t gem5::ArmISA::fplibRecpX ( uint64_t  op,
FPSCR &  fpscr 
)

Definition at line 4056 of file fplib.cc.

References flags, FP64_EXP_INF, fp64_is_NaN(), fp64_pack(), fp64_process_NaN(), fp64_unpack(), mode, modeConv(), gem5::X86ISA::op, and set_fpscr0().

◆ fplibRoundInt() [1/4]

template<class T >
T gem5::ArmISA::fplibRoundInt ( T  op,
FPRounding  rounding,
bool  exact,
FPSCR &  fpscr 
)

Floating-point convert to integer.

◆ fplibRoundInt() [2/4]

template<>
uint16_t gem5::ArmISA::fplibRoundInt ( uint16_t  op,
FPRounding  rounding,
bool  exact,
FPSCR &  fpscr 
)

Definition at line 4083 of file fplib.cc.

References err, flags, FP16_BITS, FP16_EXP_BIAS, FP16_EXP_BITS, FP16_EXP_INF, fp16_infinity(), fp16_is_NaN(), FP16_MANT_BITS, fp16_normalise(), fp16_pack(), fp16_process_NaN(), fp16_unpack(), fp16_zero(), FPLIB_IXC, FPRounding_NEGINF, FPRounding_POSINF, FPRounding_TIEAWAY, FPRounding_TIEEVEN, FPRounding_ZERO, mode, modeConv(), gem5::X86ISA::op, panic, set_fpscr0(), and gem5::VegaISA::x.

◆ fplibRoundInt() [3/4]

template<>
uint32_t gem5::ArmISA::fplibRoundInt ( uint32_t  op,
FPRounding  rounding,
bool  exact,
FPSCR &  fpscr 
)

Definition at line 4148 of file fplib.cc.

References err, flags, FP32_BITS, FP32_EXP_BIAS, FP32_EXP_BITS, FP32_EXP_INF, fp32_infinity(), fp32_is_NaN(), FP32_MANT_BITS, fp32_normalise(), fp32_pack(), fp32_process_NaN(), fp32_unpack(), fp32_zero(), FPLIB_IXC, FPRounding_NEGINF, FPRounding_POSINF, FPRounding_TIEAWAY, FPRounding_TIEEVEN, FPRounding_ZERO, mode, modeConv(), gem5::X86ISA::op, panic, set_fpscr0(), and gem5::VegaISA::x.

◆ fplibRoundInt() [4/4]

template<>
uint64_t gem5::ArmISA::fplibRoundInt ( uint64_t  op,
FPRounding  rounding,
bool  exact,
FPSCR &  fpscr 
)

Definition at line 4213 of file fplib.cc.

References err, flags, FP64_BITS, FP64_EXP_BIAS, FP64_EXP_BITS, FP64_EXP_INF, fp64_infinity(), fp64_is_NaN(), FP64_MANT_BITS, fp64_normalise(), fp64_pack(), fp64_process_NaN(), fp64_unpack(), fp64_zero(), FPLIB_IXC, FPRounding_NEGINF, FPRounding_POSINF, FPRounding_TIEAWAY, FPRounding_TIEEVEN, FPRounding_ZERO, mode, modeConv(), gem5::X86ISA::op, panic, set_fpscr0(), and gem5::VegaISA::x.

◆ fplibRSqrtEstimate() [1/4]

template<class T >
T gem5::ArmISA::fplibRSqrtEstimate ( T  op,
FPSCR &  fpscr 
)

Floating-point reciprocal square root estimate.

◆ fplibRSqrtEstimate() [2/4]

template<>
uint16_t gem5::ArmISA::fplibRSqrtEstimate ( uint16_t  op,
FPSCR &  fpscr 
)

Definition at line 3531 of file fplib.cc.

References flags, FP16_BITS, fp16_defaultNaN(), FP16_EXP_BIAS, FP16_EXP_BITS, FP16_EXP_INF, fp16_infinity(), fp16_is_NaN(), FP16_MANT_BITS, fp16_normalise(), fp16_pack(), fp16_process_NaN(), fp16_unpack(), fp16_zero(), FPLIB_DZC, FPLIB_IOC, mode, modeConv(), gem5::X86ISA::op, recip_sqrt_estimate, and set_fpscr0().

◆ fplibRSqrtEstimate() [3/4]

template<>
uint32_t gem5::ArmISA::fplibRSqrtEstimate ( uint32_t  op,
FPSCR &  fpscr 
)

Definition at line 3566 of file fplib.cc.

References flags, FP32_BITS, fp32_defaultNaN(), FP32_EXP_BIAS, FP32_EXP_BITS, FP32_EXP_INF, fp32_infinity(), fp32_is_NaN(), FP32_MANT_BITS, fp32_normalise(), fp32_pack(), fp32_process_NaN(), fp32_unpack(), fp32_zero(), FPLIB_DZC, FPLIB_IOC, mode, modeConv(), gem5::X86ISA::op, recip_sqrt_estimate, and set_fpscr0().

◆ fplibRSqrtEstimate() [4/4]

template<>
uint64_t gem5::ArmISA::fplibRSqrtEstimate ( uint64_t  op,
FPSCR &  fpscr 
)

Definition at line 3601 of file fplib.cc.

References flags, fp32_zero(), FP64_BITS, fp64_defaultNaN(), FP64_EXP_BIAS, FP64_EXP_BITS, FP64_EXP_INF, fp64_infinity(), fp64_is_NaN(), FP64_MANT_BITS, fp64_normalise(), fp64_pack(), fp64_process_NaN(), fp64_unpack(), FPLIB_DZC, FPLIB_IOC, mode, modeConv(), gem5::X86ISA::op, recip_sqrt_estimate, and set_fpscr0().

◆ fplibRSqrtStepFused() [1/4]

template<class T >
T gem5::ArmISA::fplibRSqrtStepFused ( T  op1,
T  op2,
FPSCR &  fpscr 
)

Floating-point reciprocal square root step.

◆ fplibRSqrtStepFused() [2/4]

template<>
uint16_t gem5::ArmISA::fplibRSqrtStepFused ( uint16_t  op1,
uint16_t  op2,
FPSCR &  fpscr 
)

Definition at line 3636 of file fplib.cc.

References flags, FP16_EXP_INF, fp16_FPOnePointFive(), fp16_FPThree(), fp16_infinity(), fp16_muladd(), fp16_process_NaNs(), fp16_unpack(), mode, modeConv(), and set_fpscr0().

◆ fplibRSqrtStepFused() [3/4]

template<>
uint32_t gem5::ArmISA::fplibRSqrtStepFused ( uint32_t  op1,
uint32_t  op2,
FPSCR &  fpscr 
)

Definition at line 3666 of file fplib.cc.

References flags, FP32_EXP_INF, fp32_FPOnePointFive(), fp32_FPThree(), fp32_infinity(), fp32_muladd(), fp32_process_NaNs(), fp32_unpack(), mode, modeConv(), and set_fpscr0().

◆ fplibRSqrtStepFused() [4/4]

template<>
uint64_t gem5::ArmISA::fplibRSqrtStepFused ( uint64_t  op1,
uint64_t  op2,
FPSCR &  fpscr 
)

Definition at line 3696 of file fplib.cc.

References flags, FP64_EXP_INF, fp64_FPOnePointFive(), fp64_FPThree(), fp64_infinity(), fp64_muladd(), fp64_process_NaNs(), fp64_unpack(), mode, modeConv(), and set_fpscr0().

◆ fplibScale() [1/4]

template<class T >
T gem5::ArmISA::fplibScale ( T  op1,
T  op2,
FPSCR &  fpscr 
)

Floating-point adjust exponent.

◆ fplibScale() [2/4]

template<>
uint16_t gem5::ArmISA::fplibScale ( uint16_t  op1,
uint16_t  op2,
FPSCR &  fpscr 
)

Definition at line 4278 of file fplib.cc.

References flags, fp16_scale(), modeConv(), and set_fpscr0().

◆ fplibScale() [3/4]

template<>
uint32_t gem5::ArmISA::fplibScale ( uint32_t  op1,
uint32_t  op2,
FPSCR &  fpscr 
)

Definition at line 4288 of file fplib.cc.

References flags, fp32_scale(), modeConv(), and set_fpscr0().

◆ fplibScale() [4/4]

template<>
uint64_t gem5::ArmISA::fplibScale ( uint64_t  op1,
uint64_t  op2,
FPSCR &  fpscr 
)

Definition at line 4298 of file fplib.cc.

References flags, fp64_scale(), modeConv(), and set_fpscr0().

◆ fplibSqrt() [1/4]

template<class T >
T gem5::ArmISA::fplibSqrt ( T  op,
FPSCR &  fpscr 
)

Floating-point square root.

◆ fplibSqrt() [2/4]

template<>
uint16_t gem5::ArmISA::fplibSqrt ( uint16_t  op,
FPSCR &  fpscr 
)

Definition at line 4308 of file fplib.cc.

References flags, fp16_sqrt(), modeConv(), gem5::X86ISA::op, and set_fpscr0().

◆ fplibSqrt() [3/4]

template<>
uint32_t gem5::ArmISA::fplibSqrt ( uint32_t  op,
FPSCR &  fpscr 
)

Definition at line 4318 of file fplib.cc.

References flags, fp32_sqrt(), modeConv(), gem5::X86ISA::op, and set_fpscr0().

◆ fplibSqrt() [4/4]

template<>
uint64_t gem5::ArmISA::fplibSqrt ( uint64_t  op,
FPSCR &  fpscr 
)

Definition at line 4328 of file fplib.cc.

References flags, fp64_sqrt(), modeConv(), gem5::X86ISA::op, and set_fpscr0().

◆ fplibSub() [1/4]

template<class T >
T gem5::ArmISA::fplibSub ( T  op1,
T  op2,
FPSCR &  fpscr 
)

Floating-point subtract.

◆ fplibSub() [2/4]

template<>
uint16_t gem5::ArmISA::fplibSub ( uint16_t  op1,
uint16_t  op2,
FPSCR &  fpscr 
)

Definition at line 4338 of file fplib.cc.

References flags, fp16_add(), modeConv(), and set_fpscr0().

◆ fplibSub() [3/4]

template<>
uint32_t gem5::ArmISA::fplibSub ( uint32_t  op1,
uint32_t  op2,
FPSCR &  fpscr 
)

Definition at line 4348 of file fplib.cc.

References flags, fp32_add(), modeConv(), and set_fpscr0().

◆ fplibSub() [4/4]

template<>
uint64_t gem5::ArmISA::fplibSub ( uint64_t  op1,
uint64_t  op2,
FPSCR &  fpscr 
)

Definition at line 4358 of file fplib.cc.

References flags, fp64_add(), modeConv(), and set_fpscr0().

◆ fplibTrigMulAdd() [1/4]

template<class T >
T gem5::ArmISA::fplibTrigMulAdd ( uint8_t  coeff_index,
T  op1,
T  op2,
FPSCR &  fpscr 
)

Floating-point trigonometric multiply-add coefficient.

◆ fplibTrigMulAdd() [2/4]

template<>
uint16_t gem5::ArmISA::fplibTrigMulAdd ( uint8_t  coeff_index,
uint16_t  op1,
uint16_t  op2,
FPSCR &  fpscr 
)

Definition at line 4368 of file fplib.cc.

References flags, FP16_BITS, fp16_muladd(), fplibAbs(), modeConv(), and set_fpscr0().

◆ fplibTrigMulAdd() [3/4]

template<>
uint32_t gem5::ArmISA::fplibTrigMulAdd ( uint8_t  coeff_index,
uint32_t  op1,
uint32_t  op2,
FPSCR &  fpscr 
)

Definition at line 4402 of file fplib.cc.

References flags, FP32_BITS, fp32_muladd(), fplibAbs(), modeConv(), and set_fpscr0().

◆ fplibTrigMulAdd() [4/4]

template<>
uint64_t gem5::ArmISA::fplibTrigMulAdd ( uint8_t  coeff_index,
uint64_t  op1,
uint64_t  op2,
FPSCR &  fpscr 
)

Definition at line 4436 of file fplib.cc.

References flags, FP64_BITS, fp64_muladd(), fplibAbs(), modeConv(), and set_fpscr0().

◆ fplibTrigSMul() [1/4]

template<class T >
T gem5::ArmISA::fplibTrigSMul ( T  op1,
T  op2,
FPSCR &  fpscr 
)

Floating-point trigonometric starting value.

◆ fplibTrigSMul() [2/4]

template<>
uint16_t gem5::ArmISA::fplibTrigSMul ( uint16_t  op1,
uint16_t  op2,
FPSCR &  fpscr 
)

Definition at line 4470 of file fplib.cc.

References flags, FP16_BITS, fp16_is_NaN(), fp16_mul(), fp16_unpack(), mode, modeConv(), and set_fpscr0().

◆ fplibTrigSMul() [3/4]

template<>
uint32_t gem5::ArmISA::fplibTrigSMul ( uint32_t  op1,
uint32_t  op2,
FPSCR &  fpscr 
)

Definition at line 4490 of file fplib.cc.

References flags, FP32_BITS, fp32_is_NaN(), fp32_mul(), fp32_unpack(), mode, modeConv(), and set_fpscr0().

◆ fplibTrigSMul() [4/4]

template<>
uint64_t gem5::ArmISA::fplibTrigSMul ( uint64_t  op1,
uint64_t  op2,
FPSCR &  fpscr 
)

Definition at line 4509 of file fplib.cc.

References flags, FP64_BITS, fp64_is_NaN(), fp64_mul(), fp64_unpack(), mode, modeConv(), and set_fpscr0().

◆ fplibTrigSSel() [1/4]

template<class T >
T gem5::ArmISA::fplibTrigSSel ( T  op1,
T  op2,
FPSCR &  fpscr 
)

Floating-point trigonometric select coefficient.

◆ fplibTrigSSel() [2/4]

template<>
uint16_t gem5::ArmISA::fplibTrigSSel ( uint16_t  op1,
uint16_t  op2,
FPSCR &  fpscr 
)

Definition at line 4528 of file fplib.cc.

References FP16_BITS, FP16_EXP_BIAS, and FP16_MANT_BITS.

◆ fplibTrigSSel() [3/4]

template<>
uint32_t gem5::ArmISA::fplibTrigSSel ( uint32_t  op1,
uint32_t  op2,
FPSCR &  fpscr 
)

Definition at line 4539 of file fplib.cc.

References FP32_BITS, FP32_EXP_BIAS, and FP32_MANT_BITS.

◆ fplibTrigSSel() [4/4]

template<>
uint64_t gem5::ArmISA::fplibTrigSSel ( uint64_t  op1,
uint64_t  op2,
FPSCR &  fpscr 
)

Definition at line 4550 of file fplib.cc.

References FP64_BITS, FP64_EXP_BIAS, and FP64_MANT_BITS.

◆ fpMax()

template<typename T >
static T gem5::ArmISA::fpMax ( T  a,
T  b 
)
inlinestatic

Definition at line 643 of file vfp.hh.

References a, and b.

◆ fpMaxNum()

template<typename T >
static T gem5::ArmISA::fpMaxNum ( T  a,
T  b 
)
inlinestatic

Definition at line 626 of file vfp.hh.

References a, b, and fpToBits().

◆ fpMin()

template<typename T >
static T gem5::ArmISA::fpMin ( T  a,
T  b 
)
inlinestatic

Definition at line 671 of file vfp.hh.

References a, and b.

◆ fpMinNum()

template<typename T >
static T gem5::ArmISA::fpMinNum ( T  a,
T  b 
)
inlinestatic

Definition at line 654 of file vfp.hh.

References a, b, and fpToBits().

◆ fpMul()

template<typename T >
static T gem5::ArmISA::fpMul ( T  a,
T  b 
)
inlinestatic

Definition at line 573 of file vfp.hh.

References a, and b.

◆ fpMulAdd()

template<typename T >
static T gem5::ArmISA::fpMulAdd ( T  op1,
T  op2,
T  addend 
)
inlinestatic

Definition at line 593 of file vfp.hh.

References bitsToFp(), and fpToBits().

◆ fpMulD()

static double gem5::ArmISA::fpMulD ( double  a,
double  b 
)
inlinestatic

Definition at line 585 of file vfp.hh.

References a, and b.

◆ fpMulS()

static float gem5::ArmISA::fpMulS ( float  a,
float  b 
)
inlinestatic

Definition at line 579 of file vfp.hh.

References a, and b.

◆ fpMulX()

template<typename T >
static T gem5::ArmISA::fpMulX ( T  a,
T  b 
)
inlinestatic

Definition at line 539 of file vfp.hh.

References a, b, and fpToBits().

◆ fpRecipEstimate()

float gem5::ArmISA::fpRecipEstimate ( FPSCR &  fpscr,
float  op 
)

Definition at line 853 of file vfp.cc.

References gem5::bits(), bitsToFp(), fpToBits(), gem5::X86ISA::op, and recipEstimate().

◆ fpRecps()

template<typename T >
static T gem5::ArmISA::fpRecps ( T  a,
T  b 
)
inlinestatic

Definition at line 704 of file vfp.hh.

References a, b, and FeUnderflow.

◆ fpRecpsS()

static float gem5::ArmISA::fpRecpsS ( float  a,
float  b 
)
inlinestatic

Definition at line 747 of file vfp.hh.

References a, b, and FeUnderflow.

◆ fpRIntX()

template<typename T >
static T gem5::ArmISA::fpRIntX ( T  a,
FPSCR &  fpscr 
)
inlinestatic

Definition at line 614 of file vfp.hh.

References a.

◆ fprSqrtEstimate()

float gem5::ArmISA::fprSqrtEstimate ( FPSCR &  fpscr,
float  op 
)

Definition at line 771 of file vfp.cc.

References gem5::bits(), bitsToFp(), fpToBits(), gem5::X86ISA::op, and recipSqrtEstimate().

◆ fpRSqrts()

template<typename T >
static T gem5::ArmISA::fpRSqrts ( T  a,
T  b 
)
inlinestatic

Definition at line 682 of file vfp.hh.

References a, b, and FeUnderflow.

◆ fpRSqrtsS()

static float gem5::ArmISA::fpRSqrtsS ( float  a,
float  b 
)
inlinestatic

Definition at line 726 of file vfp.hh.

References a, b, and FeUnderflow.

◆ fpStandardFPSCRValue()

FPSCR gem5::ArmISA::fpStandardFPSCRValue ( const FPSCR &  fpscr)

Definition at line 905 of file vfp.cc.

◆ fpSub()

template<typename T >
static T gem5::ArmISA::fpSub ( T  a,
T  b 
)
inlinestatic

Definition at line 489 of file vfp.hh.

References a, and b.

◆ fpSubD()

static double gem5::ArmISA::fpSubD ( double  a,
double  b 
)
inlinestatic

Definition at line 513 of file vfp.hh.

References a, and b.

◆ fpSubS()

static float gem5::ArmISA::fpSubS ( float  a,
float  b 
)
inlinestatic

Definition at line 507 of file vfp.hh.

References a, and b.

◆ fpToBits() [1/2]

static uint64_t gem5::ArmISA::fpToBits ( double  fp)
inlinestatic

Definition at line 172 of file vfp.hh.

References gem5::bits(), fp, and gem5::X86ISA::val.

◆ fpToBits() [2/2]

static uint32_t gem5::ArmISA::fpToBits ( float  fp)
inlinestatic

Definition at line 160 of file vfp.hh.

References gem5::bits(), fp, and gem5::X86ISA::val.

Referenced by gem5::ArmISA::FpOp::binaryOp(), gem5::ArmISA::FpOp::dblHi(), gem5::ArmISA::FpOp::dblLow(), fixDest(), fixFpDFpSDest(), fixFpSFpDDest(), flushToZero(), fpMaxNum(), fpMinNum(), fpMulAdd(), fpMulX(), fpRecipEstimate(), fprSqrtEstimate(), highFromDouble(), isSnan(), lowFromDouble(), gem5::ArmISA::FpOp::processNans(), gem5::ArmISA::FpOp::ternaryOp(), gem5::ArmISA::FpOp::unaryOp(), unsignedRecipEstimate(), unsignedRSqrtEstimate(), vcvtFpDFpH(), and vcvtFpSFpH().

◆ FPToFixed_16()

static uint16_t gem5::ArmISA::FPToFixed_16 ( int  sgn,
int  exp,
uint64_t  mnt,
bool  u,
FPRounding  rounding,
int *  flags 
)
static

Definition at line 4623 of file fplib.cc.

References flags, FP16_BITS, FPLIB_IOC, FPToFixed_64(), u, and gem5::VegaISA::x.

Referenced by fplibFPToFixed().

◆ FPToFixed_32()

static uint32_t gem5::ArmISA::FPToFixed_32 ( int  sgn,
int  exp,
uint64_t  mnt,
bool  u,
FPRounding  rounding,
int *  flags 
)
static

Definition at line 4609 of file fplib.cc.

References flags, FP32_BITS, FPLIB_IOC, FPToFixed_64(), u, and gem5::VegaISA::x.

Referenced by fplibFPToFixed().

◆ FPToFixed_64()

static uint64_t gem5::ArmISA::FPToFixed_64 ( int  sgn,
int  exp,
uint64_t  mnt,
bool  u,
FPRounding  rounding,
int *  flags 
)
static

Definition at line 4560 of file fplib.cc.

References err, flags, FP64_BITS, FP64_EXP_BIAS, FP64_EXP_BITS, FPLIB_IOC, FPLIB_IXC, FPRounding_NEGINF, FPRounding_POSINF, FPRounding_TIEAWAY, FPRounding_TIEEVEN, FPRounding_ZERO, lsl64(), lsr64(), panic, u, and gem5::VegaISA::x.

Referenced by FPToFixed_16(), and FPToFixed_32().

◆ getAff0()

static RegVal gem5::ArmISA::getAff0 ( ArmSystem *  arm_sys,
ThreadContext *  tc 
)
static

Definition at line 206 of file utility.cc.

References gem5::ThreadContext::cpuId(), gem5::System::multiThread, and gem5::ThreadContext::threadId().

Referenced by getAffinity().

◆ getAff1()

static RegVal gem5::ArmISA::getAff1 ( ArmSystem *  arm_sys,
ThreadContext *  tc 
)
static

Definition at line 200 of file utility.cc.

References gem5::ThreadContext::cpuId(), gem5::System::multiThread, and gem5::ThreadContext::socketId().

Referenced by getAffinity().

◆ getAff2()

static RegVal gem5::ArmISA::getAff2 ( ArmSystem *  arm_sys,
ThreadContext *  tc 
)
static

Definition at line 194 of file utility.cc.

References gem5::System::multiThread, and gem5::ThreadContext::socketId().

Referenced by getAffinity().

◆ getAffinity()

Affinity gem5::ArmISA::getAffinity ( ArmSystem *  arm_sys,
ThreadContext *  tc 
)

Retrieves MPIDR_EL1.

{Aff2,Aff1,Aff0} affinity numbers

Definition at line 212 of file utility.cc.

References getAff0(), getAff1(), and getAff2().

Referenced by gem5::Gicv3Redistributor::getAffinity(), getMPIDR(), and gem5::FVPBasePwrCtrl::getThreadContextByMPID().

◆ getFaultVAddr()

bool gem5::ArmISA::getFaultVAddr ( Fault  fault,
Addr &  va 
)

Returns true if the fault passed as a first argument was triggered by a memory access, false otherwise.

If true it is storing the faulting address in the va argument

Parameters
faultgenerated fault
vafunction will modify this passed-by-reference parameter with the correct faulting virtual address
Returns
true if va contains a valid value, false otherwise

Definition at line 1800 of file faults.cc.

References gem5::ArmISA::ArmFault::getFaultVAddr(), and va.

◆ getHSlice()

template<typename ElemType >
MatRow<ElemType> gem5::ArmISA::getHSlice ( MatRegContainer &  reg,
uint8_t  row_idx 
)

Definition at line 122 of file mat.hh.

References gem5::X86ISA::reg.

◆ getMMUPtr()

template<typename T >
MMU* gem5::ArmISA::getMMUPtr ( T *  tc)

Definition at line 516 of file mmu.hh.

Referenced by gem5::ArmISA::ISA::addressTranslation(), gem5::ArmISA::ISA::addressTranslation64(), gem5::ArmISA::ISA::clear(), gem5::ArmISA::TLBIALL::operator()(), gem5::ArmISA::ITLBIALL::operator()(), gem5::ArmISA::DTLBIALL::operator()(), gem5::ArmISA::TLBIALLEL::operator()(), gem5::ArmISA::TLBIVMALL::operator()(), gem5::ArmISA::TLBIASID::operator()(), gem5::ArmISA::ITLBIASID::operator()(), gem5::ArmISA::DTLBIASID::operator()(), gem5::ArmISA::TLBIALLN::operator()(), gem5::ArmISA::TLBIMVAA::operator()(), gem5::ArmISA::TLBIMVA::operator()(), gem5::ArmISA::ITLBIMVA::operator()(), gem5::ArmISA::DTLBIMVA::operator()(), gem5::ArmISA::TLBIIPA::operator()(), and gem5::ArmISA::ISA::setMiscReg().

◆ getMPIDR()

RegVal gem5::ArmISA::getMPIDR ( ArmSystem *  arm_sys,
ThreadContext *  tc 
)

This helper function is returning the value of MPIDR_EL1.

Definition at line 164 of file utility.cc.

References gem5::ThreadContext::cpuId(), getAffinity(), gem5::ArmSystem::multiProc, gem5::System::multiThread, gem5::replaceBits(), and gem5::ThreadContext::socketId().

Referenced by gem5::ArmISA::Reset::invoke(), and readMPIDR().

◆ getPageTableOps()

const PageTableOps * gem5::ArmISA::getPageTableOps ( GrainSize  trans_granule)

Definition at line 476 of file pagetable.cc.

References Grain16KB, Grain4KB, Grain64KB, and panic.

Referenced by gem5::ArmISA::TableWalker::LongDescriptor::offsetBits(), gem5::SMMUTranslationProcess::translateStage1And2(), gem5::SMMUTranslationProcess::translateStage2(), gem5::ArmISA::TableWalker::walkAddresses(), and gem5::SMMUTranslationProcess::walkCacheLookup().

◆ getRestoredITBits()

static uint8_t gem5::ArmISA::getRestoredITBits ( ThreadContext *  tc,
CPSR  spsr 
)
static

Definition at line 1204 of file static_inst.cc.

References gem5::bits(), el, EL2, itd, itState(), MISCREG_HSCTLR, MISCREG_SCTLR, opModeToEL(), and gem5::ThreadContext::readMiscReg().

Referenced by gem5::ArmISA::ArmStaticInst::getPSTATEFromPSR().

◆ getTile()

template<typename ElemType >
MatTile<ElemType> gem5::ArmISA::getTile ( MatRegContainer &  reg,
uint8_t  tile_idx 
)

Definition at line 104 of file mat.hh.

References gem5::X86ISA::reg.

◆ getTileHSlice()

template<typename ElemType >
MatTileRow<ElemType> gem5::ArmISA::getTileHSlice ( MatRegContainer &  reg,
uint8_t  tile_idx,
uint8_t  row_idx 
)

Definition at line 110 of file mat.hh.

References gem5::X86ISA::reg.

◆ getTileVSlice()

template<typename ElemType >
MatTileCol<ElemType> gem5::ArmISA::getTileVSlice ( MatRegContainer &  reg,
uint8_t  tile_idx,
uint8_t  col_idx 
)

Definition at line 116 of file mat.hh.

References gem5::X86ISA::reg.

◆ getVSlice()

template<typename ElemType >
MatCol<ElemType> gem5::ArmISA::getVSlice ( MatRegContainer &  reg,
uint8_t  col_idx 
)

Definition at line 128 of file mat.hh.

References gem5::X86ISA::reg.

◆ haveAArch32EL()

bool gem5::ArmISA::haveAArch32EL ( ThreadContext *  tc,
ExceptionLevel  el 
)

Definition at line 299 of file utility.cc.

References el, EL0, gem5::ArmSystem::haveEL(), gem5::ArmSystem::highestEL(), and gem5::ArmSystem::highestELIs64().

Referenced by ELStateUsingAArch32K().

◆ HaveExt()

bool gem5::ArmISA::HaveExt ( ThreadContext *  tc,
ArmExtension  ext 
)

Returns true if the provided ThreadContext supports the ArmExtension passed as a second argument.

Definition at line 222 of file utility.cc.

References ext, gem5::ThreadContext::getIsaPtr(), gem5::ArmISA::ISA::getRelease(), and gem5::ArmRelease::has().

Referenced by gem5::ArmISA::ArmStaticInst::checkFPAdvSIMDTrap64(), gem5::ArmISA::Interrupts::checkInterrupts(), gem5::ArmISA::MMU::checkPAN(), gem5::ArmISA::ArmStaticInst::checkSmeAccess(), gem5::ArmISA::ArmStaticInst::checkSmeEnabled(), gem5::ArmISA::ArmStaticInst::checkSveEnabled(), gem5::ArmISA::TableWalker::checkVAddrSizeFaultAArch64(), computeAddrTop(), debugTargetFrom(), ELIsInHost(), ELStateUsingAArch32K(), gem5::ArmISA::Interrupts::getInterrupt(), gem5::ArmISA::SelfDebug::isDebugEnabledForEL64(), IsSecureEL2Enabled(), isUnpriviledgeAccess(), gem5::ArmISA::TableWalker::processWalkAArch64(), gem5::ArmISA::DataAbort::routeToHyp(), s1TranslationRegime(), gem5::ArmISA::BrkPoint::test(), gem5::ArmISA::MMU::translateFs(), gem5::ArmISA::MMU::translateMmuOff(), gem5::ArmISA::ArmFault::update(), gem5::ArmISA::MMU::CachedState::updateMiscReg(), and gem5::ArmISA::TableWalker::walk().

◆ highFromDouble()

static uint32_t gem5::ArmISA::highFromDouble ( double  val)
inlinestatic

Definition at line 256 of file vfp.hh.

References fpToBits(), and gem5::X86ISA::val.

◆ illegalExceptionReturn()

static bool gem5::ArmISA::illegalExceptionReturn ( ThreadContext *  tc,
CPSR  cpsr,
CPSR  spsr 
)
static

Definition at line 1233 of file static_inst.cc.

References currEL(), EL0, EL1, EL2, EL3, ELIs64(), ELUsingAArch32K(), gem5::ArmSystem::haveEL(), gem5::ArmSystem::highestELIs64(), isSecureBelowEL3(), IsSecureEL2Enabled(), MISCREG_HCR_EL2, MISCREG_SCR_EL3, mode, opModeToEL(), gem5::ThreadContext::readMiscReg(), unknownMode(), and unknownMode32().

Referenced by gem5::ArmISA::ArmStaticInst::getPSTATEFromPSR().

◆ inAArch64()

bool gem5::ArmISA::inAArch64 ( ThreadContext *  tc)

Definition at line 117 of file utility.cc.

References MISCREG_CPSR, and gem5::ThreadContext::readMiscReg().

Referenced by gem5::ArmSystem::callSemihosting(), gem5::ArmISA::MMU::finalizePhysical(), gem5::fastmodel::FastmodelRemoteGDB::gdbRegs(), gem5::ArmISA::RemoteGDB::gdbRegs(), gem5::ArmISA::RemoteGDB::getXferFeaturesRead(), gem5::Gicv3CPUInterface::isAA64(), gem5::ArmISA::SkipFunc::returnFromFuncIn(), gem5::ArmV8KvmCPU::updateKvmState(), and gem5::ArmV8KvmCPU::updateThreadContext().

◆ inPrivilegedMode()

static bool gem5::ArmISA::inPrivilegedMode ( CPSR  cpsr)
inlinestatic

Definition at line 103 of file utility.hh.

References inUserMode().

◆ inUserMode()

static bool gem5::ArmISA::inUserMode ( CPSR  cpsr)
inlinestatic

Definition at line 97 of file utility.hh.

References MODE_EL0T, and MODE_USER.

Referenced by inPrivilegedMode(), gem5::Iris::ISA::inUserMode(), and gem5::ArmISA::ISA::inUserMode().

◆ isAArch64AArch32SystemAccessTrapEL1()

bool gem5::ArmISA::isAArch64AArch32SystemAccessTrapEL1 ( const MiscRegIndex  misc_reg,
ThreadContext *  tc 
)

Definition at line 791 of file utility.cc.

References currEL(), EL0, isGenericTimerSystemAccessTrapEL1(), MISCREG_CNTFRQ, and MISCREG_CNTVOFF.

Referenced by AArch64AArch32SystemAccessTrap().

◆ isAArch64AArch32SystemAccessTrapEL2()

bool gem5::ArmISA::isAArch64AArch32SystemAccessTrapEL2 ( const MiscRegIndex  misc_reg,
ThreadContext *  tc 
)

Definition at line 915 of file utility.cc.

References currEL(), EL1, isGenericTimerSystemAccessTrapEL2(), MISCREG_CNTFRQ, and MISCREG_CNTVOFF.

Referenced by AArch64AArch32SystemAccessTrap().

◆ isBigEndian64()

bool gem5::ArmISA::isBigEndian64 ( const ThreadContext *  tc)

Definition at line 373 of file utility.cc.

References currEL(), EL0, EL1, EL2, EL3, MISCREG_SCTLR_EL1, MISCREG_SCTLR_EL2, MISCREG_SCTLR_EL3, panic, and gem5::ThreadContext::readMiscRegNoEffect().

Referenced by byteOrder().

◆ isGenericTimerCommonEL0HypTrap()

bool gem5::ArmISA::isGenericTimerCommonEL0HypTrap ( const MiscRegIndex  misc_reg,
ThreadContext *  tc,
ExceptionClass *  ec 
)

Definition at line 831 of file utility.cc.

References condGenericTimerSystemAccessTrapEL1(), ec, EL1, ELIs32(), MISCREG_HCR_EL2, gem5::ThreadContext::readMiscReg(), and UNKNOWN.

Referenced by isGenericTimerHypTrap().

◆ isGenericTimerCommonEL0SystemAccessTrapEL2()

bool gem5::ArmISA::isGenericTimerCommonEL0SystemAccessTrapEL2 ( const MiscRegIndex  misc_reg,
ThreadContext *  tc 
)

Definition at line 963 of file utility.cc.

References condGenericTimerCommonEL0SystemAccessTrapEL2(), condGenericTimerSystemAccessTrapEL1(), EL1, ELIs32(), MISCREG_HCR_EL2, and gem5::ThreadContext::readMiscReg().

Referenced by isGenericTimerSystemAccessTrapEL2().

◆ isGenericTimerHypTrap()

bool gem5::ArmISA::isGenericTimerHypTrap ( const MiscRegIndex  misc_reg,
ThreadContext *  tc,
ExceptionClass *  ec 
)

Definition at line 805 of file utility.cc.

References currEL(), ec, EL0, EL1, EL2, EL2Enabled(), ELIs32(), isGenericTimerCommonEL0HypTrap(), isGenericTimerPhysHypTrap(), MISCREG_CNTFRQ, MISCREG_CNTP_CTL, MISCREG_CNTP_TVAL_S, MISCREG_CNTPCT, and MISCREG_CNTV_TVAL.

Referenced by mcrMrc15TrapToHyp(), and mcrrMrrc15TrapToHyp().

◆ isGenericTimerPhysEL0SystemAccessTrapEL2()

bool gem5::ArmISA::isGenericTimerPhysEL0SystemAccessTrapEL2 ( const MiscRegIndex  misc_reg,
ThreadContext *  tc 
)

Definition at line 976 of file utility.cc.

References condGenericTimerCommonEL1SystemAccessTrapEL2(), condGenericTimerPhysEL1SystemAccessTrapEL2(), MISCREG_CNTP_CTL, MISCREG_CNTP_CTL_EL0, MISCREG_CNTP_TVAL_EL0, MISCREG_CNTP_TVAL_S, MISCREG_CNTPCT, MISCREG_CNTPCT_EL0, MISCREG_HCR_EL2, and gem5::ThreadContext::readMiscReg().

Referenced by isGenericTimerSystemAccessTrapEL2().

◆ isGenericTimerPhysEL1SystemAccessTrapEL2()

bool gem5::ArmISA::isGenericTimerPhysEL1SystemAccessTrapEL2 ( const MiscRegIndex  misc_reg,
ThreadContext *  tc 
)

Definition at line 1001 of file utility.cc.

References condGenericTimerCommonEL1SystemAccessTrapEL2(), condGenericTimerPhysEL1SystemAccessTrapEL2(), MISCREG_CNTP_CTL, MISCREG_CNTP_CTL_EL0, MISCREG_CNTP_TVAL_EL0, MISCREG_CNTP_TVAL_S, MISCREG_CNTPCT, MISCREG_CNTPCT_EL0, MISCREG_HCR_EL2, and gem5::ThreadContext::readMiscReg().

Referenced by isGenericTimerSystemAccessTrapEL2().

◆ isGenericTimerPhysHypTrap()

bool gem5::ArmISA::isGenericTimerPhysHypTrap ( const MiscRegIndex  misc_reg,
ThreadContext *  tc,
ExceptionClass *  ec 
)

Definition at line 847 of file utility.cc.

References condGenericTimerPhysHypTrap().

Referenced by isGenericTimerHypTrap().

◆ isGenericTimerSystemAccessTrapEL1()

bool gem5::ArmISA::isGenericTimerSystemAccessTrapEL1 ( const MiscRegIndex  misc_reg,
ThreadContext *  tc 
)

Definition at line 869 of file utility.cc.

References condGenericTimerSystemAccessTrapEL1(), EL2, EL2Enabled(), ELIs32(), MISCREG_CNTFRQ, MISCREG_CNTFRQ_EL0, MISCREG_CNTV_TVAL, MISCREG_CNTV_TVAL_EL0, MISCREG_HCR_EL2, and gem5::ThreadContext::readMiscReg().

Referenced by isAArch64AArch32SystemAccessTrapEL1().

◆ isGenericTimerSystemAccessTrapEL2()

bool gem5::ArmISA::isGenericTimerSystemAccessTrapEL2 ( const MiscRegIndex  misc_reg,
ThreadContext *  tc 
)

Definition at line 929 of file utility.cc.

References currEL(), EL0, EL1, isGenericTimerCommonEL0SystemAccessTrapEL2(), isGenericTimerPhysEL0SystemAccessTrapEL2(), isGenericTimerPhysEL1SystemAccessTrapEL2(), isGenericTimerVirtSystemAccessTrapEL2(), MISCREG_CNTFRQ, MISCREG_CNTFRQ_EL0, MISCREG_CNTP_CTL, MISCREG_CNTP_CTL_EL0, MISCREG_CNTP_TVAL_EL0, MISCREG_CNTP_TVAL_S, MISCREG_CNTPCT, MISCREG_CNTPCT_EL0, MISCREG_CNTV_CTL, MISCREG_CNTV_CTL_EL0, MISCREG_CNTV_TVAL, MISCREG_CNTV_TVAL_EL0, MISCREG_CNTVCT, and MISCREG_CNTVCT_EL0.

Referenced by isAArch64AArch32SystemAccessTrapEL2().

◆ isGenericTimerSystemAccessTrapEL3()

bool gem5::ArmISA::isGenericTimerSystemAccessTrapEL3 ( const MiscRegIndex  misc_reg,
ThreadContext *  tc 
)

Definition at line 1104 of file utility.cc.

References currEL(), EL1, MISCREG_CNTPS_CTL_EL1, MISCREG_CNTPS_TVAL_EL1, MISCREG_SCR_EL3, and gem5::ThreadContext::readMiscReg().

◆ isGenericTimerVirtSystemAccessTrapEL2()

bool gem5::ArmISA::isGenericTimerVirtSystemAccessTrapEL2 ( const MiscRegIndex  misc_reg,
ThreadContext *  tc 
)

Definition at line 1025 of file utility.cc.

References condGenericTimerCommonEL1SystemAccessTrapEL2(), EL1, ELIs32(), MISCREG_HCR_EL2, and gem5::ThreadContext::readMiscReg().

Referenced by isGenericTimerSystemAccessTrapEL2().

◆ isSecure()

bool gem5::ArmISA::isSecure ( ThreadContext *  tc)

Definition at line 74 of file utility.cc.

References currEL(), EL3, gem5::ArmSystem::haveEL(), isSecureBelowEL3(), MISCREG_CPSR, MODE_MON, and gem5::ThreadContext::readMiscReg().

Referenced by gem5::ArmISA::ArmStaticInst::checkAdvSIMDOrFPEnabled32(), gem5::ArmISA::Interrupts::checkInterrupts(), gem5::ArmISA::ArmStaticInst::checkSETENDEnabled(), gem5::ArmISA::Interrupts::checkWfiWake(), gem5::ArmISA::ArmStaticInst::cpsrWriteByInstr(), gem5::ArmISA::ArmStaticInst::generalExceptionsToAArch64(), gem5::ArmISA::ISA::getCurSmeVecLenInBits(), gem5::ArmISA::ISA::getCurSveVecLenInBits(), gem5::ArmISA::Interrupts::getInterrupt(), gem5::ArmISA::Interrupts::getISR(), gem5::Gicv3CPUInterface::inSecureState(), gem5::ArmISA::SelfDebug::isDebugEnabled(), IsSecureEL2Enabled(), gem5::ArmSemihosting::portProxy(), gem5::ArmISA::ISA::readMiscReg(), gem5::ArmISA::PrefetchAbort::routeToHyp(), gem5::ArmISA::SelfDebug::securityStateMatch(), gem5::Iris::ThreadContext::sendFunctional(), gem5::ArmISA::ISA::setMiscReg(), gem5::ArmISA::Interrupts::takeInt(), gem5::ArmISA::SelfDebug::targetAArch32(), gem5::ArmISA::BrkPoint::test(), gem5::trace::TarmacTracerRecord::TraceInstEntry::TraceInstEntry(), gem5::fastmodel::CortexA76TC::translateAddress(), and gem5::ArmISA::MMU::CachedState::updateMiscReg().

◆ isSecureBelowEL3()

bool gem5::ArmISA::isSecureBelowEL3 ( ThreadContext *  tc)

Definition at line 86 of file utility.cc.

References EL3, gem5::ArmSystem::haveEL(), MISCREG_SCR_EL3, ns, and gem5::ThreadContext::readMiscRegNoEffect().

Referenced by gem5::ArmISA::SoftwareStep::debugExceptionReturnSS(), gem5::ArmISA::MiscRegLUTEntry::defaultFault(), ELIsInHost(), ELUsingAArch32K(), illegalExceptionReturn(), isSecure(), and gem5::Gicv3CPUInterface::isSecureBelowEL3().

◆ IsSecureEL2Enabled()

bool gem5::ArmISA::IsSecureEL2Enabled ( ThreadContext *  tc)

Definition at line 244 of file utility.cc.

References eel2, EL2, EL3, ELIs32(), gem5::ArmSystem::haveEL(), HaveExt(), isSecure(), MISCREG_SCR_EL3, and gem5::ThreadContext::readMiscRegNoEffect().

Referenced by EL2Enabled(), ELIsInHost(), illegalExceptionReturn(), and gem5::ArmISA::MMU::CachedState::updateMiscReg().

◆ issetugidFunc()

static SyscallReturn gem5::ArmISA::issetugidFunc ( SyscallDesc *  desc,
ThreadContext *  tc 
)
static

Definition at line 86 of file se_workload.cc.

◆ isSnan()

template<class fpType >
static bool gem5::ArmISA::isSnan ( fpType  val)
inlinestatic

Definition at line 209 of file vfp.hh.

References fpToBits(), and gem5::X86ISA::val.

◆ isSP()

static bool gem5::ArmISA::isSP ( RegIndex  reg)
inlinestatic

Definition at line 619 of file int.hh.

References gem5::X86ISA::reg, and gem5::ArmISA::int_reg::Spx.

Referenced by gem5::ArmISA::Memory64::Memory64(), gem5::ArmISA::SveContigMemSI::SveContigMemSI(), gem5::ArmISA::SveContigMemSS::SveContigMemSS(), gem5::ArmISA::SveMemPredFillSpill::SveMemPredFillSpill(), gem5::ArmISA::SveMemVecFillSpill::SveMemVecFillSpill(), gem5::ArmISA::VldMultOp64::VldMultOp64(), gem5::ArmISA::VldSingleOp64::VldSingleOp64(), gem5::ArmISA::VstMultOp64::VstMultOp64(), and gem5::ArmISA::VstSingleOp64::VstSingleOp64().

◆ isUnpriviledgeAccess()

bool gem5::ArmISA::isUnpriviledgeAccess ( ThreadContext *  tc)

Definition at line 1237 of file utility.cc.

References currEL(), EL1, EL2, gem5::ArmSystem::haveEL(), HaveExt(), MISCREG_CPSR, MISCREG_HCR_EL2, and gem5::ThreadContext::readMiscReg().

◆ isZero()

static bool gem5::ArmISA::isZero ( RegIndex  reg)
inlinestatic

Definition at line 631 of file int.hh.

References gem5::X86ISA::reg, and gem5::ArmISA::int_reg::Zero.

◆ itState()

static uint8_t gem5::ArmISA::itState ( CPSR  psr)
inlinestatic

Definition at line 191 of file utility.hh.

Referenced by getRestoredITBits(), and gem5::Iris::ThreadContext::pcState().

◆ lockedSnoopHandler()

template<class XC >
static void gem5::ArmISA::lockedSnoopHandler ( ThreadContext *  tc,
XC *  xc,
PacketPtr  pkt,
Addr  cacheBlockMask 
)
inlinestatic

Definition at line 1688 of file isa.cc.

References DPRINTF, gem5::Packet::getAddr(), gem5::ThreadContext::getCpuPtr(), gem5::Packet::isInvalidate(), gem5::Packet::isWrite(), MISCREG_LOCKADDR, MISCREG_LOCKFLAG, MISCREG_SEV_MAILBOX, gem5::Named::name(), and sendEvent().

Referenced by gem5::ArmISA::ISA::handleLockedSnoop().

◆ lockedWriteHandler()

template<class XC >
static bool gem5::ArmISA::lockedWriteHandler ( ThreadContext *  tc,
XC *  xc,
const RequestPtr &  req,
Addr  cacheBlockMask 
)
inlinestatic

Definition at line 1767 of file isa.cc.

References gem5::ThreadContext::contextId(), DPRINTF, gem5::ThreadContext::getCpuPtr(), MISCREG_LOCKADDR, MISCREG_LOCKFLAG, gem5::Named::name(), and warn.

Referenced by gem5::ArmISA::ISA::handleLockedWrite().

◆ longDescFormatInUse()

bool gem5::ArmISA::longDescFormatInUse ( ThreadContext *  tc)

Definition at line 131 of file utility.cc.

References gem5::ArmSystem::has(), MISCREG_TTBCR, and gem5::ThreadContext::readMiscReg().

Referenced by gem5::ArmISA::AbortFault< DataAbort >::invoke(), gem5::ArmISA::TableWalker::processWalkLPAE(), gem5::ArmISA::TableWalker::processWalkWrapper(), gem5::ArmISA::MMU::translateFs(), gem5::ArmISA::MMU::CachedState::updateMiscReg(), and gem5::ArmISA::TableWalker::walk().

◆ lowFromDouble()

static uint32_t gem5::ArmISA::lowFromDouble ( double  val)
inlinestatic

Definition at line 250 of file vfp.hh.

References fpToBits(), and gem5::X86ISA::val.

◆ lsl128()

static void gem5::ArmISA::lsl128 ( uint64_t *  r0,
uint64_t *  r1,
uint64_t  x0,
uint64_t  x1,
uint32_t  shift 
)
inlinestatic

Definition at line 134 of file fplib.cc.

References gem5::MipsISA::r0, and shift.

Referenced by fp64_muladd(), and fp64_sqrt().

◆ lsl16()

static uint16_t gem5::ArmISA::lsl16 ( uint16_t  x,
uint32_t  shift 
)
inlinestatic

Definition at line 98 of file fplib.cc.

References shift, and gem5::VegaISA::x.

Referenced by fp16_add(), and fp16_round_().

◆ lsl32()

static uint32_t gem5::ArmISA::lsl32 ( uint32_t  x,
uint32_t  shift 
)
inlinestatic

Definition at line 110 of file fplib.cc.

References shift, and gem5::VegaISA::x.

Referenced by fp16_mul(), fp16_muladd(), fp32_add(), and fp32_round_().

◆ lsl64()

static uint64_t gem5::ArmISA::lsl64 ( uint64_t  x,
uint32_t  shift 
)
inlinestatic

Definition at line 122 of file fplib.cc.

References shift, and gem5::VegaISA::x.

Referenced by fp32_mul(), fp32_muladd(), fp64_add(), fp64_round_(), fplibFPToFixedJS(), and FPToFixed_64().

◆ lsr128()

static void gem5::ArmISA::lsr128 ( uint64_t *  r0,
uint64_t *  r1,
uint64_t  x0,
uint64_t  x1,
uint32_t  shift 
)
inlinestatic

Definition at line 152 of file fplib.cc.

References gem5::MipsISA::r0, and shift.

Referenced by fp64_div(), fp64_muladd(), and fp64_sqrt().

◆ lsr16()

static uint16_t gem5::ArmISA::lsr16 ( uint16_t  x,
uint32_t  shift 
)
inlinestatic

Definition at line 104 of file fplib.cc.

References shift.

Referenced by fp16_add(), and fp16_round_().

◆ lsr32()

static uint32_t gem5::ArmISA::lsr32 ( uint32_t  x,
uint32_t  shift 
)
inlinestatic

Definition at line 116 of file fplib.cc.

References shift.

Referenced by fp16_mul(), fp16_muladd(), fp32_add(), and fp32_round_().

◆ lsr64()

static uint64_t gem5::ArmISA::lsr64 ( uint64_t  x,
uint32_t  shift 
)
inlinestatic

Definition at line 128 of file fplib.cc.

References shift.

Referenced by fp32_mul(), fp32_muladd(), fp64_add(), fp64_round_(), fplibFPToFixedJS(), and FPToFixed_64().

◆ makeDouble()

static double gem5::ArmISA::makeDouble ( uint32_t  low,
uint32_t  high 
)
inlinestatic

Definition at line 243 of file vfp.hh.

References bitsToFp(), and gem5::high.

◆ makeSP()

static RegIndex gem5::ArmISA::makeSP ( RegIndex  reg)
inlinestatic

Definition at line 605 of file int.hh.

References gem5::X86ISA::reg, gem5::ArmISA::int_reg::Spx, and gem5::ArmISA::int_reg::X31.

Referenced by gem5::ArmISA::PairMemOp::PairMemOp(), gem5::ArmISA::VldMultOp64::VldMultOp64(), gem5::ArmISA::VldSingleOp64::VldSingleOp64(), gem5::ArmISA::VstMultOp64::VstMultOp64(), and gem5::ArmISA::VstSingleOp64::VstSingleOp64().

◆ makeZero()

static RegIndex gem5::ArmISA::makeZero ( RegIndex  reg)
inlinestatic

Definition at line 637 of file int.hh.

References gem5::X86ISA::reg, gem5::ArmISA::int_reg::X31, and gem5::ArmISA::int_reg::Zero.

◆ maskTaggedAddr()

Addr gem5::ArmISA::maskTaggedAddr ( Addr  addr,
ThreadContext *  tc,
ExceptionLevel  el,
int  topbit 
)

Definition at line 449 of file utility.cc.

References gem5::X86ISA::addr, gem5::bits(), el, EL1, ELIsInHost(), and mask.

Referenced by gem5::ArmISA::MMU::purifyTaggedAddr(), and purifyTaggedAddr().

◆ mcrMrc14TrapToHyp()

bool gem5::ArmISA::mcrMrc14TrapToHyp ( const MiscRegIndex  misc_reg,
ThreadContext *  tc,
uint32_t  iss 
)

Definition at line 652 of file utility.cc.

References currEL(), EL2, EL2Enabled(), inform, iss, mcrMrcIssExtract(), MISCREG_DBGDRAR, MISCREG_DBGDSAR, MISCREG_DBGOSDLR, MISCREG_DBGOSLAR, MISCREG_DBGOSLSR, MISCREG_DBGPRCR, MISCREG_HCPTR, MISCREG_HCR_EL2, MISCREG_HDCR, MISCREG_HSTR, MISCREG_JIDR, MISCREG_JMCR, MISCREG_JOSCR, MISCREG_TEECR, MISCREG_TEEHBR, opc2, gem5::ThreadContext::readMiscReg(), rt, and unflattenMiscReg().

◆ mcrMrc15Trap()

Fault gem5::ArmISA::mcrMrc15Trap ( const MiscRegIndex  misc_reg,
ExtMachInst  mach_inst,
ThreadContext *  tc,
uint32_t  imm 
)

Definition at line 495 of file utility.cc.

References AArch64AArch32SystemAccessTrap(), ec, imm, mcrMrc15TrapToHyp(), and TRAPPED_CP15_MCR_MRC.

Referenced by gem5::McrMrcMiscInst::execute(), and gem5::McrMrcImplDefined::execute().

◆ mcrMrc15TrapToHyp()

bool gem5::ArmISA::mcrMrc15TrapToHyp ( const MiscRegIndex  misc_reg,
ThreadContext *  tc,
uint32_t  iss,
ExceptionClass *  ec 
)

Definition at line 505 of file utility.cc.

References currEL(), ec, EL2, EL2Enabled(), isGenericTimerHypTrap(), iss, mcrMrcIssExtract(), MISCREG_ACTLR, MISCREG_ADFSR, MISCREG_AIDR, MISCREG_AIFSR, MISCREG_CCSIDR, MISCREG_CLIDR, MISCREG_CNTFRQ, MISCREG_CNTV_TVAL, MISCREG_CNTVCT, MISCREG_CONTEXTIDR, MISCREG_CPACR, MISCREG_CSSELR, MISCREG_CTR, MISCREG_DACR, MISCREG_DCCIMVAC, MISCREG_DCCISW, MISCREG_DCCMVAC, MISCREG_DCCMVAU, MISCREG_DCCSW, MISCREG_DCIMVAC, MISCREG_DCISW, MISCREG_DFAR, MISCREG_DFSR, MISCREG_DTLBIALL, MISCREG_DTLBIASID, MISCREG_DTLBIMVA, MISCREG_HCPTR, MISCREG_HCR_EL2, MISCREG_HDCR, MISCREG_HSTR, MISCREG_ICC_ASGI1R, MISCREG_ICC_SGI0R, MISCREG_ICC_SGI1R, MISCREG_ICIALLU, MISCREG_ICIALLUIS, MISCREG_ICIMVAU, MISCREG_ID_AFR0, MISCREG_ID_DFR0, MISCREG_ID_ISAR0, MISCREG_ID_ISAR1, MISCREG_ID_ISAR2, MISCREG_ID_ISAR3, MISCREG_ID_ISAR4, MISCREG_ID_ISAR5, MISCREG_ID_ISAR6, MISCREG_ID_MMFR0, MISCREG_ID_MMFR1, MISCREG_ID_MMFR2, MISCREG_ID_MMFR3, MISCREG_ID_MMFR4, MISCREG_ID_PFR0, MISCREG_ID_PFR1, MISCREG_IFAR, MISCREG_IFSR, MISCREG_ITLBIALL, MISCREG_ITLBIASID, MISCREG_ITLBIMVA, MISCREG_MAIR0, MISCREG_MAIR1, MISCREG_NMRR, MISCREG_PMCR, MISCREG_PRRR, MISCREG_REVIDR, MISCREG_SCTLR, MISCREG_TCMTR, MISCREG_TLBIALL, MISCREG_TLBIALLIS, MISCREG_TLBIASID, MISCREG_TLBIASIDIS, MISCREG_TLBIMVA, MISCREG_TLBIMVAA, MISCREG_TLBIMVAAIS, MISCREG_TLBIMVAAL, MISCREG_TLBIMVAALIS, MISCREG_TLBIMVAIS, MISCREG_TLBIMVAL, MISCREG_TLBIMVALIS, MISCREG_TLBTR, MISCREG_TTBCR, MISCREG_TTBR0, MISCREG_TTBR1, opc2, gem5::ThreadContext::readMiscReg(), rt, and unflattenMiscReg().

Referenced by mcrMrc15Trap().

◆ mcrMrcIssBuild()

static uint32_t gem5::ArmISA::mcrMrcIssBuild ( bool  isRead,
uint32_t  crm,
RegIndex  rt,
uint32_t  crn,
uint32_t  opc1,
uint32_t  opc2 
)
inlinestatic

Definition at line 234 of file utility.hh.

References opc2, and rt.

◆ mcrMrcIssExtract()

static void gem5::ArmISA::mcrMrcIssExtract ( uint32_t  iss,
bool &  isRead,
uint32_t &  crm,
RegIndex &  rt,
uint32_t &  crn,
uint32_t &  opc1,
uint32_t &  opc2 
)
inlinestatic

Definition at line 246 of file utility.hh.

References iss, opc2, and rt.

Referenced by mcrMrc14TrapToHyp(), mcrMrc15TrapToHyp(), and mcrrMrrc15TrapToHyp().

◆ mcrrMrrc15Trap()

Fault gem5::ArmISA::mcrrMrrc15Trap ( const MiscRegIndex  misc_reg,
ExtMachInst  mach_inst,
ThreadContext *  tc,
uint32_t  imm 
)

Definition at line 707 of file utility.cc.

References AArch64AArch32SystemAccessTrap(), ec, imm, mcrrMrrc15TrapToHyp(), and TRAPPED_CP15_MCRR_MRRC.

◆ mcrrMrrc15TrapToHyp()

bool gem5::ArmISA::mcrrMrrc15TrapToHyp ( const MiscRegIndex  misc_reg,
ThreadContext *  tc,
uint32_t  iss,
ExceptionClass *  ec 
)

Definition at line 717 of file utility.cc.

References currEL(), ec, EL2, EL2Enabled(), isGenericTimerHypTrap(), iss, mcrMrcIssExtract(), MISCREG_ADFSR, MISCREG_AIFSR, MISCREG_CNTFRQ, MISCREG_CNTV_TVAL, MISCREG_CNTVCT, MISCREG_CONTEXTIDR, MISCREG_DACR, MISCREG_DFAR, MISCREG_DFSR, MISCREG_HCR_EL2, MISCREG_HSTR, MISCREG_IFAR, MISCREG_IFSR, MISCREG_MAIR0, MISCREG_MAIR1, MISCREG_NMRR, MISCREG_PRRR, MISCREG_SCTLR, MISCREG_TTBCR, MISCREG_TTBR0, MISCREG_TTBR1, opc2, gem5::ThreadContext::readMiscReg(), rt, and unflattenMiscReg().

Referenced by mcrrMrrc15Trap().

◆ mcrrMrrcIssBuild()

static uint32_t gem5::ArmISA::mcrrMrrcIssBuild ( bool  isRead,
uint32_t  crm,
RegIndex  rt,
RegIndex  rt2,
uint32_t  opc1 
)
inlinestatic

Definition at line 258 of file utility.hh.

References rt.

◆ modeConv()

static int gem5::ArmISA::modeConv ( FPSCR  fpscr)
static

Definition at line 2217 of file fplib.cc.

References FPLIB_FZ16, and gem5::VegaISA::x.

Referenced by fplibAdd(), fplibCompare(), fplibCompareEQ(), fplibCompareGE(), fplibCompareGT(), fplibCompareUN(), fplibConvert(), fplibDiv(), fplibFPToFixed(), fplibMax(), fplibMin(), fplibMul(), fplibMulAdd(), fplibMulX(), fplibRecipEstimate(), fplibRecipStepFused(), fplibRecpX(), fplibRoundInt(), fplibRSqrtEstimate(), fplibRSqrtStepFused(), fplibScale(), fplibSqrt(), fplibSub(), fplibTrigMulAdd(), and fplibTrigSMul().

◆ modified_imm()

static uint32_t gem5::ArmISA::modified_imm ( uint8_t  ctrlImm,
uint8_t  dataImm 
)
inlinestatic

Definition at line 65 of file pred_inst.hh.

◆ mul62x62()

static void gem5::ArmISA::mul62x62 ( uint64_t *  x0,
uint64_t *  x1,
uint64_t  a,
uint64_t  b 
)
inlinestatic

Definition at line 170 of file fplib.cc.

References a, gem5::MipsISA::a0, a1, b, gem5::QARMA::b0, gem5::QARMA::b1, and mask.

Referenced by fp64_div(), fp64_mul(), fp64_muladd(), and fp64_sqrt().

◆ mul64x32()

static void gem5::ArmISA::mul64x32 ( uint64_t *  x0,
uint64_t *  x1,
uint64_t  a,
uint32_t  b 
)
inlinestatic

Definition at line 188 of file fplib.cc.

References a, b, t0, and t1.

Referenced by fp64_div(), and fp64_sqrt().

◆ number_of_ones()

static unsigned int gem5::ArmISA::number_of_ones ( int32_t  val)
inlinestatic

Definition at line 56 of file macromem.hh.

References i, and gem5::X86ISA::val.

Referenced by gem5::ArmISA::MacroMemOp::MacroMemOp().

◆ opModeIsH()

static bool gem5::ArmISA::opModeIsH ( OperatingMode  mode)
inlinestatic

Definition at line 378 of file types.hh.

References mode, MODE_EL1H, MODE_EL2H, and MODE_EL3H.

◆ opModeIsT()

static bool gem5::ArmISA::opModeIsT ( OperatingMode  mode)
inlinestatic

Definition at line 384 of file types.hh.

References mode, MODE_EL0T, MODE_EL1T, MODE_EL2T, and MODE_EL3T.

Referenced by gem5::ArmISA::ArmFaultVals< FastInterrupt >::offset64().

◆ opModeToEL()

static ExceptionLevel gem5::ArmISA::opModeToEL ( OperatingMode  mode)
inlinestatic

Definition at line 391 of file types.hh.

References EL0, EL1, EL2, EL3, mode, MODE_ABORT, MODE_FIQ, MODE_HYP, MODE_IRQ, MODE_MON, MODE_SVC, MODE_SYSTEM, MODE_UNDEFINED, MODE_USER, and panic.

Referenced by badMode(), badMode32(), currEL(), gem5::ArmISA::ISA::currEL(), gem5::ArmISA::IntRegClassOps::flatten(), getRestoredITBits(), illegalExceptionReturn(), and gem5::ArmISA::ArmFault::update().

◆ prepFpState()

VfpSavedState gem5::ArmISA::prepFpState ( uint32_t  rMode)

Definition at line 183 of file vfp.cc.

References FeAllExceptions, FeRoundDown, FeRoundNearest, FeRoundUpward, FeRoundZero, rMode, VfpRoundDown, VfpRoundNearest, VfpRoundUpward, and VfpRoundZero.

Referenced by gem5::ArmISA::FpOp::binaryOp(), gem5::ArmISA::FpOp::ternaryOp(), and gem5::ArmISA::FpOp::unaryOp().

◆ preUnflattenMiscReg()

void gem5::ArmISA::preUnflattenMiscReg ( )

Definition at line 707 of file misc.cc.

References i, lookUpMiscReg, MISCREG_BANKED, MISCREG_BANKED_CHILD, NUM_MISCREGS, gem5::X86ISA::reg, and unflattenResultMiscReg.

Referenced by gem5::ArmISA::ISA::ISA().

◆ purifyTaggedAddr() [1/2]

Addr gem5::ArmISA::purifyTaggedAddr ( Addr  addr,
ThreadContext *  tc,
ExceptionLevel  el,
bool  is_instr 
)

Definition at line 474 of file utility.cc.

References gem5::X86ISA::addr, el, MISCREG_TCR_EL1, purifyTaggedAddr(), and gem5::ThreadContext::readMiscReg().

◆ purifyTaggedAddr() [2/2]

Addr gem5::ArmISA::purifyTaggedAddr ( Addr  addr,
ThreadContext *  tc,
ExceptionLevel  el,
TCR  tcr,
bool  isInstr 
)

Removes the tag from tagged addresses if that mode is enabled.

Parameters
addrThe address to be purified.
tcThe thread context.
elThe controlled exception level.
Returns
The purified address.

Definition at line 464 of file utility.cc.

References gem5::X86ISA::addr, gem5::bits(), computeAddrTop(), el, and maskTaggedAddr().

Referenced by gem5::ArmISA::ArmFault::invoke64(), purifyTaggedAddr(), and gem5::ArmISA::TableWalker::walk().

◆ readMPIDR()

RegVal gem5::ArmISA::readMPIDR ( ArmSystem *  arm_sys,
ThreadContext *  tc 
)

This helper function is either returing the value of MPIDR_EL1 (by calling getMPIDR), or it is issuing a read to VMPIDR_EL2 (as it happens in virtualized systems)

Definition at line 138 of file utility.cc.

References currEL(), EL0, EL1, EL2, EL2Enabled(), EL3, getMPIDR(), MISCREG_VMPIDR_EL2, panic, gem5::ThreadContext::readMiscReg(), and warn_once.

Referenced by gem5::ArmISA::ISA::readMiscReg().

◆ readVecElem()

XReg gem5::ArmISA::readVecElem ( VReg  src,
int  index,
int  eSize 
)
inline

Read a single NEON vector element.

Definition at line 98 of file neon64_mem.hh.

References data, gem5::ArmISA::VReg::hi, gem5::MipsISA::index, and gem5::ArmISA::VReg::lo.

◆ recipEstimate()

static double gem5::ArmISA::recipEstimate ( double  a)
static

Definition at line 840 of file vfp.cc.

References a, q, gem5::VegaISA::r, and s.

Referenced by fpRecipEstimate(), and unsignedRecipEstimate().

◆ recipSqrtEstimate()

static double gem5::ArmISA::recipSqrtEstimate ( double  a)
static

Definition at line 753 of file vfp.cc.

References a, gem5::VegaISA::r, and s.

Referenced by fprSqrtEstimate(), and unsignedRSqrtEstimate().

◆ resetCPSR()

static CPSR gem5::ArmISA::resetCPSR ( ArmSystem *  system)
static

Definition at line 2256 of file misc.cc.

References EL1, EL2, EL3, gem5::FullSystem, MODE_EL1H, MODE_EL2H, MODE_EL3H, MODE_USER, panic, and gem5::X86ISA::system.

Referenced by gem5::ArmISA::ISA::initializeMiscRegMetadata().

◆ rotate_imm()

static uint32_t gem5::ArmISA::rotate_imm ( uint32_t  immValue,
uint32_t  rotateValue 
)
inlinestatic

Definition at line 57 of file pred_inst.hh.

Referenced by gem5::ArmISA::PredImmOp::PredImmOp().

◆ roundNEven()

template<typename T >
static T gem5::ArmISA::roundNEven ( T  a)
inlinestatic

Definition at line 769 of file vfp.hh.

References a, and gem5::X86ISA::val.

◆ roundPage()

Addr gem5::ArmISA::roundPage ( Addr  addr)

Definition at line 489 of file utility.cc.

References gem5::X86ISA::addr, and PageBytes.

◆ s1TranslationRegime()

ExceptionLevel gem5::ArmISA::s1TranslationRegime ( ThreadContext *  tc,
ExceptionLevel  el 
)

Definition at line 229 of file utility.cc.

References el, EL0, EL1, EL2, EL3, ELIs32(), ELIsInHost(), gem5::ArmSystem::haveEL(), HaveExt(), MISCREG_SCR_EL3, and gem5::ThreadContext::readMiscRegNoEffect().

Referenced by addPAC(), addPACDA(), addPACDB(), addPACIA(), addPACIB(), authDA(), authDB(), authIA(), authIB(), calculateBottomPACBit(), calculateTBI(), computeAddrTop(), gem5::ArmISA::TableWalker::memAttrsAArch64(), and SPAlignmentCheckEnabled().

◆ sendEvent()

void gem5::ArmISA::sendEvent ( ThreadContext *  tc)

Send an event (SEV) to a specific PE if there isn't already a pending event.

Definition at line 65 of file utility.cc.

References gem5::ThreadContext::getCpuPtr(), INT_SEV, MISCREG_SEV_MAILBOX, gem5::BaseCPU::postInterrupt(), gem5::ThreadContext::readMiscReg(), and gem5::ThreadContext::threadId().

Referenced by gem5::GenericTimer::CoreTimers::eventStreamCallback(), gem5::ArmISA::ISA::globalClearExclusive(), lockedSnoopHandler(), gem5::SerialLink::SerialLinkRequestPort::schedTimingReq(), gem5::Bridge::BridgeRequestPort::schedTimingReq(), gem5::SerialLink::SerialLinkResponsePort::schedTimingResp(), gem5::Bridge::BridgeResponsePort::schedTimingResp(), gem5::SerialLink::SerialLinkResponsePort::trySendTiming(), gem5::Bridge::BridgeResponsePort::trySendTiming(), gem5::SerialLink::SerialLinkRequestPort::trySendTiming(), and gem5::Bridge::BridgeRequestPort::trySendTiming().

◆ set_fpscr()

static void gem5::ArmISA::set_fpscr ( FPSCR &  fpscr,
int  flags 
)
static

Definition at line 2225 of file fplib.cc.

References flags, FPLIB_DZC, FPLIB_IDC, FPLIB_IOC, FPLIB_IXC, FPLIB_OFC, and FPLIB_UFC.

Referenced by fplibCompareEQ(), fplibCompareGE(), fplibCompareGT(), and fplibCompareUN().

◆ set_fpscr0()

static void gem5::ArmISA::set_fpscr0 ( FPSCR &  fpscr,
int  flags 
)
static

Definition at line 1915 of file fplib.cc.

References flags, FPLIB_DZC, FPLIB_IDC, FPLIB_IOC, FPLIB_IXC, FPLIB_OFC, and FPLIB_UFC.

Referenced by fplibAdd(), fplibCompare(), fplibConvert(), fplibDiv(), fplibFixedToFP(), fplibFPToFixed(), fplibFPToFixedJS(), fplibMax(), fplibMin(), fplibMul(), fplibMulAdd(), fplibMulX(), fplibRecipEstimate(), fplibRecipStepFused(), fplibRecpX(), fplibRoundInt(), fplibRSqrtEstimate(), fplibRSqrtStepFused(), fplibScale(), fplibSqrt(), fplibSub(), fplibTrigMulAdd(), and fplibTrigSMul().

◆ setFPExceptions()

static void gem5::ArmISA::setFPExceptions ( int  exceptions)
inlinestatic

Definition at line 262 of file vfp.hh.

References FeAllExceptions.

Referenced by vfpFpToFixed().

◆ setTLSFunc32()

static SyscallReturn gem5::ArmISA::setTLSFunc32 ( SyscallDesc *  desc,
ThreadContext *  tc,
uint32_t  tlsPtr 
)
static

Target set_tls() handler.

Definition at line 131 of file se_workload.cc.

References gem5::ArmLinuxProcess32::commPage, MISCREG_TPIDRURO, gem5::ThreadContext::setMiscReg(), and gem5::PortProxy::writeBlob().

◆ setTLSFunc64()

static SyscallReturn gem5::ArmISA::setTLSFunc64 ( SyscallDesc *  desc,
ThreadContext *  tc,
uint32_t  tlsPtr 
)
static

Definition at line 140 of file se_workload.cc.

References MISCREG_TPIDRRO_EL0, and gem5::ThreadContext::setMiscReg().

◆ setVfpMicroFlags()

template<class T >
static void gem5::ArmISA::setVfpMicroFlags ( VfpMicroMode  mode,
T &  flags 
)
inlinestatic

Definition at line 66 of file vfp.hh.

References flags, mode, VfpFirstMicroop, VfpLastMicroop, VfpMicroop, and VfpNotAMicroop.

Referenced by gem5::ArmISA::FpRegImmOp::FpRegImmOp(), gem5::ArmISA::FpRegRegImmOp::FpRegRegImmOp(), gem5::ArmISA::FpRegRegOp::FpRegRegOp(), gem5::ArmISA::FpRegRegRegCondOp::FpRegRegRegCondOp(), gem5::ArmISA::FpRegRegRegImmOp::FpRegRegRegImmOp(), gem5::ArmISA::FpRegRegRegOp::FpRegRegRegOp(), and gem5::ArmISA::FpRegRegRegRegOp::FpRegRegRegRegOp().

◆ simd_modified_imm()

static uint64_t gem5::ArmISA::simd_modified_imm ( bool  op,
uint8_t  cmode,
uint8_t  data,
bool &  immValid,
bool  isAarch64 = false 
)
inlinestatic

Definition at line 88 of file pred_inst.hh.

References gem5::bits(), data, i, and gem5::X86ISA::op.

◆ snsBankedIndex() [1/2]

int gem5::ArmISA::snsBankedIndex ( MiscRegIndex  reg,
ThreadContext *  tc 
)

Definition at line 671 of file misc.cc.

References MISCREG_SCR_EL3, gem5::ThreadContext::readMiscReg(), and gem5::X86ISA::reg.

Referenced by gem5::ArmISA::ArmStaticInst::checkSETENDEnabled(), gem5::ArmISA::TableWalker::memAttrs(), gem5::ArmISA::TableWalker::memAttrsLPAE(), gem5::ArmISA::TableWalker::processWalk(), gem5::ArmISA::TableWalker::processWalkLPAE(), gem5::ArmISA::MMU::CachedState::updateMiscReg(), and gem5::ArmISA::TableWalker::walk().

◆ snsBankedIndex() [2/2]

int gem5::ArmISA::snsBankedIndex ( MiscRegIndex  reg,
ThreadContext *  tc,
bool  ns 
)

Definition at line 678 of file misc.cc.

References EL3, gem5::ArmSystem::haveEL(), gem5::ArmSystem::highestELIs64(), lookUpMiscReg, MISCREG_BANKED, ns, and gem5::X86ISA::reg.

◆ snsBankedIndex64()

int gem5::ArmISA::snsBankedIndex64 ( MiscRegIndex  reg,
ThreadContext *  tc 
)

Definition at line 689 of file misc.cc.

References gem5::ThreadContext::getIsaPtr(), MISCREG_SCR_EL3, gem5::ThreadContext::readMiscReg(), and gem5::X86ISA::reg.

◆ SPAlignmentCheckEnabled()

bool gem5::ArmISA::SPAlignmentCheckEnabled ( ThreadContext *  tc)

Definition at line 1255 of file utility.cc.

References currEL(), EL0, EL1, EL2, EL3, MISCREG_SCTLR_EL1, MISCREG_SCTLR_EL2, MISCREG_SCTLR_EL3, panic, gem5::ThreadContext::readMiscReg(), and s1TranslationRegime().

◆ stripPAC()

void gem5::ArmISA::stripPAC ( ThreadContext *  tc,
uint64_t  A,
bool  data,
uint64_t *  out 
)

Definition at line 866 of file pauth_helpers.cc.

References gem5::bits(), calculateBottomPACBit(), calculateTBI(), currEL(), data, el, mask, and tbi.

◆ sub128()

static void gem5::ArmISA::sub128 ( uint64_t *  x0,
uint64_t *  x1,
uint64_t  a0,
uint64_t  a1,
uint64_t  b0,
uint64_t  b1 
)
inlinestatic

Definition at line 205 of file fplib.cc.

References gem5::MipsISA::a0, a1, gem5::QARMA::b0, and gem5::QARMA::b1.

Referenced by fp64_div(), and fp64_muladd().

◆ SubBitUnion() [1/2]

gem5::ArmISA::SubBitUnion ( cond_iss  ,
24  ,
0   
)

◆ SubBitUnion() [2/2]

gem5::ArmISA::SubBitUnion ( puswl  ,
24  ,
20   
)

◆ sveDecodePredCount()

unsigned int gem5::ArmISA::sveDecodePredCount ( uint8_t  imm,
unsigned int  num_elems 
)

Returns the actual number of elements active for PTRUE(S) instructions.

Parameters
imm5-bit immediate encoding the predicate pattern.
num_elemsCurrent number of elements per vector (depending on current vector length and element size).

Definition at line 913 of file sve.cc.

References imm.

◆ sveDisasmPredCountImm()

std::string gem5::ArmISA::sveDisasmPredCountImm ( uint8_t  imm)

Returns the symbolic name associated with pattern imm for PTRUE(S) instructions.

Definition at line 881 of file sve.cc.

References imm, and sc_dt::to_string().

Referenced by gem5::ArmISA::SvePtrueOp::generateDisassembly(), and gem5::ArmISA::SveElemCountOp::generateDisassembly().

◆ sveExpandFpImmAddSub()

uint64_t gem5::ArmISA::sveExpandFpImmAddSub ( uint8_t  imm,
uint8_t  size 
)

Expand 1-bit floating-point immediate to 0.5 or 1.0 (FADD, FSUB, FSUBR).

Parameters
imm1-bit immediate.
sizeEncoding of the vector element size.
Returns
Encoding of the expanded value.

Definition at line 956 of file sve.cc.

References imm, and panic.

◆ sveExpandFpImmMaxMin()

uint64_t gem5::ArmISA::sveExpandFpImmMaxMin ( uint8_t  imm,
uint8_t  size 
)

Expand 1-bit floating-point immediate to 0.0 or 1.0 (FMAX, FMAXNM, FMIN, FMINNM).

Parameters
imm1-bit immediate.
sizeEncoding of the vector element size.
Returns
Encoding of the expanded value.

Definition at line 978 of file sve.cc.

References imm, and panic.

◆ sveExpandFpImmMul()

uint64_t gem5::ArmISA::sveExpandFpImmMul ( uint8_t  imm,
uint8_t  size 
)

Expand 1-bit floating-point immediate to 0.5 or 2.0 (FMUL).

Parameters
imm1-bit immediate.
sizeEncoding of the vector element size.
Returns
Encoding of the expanded value.

Definition at line 997 of file sve.cc.

References imm, and panic.

◆ svePredTypeToStr()

const char * gem5::ArmISA::svePredTypeToStr ( SvePredType  pt)

Returns the specifier for the predication type pt as a string.

Definition at line 48 of file sve.cc.

References MERGE, and ZERO.

Referenced by gem5::ArmISA::SveBinConstrPredOp::generateDisassembly().

◆ syncVecElemsToRegs()

void gem5::ArmISA::syncVecElemsToRegs ( ThreadContext *  tc)

Definition at line 1337 of file utility.cc.

References gem5::ThreadContext::getReg(), j, NumVecElemPerVecReg, NumVecRegs, gem5::X86ISA::reg, gem5::PowerISA::ri, gem5::ThreadContext::setReg(), vecElemClass, and vecRegClass.

Referenced by gem5::ArmISA::ArmFault::invoke(), and gem5::ArmV8KvmCPU::updateKvmState().

◆ syncVecRegsToElems()

void gem5::ArmISA::syncVecRegsToElems ( ThreadContext *  tc)

Definition at line 1325 of file utility.cc.

References gem5::ThreadContext::getReg(), j, NumVecElemPerVecReg, NumVecRegs, gem5::X86ISA::reg, gem5::PowerISA::ri, gem5::ThreadContext::setReg(), vecElemClass, and vecRegClass.

Referenced by gem5::ArmISA::ArmFault::invoke(), and gem5::ArmV8KvmCPU::updateThreadContext().

◆ sysctlFunc()

static SyscallReturn gem5::ArmISA::sysctlFunc ( SyscallDesc *  desc,
ThreadContext *  tc,
VPtr<>  namep,
size_t  nameLen,
VPtr<>  oldp,
VPtr<>  oldlenp,
VPtr<>  newp,
size_t  newlen 
)
static

Definition at line 93 of file se_workload.cc.

References gem5::BufferArg::bufferPtr(), gem5::BaseBufferArg::copyIn(), and gem5::BaseBufferArg::copyOut().

◆ testPredicate()

bool gem5::ArmISA::testPredicate ( uint32_t  nz,
uint32_t  c,
uint32_t  v,
ConditionCode  code 
)
inline

Definition at line 65 of file utility.hh.

References c, COND_AL, COND_CC, COND_CS, COND_EQ, COND_GE, COND_GT, COND_HI, COND_LE, COND_LS, COND_LT, COND_MI, COND_NE, COND_PL, COND_UC, COND_VC, COND_VS, n, nz, panic, v, and z.

◆ trapPACUse()

Fault gem5::ArmISA::trapPACUse ( ThreadContext *  tc,
ExceptionLevel  el 
)

Definition at line 117 of file pauth_helpers.cc.

References currEL(), EL0, EL2, EL3, gem5::ArmSystem::haveEL(), gem5::NoFault, and TRAPPED_PAC.

Referenced by addPACDA(), addPACDB(), addPACGA(), addPACIA(), addPACIB(), authDA(), authDB(), authIA(), and authIB().

◆ truncPage()

Addr gem5::ArmISA::truncPage ( Addr  addr)

Definition at line 483 of file utility.cc.

References gem5::X86ISA::addr, and PageBytes.

◆ unameFunc32()

static SyscallReturn gem5::ArmISA::unameFunc32 ( SyscallDesc *  desc,
ThreadContext *  tc,
VPtr< Linux::utsname >  name 
)
static

Target uname() handler.

Definition at line 101 of file se_workload.cc.

References gem5::ThreadContext::getProcessPtr(), and name().

Referenced by gem5::ArmISA::SyscallTable32::SyscallTable32().

◆ unameFunc64()

static SyscallReturn gem5::ArmISA::unameFunc64 ( SyscallDesc *  desc,
ThreadContext *  tc,
VPtr< Linux::utsname >  name 
)
static

Target uname() handler.

Definition at line 116 of file se_workload.cc.

References gem5::ThreadContext::getProcessPtr(), and name().

Referenced by gem5::ArmISA::SyscallTable64::SyscallTable64().

◆ unflattenMiscReg()

int gem5::ArmISA::unflattenMiscReg ( int  reg)

Definition at line 723 of file misc.cc.

References gem5::X86ISA::reg, and unflattenResultMiscReg.

Referenced by mcrMrc14TrapToHyp(), mcrMrc15TrapToHyp(), mcrrMrrc15TrapToHyp(), gem5::ArmISA::PMU::readMiscReg(), gem5::ArmISA::ISA::readMiscReg(), gem5::ArmISA::PMU::readMiscRegInt(), gem5::ArmISA::PMU::setMiscReg(), and gem5::ArmISA::ISA::setMiscReg().

◆ unknownMode()

static bool gem5::ArmISA::unknownMode ( OperatingMode  mode)
inlinestatic

Definition at line 420 of file types.hh.

References mode, MODE_ABORT, MODE_EL0T, MODE_EL1H, MODE_EL1T, MODE_EL2H, MODE_EL2T, MODE_EL3H, MODE_EL3T, MODE_FIQ, MODE_HYP, MODE_IRQ, MODE_MON, MODE_SVC, MODE_SYSTEM, MODE_UNDEFINED, and MODE_USER.

Referenced by badMode(), and illegalExceptionReturn().

◆ unknownMode32()

static bool gem5::ArmISA::unknownMode32 ( OperatingMode  mode)
inlinestatic

Definition at line 446 of file types.hh.

References mode, MODE_ABORT, MODE_FIQ, MODE_HYP, MODE_IRQ, MODE_MON, MODE_SVC, MODE_SYSTEM, MODE_UNDEFINED, and MODE_USER.

Referenced by badMode32(), gem5::ArmISA::ArmStaticInst::getPSTATEFromPSR(), and illegalExceptionReturn().

◆ unsignedRecipEstimate()

uint32_t gem5::ArmISA::unsignedRecipEstimate ( uint32_t  op)

Definition at line 889 of file vfp.cc.

References gem5::bits(), bitsToFp(), fpToBits(), gem5::X86ISA::op, and recipEstimate().

◆ unsignedRSqrtEstimate()

uint32_t gem5::ArmISA::unsignedRSqrtEstimate ( uint32_t  op)

Definition at line 814 of file vfp.cc.

References gem5::bits(), bitsToFp(), fpToBits(), gem5::X86ISA::op, and recipSqrtEstimate().

◆ upperAndLowerRange()

bool gem5::ArmISA::upperAndLowerRange ( ThreadContext *  tc,
ExceptionLevel  el 
)
inline

Definition at line 57 of file pauth_helpers.hh.

References el, EL0, EL1, EL2, MISCREG_HCR_EL2, and gem5::ThreadContext::readMiscReg().

Referenced by addPAC(), calculateBottomPACBit(), and calculateTBI().

◆ vcvtFpDFpH()

uint16_t gem5::ArmISA::vcvtFpDFpH ( FPSCR &  fpscr,
bool  flush,
bool  defaultNan,
uint32_t  rMode,
bool  ahp,
double  op 
)

Definition at line 585 of file vfp.cc.

References ahp, fpToBits(), gem5::X86ISA::op, rMode, and vcvtFpFpH().

◆ vcvtFpFpH()

static uint16_t gem5::ArmISA::vcvtFpFpH ( FPSCR &  fpscr,
bool  flush,
bool  defaultNan,
uint32_t  rMode,
bool  ahp,
uint64_t  opBits,
bool  isDouble 
)
inlinestatic

Definition at line 405 of file vfp.cc.

References ahp, gem5::bits(), mask, mode, sc_dt::neg(), gem5::replaceBits(), rMode, VfpRoundDown, VfpRoundNearest, and VfpRoundUpward.

Referenced by vcvtFpDFpH(), and vcvtFpSFpH().

◆ vcvtFpHFp()

static uint64_t gem5::ArmISA::vcvtFpHFp ( FPSCR &  fpscr,
bool  defaultNan,
bool  ahp,
uint16_t  op,
bool  isDouble 
)
inlinestatic

Definition at line 593 of file vfp.cc.

References ahp, gem5::bits(), mask, sc_dt::neg(), gem5::X86ISA::op, and gem5::replaceBits().

Referenced by vcvtFpHFpD(), and vcvtFpHFpS().

◆ vcvtFpHFpD()

double gem5::ArmISA::vcvtFpHFpD ( FPSCR &  fpscr,
bool  defaultNan,
bool  ahp,
uint16_t  op 
)

Definition at line 655 of file vfp.cc.

References ahp, bitsToFp(), gem5::X86ISA::op, and vcvtFpHFp().

◆ vcvtFpHFpS()

float gem5::ArmISA::vcvtFpHFpS ( FPSCR &  fpscr,
bool  defaultNan,
bool  ahp,
uint16_t  op 
)

Definition at line 665 of file vfp.cc.

References ahp, bitsToFp(), gem5::X86ISA::op, and vcvtFpHFp().

◆ vcvtFpSFpH()

uint16_t gem5::ArmISA::vcvtFpSFpH ( FPSCR &  fpscr,
bool  flush,
bool  defaultNan,
uint32_t  rMode,
bool  ahp,
float  op 
)

Definition at line 577 of file vfp.cc.

References ahp, fpToBits(), gem5::X86ISA::op, rMode, and vcvtFpFpH().

◆ vfp_modified_imm()

static uint64_t gem5::ArmISA::vfp_modified_imm ( uint8_t  data,
FpDataType  dtype 
)
inlinestatic

Definition at line 171 of file pred_inst.hh.

References gem5::bits(), data, Fp16, Fp32, Fp64, and panic.

◆ vfpFlushToZero() [1/2]

template<class fpType >
static void gem5::ArmISA::vfpFlushToZero ( FPSCR &  fpscr,
fpType &  op 
)
inlinestatic

Definition at line 144 of file vfp.hh.

References flushToZero, and gem5::X86ISA::op.

Referenced by vfpFlushToZero().

◆ vfpFlushToZero() [2/2]

template<class fpType >
static void gem5::ArmISA::vfpFlushToZero ( FPSCR &  fpscr,
fpType &  op1,
fpType &  op2 
)
inlinestatic

Definition at line 153 of file vfp.hh.

References vfpFlushToZero().

◆ vfpFpToFixed()

template<typename T >
uint64_t gem5::ArmISA::vfpFpToFixed ( T  val,
bool  isSigned,
uint8_t  width,
uint8_t  imm,
bool  useRmode = true,
VfpRoundingMode  roundMode = VfpRoundZero,
bool  aarch64 = false 
)

Definition at line 269 of file vfp.hh.

References aarch64, error, FeAllExceptions, FeInexact, FeInvalid, FeRoundDown, FeRoundNearest, FeRoundUpward, FeRoundZero, imm, mask, panic, setFPExceptions(), gem5::X86ISA::val, VfpRoundAway, VfpRoundDown, VfpRoundNearest, VfpRoundUpward, VfpRoundZero, and width.

◆ vfpSFixedToFpD()

double gem5::ArmISA::vfpSFixedToFpD ( bool  flush,
bool  defaultNan,
int64_t  val,
uint8_t  width,
uint8_t  imm 
)

Definition at line 732 of file vfp.cc.

References FeAllExceptions, FeRoundNearest, fixDivDest(), imm, panic, gem5::X86ISA::scale, gem5::X86ISA::val, and width.

◆ vfpSFixedToFpS()

float gem5::ArmISA::vfpSFixedToFpS ( bool  flush,
bool  defaultNan,
int64_t  val,
uint8_t  width,
uint8_t  imm 
)

Definition at line 693 of file vfp.cc.

References FeAllExceptions, FeRoundNearest, fixDivDest(), imm, panic, gem5::X86ISA::scale, gem5::X86ISA::val, and width.

◆ vfpUFixedToFpD()

double gem5::ArmISA::vfpUFixedToFpD ( bool  flush,
bool  defaultNan,
uint64_t  val,
uint8_t  width,
uint8_t  imm 
)

Definition at line 713 of file vfp.cc.

References FeAllExceptions, FeRoundNearest, fixDivDest(), imm, panic, gem5::X86ISA::scale, gem5::X86ISA::val, and width.

◆ vfpUFixedToFpS()

float gem5::ArmISA::vfpUFixedToFpS ( bool  flush,
bool  defaultNan,
uint64_t  val,
uint8_t  width,
uint8_t  imm 
)

Definition at line 675 of file vfp.cc.

References FeAllExceptions, FeRoundNearest, fixDivDest(), imm, panic, gem5::X86ISA::scale, gem5::X86ISA::val, and width.

◆ writeVecElem()

void gem5::ArmISA::writeVecElem ( VReg *  dest,
XReg  src,
int  index,
int  eSize 
)
inline

Write a single NEON vector element leaving the others untouched.

Definition at line 64 of file neon64_mem.hh.

References gem5::ArmISA::VReg::hi, gem5::MipsISA::index, and gem5::ArmISA::VReg::lo.

Variable Documentation

◆ a

Bitfield< 1 > gem5::ArmISA::a

Definition at line 66 of file misc_types.hh.

Referenced by gem5::AddrRange::addIntlvBits(), addSubColumns(), gem5::ArmISA::Crypto::aesFFMul(), gem5::ArmISA::Crypto::aesFFMul2(), sc_dt::sc_uint_subref_r::and_reduce(), sc_dt::sc_int_subref_r::and_reduce(), sc_dt::and_reduce(), sc_dt::sc_proxy< sc_bv_base >::assign_(), sc_dt::assign_v_(), gem5::SMMUv3DeviceInterface::atsRecvAtomic(), sc_dt::b_and_assign_(), sc_dt::sc_bit::b_not(), sc_dt::b_not(), sc_dt::b_xor(), gem5::prefetch::Base::blockAddress(), gem5::prefetch::Base::blockIndex(), gem5::branch_prediction::TAGE_SC_L_TAGE::calcDep(), gem5::PowerISA::IntTrapOp::checkTrap(), gem5::ruby::MN_TBETable::chooseNewDistributor(), sc_dt::sc_lv_base::clean_tail(), gem5::GicV2Registers::clearBankedDistRange(), gem5::GicV2Registers::clearDistRange(), gem5::Gicv3Registers::clearDistRange(), sc_dt::sc_concref< X, Y >::clone(), gem5::SMMUTranslationProcess::completePrefetch(), gem5::SMMUTranslationProcess::completeTransaction(), gem5::IGbE::TxDescCache::completionWriteback(), sc_dt::concat(), gem5::VMA::contains(), gem5::ChannelAddrRange::contains(), gem5::AddrRange::contains(), sc_dt::convert_to_bin(), gem5::GicV2Registers::copyBankedDistRange(), gem5::GicV2Registers::copyDistRange(), gem5::Gicv3Registers::copyDistRange(), gem5::Gicv3Registers::copyRedistRange(), gem5::divCeil(), gem5::SMMUProcess::doDelay(), gem5::SMMUProcess::doRead(), gem5::ItsProcess::doRead(), gem5::SMMUProcess::doSleep(), gem5::SMMUProcess::doWrite(), gem5::ItsProcess::doWrite(), sc_dt::equal(), sc_dt::scfx_ieee_double::exponent(), sc_dt::extend_sign_w_(), gem5::branch_prediction::TAGE_SC_L_TAGE::F(), fp16_add(), fp16_compare_eq(), fp16_compare_ge(), fp16_compare_gt(), fp16_compare_un(), fp16_cvtf(), fp16_div(), fp16_mul(), fp16_muladd(), fp16_process_NaN(), fp16_process_NaNs(), fp16_process_NaNs3(), fp16_scale(), fp16_sqrt(), fp32_add(), fp32_compare_eq(), fp32_compare_ge(), fp32_compare_gt(), fp32_compare_un(), fp32_cvtf(), fp32_div(), fp32_mul(), fp32_muladd(), fp32_process_NaN(), fp32_process_NaNs(), fp32_process_NaNs3(), fp32_scale(), fp32_sqrt(), fp64_add(), fp64_compare_eq(), fp64_compare_ge(), fp64_compare_gt(), fp64_compare_un(), fp64_cvtf(), fp64_div(), fp64_mul(), fp64_muladd(), fp64_process_NaN(), fp64_process_NaNs(), fp64_process_NaNs3(), fp64_scale(), fp64_sqrt(), fpAdd(), fpAddD(), fpAddS(), fpDiv(), fpDivD(), fpDivS(), fplibCompareEQ(), fplibCompareGE(), fplibCompareGT(), fplibCompareUN(), fpMax(), fpMaxNum(), fpMin(), fpMinNum(), fpMul(), fpMulD(), fpMulS(), fpMulX(), fpRecps(), fpRecpsS(), fpRIntX(), fpRSqrts(), fpRSqrtsS(), fpSub(), fpSubD(), fpSubS(), gem5::Gicv2m::frameFromAddr(), gem5::fastmodel::ScxEvsCortexR52< Types >::gem5_getPort(), sc_dt::sc_bitref_r< T >::get_word(), gem5::branch_prediction::MultiperspectivePerceptron::ACYCLIC::getHash(), gem5::branch_prediction::MultiperspectivePerceptron::MODHIST::getHash(), gem5::branch_prediction::MultiperspectivePerceptron::MODPATH::getHash(), gem5::branch_prediction::MultiperspectivePerceptron::GHISTMODPATH::getHash(), gem5::branch_prediction::MultiperspectivePerceptron::SGHISTPATH::getHash(), gem5::AddrRange::getOffset(), gem5::branch_prediction::MPP_TAGE::handleAllocAndUReset(), gem5::branch_prediction::MultiperspectivePerceptron::GHIST::hash(), gem5::branch_prediction::MultiperspectivePerceptron::MPPBranchInfo::hash1(), gem5::stl_helpers::hash_impl::hash_combine(), gem5::KernelWorkload::initState(), sc_dt::scfx_rep::is_neg(), QTIsaac< ALPHA >::isaac(), gem5::KernelWorkload::KernelWorkload(), sc_dt::sc_proxy< sc_bv_base >::lrotate(), sc_dt::lrotate(), sc_dt::lshift(), gem5::pseudo_inst::m5sum(), gem5::SMMUCommandExecProcess::main(), gem5::SMMUTranslationProcess::main(), gem5::ItsCommand::main(), gem5::PowerISA::FloatOp::makeCRField(), gem5::PowerISA::IntOp::makeCRFieldSigned(), gem5::PowerISA::IntOp::makeCRFieldUnsigned(), gem5::loader::MemoryImage::mask(), gem5::MathExpr::MathExpr(), mul62x62(), mul64x32(), multiply2Op(), multiply3Op(), sc_dt::nand_reduce(), sc_dt::neg(), sc_dt::scfx_ieee_double::negative(), sc_dt::scfx_ieee_float::negative(), sc_dt::nor_reduce(), gem5::loader::MemoryImage::offset(), sc_dt::sc_logic::operator delete(), sc_dt::sc_logic::operator new(), gem5::operator!=(), sc_dt::operator!=(), sc_dt::operator&(), sc_dt::operator&=(), sc_dt::sc_bitref< X >::operator&=(), gem5::SNHash::operator()(), std::hash< gem5::ChannelAddr >::operator()(), gem5::ConstProxyPtr< T, Proxy >::operator+(), gem5::operator+(), sc_core::operator+(), sc_dt::operator,(), gem5::ConstProxyPtr< T, Proxy >::operator-(), sc_core::operator-(), sc_dt::operator/(), sc_dt::operator<(), operator<<(), gem5::networking::operator<<(), sc_dt::operator<<(), sc_core::operator<<(), sc_dt::operator<=(), sc_dt::sc_fxcast_switch::operator=(), sc_dt::sc_fxtype_params::operator=(), sc_dt::sc_length_param::operator=(), sc_dt::sc_bv_base::operator=(), sc_dt::scfx_ieee_double::operator=(), sc_dt::sc_lv_base::operator=(), gem5::ConstProxyPtr< T, Proxy >::operator=(), sc_dt::sc_uint< W >::operator=(), sc_dt::sc_int< W >::operator=(), sc_dt::sc_uint_subref::operator=(), sc_dt::scfx_ieee_float::operator=(), sc_dt::sc_bitref< X >::operator=(), sc_dt::sc_int_subref::operator=(), sc_dt::sc_uint_base::operator=(), sc_dt::sc_int_base::operator=(), sc_dt::sc_unsigned_subref::operator=(), sc_dt::sc_subref< X >::operator=(), sc_dt::sc_signed_subref::operator=(), sc_dt::sc_unsigned::operator=(), sc_dt::sc_signed::operator=(), gem5::operator==(), sc_dt::operator==(), sc_dt::operator>(), sc_dt::operator>=(), sc_dt::sc_proxy< sc_bv_base >::operator>>(), sc_dt::operator>>(), sc_dt::operator^=(), sc_dt::operator|(), sc_dt::operator|=(), sc_dt::sc_bitref< X >::operator|=(), sc_dt::operator~(), sc_dt::sc_uint_subref_r::or_reduce(), sc_dt::sc_int_subref_r::or_reduce(), sc_dt::or_reduce(), gem5::prefetch::Base::pageAddress(), gem5::EmulationPageTable::pageAlign(), gem5::EmulationPageTable::pageOffset(), gem5::prefetch::Base::pageOffset(), gem5::IGbE::DescCache< igbreg::RxDesc >::pciToDma(), gem5::PMP::pmpGetAField(), gem5::GarnetSyntheticTraffic::printAddr(), gem5::RequestPort::printAddr(), gem5::AtomicSimpleCPU::printAddr(), gem5::TimingSimpleCPU::printAddr(), gem5::StackDistCalc::printStack(), gem5::SMMUv3::processCommands(), QTIsaac< ALPHA >::QTIsaac(), QTIsaac< ALPHA >::randinit(), recipEstimate(), recipSqrtEstimate(), gem5::SMMUv3DeviceInterface::recvAtomic(), gem5::Gicv3Its::recvReqRetry(), gem5::SMMUv3::recvReqRetry(), gem5::AddrRange::removeIntlvBits(), QTIsaac< ALPHA >::rngstep(), roundNEven(), sc_dt::sc_proxy< sc_bv_base >::rrotate(), sc_dt::rsh_scfx_rep(), sc_dt::scfx_rep::rshift(), sc_dt::rshift(), gem5::prefetch::Base::samePage(), sc_dt::sc_abs(), sc_dt::sc_biguint< W >::sc_biguint(), sc_dt::sc_bitref< X >::sc_bitref(), sc_dt::sc_bv< W >::sc_bv(), sc_dt::sc_bv_base::sc_bv_base(), sc_dt::sc_fxval::sc_fxval(), sc_dt::sc_fxval_fast::sc_fxval_fast(), sc_dt::sc_int< W >::sc_int(), sc_dt::sc_int_base::sc_int_base(), sc_dt::sc_lv< W >::sc_lv(), sc_dt::sc_lv_base::sc_lv_base(), sc_dt::sc_max(), sc_dt::sc_min(), SC_MODULE(), sc_dt::sc_uint< W >::sc_uint(), sc_dt::sc_uint_base::sc_uint_base(), sc_dt::sc_bitref< X >::scan(), sc_dt::sc_subref< X >::scan(), sc_dt::sc_concref< X, Y >::scan(), sc_dt::scfx_ieee_double::scfx_ieee_double(), sc_dt::scfx_ieee_float::scfx_ieee_float(), sc_dt::scfx_pow2(), sc_dt::scfx_rep::scfx_rep(), sc_dt::sc_lv_base::set_bit(), sc_dt::sc_bitref< X >::set_cword(), sc_dt::scfx_rep::set_inf(), gem5::trace::InstRecord::setMem(), QTIsaac< ALPHA >::shuffle(), gem5::ruby::WeightBased::sortLinks(), QTIsaac< ALPHA >::srand(), gem5::swap_byte(), gem5::SMMUv3::tableWalkRecvReqRetry(), gem5::ItsProcess::terminate(), TEST(), test2DVoid(), testIntVoid(), testPrepareInt(), testPrepareVoid(), testTcInit(), sc_dt::sc_proxy< sc_bv_base >::to_anything_signed(), sc_dt::sc_uint_subref_r::to_double(), sc_dt::sc_uint_subref_r::to_int(), sc_dt::sc_uint_subref_r::to_int64(), sc_dt::sc_uint_subref_r::to_long(), sc_dt::scfx_rep::to_string(), sc_dt::sc_uint_subref_r::to_string(), sc_dt::sc_int_subref_r::to_string(), sc_dt::sc_uint_subref_r::to_uint(), sc_dt::sc_uint_subref_r::to_uint64(), sc_dt::sc_uint_subref_r::to_ulong(), gem5::trace::InstPBTrace::traceMem(), gem5::branch_prediction::MultiperspectivePerceptron::update(), gem5::StackDistCalc::verifyStackDist(), gem5::SparcISA::TLB::writeSfsr(), sc_dt::xnor_reduce(), sc_dt::sc_uint_subref_r::xor_reduce(), sc_dt::sc_int_subref_r::xor_reduce(), sc_dt::xor_reduce(), and sc_dt::sc_lv_base::~sc_lv_base().

◆ a1

Bitfield< 22 > gem5::ArmISA::a1

Definition at line 558 of file misc_types.hh.

Referenced by add128(), gem5::branch_prediction::TAGE_SC_L_TAGE::F(), mul62x62(), SC_MODULE(), and sub128().

◆ aarch64

Bitfield<34> gem5::ArmISA::aarch64

Definition at line 81 of file types.hh.

Referenced by gem5::ArmSemihosting::gatherHeapInfo(), gem5::ArmISA::MMU::CachedState::updateMiscReg(), and vfpFpToFixed().

◆ advsimd

Bitfield<23, 20> gem5::ArmISA::advsimd

Definition at line 200 of file misc_types.hh.

Referenced by gem5::ArmISA::ArmStaticInst::checkAdvSIMDOrFPEnabled32().

◆ advSimdHalfPrecision

Bitfield<23, 20> gem5::ArmISA::advSimdHalfPrecision

Definition at line 539 of file misc_types.hh.

◆ advSimdInteger

Bitfield<15, 12> gem5::ArmISA::advSimdInteger

Definition at line 537 of file misc_types.hh.

◆ advSimdLoadStore

Bitfield<11, 8> gem5::ArmISA::advSimdLoadStore

Definition at line 536 of file misc_types.hh.

◆ advSimdRegisters

gem5::ArmISA::advSimdRegisters

Definition at line 523 of file misc_types.hh.

◆ advSimdSinglePrecision

Bitfield<19, 16> gem5::ArmISA::advSimdSinglePrecision

Definition at line 538 of file misc_types.hh.

◆ aes

Bitfield< 7, 4 > gem5::ArmISA::aes

Definition at line 84 of file misc_types.hh.

◆ afe

Bitfield<29> gem5::ArmISA::afe

Definition at line 395 of file misc_types.hh.

◆ aff0

Bitfield<7, 0> gem5::ArmISA::aff0

Definition at line 209 of file types.hh.

◆ aff1

Bitfield<15, 8> gem5::ArmISA::aff1

Definition at line 208 of file types.hh.

Referenced by gem5::Gicv3CPUInterface::generateSGI().

◆ aff2

Bitfield<23, 16> gem5::ArmISA::aff2

Definition at line 207 of file types.hh.

Referenced by gem5::Gicv3CPUInterface::generateSGI().

◆ aff3

gem5::ArmISA::aff3

Definition at line 206 of file types.hh.

Referenced by gem5::Gicv3CPUInterface::generateSGI().

◆ affinity

Bitfield<11, 0> gem5::ArmISA::affinity

Definition at line 828 of file misc_types.hh.

Referenced by gem5::Gicv3Redistributor::copy(), gem5::Gicv3CPUInterface::copy(), gem5::Gicv3Redistributor::read(), and gem5::Gicv3Distributor::route().

◆ ahp

Bitfield<26> gem5::ArmISA::ahp

Definition at line 508 of file misc_types.hh.

Referenced by vcvtFpDFpH(), vcvtFpFpH(), vcvtFpHFp(), vcvtFpHFpD(), vcvtFpHFpS(), and vcvtFpSFpH().

◆ aif

Bitfield<8, 6> gem5::ArmISA::aif

Definition at line 69 of file misc_types.hh.

◆ amo

Bitfield<5> gem5::ArmISA::amo

Definition at line 334 of file misc_types.hh.

Referenced by gem5::ArmISA::Interrupts::checkInterrupts(), gem5::ArmISA::Interrupts::getInterrupt(), and gem5::ArmISA::DataAbort::routeToHyp().

◆ amu

Bitfield<47, 44> gem5::ArmISA::amu

Definition at line 194 of file misc_types.hh.

◆ apa

Bitfield<7, 4> gem5::ArmISA::apa

Definition at line 140 of file misc_types.hh.

◆ api

Bitfield< 17 > gem5::ArmISA::api

Definition at line 139 of file misc_types.hh.

◆ apk

Bitfield< 16 > gem5::ArmISA::apk

Definition at line 299 of file misc_types.hh.

◆ ApsrMask

const uint32_t gem5::ArmISA::ApsrMask = CpsrMaskQ | CondCodesMask | 0x000001D0
static

Definition at line 2826 of file misc.hh.

◆ ar

Bitfield<14> gem5::ArmISA::ar

Definition at line 749 of file misc_types.hh.

◆ ArgumentReg0

constexpr auto & gem5::ArmISA::ArgumentReg0 = int_reg::X0

Definition at line 650 of file int.hh.

Referenced by gem5::ArmProcess::argsInit().

◆ ArgumentReg1

constexpr auto & gem5::ArmISA::ArgumentReg1 = int_reg::X1

Definition at line 651 of file int.hh.

Referenced by gem5::ArmProcess::argsInit().

◆ ArgumentReg2

constexpr auto & gem5::ArmISA::ArgumentReg2 = int_reg::X2

Definition at line 652 of file int.hh.

Referenced by gem5::ArmProcess::argsInit().

◆ as

Bitfield< 36 > gem5::ArmISA::as

Definition at line 565 of file misc_types.hh.

◆ asedis

Bitfield<31> gem5::ArmISA::asedis

Definition at line 475 of file misc_types.hh.

◆ asid

gem5::ArmISA::asid

Definition at line 675 of file misc_types.hh.

Referenced by gem5::ArmISA::TLB::insert(), gem5::SMMUTLB::invalidateASID(), gem5::ARMArchTLB::invalidateASID(), gem5::WalkCache::invalidateASID(), gem5::SMMUTLB::invalidateVA(), gem5::ARMArchTLB::invalidateVA(), gem5::WalkCache::invalidateVA(), gem5::RiscvISA::TLB::lookup(), gem5::ARMArchTLB::lookup(), gem5::WalkCache::lookup(), gem5::ArmISA::MMU::lookup(), gem5::TlbiOp64::performTlbi(), gem5::ARMArchTLB::pickSetIdx(), gem5::RiscvISA::TLB::remove(), gem5::RiscvISA::TLB::translateWithTLB(), gem5::ArmISA::MMU::CachedState::updateMiscReg(), and gem5::SMMUTranslationProcess::walkCacheLookup().

◆ asidbits

Bitfield<7, 4> gem5::ArmISA::asidbits

Definition at line 156 of file misc_types.hh.

◆ at

Bitfield< 44 > gem5::ArmISA::at

Definition at line 179 of file misc_types.hh.

Referenced by gem5::fastmodel::PL330::gem5_getPort(), and gem5::X86KvmCPU::updateThreadContextMSRs().

◆ atomic

Bitfield<23, 20> gem5::ArmISA::atomic

Definition at line 122 of file misc_types.hh.

Referenced by gem5::System::isAtomicMode(), gem5::ArmISA::WatchPoint::test(), and gem5::ArmISA::SelfDebug::testWatchPoints().

◆ attr

gem5::ArmISA::attr

Definition at line 713 of file misc_types.hh.

Referenced by sc_core::sc_object::add_attribute(), sc_gem5::Object::add_attribute(), gem5::ArmISA::ISA::addressTranslation64(), gem5::MemCmd::buildAttributes(), sc_gem5::Object::get_attribute(), gem5::KvmDevice::getAttr(), gem5::KvmDevice::getAttrPtr(), gem5::KvmKernelGicV2::getGicReg(), gem5::KvmKernelGicV3::getGicReg(), gem5::KvmDevice::hasAttr(), gem5::X86ISA::I386Process::initState(), gem5::X86ISA::installSegDesc(), gem5::ArmISA::TableWalker::memAttrsAArch64(), gem5::ArmISA::TableWalker::memAttrsLPAE(), sc_core::sc_attr_cltn::operator[](), sc_core::sc_attr_cltn::push_back(), sc_core::sc_attr_cltn::remove(), sc_gem5::Object::remove_attribute(), gem5::KvmDevice::setAttr(), gem5::ArmISA::MMU::setAttr(), gem5::KvmDevice::setAttrPtr(), gem5::setContextSegment(), gem5::KvmKernelGicV2::setGicReg(), gem5::KvmKernelGicV3::setGicReg(), gem5::setKvmSegmentReg(), gem5::X86ISA::TLB::translate(), and gem5::X86ISA::GpuTLB::translate().

◆ auxregs

Bitfield<27,24> gem5::ArmISA::auxregs

Definition at line 925 of file misc_types.hh.

◆ aw

Bitfield<5> gem5::ArmISA::aw

Definition at line 383 of file misc_types.hh.

◆ b

Bitfield<7> gem5::ArmISA::b

Definition at line 438 of file misc_types.hh.

Referenced by gem5::RiscvISA::_rvk_emu_clmul_32(), gem5::RiscvISA::_rvk_emu_clmul_64(), gem5::RiscvISA::_rvk_emu_clmulh_32(), gem5::RiscvISA::_rvk_emu_clmulh_64(), addSubColumns(), gem5::ArmISA::Crypto::aesFFMul(), sc_dt::sc_proxy< sc_bv_base >::assign_(), sc_dt::b_and_assign_(), sc_dt::sc_bit::b_not(), sc_dt::b_not(), gem5::PowerISA::IntTrapOp::checkTrap(), gem5::ruby::MN_TBETable::chooseNewDistributor(), sc_dt::concat(), gem5::branch_prediction::StatisticalCorrector::condBranchUpdate(), gem5::divCeil(), gem5::MipsISA::dspAdd(), gem5::MipsISA::dspAddh(), gem5::MipsISA::dspCmp(), gem5::MipsISA::dspCmpg(), gem5::MipsISA::dspCmpgd(), gem5::MipsISA::dspDpa(), gem5::MipsISA::dspDpaq(), gem5::MipsISA::dspDps(), gem5::MipsISA::dspDpsq(), gem5::MipsISA::dspMaq(), gem5::MipsISA::dspMul(), gem5::MipsISA::dspMuleq(), gem5::MipsISA::dspMuleu(), gem5::MipsISA::dspMulq(), gem5::MipsISA::dspMulsa(), gem5::MipsISA::dspMulsaq(), gem5::MipsISA::dspPack(), gem5::MipsISA::dspPick(), gem5::MipsISA::dspPrecrq(), gem5::MipsISA::dspPrecrqu(), gem5::MipsISA::dspPrecrSra(), gem5::MipsISA::dspSub(), gem5::MipsISA::dspSubh(), gem5::o3::DynInst::effAddrValid(), sc_gem5::Scheduler::elaborationDone(), sc_dt::equal(), gem5::AtomicOpCAS< T >::execute(), gem5::AtomicGeneric2Op< T >::execute(), gem5::AtomicGeneric3Op< T >::execute(), gem5::AtomicGenericPair3Op< T >::execute(), gem5::RiscvISA::AtomicGenericOp< T >::execute(), gem5::AtomicOpAnd< T >::execute(), gem5::AtomicOpOr< T >::execute(), gem5::AtomicOpXor< T >::execute(), gem5::AtomicOpExch< T >::execute(), gem5::AtomicOpAdd< T >::execute(), gem5::AtomicOpSub< T >::execute(), gem5::AtomicOpInc< T >::execute(), gem5::AtomicOpDec< T >::execute(), gem5::AtomicOpMax< T >::execute(), gem5::AtomicOpMin< T >::execute(), gem5::AtomicOpAnd< T >::executeImpl(), gem5::AtomicOpOr< T >::executeImpl(), gem5::AtomicOpXor< T >::executeImpl(), gem5::execveFunc(), sc_gem5::Port::finalize(), fp16_add(), fp16_compare_eq(), fp16_compare_ge(), fp16_compare_gt(), fp16_compare_un(), fp16_div(), fp16_mul(), fp16_muladd(), fp16_process_NaNs(), fp16_process_NaNs3(), fp16_scale(), fp32_add(), fp32_compare_eq(), fp32_compare_ge(), fp32_compare_gt(), fp32_compare_un(), fp32_div(), fp32_mul(), fp32_muladd(), fp32_process_NaNs(), fp32_process_NaNs3(), fp32_scale(), fp64_add(), fp64_compare_eq(), fp64_compare_ge(), fp64_compare_gt(), fp64_compare_un(), fp64_div(), fp64_mul(), fp64_muladd(), fp64_process_NaNs(), fp64_process_NaNs3(), fp64_scale(), fpAdd(), fpAddD(), fpAddS(), fpDiv(), fpDivD(), fpDivS(), fplibCompareEQ(), fplibCompareGE(), fplibCompareGT(), fplibCompareUN(), fpMax(), fpMaxNum(), fpMin(), fpMinNum(), fpMul(), fpMulD(), fpMulS(), fpMulX(), fpRecps(), fpRecpsS(), fpRSqrts(), fpRSqrtsS(), fpSub(), fpSubD(), fpSubS(), sc_dt::sc_bitref_r< T >::get_word(), gem5::BaseRemoteGDB::getbyte(), gem5::ruby::AbstractCacheEntry::getDataBlk(), gem5::branch_prediction::MultiperspectivePerceptron::MODHIST::getHash(), gem5::branch_prediction::MultiperspectivePerceptron::SGHISTPATH::getHash(), gem5::branch_prediction::MultiperspectivePerceptron::GHIST::hash(), gem5::stl_helpers::hash_impl::hash_combine(), sc_core::sc_inout< bool >::initialize(), gem5::branch_prediction::MultiperspectivePerceptron::ThreadData::insertRecency(), sc_dt::sc_bit::invalid_value(), QTIsaac< ALPHA >::isaac(), sc_dt::sc_proxy< sc_bv_base >::lrotate(), sc_dt::lshift(), gem5::pseudo_inst::m5sum(), gem5::PowerISA::FloatOp::makeCRField(), gem5::PowerISA::IntOp::makeCRFieldSigned(), gem5::PowerISA::IntOp::makeCRFieldUnsigned(), gem5::MathExpr::MathExpr(), mul62x62(), mul64x32(), multiply2Op(), multiply3Op(), sc_dt::sc_logic::operator delete(), sc_dt::sc_logic::operator new(), gem5::ChannelAddr::operator!=(), gem5::operator!=(), sc_dt::operator!=(), gem5::ChannelAddr::operator%(), gem5::ChannelAddr::operator&(), sc_dt::operator&(), sc_dt::sc_uint_bitref::operator&=(), sc_dt::sc_int_bitref::operator&=(), gem5::stl_helpers::hash_impl::hash< T, std::enable_if_t< !is_std_hash_enabled_v< T > &&is_iterable_v< T > > >::operator()(), gem5::ChannelAddr::operator*(), gem5::Cycles::operator+(), gem5::ChannelAddr::operator+(), sc_core::operator+(), sc_dt::operator,(), gem5::ChannelAddr::operator-(), gem5::Cycles::operator-(), sc_core::operator-(), gem5::ChannelAddr::operator/(), sc_dt::operator/(), sc_dt::operator<(), gem5::ChannelAddr::operator<(), sc_core::sc_sensitive::operator<<(), gem5::ChannelAddr::operator<<(), sc_dt::operator<<(), sc_dt::operator<=(), gem5::ChannelAddr::operator<=(), sc_dt::sc_bit::operator=(), sc_dt::sc_uint_bitref::operator=(), sc_dt::sc_int_bitref::operator=(), sc_core::sc_inout< bool >::operator=(), sc_dt::sc_subref< X >::operator=(), sc_dt::operator==(), gem5::ChannelAddr::operator==(), gem5::operator==(), sc_dt::operator>(), gem5::ChannelAddr::operator>(), sc_dt::operator>=(), gem5::ChannelAddr::operator>=(), gem5::ChannelAddr::operator>>(), sc_dt::operator>>(), gem5::ChannelAddr::operator^(), sc_dt::sc_uint_bitref::operator^=(), sc_dt::sc_int_bitref::operator^=(), gem5::ChannelAddr::operator|(), sc_dt::operator|(), sc_dt::sc_uint_bitref::operator|=(), sc_dt::sc_int_bitref::operator|=(), sc_dt::operator~(), gem5::QARMA::PACInvSub(), gem5::QARMA::PACSub(), gem5::Gicv3Its::pageAddress(), gem5::ParseParam< VecRegContainer< Sz > >::parse(), gem5::ParseParam< MatStore< X, Y > >::parse(), gem5::branch_prediction::TAGE::predict(), gem5::branch_prediction::LTAGE::predict(), gem5::branch_prediction::TAGE_SC_L::predict(), gem5::memory::DRAMInterface::Rank::processRefreshEvent(), gem5::BaseRemoteGDB::putbyte(), QTIsaac< ALPHA >::QTIsaac(), QTIsaac< ALPHA >::randinit(), gem5::memory::NVMInterface::Rank::Rank(), QTIsaac< ALPHA >::rngstep(), sc_dt::scfx_rep::rshift(), sc_dt::rshift(), gem5::prefetch::Base::samePage(), sc_dt::sc_bit::sc_bit(), sc_dt::sc_max(), sc_dt::sc_min(), SC_MODULE(), sc_dt::sc_fxnum_bitref::scan(), sc_dt::sc_uint_bitref::scan(), sc_dt::sc_int_bitref::scan(), sc_dt::sc_bitref< X >::scan(), sc_dt::sc_subref< X >::scan(), sc_dt::sc_concref< X, Y >::scan(), sc_dt::scfx_rep::scfx_rep(), gem5::memory::DRAMInterface::Rank::scheduleWakeUpEvent(), gem5::ArmISA::SelfDebug::securityStateMatch(), sc_dt::sc_bitref< X >::set_cword(), gem5::ruby::Network::setFromNetQueue(), gem5::ruby::Network::setToNetQueue(), gem5::ShowParam< VecRegContainer< Sz > >::show(), gem5::ShowParam< VecPredRegContainer< NumBits, Packed > >::show(), gem5::ShowParam< MatStore< X, Y > >::show(), QTIsaac< ALPHA >::shuffle(), gem5::ruby::WeightBased::sortLinks(), QTIsaac< ALPHA >::srand(), BitUnionData::templatedFunction(), TEST(), test2DVoid(), testIntVoid(), testPrepareInt(), testPrepareVoid(), sc_dt::to_string(), sc_dt::scfx_rep::to_string(), sc_dt::vec_from_str(), gem5::ruby::garnet::NetworkInterface::wakeup(), and sc_core::sc_inout< bool >::write().

◆ b16b16

Bitfield<27, 24> gem5::ArmISA::b16b16

Definition at line 214 of file misc_types.hh.

◆ b16f32

Bitfield<34> gem5::ArmISA::b16f32

Definition at line 228 of file misc_types.hh.

◆ bas

Bitfield< 12, 5 > gem5::ArmISA::bas

Definition at line 851 of file misc_types.hh.

Referenced by gem5::ArmISA::WatchPoint::compareAddress(), gem5::ArmISA::BrkPoint::testAddrMatch(), and gem5::ArmISA::BrkPoint::testAddrMissMatch().

◆ bbm

Bitfield<55, 52> gem5::ArmISA::bbm

Definition at line 175 of file misc_types.hh.

◆ bf16

Bitfield< 23, 20 > gem5::ArmISA::bf16

Definition at line 91 of file misc_types.hh.

◆ bigend

Bitfield<11, 8> gem5::ArmISA::bigend

Definition at line 155 of file misc_types.hh.

◆ bigendEL0

Bitfield<19, 16> gem5::ArmISA::bigendEL0

Definition at line 153 of file misc_types.hh.

◆ bigThumb

Bitfield<35> gem5::ArmISA::bigThumb

Definition at line 80 of file types.hh.

◆ bitPerm

Bitfield<19, 16> gem5::ArmISA::bitPerm

Definition at line 216 of file misc_types.hh.

◆ bottom2

Bitfield<1, 0> gem5::ArmISA::bottom2

Definition at line 66 of file pcstate.hh.

◆ bpaddremask

Bitfield<11,8> gem5::ArmISA::bpaddremask

Definition at line 929 of file misc_types.hh.

◆ brps

Bitfield<15, 12> gem5::ArmISA::brps

Definition at line 105 of file misc_types.hh.

◆ bsu

Bitfield<11, 10> gem5::ArmISA::bsu

Definition at line 328 of file misc_types.hh.

◆ bt

Bitfield<23, 20> gem5::ArmISA::bt

Definition at line 846 of file misc_types.hh.

◆ c

Bitfield< 29 > gem5::ArmISA::c

Definition at line 53 of file misc_types.hh.

Referenced by fp16_muladd(), fp16_process_NaNs3(), fp32_muladd(), fp32_process_NaNs3(), fp64_div(), fp64_muladd(), fp64_process_NaNs3(), fp64_sqrt(), and testPredicate().

◆ ccidx

Bitfield<23, 20> gem5::ArmISA::ccidx

Definition at line 182 of file misc_types.hh.

◆ ccRegClass

constexpr RegClass gem5::ArmISA::ccRegClass
inlineconstexpr
Initial value:
= RegClass(CCRegClass, CCRegClassName,
cc_reg::NumRegs, debug::CCRegs).ops(ccRegClassOps)

Definition at line 87 of file cc.hh.

Referenced by gem5::ArmISA::ISA::copyRegsFrom(), gem5::PowerISA::ISA::ISA(), gem5::RiscvISA::ISA::ISA(), gem5::MipsISA::ISA::ISA(), gem5::SparcISA::ISA::ISA(), gem5::ArmISA::ISA::ISA(), and gem5::Iris::ThreadContext::setCCRegFlat().

◆ ccRegClassOps

CCRegClassOps gem5::ArmISA::ccRegClassOps
inlinestatic

Definition at line 85 of file cc.hh.

◆ cd

Bitfield<32> gem5::ArmISA::cd

Definition at line 306 of file misc_types.hh.

Referenced by gem5::ClockDomain::ClockDomainStats::ClockDomainStats(), gem5::SMMUTranslationProcess::doReadCD(), and gem5::SMMUTranslationProcess::findConfig().

◆ cidmask

gem5::ArmISA::cidmask

Definition at line 924 of file misc_types.hh.

◆ clrbhb

gem5::ArmISA::clrbhb

Definition at line 89 of file misc_types.hh.

◆ cm

Bitfield< 8 > gem5::ArmISA::cm

Definition at line 486 of file misc_types.hh.

Referenced by gem5::ArmISA::SelfDebug::testWatchPoints(), and gem5::ArmISA::SelfDebug::triggerWatchpointException().

◆ cnp

Bitfield<3, 0> gem5::ArmISA::cnp

Definition at line 187 of file misc_types.hh.

◆ cond

Bitfield< 23, 20 > gem5::ArmISA::cond

Definition at line 62 of file pcstate.hh.

Referenced by gem5::AddrRangeMap< gem5::MemBackdoor, 1 >::find().

◆ condCode

Bitfield<31, 28> gem5::ArmISA::condCode

Definition at line 111 of file types.hh.

◆ CondCodesMask

const uint32_t gem5::ArmISA::CondCodesMask = 0xF00F0000
static

Definition at line 2817 of file misc.hh.

◆ cp0

gem5::ArmISA::cp0

Definition at line 360 of file misc_types.hh.

◆ cp1

Bitfield< 3, 2 > gem5::ArmISA::cp1

Definition at line 359 of file misc_types.hh.

◆ cp10

Bitfield< 21, 20 > gem5::ArmISA::cp10

Definition at line 350 of file misc_types.hh.

◆ cp11

Bitfield< 23, 22 > gem5::ArmISA::cp11

Definition at line 349 of file misc_types.hh.

◆ cp12

Bitfield< 25, 24 > gem5::ArmISA::cp12

Definition at line 348 of file misc_types.hh.

◆ cp13

Bitfield< 27, 26 > gem5::ArmISA::cp13

Definition at line 347 of file misc_types.hh.

◆ cp15ben

Bitfield<5> gem5::ArmISA::cp15ben

Definition at line 444 of file misc_types.hh.

◆ cp2

Bitfield< 5, 4 > gem5::ArmISA::cp2

Definition at line 358 of file misc_types.hh.

◆ cp3

Bitfield< 7, 6 > gem5::ArmISA::cp3

Definition at line 357 of file misc_types.hh.

◆ cp4

Bitfield< 9, 8 > gem5::ArmISA::cp4

Definition at line 356 of file misc_types.hh.

◆ cp5

Bitfield< 11, 10 > gem5::ArmISA::cp5

Definition at line 355 of file misc_types.hh.

◆ cp6

Bitfield< 13, 12 > gem5::ArmISA::cp6

Definition at line 354 of file misc_types.hh.

◆ cp7

Bitfield< 15, 14 > gem5::ArmISA::cp7

Definition at line 353 of file misc_types.hh.

◆ cp8

Bitfield< 17, 16 > gem5::ArmISA::cp8

Definition at line 352 of file misc_types.hh.

◆ cp9

Bitfield< 19, 18 > gem5::ArmISA::cp9

Definition at line 351 of file misc_types.hh.

◆ cpNum

Bitfield<11, 8> gem5::ArmISA::cpNum

Definition at line 148 of file types.hh.

◆ CpsrMask

const uint32_t gem5::ArmISA::CpsrMask = ApsrMask | 0x00F003DF
static

Definition at line 2829 of file misc.hh.

◆ CpsrMaskQ

const uint32_t gem5::ArmISA::CpsrMaskQ = 0x08000000
static

Definition at line 2818 of file misc.hh.

Referenced by gem5::ArmISA::ISA::setMiscReg().

◆ crc32

Bitfield< 19, 16 > gem5::ArmISA::crc32

Definition at line 81 of file misc_types.hh.

◆ csv2

Bitfield<59, 56> gem5::ArmISA::csv2

Definition at line 192 of file misc_types.hh.

◆ csv3

gem5::ArmISA::csv3

Definition at line 191 of file misc_types.hh.

◆ ctx_cmps

Bitfield<31, 28> gem5::ArmISA::ctx_cmps

Definition at line 103 of file misc_types.hh.

◆ cwg

Bitfield<27,24> gem5::ArmISA::cwg

Definition at line 702 of file misc_types.hh.

◆ d

Bitfield<9> gem5::ArmISA::d

Definition at line 64 of file misc_types.hh.

Referenced by gem5::statistics::DistBase< Distribution, DistStor >::add(), sc_dt::add_on_help(), gem5::ThermalModel::addDomain(), gem5::prefetch::Tagged::calculatePrefetch(), gem5::prefetch::IrregularStreamBuffer::calculatePrefetch(), gem5::prefetch::Stride::calculatePrefetch(), sc_dt::check_for_zero(), gem5::DVFSHandler::clkPeriodAtPerfLevel(), sc_dt::compare_unsigned(), gem5::Wavefront::computeActualWgSz(), gem5::VirtQueue::consumeDescriptor(), sc_dt::convert_signed_2C_to_SM(), sc_dt::convert_signed_SM_to_2C(), sc_dt::convert_signed_SM_to_2C_trimmed(), sc_dt::convert_SM_to_2C(), gem5::RefCountingPtr< MinorDynInst >::copy(), sc_dt::sc_unsigned::copy_digits(), sc_dt::sc_signed::copy_digits(), sc_dt::copy_digits_signed(), gem5::trace::Logger::dump(), gem5::VirtQueue::dump(), gem5::DVFSHandler::DVFSHandler(), gem5::igbreg::txd_op::eop(), gem5::Process::findDriver(), sc_core::sc_time::from_seconds(), sc_core::sc_time::from_string(), gem5::igbreg::txd_op::getBuf(), gem5::igbreg::txd_op::getCso(), gem5::igbreg::txd_op::getCss(), gem5::igbreg::txd_op::getLen(), gem5::igbreg::txd_op::getTsoLen(), gem5::igbreg::txd_op::getType(), gem5::o3::LSQ::SplitDataRequest::handleLocalAccess(), gem5::ComputeUnit::hasDispResources(), gem5::igbreg::txd_op::hdrlen(), gem5::I2CBus::I2CBus(), gem5::igbreg::txd_op::ic(), gem5::igbreg::txd_op::ide(), gem5::igbreg::txd_op::ifcs(), gem5::SparcISA::TlbMap::insert(), gem5::AddrRangeMap< gem5::MemBackdoor, 1 >::insert(), gem5::igbreg::txd_op::ip(), gem5::igbreg::txd_op::ipcse(), gem5::igbreg::txd_op::ipcso(), gem5::igbreg::txd_op::ipcss(), gem5::igbreg::txd_op::isAdvDesc(), gem5::igbreg::txd_op::isContext(), gem5::igbreg::txd_op::isData(), gem5::igbreg::txd_op::isLegacy(), gem5::igbreg::txd_op::isType(), gem5::igbreg::txd_op::isTypes(), sc_dt::sc_unsigned::iszero(), gem5::igbreg::txd_op::ixsm(), gem5::pseudo_inst::m5sum(), gem5::igbreg::txd_op::mss(), sc_core::sc_prim_channel::next_trigger(), sc_core::sc_module::next_trigger(), sc_core::next_trigger(), sc_core::sc_event_queue::notify(), sc_gem5::Event::notify(), sc_core::sc_event::notify(), gem5::VirtQueue::onNotify(), gem5::copy_engine_reg::Reg< uint64_t >::operator()(), gem5::igbreg::Regs::Reg< uint64_t >::operator()(), sc_core::operator*(), sc_core::sc_time::operator*=(), sc_core::operator/(), sc_core::sc_time::operator/=(), gem5::copy_engine_reg::Reg< uint64_t >::operator=(), gem5::igbreg::Regs::Reg< uint64_t >::operator=(), gem5::copy_engine_reg::Reg< uint64_t >::operator==(), gem5::igbreg::Regs::Reg< uint64_t >::operator==(), gem5::DVFSHandler::perfLevel(), QTIsaac< ALPHA >::randinit(), gem5::DistIface::RecvScheduler::resumeRecvTicks(), gem5::igbreg::txd_op::rs(), gem5::VoltageDomain::sanitiseVoltages(), SC_MODULE(), sc_core::sc_set_default_time_unit(), sc_core::sc_set_time_resolution(), sc_core::sc_start(), sc_core::sc_time::sc_time(), gem5::RefCountingPtr< MinorDynInst >::set(), sc_gem5::TraceFile::set_time_unit(), gem5::trace::InstRecord::setData(), gem5::igbreg::txd_op::setDd(), gem5::OutputDirectory::setDirectory(), gem5::ruby::Topology::shortest_path_to_node(), QTIsaac< ALPHA >::shuffle(), gem5::igbreg::txd_op::tcp(), TEST(), test2DVoid(), testIntVoid(), tlm::tlm_from_hostendian_word(), tlm::tlm_to_hostendian_word(), gem5::ArmISA::SelfDebug::triggerWatchpointException(), sc_dt::trim(), sc_dt::trim_unsigned(), gem5::VirtIORng::RngQueue::trySend(), gem5::VirtIOConsole::TermRecvQueue::trySend(), gem5::igbreg::txd_op::tse(), gem5::igbreg::txd_op::tucse(), gem5::igbreg::txd_op::tucso(), gem5::igbreg::txd_op::tucss(), gem5::igbreg::txd_op::txsm(), gem5::DVFSHandler::UpdateEvent::updatePerfLevel(), gem5::igbreg::txd_op::utcmd(), gem5::igbreg::txd_op::vle(), gem5::DVFSHandler::voltageAtPerfLevel(), sc_core::sc_prim_channel::wait(), sc_core::sc_module::wait(), sc_core::wait(), gem5::I2CBus::write(), and gem5::VGic::writeCtrl().

◆ d32dis

Bitfield<30> gem5::ArmISA::d32dis

Definition at line 474 of file misc_types.hh.

◆ daif

Bitfield<9, 6> gem5::ArmISA::daif

Definition at line 70 of file misc_types.hh.

Referenced by gem5::ArmISA::ISA::readMiscReg(), gem5::ArmISA::HTMCheckpoint::restore(), gem5::ArmISA::HTMCheckpoint::save(), and gem5::ArmISA::ISA::setMiscReg().

◆ dataRAMSetup

Bitfield<5> gem5::ArmISA::dataRAMSetup

Definition at line 682 of file misc_types.hh.

◆ dataRAMSlice

Bitfield<11,10> gem5::ArmISA::dataRAMSlice

Definition at line 685 of file misc_types.hh.

◆ dc

Bitfield<12> gem5::ArmISA::dc

Definition at line 327 of file misc_types.hh.

Referenced by gem5::ArmISA::MMU::translateMmuOff().

◆ dCacheLineSize

Bitfield<19,16> gem5::ArmISA::dCacheLineSize

Definition at line 700 of file misc_types.hh.

◆ debugStep

Bitfield<60> gem5::ArmISA::debugStep

Definition at line 63 of file types.hh.

◆ debugver

Bitfield<3, 0> gem5::ArmISA::debugver

Definition at line 108 of file misc_types.hh.

◆ decoderFault

gem5::ArmISA::decoderFault

Definition at line 61 of file types.hh.

◆ defaultNaN

Bitfield<7, 4> gem5::ArmISA::defaultNaN

Definition at line 535 of file misc_types.hh.

◆ dfsc

Bitfield< 5, 0 > gem5::ArmISA::dfsc

Definition at line 756 of file misc_types.hh.

◆ dit

Bitfield<51, 48> gem5::ArmISA::dit

Definition at line 193 of file misc_types.hh.

Referenced by gem5::DVFSHandler::DVFSHandler(), and gem5::VoltageDomain::sanitiseVoltages().

◆ divide

Bitfield<19, 16> gem5::ArmISA::divide

Definition at line 527 of file misc_types.hh.

Referenced by SC_MODULE().

◆ dn

Bitfield<25> gem5::ArmISA::dn

Definition at line 507 of file misc_types.hh.

◆ domain

Bitfield<7, 4> gem5::ArmISA::domain

Definition at line 481 of file misc_types.hh.

Referenced by gem5::ArmISA::AbortFault< DataAbort >::getFsr(), gem5::ListenSocket::socketCloexec(), gem5::socketFunc(), gem5::socketpairFunc(), gem5::ArmISA::MMU::testTranslation(), gem5::ArmISA::MMU::testWalk(), and gem5::ArmISA::TableWalker::testWalk().

◆ doublelock

Bitfield< 23, 20 > gem5::ArmISA::doublelock

Definition at line 101 of file misc_types.hh.

◆ doublePrecision

Bitfield<11, 8> gem5::ArmISA::doublePrecision

Definition at line 525 of file misc_types.hh.

◆ dp

Bitfield< 47, 44 > gem5::ArmISA::dp

Definition at line 95 of file misc_types.hh.

Referenced by gem5::prefetch::Queued::processMissingTranslations(), gem5::PacketQueue::sendDeferredPacket(), and gem5::prefetch::Queued::translationComplete().

◆ dpb

Bitfield<3, 0> gem5::ArmISA::dpb

Definition at line 141 of file misc_types.hh.

◆ ds0

Bitfield<16> gem5::ArmISA::ds0

Definition at line 641 of file misc_types.hh.

◆ ds1

Bitfield<17> gem5::ArmISA::ds1

Definition at line 642 of file misc_types.hh.

◆ dz

Bitfield<19> gem5::ArmISA::dz

Definition at line 414 of file misc_types.hh.

◆ dzc

Bitfield<1> gem5::ArmISA::dzc

Definition at line 491 of file misc_types.hh.

◆ dze

Bitfield< 9 > gem5::ArmISA::dze

Definition at line 426 of file misc_types.hh.

◆ e

Bitfield< 0 > gem5::ArmISA::e

Definition at line 65 of file misc_types.hh.

Referenced by sc_gem5::Object::addChildEvent(), gem5::Workload::addFuncEventOrPanic(), gem5::KernelWorkload::addKernelFuncEventOrPanic(), sc_gem5::DynamicSensitivity::addToEvent(), sc_gem5::StaticSensitivity::addToEvent(), gem5::statistics::Hdf5::appendStat(), gem5::ARMArchTLB::ARMArchTLB(), sc_gem5::Module::beforeEndOfElaboration(), gem5::statistics::Hdf5::beginGroup(), tlm_utils::simple_target_socket_b< MODULE, BUSWIDTH, TYPES, POL >::bw_process::bw_process(), SwitchingFiber::checkExpected(), gem5::BaseRemoteGDB::cmdMultiLetter(), gem5::ConfigCache::ConfigCache(), gem5::SMMUTranslationProcess::configCacheLookup(), gem5::SMMUTranslationProcess::configCacheUpdate(), gem5::fastmodel::CortexA76Cluster::CortexA76Cluster(), gem5::fastmodel::CortexR52Cluster::CortexR52Cluster(), gem5::ruby::countBoolVec(), sc_gem5::Object::delChildEvent(), sc_gem5::DynamicSensitivity::delFromEvent(), sc_gem5::StaticSensitivity::delFromEvent(), gem5::DmaReadFifo::DmaReadFifo(), gem5::ThermalModel::doStep(), gem5::RiscvISA::TLB::doTranslate(), gem5::PCEventQueue::dump(), gem5::o3::LSQUnit::dumpInsts(), gem5::X86KvmCPU::dumpMSRs(), tlm_utils::time_ordered_list< PAYLOAD >::element::element(), sc_gem5::Module::endOfElaboration(), sc_gem5::Module::endOfSimulation(), gem5::ruby::RubySystem::enqueueRubyEvent(), ExtensionPool< T >::entry::entry(), gem5::AddrRange::exclude(), ExtensionPool< MultiSocketSimpleSwitchAT::ConnectionInfo >::ExtensionPool(), gem5::qemu::FwCfgItemE820::FwCfgItemE820(), sc_gem5::Event::getFromScEvent(), gem5::SMMUTranslationProcess::ifcTLBLookup(), gem5::SMMUTranslationProcess::ifcTLBUpdate(), sc_core::sc_event_and_list::insert(), sc_core::sc_event_or_list::insert(), sc_core::sc_event_and_expr::insert(), sc_core::sc_event_or_expr::insert(), gem5::SMMUTLB::invalidateASID(), gem5::ARMArchTLB::invalidateASID(), gem5::WalkCache::invalidateASID(), gem5::IPACache::invalidateIPA(), gem5::IPACache::invalidateIPAA(), gem5::SMMUTLB::invalidateSID(), gem5::ConfigCache::invalidateSID(), gem5::SMMUTLB::invalidateSSID(), gem5::ConfigCache::invalidateSSID(), gem5::SMMUTLB::invalidateVA(), gem5::ARMArchTLB::invalidateVA(), gem5::WalkCache::invalidateVA(), gem5::SMMUTLB::invalidateVAA(), gem5::ARMArchTLB::invalidateVAA(), gem5::WalkCache::invalidateVAA(), gem5::SMMUTLB::invalidateVMID(), gem5::ARMArchTLB::invalidateVMID(), gem5::IPACache::invalidateVMID(), gem5::WalkCache::invalidateVMID(), gem5::IPACache::IPACache(), gem5::SMMUTLB::lookup(), gem5::ARMArchTLB::lookup(), gem5::IPACache::lookup(), gem5::ConfigCache::lookup(), gem5::WalkCache::lookup(), gem5::SMMUTLB::lookupAnyVA(), gem5::pseudo_inst::m5sum(), main(), gem5::makeKvmCpuid(), gem5::SMMUTranslationProcess::microTLBLookup(), gem5::SMMUTranslationProcess::microTLBUpdate(), sc_gem5::newDynamicSensitivityEvent(), sc_gem5::newStaticSensitivityEvent(), sc_core::sc_prim_channel::next_trigger(), sc_core::sc_module::next_trigger(), sc_core::next_trigger(), sc_gem5::Sensitivity::notify(), sc_gem5::DynamicSensitivityEventOrList::notifyWork(), sc_gem5::DynamicSensitivityEventAndList::notifyWork(), gem5::Time::operator double(), sc_core::sc_event_and_list::operator&(), sc_core::sc_event::operator&(), sc_core::operator&(), sc_core::sc_event_and_list::operator&=(), gem5::stl_helpers::hash_impl::hash< std::tuple< T... > >::operator()(), gem5::stl_helpers::hash_impl::hash< T, std::enable_if_t< !is_std_hash_enabled_v< T > &&is_iterable_v< T > > >::operator()(), gem5::ruby::operator<<(), sc_core::sc_sensitive::operator<<(), gem5::SparcISA::TteTag::operator=(), gem5::SparcISA::PageTableEntry::operator=(), sc_core::sc_event_or_list::operator|(), sc_core::sc_event::operator|(), sc_core::operator|(), sc_core::sc_event_or_list::operator|=(), gem5::stl_helpers::opExtract_impl::opExtractPrimDisp(), gem5::SparcISA::SparcStaticInst::passesFpCondition(), gem5::SparcISA::PageTableEntry::populate(), gem5::BaseRemoteGDB::processCommands(), gem5::memory::qos::MemSinkCtrl::processNextReqEvent(), gem5::VirtQueue::produceDescriptor(), gem5::pybind_init_event(), QTIsaac< ALPHA >::randinit(), tlm_utils::simple_target_socket_b< SimpleLTTarget_ext, BUSWIDTH, my_extended_payload_types >::register_transport_dbg(), gem5::System::registerThreadContext(), gem5::o3::ThreadContext::remove(), gem5::CheckerThreadContext< TC >::remove(), gem5::SimpleThread::remove(), gem5::Iris::ThreadContext::remove(), gem5::System::replaceThreadContext(), sc_gem5::reportifyException(), gem5::DmaReadFifo::resumeFillTiming(), gem5::ArmSemihosting::retError(), sc_core::sc_event_and_expr::sc_event_and_expr(), sc_core::sc_event_and_list::sc_event_and_list(), sc_core::sc_event_or_expr::sc_event_or_expr(), sc_core::sc_event_or_list::sc_event_or_list(), gem5::o3::ThreadContext::schedule(), gem5::CheckerThreadContext< TC >::schedule(), gem5::SimpleThread::schedule(), gem5::Iris::ThreadContext::schedule(), sc_core::sc_spawn_options::set_sensitivity(), QTIsaac< ALPHA >::shuffle(), gem5::Iris::ThreadContext::simulationTimeEvent(), gem5::SMMUTLB::SMMUTLB(), gem5::SMMUTranslationProcess::smmuTLBLookup(), gem5::SMMUTranslationProcess::smmuTLBUpdate(), sc_gem5::spawnWork(), tlm_utils::simple_target_socket_tagged_b< SimpleBusLT, 32, tlm::tlm_base_protocol_types >::start_of_simulation(), sc_gem5::Module::startOfSimulation(), TEST(), TEST_F(), gem5::ArmISA::MMU::translateFunctional(), gem5::SMMUTranslationProcess::translateStage2(), gem5::RiscvISA::TLB::translateWithTLB(), gem5::prefetch::STeMS::ActiveGenerationTableEntry::update(), gem5::X86KvmCPU::updateKvmStateMSRs(), sc_core::sc_prim_channel::wait(), sc_core::sc_module::wait(), sc_core::wait(), gem5::WalkCache::WalkCache(), gem5::SMMUTranslationProcess::walkCacheUpdate(), and gem5::DmaReadFifo::~DmaReadFifo().

◆ e0e

Bitfield<24> gem5::ArmISA::e0e

Definition at line 403 of file misc_types.hh.

◆ e0pd

gem5::ArmISA::e0pd

Definition at line 173 of file misc_types.hh.

◆ e2h

Bitfield<34> gem5::ArmISA::e2h

Definition at line 304 of file misc_types.hh.

Referenced by gem5::ArmISA::MMU::hasUnprivRegime().

◆ ea

Bitfield< 9 > gem5::ArmISA::ea

Definition at line 385 of file misc_types.hh.

Referenced by gem5::networking::EthAddr::EthAddr(), gem5::networking::operator<<(), and gem5::networking::EthAddr::operator=().

◆ eae

Bitfield<31> gem5::ArmISA::eae

Definition at line 569 of file misc_types.hh.

◆ ease

Bitfield<19> gem5::ArmISA::ease

Definition at line 368 of file misc_types.hh.

◆ ec

gem5::ArmISA::ec

Definition at line 727 of file misc_types.hh.

Referenced by AArch64AArch32SystemAccessTrap(), gem5::MiscRegOp64::generateTrap(), isGenericTimerCommonEL0HypTrap(), isGenericTimerHypTrap(), gem5::ListenSocketUnixFile::listen(), mcrMrc15Trap(), mcrMrc15TrapToHyp(), mcrrMrrc15Trap(), and mcrrMrrc15TrapToHyp().

◆ eccandParityEnable

Bitfield<21> gem5::ArmISA::eccandParityEnable

Definition at line 688 of file misc_types.hh.

◆ ecv

Bitfield< 12 > gem5::ArmISA::ecv

Definition at line 145 of file misc_types.hh.

◆ ee

Bitfield<25> gem5::ArmISA::ee

Definition at line 402 of file misc_types.hh.

◆ eel2

Bitfield<18> gem5::ArmISA::eel2

Definition at line 369 of file misc_types.hh.

Referenced by IsSecureEL2Enabled().

◆ el

Bitfield< 3, 2 > gem5::ArmISA::el

Definition at line 73 of file misc_types.hh.

Referenced by addPAC(), addPACDA(), addPACDB(), addPACGA(), addPACIA(), addPACIB(), gem5::ArmISA::ArmStaticInst::advSIMDFPAccessTrap64(), auth(), authDA(), authDB(), authIA(), authIB(), calculateBottomPACBit(), calculateTBI(), gem5::ArmISA::MiscRegLUTEntry::checkFault(), gem5::ArmISA::ArmStaticInst::checkFPAdvSIMDEnabled64(), gem5::ArmISA::ArmStaticInst::checkSmeAccess(), gem5::ArmISA::ArmStaticInst::checkSmeEnabled(), gem5::ArmISA::ArmStaticInst::checkSveEnabled(), computeAddrTop(), ELIs32(), ELIs64(), ELIsInHost(), ELStateUsingAArch32(), ELStateUsingAArch32K(), ELUsingAArch32K(), gem5::ArmISA::MiscRegLUTEntryInitializer::fault(), gem5::ArmISA::MiscRegLUTEntryInitializer::faultRead(), gem5::ArmISA::MiscRegLUTEntryInitializer::faultWrite(), gem5::ArmISA::IntRegClassOps::flatten(), gem5::MiscRegOp64::generateTrap(), gem5::ArmISA::ISA::getCurSmeVecLenInBits(), gem5::ArmISA::ISA::getCurSveVecLenInBits(), getRestoredITBits(), gem5::ArmISA::MMU::hasUnprivRegime(), haveAArch32EL(), gem5::ArmSystem::haveEL(), gem5::Gicv3CPUInterface::haveEL(), gem5::ArmISA::TLB::insert(), gem5::ArmISA::SelfDebug::isDebugEnabled(), gem5::ArmISA::SelfDebug::isDebugEnabledForEL32(), gem5::ArmISA::SelfDebug::isDebugEnabledForEL64(), gem5::ArmISA::BrkPoint::isEnabled(), gem5::ArmISA::WatchPoint::isEnabled(), gem5::ArmISA::PMU::CounterState::isFiltered(), maskTaggedAddr(), gem5::ArmISA::MMU::purifyTaggedAddr(), purifyTaggedAddr(), s1TranslationRegime(), gem5::ArmISA::ISA::setMiscReg(), gem5::ArmISA::ArmStaticInst::smeAccessTrap(), stripPAC(), gem5::ArmISA::ArmStaticInst::sveAccessTrap(), gem5::ArmISA::Interrupts::takeInt(), gem5::ArmISA::BrkPoint::test(), gem5::ArmISA::WatchPoint::test(), gem5::ArmISA::SelfDebug::testBreakPoints(), gem5::ArmISA::BrkPoint::testContextMatch(), gem5::ArmISA::BrkPoint::testLinkedBk(), gem5::ArmISA::BrkPoint::testVMIDMatch(), gem5::ArmISA::SelfDebug::testWatchPoints(), and upperAndLowerRange().

◆ el0

Bitfield<3, 0> gem5::ArmISA::el0

Definition at line 205 of file misc_types.hh.

◆ el0pcten

Bitfield< 0 > gem5::ArmISA::el0pcten

Definition at line 58 of file generic_timer_miscregs_types.hh.

◆ el0pten

Bitfield< 9 > gem5::ArmISA::el0pten

Definition at line 52 of file generic_timer_miscregs_types.hh.

◆ el0vcten

Bitfield< 1 > gem5::ArmISA::el0vcten

Definition at line 57 of file generic_timer_miscregs_types.hh.

◆ el0vten

Bitfield< 8 > gem5::ArmISA::el0vten

Definition at line 53 of file generic_timer_miscregs_types.hh.

◆ el1

Bitfield<7, 4> gem5::ArmISA::el1

Definition at line 204 of file misc_types.hh.

◆ el1nvpct

Bitfield< 15 > gem5::ArmISA::el1nvpct

Definition at line 65 of file generic_timer_miscregs_types.hh.

◆ el1nvvct

Bitfield< 16 > gem5::ArmISA::el1nvvct

Definition at line 64 of file generic_timer_miscregs_types.hh.

◆ el1pcen

Bitfield<1> gem5::ArmISA::el1pcen

Definition at line 73 of file generic_timer_miscregs_types.hh.

◆ el1pcten

Bitfield< 10 > gem5::ArmISA::el1pcten

Definition at line 74 of file generic_timer_miscregs_types.hh.

◆ el1pten

Bitfield<11> gem5::ArmISA::el1pten

Definition at line 86 of file generic_timer_miscregs_types.hh.

◆ el1tvct

Bitfield< 14 > gem5::ArmISA::el1tvct

Definition at line 66 of file generic_timer_miscregs_types.hh.

◆ el1tvt

Bitfield< 13 > gem5::ArmISA::el1tvt

Definition at line 67 of file generic_timer_miscregs_types.hh.

◆ el2

Bitfield<11, 8> gem5::ArmISA::el2

Definition at line 203 of file misc_types.hh.

◆ el3

Bitfield<15, 12> gem5::ArmISA::el3

Definition at line 202 of file misc_types.hh.

◆ en

Bitfield<30> gem5::ArmISA::en

Definition at line 518 of file misc_types.hh.

Referenced by gem5::Root::timeSyncEnable(), gem5::Root::timeSyncPeriod(), and gem5::Root::timeSyncSpinThreshold().

◆ encoding

Bitfield<27, 25> gem5::ArmISA::encoding

Definition at line 90 of file types.hh.

Referenced by decode_fp_data_type(), gem5::UnknownOp64::generateDisassembly(), gem5::UnknownOp::generateDisassembly(), and gem5::VncServer::setEncodings().

◆ enda

Bitfield<27> gem5::ArmISA::enda

Definition at line 398 of file misc_types.hh.

◆ endb

Bitfield<13> gem5::ArmISA::endb

Definition at line 429 of file misc_types.hh.

◆ enib

Bitfield<30> gem5::ArmISA::enib

Definition at line 393 of file misc_types.hh.

◆ epd0

Bitfield< 7 > gem5::ArmISA::epd0

Definition at line 552 of file misc_types.hh.

◆ epd1

Bitfield< 23 > gem5::ArmISA::epd1

Definition at line 559 of file misc_types.hh.

◆ erg

Bitfield<23,20> gem5::ArmISA::erg

Definition at line 701 of file misc_types.hh.

◆ err

Bitfield<6> gem5::ArmISA::err

Definition at line 892 of file misc_types.hh.

Referenced by gem5::statistics::Hdf5::appendStat(), gem5::ArmSemihosting::call32(), gem5::ArmSemihosting::call64(), gem5::VncServer::checkProtocolVersion(), fplibFPToFixedJS(), fplibRoundInt(), FPToFixed_64(), gem5::NoMaliGpu::gpuPanic(), gem5::NoMaliGpu::panicOnErr(), gem5::IGbE::RxDescCache::pktComplete(), gem5::Iris::ThreadContext::readMem(), gem5::guest_abi::Result< ArmSemihosting::Abi32, ArmSemihosting::RetErrno >::store(), gem5::guest_abi::Result< ArmSemihosting::Abi64, ArmSemihosting::RetErrno >::store(), TEST_F(), gem5::Globals::unserialize(), and gem5::Iris::ThreadContext::writeMem().

◆ esm

Bitfield<12> gem5::ArmISA::esm

Definition at line 794 of file misc_types.hh.

◆ evntdir

Bitfield< 3 > gem5::ArmISA::evntdir

Definition at line 55 of file generic_timer_miscregs_types.hh.

◆ evnten

Bitfield< 2 > gem5::ArmISA::evnten

Definition at line 56 of file generic_timer_miscregs_types.hh.

Referenced by gem5::GenericTimer::handleStream().

◆ evnti

Bitfield< 7, 4 > gem5::ArmISA::evnti

Definition at line 54 of file generic_timer_miscregs_types.hh.

◆ evt

Bitfield<59, 56> gem5::ArmISA::evt

Definition at line 174 of file misc_types.hh.

◆ ex

Bitfield<6> gem5::ArmISA::ex

Definition at line 771 of file misc_types.hh.

◆ exs

Bitfield<47, 44> gem5::ArmISA::exs

Definition at line 146 of file misc_types.hh.

◆ ext

Bitfield<12> gem5::ArmISA::ext

Definition at line 485 of file misc_types.hh.

Referenced by gem5::RequestPort::addTrace(), gem5::ArmRelease::ArmRelease(), Gem5SystemC::Gem5Extension::copy_from(), Gem5SystemC::AtomicExtension::copy_from(), Gem5SystemC::ControlExtension::copy_from(), gem5::Extensible< Packet >::Extensible(), gem5::networking::Ip6Hdr::extensionLength(), gem5::PowerISA::IntTrapOp::generateDisassembly(), gem5::PowerISA::IntImmTrapOp::generateDisassembly(), tlm_utils::instance_specific_extensions_per_accessor::get_extension(), gem5::ArmRelease::has(), gem5::ArmSystem::has(), HaveExt(), gem5::networking::Ip6Hdr::proto(), gem5::RequestPort::removeTrace(), tlm_utils::instance_specific_extensions_per_accessor::set_extension(), gem5::Extensible< Packet >::setExtension(), and TEST().

◆ ez

Bitfield<8> gem5::ArmISA::ez

Definition at line 799 of file misc_types.hh.

◆ f

Bitfield< 0 > gem5::ArmISA::f

Definition at line 68 of file misc_types.hh.

Referenced by gem5::ArmISA::TableWalker::processWalk(), gem5::ArmISA::TableWalker::processWalkAArch64(), gem5::ArmISA::TableWalker::processWalkLPAE(), gem5::ArmISA::TableWalker::processWalkWrapper(), and gem5::ArmISA::MMU::translateMmuOff().

◆ f16f32

Bitfield<35> gem5::ArmISA::f16f32

Definition at line 227 of file misc_types.hh.

◆ f32f32

Bitfield<32> gem5::ArmISA::f32f32

Definition at line 229 of file misc_types.hh.

◆ f32mm

Bitfield<55, 52> gem5::ArmISA::f32mm

Definition at line 210 of file misc_types.hh.

◆ f64f64

Bitfield<48> gem5::ArmISA::f64f64

Definition at line 225 of file misc_types.hh.

◆ f64mm

gem5::ArmISA::f64mm

Definition at line 209 of file misc_types.hh.

◆ fa64

Bitfield<31, 31> gem5::ArmISA::fa64

Definition at line 810 of file misc_types.hh.

◆ fb

Bitfield<9> gem5::ArmISA::fb

Definition at line 329 of file misc_types.hh.

Referenced by gem5::FrameBuffer::copyIn(), gem5::FrameBuffer::copyOut(), and gem5::createImgWriter().

◆ fcma

Bitfield<19, 16> gem5::ArmISA::fcma

Definition at line 137 of file misc_types.hh.

◆ fd

Bitfield<14, 12> gem5::ArmISA::fd

Definition at line 150 of file types.hh.

Referenced by gem5::Terminal::accept(), gem5::VncServer::accept(), gem5::atomic_read(), gem5::atomic_write(), gem5::EtherTapStub::attach(), gem5::KvmVM::createVCPU(), gem5::loader::doGzipLoad(), gem5::fcntlHelper(), gem5::loader::DtbFile::findReleaseAddr(), gem5::loader::hasGzipMagic(), gem5::loader::ImageFileData::ImageFileData(), gem5::VMA::MappedFileBuffer::MappedFileBuffer(), gem5::Linux::openSpecialFile(), gem5::EtherTapBase::pollFd(), gem5::pollFunc(), gem5::ruby::RubySystem::readCompressedTrace(), gem5::pseudo_inst::readfile(), gem5::FDArray::serialize(), gem5::PollQueue::setupAsyncIO(), TEST(), gem5::VMA::VMA(), gem5::ruby::RubySystem::writeCompressedTrace(), and gem5::PollQueue::~PollQueue().

◆ fhm

Bitfield< 51, 48 > gem5::ArmISA::fhm

Definition at line 94 of file misc_types.hh.

◆ fi

Bitfield<21> gem5::ArmISA::fi

Definition at line 410 of file misc_types.hh.

Referenced by gem5::MathExprPowerModel::getStatValue().

◆ fien

Bitfield< 21 > gem5::ArmISA::fien

Definition at line 292 of file misc_types.hh.

◆ fiq

Bitfield<2> gem5::ArmISA::fiq

Definition at line 386 of file misc_types.hh.

Referenced by gem5::trace::TarmacParserRecord::advanceTrace().

◆ flatIntRegClass

constexpr RegClass gem5::ArmISA::flatIntRegClass
inlineconstexpr
Initial value:
=
RegClass(IntRegClass, IntRegClassName, int_reg::NumRegs, debug::IntRegs)

Definition at line 178 of file int.hh.

Referenced by gem5::ArmISA::ISA::copyRegsFrom(), gem5::ArmISA::IntRegClassOps::flatten(), gem5::ArmISA::ISA::ISA(), gem5::ArmKvmCPU::updateKvmStateCore(), and gem5::ArmV8KvmCPU::updateThreadContext().

◆ flushToZero

gem5::ArmISA::flushToZero

Definition at line 534 of file misc_types.hh.

Referenced by gem5::ArmISA::FpOp::binaryOp(), fixDivDest(), fixFpDFpSDest(), fixFpSFpDDest(), flushToZero(), gem5::ArmISA::FpOp::ternaryOp(), gem5::ArmISA::FpOp::unaryOp(), and vfpFlushToZero().

◆ fm

Bitfield<3, 0> gem5::ArmISA::fm

Definition at line 152 of file types.hh.

◆ fmo

Bitfield<3> gem5::ArmISA::fmo

Definition at line 336 of file misc_types.hh.

Referenced by gem5::ArmISA::Interrupts::checkInterrupts(), and gem5::ArmISA::Interrupts::getInterrupt().

◆ fn

Bitfield<18, 16> gem5::ArmISA::fn

Definition at line 149 of file types.hh.

Referenced by gem5::MathExpr::eval().

◆ fnv

Bitfield< 10 > gem5::ArmISA::fnv

Definition at line 751 of file misc_types.hh.

◆ format

Bitfield<31,29> gem5::ArmISA::format

Definition at line 704 of file misc_types.hh.

Referenced by gem5::ccprintf(), gem5::cprintf(), gem5::loader::createObjectFile(), gem5::csprintf(), gem5::Time::date(), gem5::Logger::print(), gem5::linux::printk(), gem5::procInfo(), gem5::BaseRemoteGDB::send(), and gem5::ArmSemihosting::unrecognizedCall().

◆ fp

Bitfield<19, 16> gem5::ArmISA::fp

Definition at line 201 of file misc_types.hh.

Referenced by bitsToFp(), fpToBits(), gem5::ArmISA::PairMemOp::PairMemOp(), gem5::procInfo(), gem5::X86ISA::FsWorkload::writeOutACPITables(), and gem5::X86ISA::FsWorkload::writeOutMPTable().

◆ FpCondCodesMask

const uint32_t gem5::ArmISA::FpCondCodesMask = 0xF0000000
static

Definition at line 2833 of file misc.hh.

◆ fpen

Bitfield< 21, 20 > gem5::ArmISA::fpen

Definition at line 467 of file misc_types.hh.

◆ fpImm

Bitfield<2, 0> gem5::ArmISA::fpImm

Definition at line 153 of file types.hh.

◆ fpRegImm

Bitfield<3> gem5::ArmISA::fpRegImm

Definition at line 151 of file types.hh.

◆ FpscrAhpMask

const uint32_t gem5::ArmISA::FpscrAhpMask = 0x04000000
static

Definition at line 2837 of file misc.hh.

◆ FpscrExcMask

const uint32_t gem5::ArmISA::FpscrExcMask = 0x0000009F
static

Definition at line 2839 of file misc.hh.

Referenced by gem5::ArmISA::ISA::readMiscReg(), and gem5::ArmISA::ISA::setMiscReg().

◆ fpscrLen

Bitfield<39, 37> gem5::ArmISA::fpscrLen

Definition at line 76 of file types.hh.

◆ FpscrQcMask

const uint32_t gem5::ArmISA::FpscrQcMask = 0x08000000
static

Definition at line 2835 of file misc.hh.

Referenced by gem5::ArmISA::ISA::readMiscReg(), and gem5::ArmISA::ISA::setMiscReg().

◆ fpscrStride

Bitfield<41, 40> gem5::ArmISA::fpscrStride

Definition at line 75 of file types.hh.

◆ FramePointerReg

constexpr auto & gem5::ArmISA::FramePointerReg = int_reg::X11

Definition at line 653 of file int.hh.

Referenced by gem5::ArmISA::ArmStaticInst::printIntReg(), gem5::trace::TarmacTracerRecordV8::TraceRegEntryV8::updateInt(), and gem5::trace::TarmacTracerRecord::TraceRegEntry::updateInt().

◆ frintts

Bitfield<35, 32> gem5::ArmISA::frintts

Definition at line 133 of file misc_types.hh.

◆ fs4_0

Bitfield<5, 1> gem5::ArmISA::fs4_0

Definition at line 722 of file misc_types.hh.

◆ fs5

Bitfield<6> gem5::ArmISA::fs5

Definition at line 721 of file misc_types.hh.

◆ fsHigh

Bitfield<10> gem5::ArmISA::fsHigh

Definition at line 483 of file misc_types.hh.

◆ fsLow

gem5::ArmISA::fsLow

Definition at line 479 of file misc_types.hh.

◆ fst

Bitfield<6, 1> gem5::ArmISA::fst

Definition at line 720 of file misc_types.hh.

◆ fw

Bitfield<4> gem5::ArmISA::fw

Definition at line 384 of file misc_types.hh.

◆ fwb

Bitfield< 46 > gem5::ArmISA::fwb

Definition at line 177 of file misc_types.hh.

◆ fz

Bitfield<24> gem5::ArmISA::fz

Definition at line 506 of file misc_types.hh.

◆ fz16

Bitfield<19> gem5::ArmISA::fz16

Definition at line 503 of file misc_types.hh.

◆ ge

Bitfield<19, 16> gem5::ArmISA::ge

Definition at line 62 of file misc_types.hh.

◆ gic

Bitfield<27, 24> gem5::ArmISA::gic

Definition at line 199 of file misc_types.hh.

Referenced by gem5::ArmSystem::setGIC().

◆ gpa

Bitfield<27, 24> gem5::ArmISA::gpa

Definition at line 135 of file misc_types.hh.

◆ gpi

Bitfield<31, 28> gem5::ArmISA::gpi

Definition at line 134 of file misc_types.hh.

◆ GrainMap_tg0

const GrainSize gem5::ArmISA::GrainMap_tg0
Initial value:
=
{ Grain4KB, Grain64KB, Grain16KB, ReservedGrain }

Definition at line 49 of file pagetable.cc.

Referenced by gem5::ArmISA::TableWalker::processWalkAArch64(), gem5::SMMUTranslationProcess::translateStage1And2(), gem5::SMMUTranslationProcess::translateStage2(), and gem5::SMMUTranslationProcess::walkCacheLookup().

◆ GrainMap_tg1

const GrainSize gem5::ArmISA::GrainMap_tg1
Initial value:
=
{ ReservedGrain, Grain16KB, Grain4KB, Grain64KB }

Definition at line 51 of file pagetable.cc.

Referenced by gem5::ArmISA::TableWalker::processWalkAArch64().

◆ ha

Bitfield< 21 > gem5::ArmISA::ha

Definition at line 601 of file misc_types.hh.

Referenced by gem5::guest_abi::Argument< Aapcs64, HA, typename std::enable_if_t< IsAapcs64HxaV< HA > > >::get(), gem5::guest_abi::Argument< Aapcs32Vfp, HA, typename std::enable_if_t< IsAapcs32HomogeneousAggregateV< HA > > >::get(), gem5::guest_abi::Result< Aapcs64, HA, typename std::enable_if_t< IsAapcs64HxaV< HA > > >::store(), and gem5::guest_abi::Result< Aapcs32Vfp, HA, typename std::enable_if_t< IsAapcs32HomogeneousAggregateV< HA > > >::store().

◆ hafdbs

Bitfield<3, 0> gem5::ArmISA::hafdbs

Definition at line 169 of file misc_types.hh.

◆ hcd

Bitfield<29> gem5::ArmISA::hcd

Definition at line 309 of file misc_types.hh.

◆ hce

Bitfield<8> gem5::ArmISA::hce

Definition at line 379 of file misc_types.hh.

◆ hcx

gem5::ArmISA::hcx

Definition at line 161 of file misc_types.hh.

◆ hd

Bitfield< 22 > gem5::ArmISA::hd

Definition at line 602 of file misc_types.hh.

◆ hde

Bitfield<14> gem5::ArmISA::hde

Definition at line 887 of file misc_types.hh.

◆ HighVecs

const uint32_t gem5::ArmISA::HighVecs = 0xFFFF0000

Definition at line 63 of file faults.cc.

Referenced by gem5::ArmISA::ArmFault::getVector().

◆ hmc

Bitfield< 13 > gem5::ArmISA::hmc

Definition at line 849 of file misc_types.hh.

Referenced by gem5::ArmISA::BrkPoint::isEnabled(), gem5::ArmISA::WatchPoint::isEnabled(), and gem5::ArmISA::SelfDebug::securityStateMatch().

◆ hpd

Bitfield< 24 > gem5::ArmISA::hpd

Definition at line 591 of file misc_types.hh.

◆ hpd0

Bitfield< 41 > gem5::ArmISA::hpd0

Definition at line 573 of file misc_types.hh.

◆ hpd1

Bitfield< 42 > gem5::ArmISA::hpd1

Definition at line 574 of file misc_types.hh.

◆ hpds

Bitfield<15, 12> gem5::ArmISA::hpds

Definition at line 166 of file misc_types.hh.

◆ hpme

Bitfield<7> gem5::ArmISA::hpme

Definition at line 238 of file misc_types.hh.

◆ hpmn

Bitfield<4, 0> gem5::ArmISA::hpmn

Definition at line 241 of file misc_types.hh.

◆ htopcode10_9

Bitfield<26, 25> gem5::ArmISA::htopcode10_9

Definition at line 176 of file types.hh.

◆ htopcode12_11

Bitfield<28, 27> gem5::ArmISA::htopcode12_11

Definition at line 175 of file types.hh.

◆ htopcode4

Bitfield<20> gem5::ArmISA::htopcode4

Definition at line 190 of file types.hh.

◆ htopcode5_4

Bitfield<21, 20> gem5::ArmISA::htopcode5_4

Definition at line 189 of file types.hh.

◆ htopcode6

Bitfield<22> gem5::ArmISA::htopcode6

Definition at line 187 of file types.hh.

◆ htopcode6_5

Bitfield<22, 21> gem5::ArmISA::htopcode6_5

Definition at line 188 of file types.hh.

◆ htopcode7

Bitfield<23> gem5::ArmISA::htopcode7

Definition at line 185 of file types.hh.

◆ htopcode7_5

Bitfield<23, 21> gem5::ArmISA::htopcode7_5

Definition at line 186 of file types.hh.

◆ htopcode8

Bitfield<24> gem5::ArmISA::htopcode8

Definition at line 181 of file types.hh.

◆ htopcode8_5

Bitfield<24, 21> gem5::ArmISA::htopcode8_5

Definition at line 184 of file types.hh.

◆ htopcode8_6

Bitfield<24, 22> gem5::ArmISA::htopcode8_6

Definition at line 183 of file types.hh.

◆ htopcode8_7

Bitfield<24, 23> gem5::ArmISA::htopcode8_7

Definition at line 182 of file types.hh.

◆ htopcode9

Bitfield<25> gem5::ArmISA::htopcode9

Definition at line 177 of file types.hh.

◆ htopcode9_4

Bitfield<25, 20> gem5::ArmISA::htopcode9_4

Definition at line 180 of file types.hh.

◆ htopcode9_5

Bitfield<25, 21> gem5::ArmISA::htopcode9_5

Definition at line 179 of file types.hh.

◆ htopcode9_8

Bitfield<25, 24> gem5::ArmISA::htopcode9_8

Definition at line 178 of file types.hh.

◆ htrn

Bitfield<19, 16> gem5::ArmISA::htrn

Definition at line 192 of file types.hh.

◆ hts

Bitfield<20> gem5::ArmISA::hts

Definition at line 193 of file types.hh.

◆ hxen

Bitfield<38> gem5::ArmISA::hxen

Definition at line 365 of file misc_types.hh.

◆ i

Bitfield< 12 > gem5::ArmISA::i

Definition at line 67 of file misc_types.hh.

Referenced by sc_core::sc_port_b< tlm_nonblocking_put_if< T > >::_gem5AddInterface(), gem5::System::_getRequestorId(), gem5::ArmISA::Crypto::_sha1Op(), gem5::MemChecker::abortWrite(), gem5::Terminal::accept(), gem5::TCPIface::accept(), gem5::ListenSocketInet::accept(), gem5::memory::DRAMInterface::activateBank(), gem5::ruby::Histogram::add(), gem5::statistics::HistStor::add(), gem5::CheckTable::addCheck(), gem5::ruby::PerfectSwitch::addInPort(), sc_gem5::Port::addInterfaces(), gem5::AddrRange::addIntlvBits(), gem5::statistics::Hdf5::addMetaData(), gem5::ruby::NetDest::addNetDest(), gem5::ruby::garnet::NetworkInterface::addOutPort(), gem5::ruby::Switch::addOutPort(), gem5::memory::NVMInterface::addRankToRankDelay(), gem5::memory::DRAMInterface::addRankToRankDelay(), gem5::AddressManager::AddressManager(), gem5::AddrRange::AddrRange(), gem5::IniFile::addSection(), gem5::Queue< WriteQueueEntry >::addToReadyList(), gem5::trace::TarmacParserRecord::advanceTrace(), gem5::ArmISA::Crypto::aesAddRoundKey(), gem5::ArmISA::Crypto::aesInvMixColumns(), gem5::ArmISA::Crypto::aesInvShiftRows(), gem5::ArmISA::Crypto::aesInvSubBytes(), gem5::ArmISA::Crypto::aesShiftRows(), gem5::ArmISA::Crypto::aesSubBytes(), gem5::ruby::CacheRecorder::aggregateRecords(), sc_dt::scfx_mant::alloc(), gem5::ruby::CacheMemory::allocate(), gem5::Aapcs32Vfp::State::allocate(), gem5::FetchUnit::FetchBufDesc::allocateBuf(), gem5::fastmodel::PL330::allocateIrq(), gem5::FDArray::allocFD(), gem5::AMDGPUVM::AMDGPUVM(), gem5::ruby::NetDest::AND(), sc_dt::sc_unsigned_subref_r::and_reduce(), sc_dt::sc_signed_subref_r::and_reduce(), sc_dt::sc_unsigned::and_reduce(), sc_dt::sc_signed::and_reduce(), gem5::ruby::WriteMask::andMask(), gem5::FALRU::anyBlk(), gem5::X86ISA::ACPI::apic_checksum(), gem5::ScheduleStage::arbitrateVrfToLdsBus(), gem5::MipsProcess::argsInit(), gem5::PowerProcess::argsInit(), gem5::SparcProcess::argsInit(), gem5::ArmProcess::argsInit(), gem5::X86ISA::X86Process::argsInit(), sc_dt::sc_proxy< sc_bv_base >::assign_(), sc_dt::assign_v_(), sc_core::sc_vector_assembly< T, MT >::at(), gem5::ruby::DMASequencer::atomicCallback(), gem5::ruby::DataBlock::atomicPartial(), sc_dt::b_and_assign_(), sc_dt::b_xor_assign_(), gem5::BaseGlobalEventTemplate< GlobalSyncEvent >::BaseGlobalEventTemplate(), gem5::BaseIndexingPolicy::BaseIndexingPolicy(), gem5::BaseSimpleCPU::BaseSimpleCPU(), gem5::fastmodel::ScxEvsCortexA76< Types >::before_end_of_elaboration(), sc_core::sc_export< tlm::tlm_fifo_get_if< RSP > >::bind(), sc_core::sc_in< sc_dt::sc_lv< W > >::bind(), sc_core::sc_port_base::bind(), sc_core::sc_port_b< tlm_nonblocking_put_if< T > >::bind(), sc_core::sc_in< bool >::bind(), sc_core::sc_in< sc_dt::sc_logic >::bind(), gem5::CxxConfigManager::bindAllPorts(), gem5::CxxConfigManager::bindObjectPorts(), sc_dt::sc_fxnum::bit(), sc_dt::sc_uint_base::bit(), sc_dt::sc_int_base::bit(), sc_core::sc_in< sc_dt::sc_int< W > >::bit(), sc_core::sc_in< sc_dt::sc_uint< W > >::bit(), sc_dt::sc_unsigned::bit(), sc_core::sc_in< sc_dt::sc_biguint< W > >::bit(), sc_core::sc_in< sc_dt::sc_bigint< W > >::bit(), sc_dt::sc_fxnum_fast::bit(), sc_core::sc_inout< sc_dt::sc_int< W > >::bit(), sc_dt::sc_signed::bit(), sc_core::sc_inout< sc_dt::sc_uint< W > >::bit(), sc_core::sc_inout< sc_dt::sc_biguint< W > >::bit(), sc_core::sc_inout< sc_dt::sc_bigint< W > >::bit(), gem5::bitsToFloat32(), gem5::bitsToFloat64(), gem5::bloom_filter::Block::Block(), gem5::ruby::broadcast(), gem5::ruby::NetDest::broadcast(), gem5::networking::EthAddr::broadcast(), gem5::branch_prediction::TAGEBase::btbUpdate(), gem5::minor::ForwardInstData::bubbleFill(), gem5::o3::LSQ::SplitDataRequest::buildPackets(), gem5::branch_prediction::TAGE_SC_L_TAGE::buildTageTables(), gem5::branch_prediction::TAGEBase::buildTageTables(), gem5::ruby::CacheMemory::cacheAvail(), gem5::ruby::CacheMemory::CacheMemoryStats::CacheMemoryStats(), gem5::ruby::CacheMemory::cacheProbe(), gem5::FALRU::CacheTracking::CacheTracking(), gem5::branch_prediction::TAGE_SC_L_TAGE::calculateIndicesAndTags(), gem5::branch_prediction::TAGEBase::calculateIndicesAndTags(), gem5::branch_prediction::MPP_TAGE::calculateParameters(), gem5::branch_prediction::TAGE_SC_L_TAGE::calculateParameters(), gem5::branch_prediction::TAGEBase::calculateParameters(), gem5::prefetch::IndirectMemory::calculatePrefetch(), gem5::ruby::garnet::NetworkInterface::calculateVC(), gem5::minor::LSQ::StoreBuffer::canForwardDataToLoad(), gem5::o3::UnifiedRenameMap::canRename(), gem5::trace::SparcNativeTrace::check(), gem5::trace::ArmNativeTrace::check(), gem5::PacketFifo::check(), gem5::ruby::garnet::SwitchAllocator::check_for_wakeup(), sc_dt::sc_uint_base::check_index(), sc_dt::sc_int_base::check_index(), sc_dt::sc_unsigned::check_index(), sc_dt::sc_signed::check_index(), checkExpectedDistData(), gem5::memory::AbstractMemory::checkLockedAddrList(), gem5::CheckTable::CheckTable(), gem5::memory::HeteroMemCtrl::chooseNext(), gem5::memory::MemCtrl::chooseNext(), gem5::memory::NVMInterface::chooseNextFRFCFS(), gem5::memory::DRAMInterface::chooseNextFRFCFS(), gem5::memory::NVMInterface::chooseRead(), gem5::X86ISA::GpuTLB::cleanup(), gem5::VegaISA::GpuTLB::cleanup(), gem5::ruby::Histogram::clear(), gem5::ruby::NetDest::clear(), tlm::circular_buffer< RSP >::clear(), gem5::o3::StoreSet::clear(), gem5::Plic::clear(), gem5::PacketFifo::clear(), sc_dt::scfx_rep::clear(), gem5::SparcISA::Interrupts::clearAll(), gem5::MaltaCChip::clearIntr(), gem5::ruby::CacheMemory::clearLockedAll(), gem5::SparcISA::TLB::clearUsedBits(), gem5::OutputDirectory::close(), gem5::CoherentXBar::CoherentXBar(), gem5::ruby::Profiler::collateStats(), gem5::ruby::garnet::GarnetNetwork::collateStats(), gem5::ruby::garnet::Router::collateStats(), gem5::BaseCPU::CommitCPUStats::CommitCPUStats(), gem5::o3::Commit::commitHead(), gem5::ThreadContext::compare(), gem5::ArmISA::WatchPoint::compareAddress(), gem5::ruby::GPUCoalescer::completeIssue(), gem5::MemChecker::completeRead(), gem5::MemChecker::completeWrite(), gem5::compression::Multi::compress(), gem5::compression::DictionaryCompressor< uint64_t >::compressValue(), gem5::branch_prediction::MultiperspectivePerceptron::computeBits(), gem5::branch_prediction::MultiperspectivePerceptron::computeOutput(), gem5::QARMA::computePAC(), gem5::branch_prediction::MultiperspectivePerceptronTAGE::computePartialSum(), gem5::BaseTags::computeStats(), gem5::ComputeUnit::ComputeUnitStats::ComputeUnitStats(), sc_dt::concat(), gem5::FunctionProfile::consume(), gem5::AddrRange::contains(), gem5::ruby::WriteMask::containsMask(), gem5::X86ISA::convX87TagsToXTags(), gem5::X86ISA::convX87XTagsToTags(), gem5::PollQueue::copy(), sc_dt::copy_digits_signed(), gem5::SparcISA::copyMiscRegs(), gem5::X86ISA::copyMiscRegs(), gem5::PacketFifo::copyout(), gem5::ruby::DataBlock::copyPartial(), gem5::SDMAEngine::copyReadData(), gem5::SparcISA::ISA::copyRegsFrom(), gem5::ArmISA::ISA::copyRegsFrom(), gem5::Checker< gem5::RefCountingPtr >::copyResult(), gem5::copyStringArray(), gem5::fastmodel::ScxEvsCortexR52< Types >::CorePins::CorePins(), gem5::fastmodel::CortexA76Cluster::CortexA76Cluster(), gem5::fastmodel::CortexR52Cluster::CortexR52Cluster(), gem5::ruby::NetDest::count(), gem5::ruby::WriteMask::count(), gem5::LdsState::countBankConflicts(), gem5::GenericTimerMem::counterCtrlRead(), gem5::GenericTimerMem::counterCtrlWrite(), gem5::PacketFifo::countPacketsAfter(), gem5::PacketFifo::countPacketsBefore(), gem5::ruby::PersistentTable::countReadStarvingForAddress(), gem5::ruby::PersistentTable::countStarvingForAddress(), gem5::crc32(), gem5::ruby::Topology::createLinks(), gem5::BackdoorManager::createRevertedBackdoor(), gem5::GenericTimer::createTimers(), gem5::ArmISA::ArmStaticInst::cSwap(), gem5::ruby::DMASequencer::dataCallback(), gem5::FetchUnit::FetchBufDesc::decodeSplitInst(), gem5::compression::DictionaryCompressor< uint64_t >::decompress(), gem5::compression::DictionaryCompressor< T >::RepeatedValuePattern< RepT >::decompress(), gem5::branch_prediction::DefaultBTB::DefaultBTB(), gem5::CxxConfigManager::deleteObjects(), gem5::SparcISA::TLB::demapPage(), gem5::BaseGlobalEvent::deschedule(), gem5::SkewedAssociative::deskew(), gem5::StaticInst::destRegIdx(), gem5::o3::DynInst::destRegIdx(), gem5::Linux::devRandom(), gem5::ExecStage::dispStatusToStr(), gem5::ComputeUnit::dispWorkgroup(), gem5::statistics::DistPrint::DistPrint(), gem5::PowerISA::IntArithOp::divide(), gem5::LupioBLK::dmaEventDone(), gem5::memory::NVMInterface::doBurstAccess(), gem5::memory::DRAMInterface::doBurstAccess(), gem5::statistics::VectorBase< Vector, StatStor >::doInit(), gem5::statistics::VectorDistBase< VectorAverageDeviation, AvgSampleStor >::doInit(), gem5::ObjectMatch::domatch(), gem5::PCEventQueue::doService(), gem5::ThermalModel::doStep(), gem5::ruby::Histogram::doubleBinSize(), gem5::o3::CPU::drain(), gem5::ArmISA::TableWalker::drain(), gem5::o3::Fetch::drainResume(), gem5::o3::CPU::drainResume(), gem5::o3::MemDepUnit::drainSanityCheck(), gem5::o3::LSQUnit::drainSanityCheck(), gem5::o3::Fetch::drainSanityCheck(), gem5::memory::DRAMInterface::DRAMInterface(), gem5::BaseStackTrace::dump(), gem5::ArmV8KvmCPU::dump(), gem5::ActivityRecorder::dump(), gem5::Trie< Key, Value >::Node::dump(), gem5::trace::Logger::dump(), gem5::o3::DependencyGraph< gem5::RefCountingPtr >::dump(), gem5::PCEventQueue::dump(), gem5::RegisterFile::dump(), gem5::o3::FUPool::dump(), gem5::branch_prediction::BPredUnit::dump(), gem5::IniFile::dump(), sc_dt::scfx_rep::dump(), gem5::SparcISA::TLB::dumpAll(), gem5::dumpDebugFlags(), gem5::ExecStage::dumpDispList(), gem5::dumpFpuCommon(), gem5::dumpKvm(), gem5::o3::InstructionQueue::dumpLists(), gem5::dumpMainQueue(), gem5::X86KvmCPU::dumpMSRs(), gem5::loader::ElfObject::ElfObject(), gem5::o3::DependencyGraph< gem5::RefCountingPtr >::empty(), gem5::minor::MinorBuffer< gem5::minor::BranchData >::empty(), sc_core::sc_in< sc_dt::sc_int< W > >::end_of_elaboration(), sc_core::sc_in< sc_dt::sc_uint< W > >::end_of_elaboration(), sc_core::sc_in< sc_dt::sc_biguint< W > >::end_of_elaboration(), sc_core::sc_in< sc_dt::sc_bigint< W > >::end_of_elaboration(), sc_core::sc_inout< sc_dt::sc_int< W > >::end_of_elaboration(), sc_core::sc_inout< sc_dt::sc_uint< W > >::end_of_elaboration(), sc_core::sc_inout< sc_dt::sc_biguint< W > >::end_of_elaboration(), sc_core::sc_inout< sc_dt::sc_bigint< W > >::end_of_elaboration(), SimpleLTInitiator2_dmi::end_of_simulation(), SimpleLTInitiator1_dmi::end_of_simulation(), SimpleLTInitiator_ext::end_of_simulation(), gem5::networking::EthAddr::EthAddr(), gem5::EtherSwitch::EtherSwitch(), gem5::minor::Decode::evaluate(), gem5::minor::Fetch2::evaluate(), gem5::minor::Execute::evaluate(), gem5::eventqDump(), gem5::X86ISA::TLB::evictLRU(), gem5::Shader::execScheduledAdds(), gem5::ExecStage::ExecStageStats::ExecStageStats(), gem5::minor::Execute::Execute(), gem5::Gcn3ISA::Inst_SOPP__S_ENDPGM::execute(), gem5::VegaISA::Inst_SOPP__S_ENDPGM::execute(), gem5::Gcn3ISA::Inst_VOP3__V_PERM_B32::execute(), gem5::VegaISA::Inst_VOP3__V_PERM_B32::execute(), gem5::execveFunc(), gem5::X86ISA::GpuTLB::exitCallback(), gem5::exitImpl(), gem5::ruby::Topology::extend_shortest_path(), sc_dt::extend_sign_w_(), gem5::ruby::FaultModel::fault_prob(), gem5::ruby::FaultModel::fault_vector(), gem5::ruby::FaultModel::FaultModel(), gem5::o3::Fetch::Fetch(), gem5::ruby::WriteMask::fillMask(), sc_gem5::Port::finalizeFinder(), sc_gem5::Port::finalizePort(), gem5::SparcISA::TlbMap::find(), sc_gem5::StaticSensitivityFinder::find(), gem5::OutputDirectory::find(), gem5::AddrRangeMap< gem5::MemBackdoor, 1 >::find(), gem5::loader::SymbolTable::find(), gem5::SimObject::find(), gem5::BackdoorManager::findBackdoor(), gem5::branch_prediction::MultiperspectivePerceptron::findBest(), gem5::debug::findFlag(), gem5::VGic::findHighestPendingLR(), gem5::VGic::findLRForVIRQ(), gem5::loader::SymbolTable::findNearest(), gem5::CxxConfigManager::findObject(), gem5::CxxConfigManager::findObjectParams(), gem5::BaseXBar::findPort(), gem5::IniFile::findSection(), gem5::ruby::PersistentTable::findSmallest(), gem5::minor::FUPipeline::findTiming(), gem5::CxxConfigManager::findTraversalOrder(), gem5::o3::LSQ::SplitDataRequest::finish(), gem5::VecPredRegT< VecElem, NumElems, Packed, Const >::firstActive(), gem5::ruby::WriteMask::firstBitSet(), gem5::Gcn3ISA::firstOppositeSignBit(), gem5::VegaISA::firstOppositeSignBit(), gem5::AtagCore::flags(), gem5::ruby::garnet::NetworkBridge::flitisizeAndSend(), gem5::ruby::garnet::NetworkInterface::flitisizeMessage(), gem5::floatToBits32(), gem5::floatToBits64(), gem5::X86ISA::TLB::flushAll(), gem5::FetchUnit::FetchBufDesc::flushBuf(), gem5::X86ISA::TLB::flushNonGlobal(), gem5::BaseCPU::flushTLBs(), gem5::CxxConfigManager::forEachObject(), gem5::formatParamList(), gem5::Gicv2m::frameFromAddr(), gem5::Wavefront::freeRegisterFile(), gem5::StaticRegisterManagerPolicy::freeRegisters(), gem5::compression::Base::fromChunks(), gem5::compression::DictionaryCompressor< uint64_t >::fromDictionaryEntry(), gem5::ruby::MessageBuffer::functionalAccess(), gem5::ruby::garnet::flitBuffer::functionalRead(), gem5::ruby::SimpleNetwork::functionalRead(), gem5::ruby::Switch::functionalRead(), gem5::ruby::garnet::GarnetNetwork::functionalRead(), gem5::ruby::garnet::Router::functionalRead(), gem5::ruby::garnet::flitBuffer::functionalWrite(), gem5::ruby::SimpleNetwork::functionalWrite(), gem5::ruby::Switch::functionalWrite(), gem5::ruby::garnet::GarnetNetwork::functionalWrite(), gem5::ruby::garnet::Router::functionalWrite(), gem5::ruby::RubyRequest::functionalWrite(), gem5::FuncUnit::FuncUnit(), gem5::minor::FUPipeline::FUPipeline(), gem5::o3::FUPool::FUPool(), gem5::futimesatFunc(), gem5::ruby::garnet::GarnetNetwork::GarnetNetwork(), gem5::compression::FrequentValues::generateCodes(), gem5::MrsOp::generateDisassembly(), gem5::ArmISA::SveLdStructSS< Element, MicroopLdMemType, MicroopDeIntrlvType >::generateDisassembly(), gem5::ArmISA::SveStStructSS< Element, MicroopStMemType, MicroopIntrlvType >::generateDisassembly(), gem5::ArmISA::SveLdStructSI< Element, MicroopLdMemType, MicroopDeIntrlvType >::generateDisassembly(), gem5::ArmISA::SveStStructSI< Element, MicroopStMemType, MicroopIntrlvType >::generateDisassembly(), gem5::GarnetSyntheticTraffic::generatePkt(), gem5::Gicv3CPUInterface::generateSGI(), gem5::X86ISA::genX87Tags(), gem5::guest_abi::Argument< Aapcs32, Composite, typename std::enable_if_t< IsAapcs32CompositeV< Composite > > >::get(), gem5::guest_abi::Argument< Aapcs64, HA, typename std::enable_if_t< IsAapcs64HxaV< HA > > >::get(), gem5::guest_abi::Argument< Aapcs64, Composite, typename std::enable_if_t< IsAapcs64CompositeV< Composite > &&!IsAapcs64HxaV< Composite > > >::get(), gem5::guest_abi::Argument< Aapcs32Vfp, HA, typename std::enable_if_t< IsAapcs32HomogeneousAggregateV< HA > > >::get(), tlm_utils::multi_passthrough_target_socket< MultiSocketSimpleSwitchAT >::get_base_export(), sc_dt::scfx_rep::get_bit(), sc_dt::sc_fxval::get_bit(), sc_dt::sc_subref_r< X >::get_bit(), sc_dt::sc_fxnum::get_bit(), sc_dt::sc_subref_r< X >::get_cword(), sc_dt::scfx_rep::get_slice(), sc_dt::sc_fxnum::get_slice(), gem5::ruby::garnet::NetworkInterface::get_vnet(), sc_dt::sc_lv_base::get_word(), sc_dt::sc_subref_r< X >::get_word(), gem5::Gicv2m::getAddrRanges(), gem5::ruby::RubyPort::PioResponsePort::getAddrRanges(), gem5::ruby::NetDest::getAllDest(), gem5::PciDevice::getBAR(), gem5::VecPredRegContainer< size, T >::getBits(), gem5::CheckTable::getCheck(), gem5::bloom_filter::MultiBitSel::getCount(), gem5::PowerModel::getDynamicPower(), gem5::branch_prediction::TAGEBase::getGHR(), gem5::branch_prediction::MultiperspectivePerceptron::ACYCLIC::getHash(), gem5::branch_prediction::MultiperspectivePerceptron::MODHIST::getHash(), gem5::branch_prediction::MultiperspectivePerceptron::RECENCY::getHash(), gem5::branch_prediction::MultiperspectivePerceptron::PATH::getHash(), gem5::branch_prediction::MultiperspectivePerceptron::MODPATH::getHash(), gem5::branch_prediction::MultiperspectivePerceptron::GHISTPATH::getHash(), gem5::branch_prediction::MultiperspectivePerceptron::GHISTMODPATH::getHash(), gem5::branch_prediction::MultiperspectivePerceptron::BLURRYPATH::getHash(), gem5::branch_prediction::MultiperspectivePerceptron::SGHISTPATH::getHash(), gem5::Gicv3CPUInterface::getHPPVILR(), sc_gem5::Port::getInterface(), gem5::branch_prediction::LoopPredictor::getLoop(), gem5::ruby::RubyPrefetcher::getLRUindex(), gem5::ruby::WriteMask::getMask(), gem5::CxxIniFile::getObjectChildren(), gem5::X86ISA::getPackedMem(), gem5::prefetch::PIF::CompactorEntry::getPredictedAddresses(), gem5::ruby::RubyPrefetcher::getPrefetchEntry(), gem5::getrandomFunc(), gem5::ArmKvmCPU::getRegList(), gem5::MipsISA::RemoteGDB::MipsGdbRegCache::getRegs(), gem5::ArmISA::RemoteGDB::AArch32GdbRegCache::getRegs(), gem5::ArmISA::RemoteGDB::AArch64GdbRegCache::getRegs(), gem5::RiscvISA::RemoteGDB::Riscv32GdbRegCache::getRegs(), gem5::RiscvISA::RemoteGDB::Riscv64GdbRegCache::getRegs(), gem5::IniFile::getSectionNames(), gem5::branch_prediction::SimpleIndirectPredictor::getSetIndex(), gem5::branch_prediction::TAGEBase::getSizeInBits(), gem5::PowerModel::getStaticPower(), gem5::ruby::Throttle::getTotalLinkBandwidth(), gem5::replacement_policy::Dueling::getVictim(), gem5::PowerState::getWeights(), gem5::fastmodel::GIC::GIC(), gem5::Gicv2m::Gicv2m(), gem5::branch_prediction::StatisticalCorrector::gIndex(), gem5::branch_prediction::TAGE_SC_L_64KB_StatisticalCorrector::gIndexLogsSubstr(), gem5::branch_prediction::MPP_StatisticalCorrector::gIndexLogsSubstr(), gem5::debug::Flag::globalDisable(), gem5::debug::Flag::globalEnable(), gem5::branch_prediction::StatisticalCorrector::gPredict(), gem5::GPUDynInst::GPUDynInst(), gem5::statistics::HistStor::growDown(), gem5::statistics::HistStor::growOut(), gem5::statistics::HistStor::growUp(), gem5::branch_prediction::MPP_StatisticalCorrector::gUpdate(), gem5::branch_prediction::StatisticalCorrector::gUpdate(), gem5::branch_prediction::TAGE_SC_L_TAGE_8KB::handleAllocAndUReset(), gem5::branch_prediction::TAGE_SC_L_TAGE_64KB::handleAllocAndUReset(), gem5::branch_prediction::MPP_TAGE::handleAllocAndUReset(), gem5::branch_prediction::TAGEBase::handleAllocAndUReset(), gem5::X86KvmCPU::handleKvmExitIO(), gem5::branch_prediction::MPP_TAGE::handleUReset(), gem5::branch_prediction::TAGEBase::handleUReset(), gem5::ComputeUnit::hasDispResources(), gem5::bloom_filter::H3::hash(), gem5::bloom_filter::MultiBitSel::hash(), gem5::bloom_filter::Block::hash(), gem5::branch_prediction::MultiperspectivePerceptron::MPPBranchInfo::hash(), gem5::branch_prediction::MultiperspectivePerceptron::GHIST::hash(), gem5::branch_prediction::MultiperspectivePerceptron::RECENCYPOS::hash(), gem5::o3::InstructionQueue::hasReadyInsts(), sc_dt::high_half(), gem5::HSAPacketProcessor::HSAPacketProcessor(), gem5::ruby::CacheMemory::htmAbortTransaction(), gem5::ruby::CacheMemory::htmCommitTransaction(), gem5::X86ISA::I8042::I8042(), gem5::X86ISA::I82094AA::I82094AA(), gem5::X86ISA::I8254::I8254(), gem5::X86ISA::I8259::I8259(), gem5::IdeController::IdeController(), gem5::statistics::InfoAccess::info(), gem5::ruby::garnet::SwitchAllocator::init(), gem5::FetchUnit::init(), gem5::ruby::DirectoryMemory::init(), gem5::ruby::garnet::GarnetNetwork::init(), gem5::ruby::CacheMemory::init(), gem5::o3::StoreSet::init(), gem5::ruby::PerfectSwitch::init(), gem5::ruby::AbstractController::init(), gem5::RubyTester::init(), gem5::Clint::ClintRegisters::init(), gem5::ProtocolTester::init(), sc_dt::sc_lv_base::init(), gem5::Plic::init(), gem5::Gicv3::init(), gem5::CpuLocalTimer::init(), gem5::o3::UnifiedRenameMap::init(), gem5::Plic::PlicRegisters::init(), gem5::ArmISA::SelfDebug::init(), gem5::ComputeUnit::init(), sc_core::sc_vector< svp_gicv3_comms::gicv3_comms_target_socket<> >::init(), gem5::branch_prediction::MultiperspectivePerceptron::init(), gem5::statistics::Vector2dBase< Vector2d, StatStor >::init(), gem5::GPUStaticInst::initDynOperandInfo(), gem5::branch_prediction::TAGE_SC_L_TAGE_8KB::initFoldedHistories(), gem5::branch_prediction::TAGEBase::initFoldedHistories(), gem5::branch_prediction::StatisticalCorrector::initGEHLTable(), sc_core::sc_inout< sc_dt::sc_lv< W > >::initialize(), sc_core::sc_inout< bool >::initialize(), sc_core::sc_inout< sc_dt::sc_logic >::initialize(), gem5::o3::LSQ::SplitDataRequest::initiateTranslation(), gem5::Gcn3ISA::Inst_DS::initMemRead(), gem5::VegaISA::Inst_DS::initMemRead(), gem5::Gcn3ISA::Inst_FLAT::initMemRead(), gem5::VegaISA::Inst_FLAT::initMemRead(), gem5::Gcn3ISA::Inst_DS::initMemWrite(), gem5::VegaISA::Inst_DS::initMemWrite(), gem5::Gcn3ISA::Inst_FLAT::initMemWrite(), gem5::VegaISA::Inst_FLAT::initMemWrite(), gem5::X86ISA::X86_64Process::initState(), gem5::X86ISA::I386Process::initState(), gem5::ruby::garnet::InputUnit::InputUnit(), gem5::SparcISA::TLB::insert(), gem5::ArmISA::TLB::insert(), gem5::Trie< Addr, TlbEntry >::insert(), gem5::branch_prediction::MultiperspectivePerceptron::insert(), gem5::PowerISA::TLB::insertAt(), gem5::branch_prediction::MultiperspectivePerceptron::ThreadData::insertRecency(), gem5::SparcISA::ISA::installGlobals(), gem5::SparcISA::ISA::installWindow(), gem5::ruby::SubBlock::internalMergeFrom(), gem5::ruby::SubBlock::internalMergeTo(), gem5::SparcISA::TlbMap::intersect(), gem5::ruby::NetDest::intersectionIsNotEmpty(), sc_dt::sc_uint_base::invalid_index(), sc_dt::sc_int_base::invalid_index(), sc_dt::sc_unsigned::invalid_index(), sc_dt::sc_signed::invalid_index(), gem5::VegaISA::GpuTLB::invalidateAll(), gem5::X86ISA::GpuTLB::invalidateAll(), gem5::SMMUTLB::invalidateAll(), gem5::ARMArchTLB::invalidateAll(), gem5::IPACache::invalidateAll(), gem5::ConfigCache::invalidateAll(), gem5::WalkCache::invalidateAll(), gem5::SMMUTLB::invalidateASID(), gem5::ARMArchTLB::invalidateASID(), gem5::WalkCache::invalidateASID(), gem5::IPACache::invalidateIPA(), gem5::IPACache::invalidateIPAA(), gem5::X86ISA::GpuTLB::invalidateNonGlobal(), gem5::SMMUTLB::invalidateSID(), gem5::ConfigCache::invalidateSID(), gem5::SMMUTLB::invalidateSSID(), gem5::ConfigCache::invalidateSSID(), gem5::SMMUTLB::invalidateVA(), gem5::ARMArchTLB::invalidateVA(), gem5::WalkCache::invalidateVA(), gem5::SMMUTLB::invalidateVAA(), gem5::ARMArchTLB::invalidateVAA(), gem5::WalkCache::invalidateVAA(), gem5::SMMUTLB::invalidateVMID(), gem5::ARMArchTLB::invalidateVMID(), gem5::IPACache::invalidateVMID(), gem5::WalkCache::invalidateVMID(), sc_dt::sc_unsigned::invert(), sc_dt::sc_signed::invert(), gem5::ruby::VIPERCoalescer::invTCP(), gem5::GPUComputeDriver::ioctl(), gem5::o3::InstructionQueue::IQStats::IQStats(), sc_dt::scfx_ieee_double::is_inf(), gem5::ruby::NetDest::isBroadcast(), gem5::ComputeUnit::isDone(), gem5::o3::MemDepUnit::isDrained(), gem5::o3::FUPool::isDrained(), gem5::o3::Fetch::isDrained(), gem5::ruby::NetDest::isEmpty(), gem5::ruby::WriteMask::isEmpty(), gem5::ruby::NetDest::isEqual(), gem5::ruby::WriteMask::isFull(), gem5::AQLRingBuffer::isLastOutstandingPkt(), gem5::ruby::WriteMask::isOverlap(), gem5::compression::DictionaryCompressor< T >::RepeatedValuePattern< RepT >::isPattern(), gem5::ruby::DMASequencer::issueNext(), gem5::ruby::VIPERCoalescer::issueRequest(), gem5::ruby::NetDest::isSuperset(), gem5::MSHR::TargetList::isWholeLineWrite(), gem5::KvmVM::KvmVM(), gem5::VecPredRegT< VecElem, NumElems, Packed, Const >::lastActive(), gem5::statistics::Info::less(), gem5::LinearSystem::LinearSystem(), gem5::HDLcd::lineNext(), gem5::ListenSocketInet::listen(), gem5::ArmISA::Crypto::load2Reg(), gem5::ArmISA::Crypto::load3Reg(), gem5::CxxConfigManager::loadState(), gem5::memory::qos::MemCtrl::logRequest(), gem5::PowerISA::TLB::lookup(), gem5::SparcISA::TLB::lookup(), gem5::SMMUTLB::lookup(), gem5::ARMArchTLB::lookup(), gem5::IPACache::lookup(), gem5::ConfigCache::lookup(), gem5::WalkCache::lookup(), gem5::SMMUTLB::lookupAnyVA(), gem5::System::lookupRequestorId(), gem5::ruby::lookupTraceForAddress(), gem5::branch_prediction::LoopPredictor::loopUpdate(), sc_dt::low_half(), sc_dt::sc_proxy< sc_bv_base >::lrotate(), gem5::VGic::lrPending(), gem5::VGic::lrValid(), gem5::LupioBLK::lupioBLKCmd(), gem5::ArmISA::MacroVFPMemOp::MacroVFPMemOp(), main(), gem5::ruby::GPUCoalescer::makeRequest(), gem5::Malta::Malta(), gem5::ruby::AbstractController::mapAddressToDownstreamMachine(), gem5::mappingParamIn(), gem5::mappingParamOut(), gem5::ruby::PersistentTable::markEntries(), gem5::ArmISA::TLB::match(), gem5::AtagMem::memSize(), gem5::AtagMem::memStart(), gem5::bloom_filter::Multi::merge(), gem5::bloom_filter::Base::merge(), gem5::memory::DRAMInterface::minBankPrep(), gem5::MinorCPU::MinorCPU(), gem5::MinorOpClassSet::MinorOpClassSet(), gem5::minor::Scoreboard::minorTrace(), gem5::minor::MinorBuffer< gem5::minor::BranchData >::minorTrace(), gem5::minor::Execute::minorTrace(), gem5::minor::LSQ::StoreBuffer::minorTrace(), gem5::FALRU::CacheTracking::moveBlockToHead(), gem5::FALRU::CacheTracking::moveBlockToTail(), sc_dt::scfx_ieee_double::msb(), gem5::ruby::Network::Network(), gem5::ruby::garnet::NetworkLink::NetworkLink(), sc_gem5::newStaticSensitivityInterface(), gem5::TrafficGen::nextState(), tlm::no_b1(), gem5::NoncoherentXBar::NoncoherentXBar(), gem5::VecPredRegT< VecElem, NumElems, Packed, Const >::noneActive(), number_of_ones(), gem5::BaseCPU::numSimulatedInsts(), gem5::BaseCPU::numSimulatedOps(), sc_dt::scfx_rep::o_extend(), sc_dt::scfx_rep::o_set(), sc_dt::scfx_rep::o_set_high(), sc_dt::scfx_rep::o_zero_right(), gem5::ruby::PersistentTable::okToIssueStarving(), gem5::VirtIOConsole::TermTransQueue::onNotifyDescriptor(), gem5::CowDiskImage::open(), gem5::ruby::PerfectSwitch::operateMessageBuffer(), gem5::ruby::PerfectSwitch::operateVnet(), sc_dt::operator!=(), std::hash< gem5::FutexKey >::operator()(), sc_core::sc_export< tlm::tlm_fifo_get_if< RSP > >::operator()(), sc_core::sc_sensitive::operator()(), sc_core::sc_in< sc_dt::sc_lv< W > >::operator()(), sc_core::sc_port_b< tlm_nonblocking_put_if< T > >::operator()(), sc_core::sc_in< bool >::operator()(), gem5::statistics::VectorPrint::operator()(), sc_core::sc_in< sc_dt::sc_logic >::operator()(), gem5::statistics::DistPrint::operator()(), sc_dt::sc_fxnum::operator()(), sc_dt::sc_unsigned::operator()(), sc_dt::sc_fxnum_fast::operator()(), sc_dt::sc_signed::operator()(), gem5::LinearEquation::operator+(), gem5::TimeBuffer< T >::wire::operator++(), gem5::TimeBuffer< T >::wire::operator--(), sc_core::sc_sensitive::operator<<(), gem5::ruby::operator<<(), sc_core::sc_out_resolved::operator=(), sc_core::sc_inout_resolved::operator=(), sc_core::sc_out_rv< W >::operator=(), sc_core::sc_inout_rv< W >::operator=(), gem5::TimeBuffer< T >::wire::operator=(), sc_dt::scfx_mant::operator=(), sc_core::sc_inout< sc_dt::sc_lv< W > >::operator=(), sc_core::sc_inout< bool >::operator=(), gem5::minor::ForwardInstData::operator=(), sc_dt::scfx_mant_ref::operator=(), sc_core::sc_inout< sc_dt::sc_logic >::operator=(), sc_dt::sc_uint_base::operator=(), sc_dt::sc_int_base::operator=(), gem5::networking::TcpPtr::operator=(), gem5::networking::UdpPtr::operator=(), sc_dt::sc_unsigned::operator=(), sc_dt::sc_signed::operator=(), sc_dt::scfx_mant::operator[](), gem5::TypedBufferArg< T >::operator[](), sc_core::sc_vector_assembly< T, MT >::operator[](), sc_dt::sc_fxnum::operator[](), sc_dt::sc_uint_base::operator[](), sc_dt::sc_int_base::operator[](), sc_core::sc_in< sc_dt::sc_int< W > >::operator[](), sc_core::sc_in< sc_dt::sc_uint< W > >::operator[](), sc_dt::sc_unsigned::operator[](), sc_core::sc_in< sc_dt::sc_biguint< W > >::operator[](), sc_core::sc_in< sc_dt::sc_bigint< W > >::operator[](), sc_dt::sc_fxnum_fast::operator[](), sc_dt::sc_signed::operator[](), sc_core::sc_inout< sc_dt::sc_int< W > >::operator[](), sc_core::sc_inout< sc_dt::sc_uint< W > >::operator[](), sc_core::sc_inout< sc_dt::sc_biguint< W > >::operator[](), sc_core::sc_inout< sc_dt::sc_bigint< W > >::operator[](), sc_dt::sc_proxy< sc_bv_base >::operator^=(), gem5::ruby::NetDest::OR(), sc_dt::sc_unsigned_subref_r::or_reduce(), sc_dt::sc_signed_subref_r::or_reduce(), gem5::ruby::WriteMask::orMask(), sc_gem5::VcdTraceValFinite< T >::output(), sc_gem5::VcdTraceValFxnum< T >::output(), sc_gem5::VcdTraceValTime::output(), sc_gem5::VcdTraceValInt< T >::output(), gem5::ruby::garnet::OutputUnit::OutputUnit(), gem5::QARMA::PACInvSub(), gem5::QARMA::PACMult(), gem5::QARMA::PACSub(), gem5::AtagCore::pagesize(), gem5::networking::EthAddr::parse(), gem5::MathExpr::parse(), gem5::ParseParam< VecRegContainer< Sz > >::parse(), gem5::ParseParam< VecPredRegContainer< NumBits, Packed > >::parse(), gem5::ParseParam< MatStore< X, Y > >::parse(), gem5::TrafficGen::parseConfig(), gem5::PcCountTracker::PcCountTracker(), gem5::PcCountTrackerManager::PcCountTrackerManager(), gem5::ruby::WriteMask::performAtomic(), gem5::ruby::Profiler::ProfilerStats::PerMachineTypeStats::PerMachineTypeStats(), gem5::ruby::Profiler::ProfilerStats::PerRequestTypeMachineTypeStats::PerRequestTypeMachineTypeStats(), gem5::ruby::Profiler::ProfilerStats::PerRequestTypeStats::PerRequestTypeStats(), gem5::ruby::PersistentTable::persistentRequestLock(), gem5::SMMUTLB::pickEntryIdxToReplace(), gem5::ARMArchTLB::pickEntryIdxToReplace(), gem5::IPACache::pickEntryIdxToReplace(), gem5::ConfigCache::pickEntryIdxToReplace(), gem5::WalkCache::pickEntryIdxToReplace(), gem5::fastmodel::PL330::PL330(), gem5::PMP::pmpCheck(), gem5::PMP::pmpReset(), gem5::PMP::pmpUpdateRule(), tlm::circular_buffer< RSP >::poke_data(), gem5::PortTerminator::PortTerminator(), gem5::Plic::post(), gem5::MaltaCChip::postIntr(), gem5::memory::DRAMInterface::prechargeBank(), gem5::statistics::DistStor::prepare(), gem5::statistics::DataWrapVec< VectorStandardDeviation, VectorDistInfoProxy >::prepare(), gem5::statistics::HistStor::prepare(), gem5::statistics::Vector2dBase< Vector2d, StatStor >::prepare(), gem5::statistics::VectorDistBase< VectorAverageDeviation, AvgSampleStor >::prepare(), prepareCheckDistStor(), prepareCheckHistStor(), preUnflattenMiscReg(), gem5::ruby::DataBlock::print(), gem5::ruby::NetDest::print(), gem5::ruby::Throttle::print(), gem5::ruby::RubyPrefetcher::print(), gem5::ruby::CacheMemory::print(), gem5::SparcISA::TlbMap::print(), gem5::ruby::WriteMask::print(), sc_dt::print_dec(), gem5::printByteBuf(), gem5::Packet::PrintReqState::printLabels(), gem5::MsrBase::printMsrBase(), gem5::ruby::printSorted(), gem5::System::printSystems(), gem5::IniFile::printUnreferenced(), gem5::ruby::Histogram::printWithMultiplier(), gem5::trace::TarmacParserRecord::TarmacParserRecordEvent::process(), gem5::memory::qos::MemSinkCtrl::processNextReqEvent(), gem5::HSAPacketProcessor::processPkt(), gem5::TLBCoalescer::processProbeTLBEvent(), gem5::VegaTLBCoalescer::processProbeTLBEvent(), gem5::memory::NVMInterface::processReadReadyEvent(), gem5::ruby::Profiler::ProfilerStats::ProfilerStats(), gem5::Plic::propagateOutput(), gem5::ProtocolTester::ProtocolTester(), gem5::SDMAEngine::ptePde(), sc_dt::scfx_rep::q_incr(), gem5::Queue< WriteQueueEntry >::Queue(), QTIsaac< ALPHA >::randinit(), gem5::MinorCPU::randomPriority(), sc_dt::sc_fxnum::range(), sc_dt::sc_unsigned::range(), sc_dt::sc_fxnum_fast::range(), sc_dt::sc_signed::range(), gem5::SimpleDisk::read(), tlm::circular_buffer< RSP >::read(), gem5::CowDiskImage::read(), gem5::Gcn3ISA::VecOperand< DataType, Const, NumDwords >::read(), gem5::VegaISA::VecOperand< DataType, Const, NumDwords >::read(), gem5::Gicv3Redistributor::read(), gem5::Gicv3Distributor::read(), gem5::Gcn3ISA::ScalarOperand< DataType, Const, sizeof(DataType)/sizeof(VecElemU32) >::read(), gem5::VegaISA::ScalarOperand< DataType, Const, sizeof(DataType)/sizeof(VecElemU32) >::read(), gem5::VirtQueue::VirtRing< struct vring_used_elem >::read(), gem5::TraceCPU::ElasticDataGen::InputStream::read(), gem5::VGic::readCtrl(), gem5::X86ISA::readPackedMemAtomic(), gem5::VGic::readVCpu(), gem5::readvFunc(), gem5::PixelConverter::readWord(), gem5::ruby::ExpectedMap< RespType, DataType >::ExpectedState< DataType >::receivedType(), gem5::FALRU::CacheTracking::recordAccess(), gem5::ruby::CacheMemory::recordCacheContents(), gem5::ruby::RubyPort::PioResponsePort::recvAtomic(), gem5::SerialLink::SerialLinkResponsePort::recvFunctional(), gem5::memory::DRAMSim2::recvFunctional(), gem5::Bridge::BridgeResponsePort::recvFunctional(), gem5::memory::DRAMsim3::recvFunctional(), gem5::recvmsgFunc(), gem5::ComputeUnit::DataPort::recvReqRetry(), gem5::ComputeUnit::SQCPort::recvReqRetry(), gem5::ComputeUnit::DTLBPort::recvReqRetry(), gem5::ComputeUnit::ITLBPort::recvReqRetry(), gem5::TLBCoalescer::CpuSidePort::recvTimingReq(), gem5::ruby::RubyPort::PioResponsePort::recvTimingReq(), gem5::VegaTLBCoalescer::CpuSidePort::recvTimingReq(), gem5::memory::SimpleMemory::recvTimingReq(), gem5::memory::CfiMemory::recvTimingReq(), sc_gem5::Port::regPort(), gem5::BaseMemProbe::regProbeListeners(), gem5::compression::BaseDictionaryCompressor::DictionaryStats::regStats(), gem5::SectorTags::SectorTagsStats::regStats(), gem5::BaseTags::BaseTagStats::regStats(), gem5::ruby::garnet::GarnetNetwork::regStats(), gem5::compression::Base::BaseStats::regStats(), gem5::PowerState::PowerStateStats::regStats(), gem5::memory::qos::MemCtrl::MemCtrlStats::regStats(), gem5::memory::AbstractMemory::MemStats::regStats(), gem5::BaseCPU::regStats(), gem5::BaseXBar::regStats(), gem5::memory::MemCtrl::CtrlStats::regStats(), gem5::BaseCache::CacheStats::regStats(), gem5::BaseCache::CacheCmdStats::regStatsFromParent(), gem5::ComputeUnit::releaseWFsFromBarrier(), gem5::SparcISA::ISA::reloadRegMap(), gem5::RangeAddrMapper::remapAddr(), gem5::PollQueue::remove(), gem5::PCEventQueue::remove(), gem5::PacketFifo::remove(), gem5::OutputDirectory::remove(), sc_core::sc_in< sc_dt::sc_int< W > >::remove_traces(), sc_core::sc_in< sc_dt::sc_uint< W > >::remove_traces(), sc_core::sc_in< sc_dt::sc_biguint< W > >::remove_traces(), sc_core::sc_in< sc_dt::sc_bigint< W > >::remove_traces(), sc_core::sc_inout< sc_dt::sc_int< W > >::remove_traces(), sc_core::sc_inout< sc_dt::sc_uint< W > >::remove_traces(), sc_core::sc_inout< sc_dt::sc_biguint< W > >::remove_traces(), sc_core::sc_inout< sc_dt::sc_bigint< W > >::remove_traces(), gem5::BaseRemoteGDB::removeHardBreak(), gem5::AddrRange::removeIntlvBits(), gem5::ruby::NetDest::removeNetDest(), gem5::o3::CPU::removeThread(), gem5::CxxConfigManager::rename(), gem5::minor::ForwardInstData::reportData(), gem5::BaseGlobalEvent::reschedule(), gem5::ArmISA::HTMCheckpoint::reset(), gem5::branch_prediction::DefaultBTB::reset(), gem5::o3::DependencyGraph< gem5::RefCountingPtr >::reset(), gem5::ActivityRecorder::reset(), gem5::sinic::Device::reset(), gem5::statistics::DistStor::reset(), gem5::statistics::DataWrapVec< VectorStandardDeviation, VectorDistInfoProxy >::reset(), gem5::MemChecker::reset(), gem5::statistics::HistStor::reset(), gem5::VirtIODeviceBase::reset(), gem5::statistics::Vector2dBase< Vector2d, StatStor >::reset(), gem5::ComputeUnit::resetRegisterPool(), gem5::o3::InstructionQueue::resetState(), gem5::ruby::garnet::NetworkLink::resetStats(), gem5::ruby::Sequencer::resetStats(), gem5::ruby::AbstractController::resetStats(), gem5::ruby::garnet::GarnetNetwork::resetStats(), gem5::ruby::garnet::Router::resetStats(), gem5::ruby::GPUCoalescer::resetStats(), gem5::ruby::NetDest::resize(), tlm_utils::instance_specific_extension_container::resize(), sc_dt::scfx_rep::resize_to(), gem5::statistics::VectorBase< Vector, StatStor >::result(), gem5::statistics::VectorProxy< Stat >::result(), gem5::statistics::UnaryNode< Op >::result(), gem5::statistics::BinaryNode< Op >::result(), gem5::statistics::SumNode< Op >::result(), gem5::AtagRev::rev(), gem5::AtagCore::rootdev(), gem5::MinorCPU::roundRobinPriority(), gem5::Gicv3Distributor::route(), gem5::RiscvRTC::RTC::RTC(), gem5::ruby::RubyPort::RubyPort(), gem5::SimulatorThreads::runUntilLocalExit(), gem5::sinic::Device::rxKick(), gem5::StackDistCalc::sanityCheckTree(), gem5::CowDiskImage::save(), gem5::AQLRingBuffer::saveHostDispAddr(), gem5::prefetch::SBOOE::SBOOE(), sc_dt::sc_lv_base::sc_lv_base(), SC_MODULE(), sc_core::sc_trace(), sc_core::sc_trace< bool >(), sc_core::sc_trace< sc_dt::sc_logic >(), sc_dt::scfx_mant::scfx_mant(), sc_dt::scfx_rep::scfx_rep(), gem5::fastmodel::SCGIC::SCGIC(), gem5::schedGetaffinityFunc(), gem5::BaseGlobalEvent::schedule(), gem5::BaseGlobalEvent::scheduled(), gem5::ruby::garnet::NetworkInterface::scheduleOutputPort(), gem5::BaseCPU::scheduleSimpointsInstStop(), gem5::VectorRegisterFile::scheduleWriteOperandsFromLoad(), gem5::fastmodel::ScxEvsCortexA76< Types >::ScxEvsCortexA76(), gem5::fastmodel::ScxEvsCortexR52< Types >::ScxEvsCortexR52(), gem5::memory::qos::TurnaroundPolicyIdeal::selectBusState(), gem5::selectFunc(), gem5::minor::SelfStallingPipeline< ElemType, ReportTraits, BubbleTraits >::SelfStallingPipeline(), gem5::o3::LSQ::LSQRequest::sendFragmentToTranslation(), gem5::ps2::TouchKit::sendTouchKit(), gem5::Iris::ISA::serialize(), gem5::Iris::Interrupts::serialize(), gem5::NoMaliGpu::serialize(), gem5::PM4PacketProcessor::serialize(), gem5::MemPools::serialize(), gem5::ArmISA::PMU::serialize(), gem5::Plic::serialize(), gem5::EtherSwitch::Interface::PortFifo::serialize(), gem5::SDMAEngine::serialize(), gem5::CpuLocalTimer::serialize(), gem5::PacketFifo::serialize(), gem5::ArmSemihosting::serialize(), gem5::GenericTimer::serialize(), gem5::CxxConfigManager::serialize(), gem5::loader::SymbolTable::serialize(), gem5::sinic::Device::serialize(), gem5::AMDGPUVM::serialize(), gem5::PciDevice::serialize(), gem5::BaseCPU::serialize(), gem5::DistIface::RecvScheduler::serialize(), gem5::RegisterBank< BankByteOrder >::RegisterLBuf< 0x80 >::serialize(), gem5::GicV2::serialize(), gem5::VirtIODeviceBase::serialize(), gem5::PollQueue::service(), gem5::bloom_filter::MultiBitSel::set(), gem5::WaitClass::set(), sc_dt::scfx_rep::set(), sc_dt::sc_uint_base::set(), sc_dt::sc_int_base::set(), sc_dt::sc_unsigned::set(), sc_dt::sc_signed::set(), sc_dt::scfx_rep::set_bin(), sc_dt::sc_fxnum::set_bit(), sc_dt::sc_subref_r< X >::set_cword(), sc_dt::sc_concref_r< X, Y >::set_cword(), sc_dt::scfx_rep::set_hex(), sc_dt::scfx_rep::set_oct(), sc_core::sc_spawn_options::set_sensitivity(), sc_dt::scfx_rep::set_slice(), sc_dt::sc_fxnum::set_slice(), sc_gem5::TraceFile::set_time_unit(), sc_dt::sc_bv_base::set_word(), sc_dt::sc_subref_r< X >::set_word(), sc_dt::sc_concref_r< X, Y >::set_word(), gem5::VecPredRegContainer< size, T >::setBits(), gem5::OutputDirectory::setDirectory(), gem5::ObjectMatch::setExpression(), Gem5SystemC::ControlExtension::setInstruction(), gem5::ruby::WriteMask::setInvertedMask(), gem5::DistEtherLink::Link::setLocalInt(), gem5::ruby::WriteMask::setMask(), gem5::RegisterManager::setParent(), gem5::X86ISA::Interrupts::setReg(), gem5::fastmodel::FastmodelRemoteGDB::AArch64GdbRegCache::setRegs(), gem5::MipsISA::RemoteGDB::MipsGdbRegCache::setRegs(), gem5::ArmISA::RemoteGDB::AArch64GdbRegCache::setRegs(), gem5::RiscvISA::RemoteGDB::Riscv32GdbRegCache::setRegs(), gem5::RiscvISA::RemoteGDB::Riscv64GdbRegCache::setRegs(), gem5::EtherLink::Link::setRxInt(), gem5::X86ISA::setThreadArea32Func(), gem5::EtherLink::Link::setTxInt(), TwoDifferentMatRegs::SetUp(), gem5::ArmISA::Crypto::sha256Op(), sc_dt::scfx_rep::shift_left(), sc_dt::scfx_rep::shift_right(), gem5::ruby::Topology::shortest_path_to_node(), gem5::X86ISA::I82094AA::signalInterrupt(), simd_modified_imm(), gem5::SimpleCache::SimpleCache(), gem5::branch_prediction::SimpleIndirectPredictor::SimpleIndirectPredictor(), gem5::ruby::SimpleNetwork::SimpleNetwork(), gem5::SkewedAssociative::skew(), gem5::ruby::NetDest::smallestElement(), gem5::ruby::Set::smallestElement(), gem5::AtagSerial::sn(), gem5::GicV2::softInt(), gem5::LinearSystem::solve(), gem5::o3::Decode::sortInsts(), gem5::o3::Rename::sortInsts(), gem5::o3::IEW::sortInsts(), sc_gem5::spawnWork(), gem5::o3::Rename::squash(), gem5::o3::Decode::squash(), gem5::branch_prediction::TAGEBase::squash(), QTIsaac< ALPHA >::srand(), gem5::StaticInst::srcRegIdx(), gem5::o3::DynInst::srcRegIdx(), gem5::MemChecker::startRead(), gem5::MemTraceProbe::startup(), gem5::ThermalModel::startup(), gem5::MemChecker::startWrite(), gem5::minor::LSQ::StoreBuffer::step(), gem5::guest_abi::enable_if_t< std::is_integral_v< Integer > &&(sizeof(Integer)< sizeof(uint32_t))> >::store(), gem5::guest_abi::Result< Aapcs32, Integer, typename std::enable_if_t< std::is_integral_v< Integer > &&(sizeof(Integer)==sizeof(uint32_t))> >::store(), gem5::guest_abi::Result< Aapcs32, Integer, typename std::enable_if_t< std::is_integral_v< Integer > &&(sizeof(Integer)==sizeof(uint64_t))> >::store(), gem5::guest_abi::Result< Aapcs32, Float, typename std::enable_if_t< std::is_floating_point_v< Float > > >::store(), gem5::guest_abi::enable_if_t< std::is_integral_v< Integer > &&(sizeof(Integer)<=8)> >::store(), gem5::guest_abi::Result< Aapcs64, HA, typename std::enable_if_t< IsAapcs64HxaV< HA > > >::store(), gem5::guest_abi::Result< Aapcs64, Composite, typename std::enable_if_t< IsAapcs64CompositeV< Composite > &&!IsAapcs64HxaV< Composite > > >::store(), gem5::guest_abi::Result< Aapcs32Vfp, HA, typename std::enable_if_t< IsAapcs32HomogeneousAggregateV< HA > > >::store(), gem5::ArmISA::Crypto::store1Reg(), gem5::o3::StoreSet::StoreSet(), gem5::statistics::ConstVectorNode< T >::str(), gem5::ruby::SubBlock::SubBlock(), gem5::ArmISA::SveIndexedMemSV< RegElemType, MemElemType, MicroopType, FirstFaultWritebackMicroopType >::SveIndexedMemSV(), gem5::ArmISA::SveIndexedMemVI< RegElemType, MemElemType, MicroopType, FirstFaultWritebackMicroopType >::SveIndexedMemVI(), gem5::ArmISA::SveLdStructSI< Element, MicroopLdMemType, MicroopDeIntrlvType >::SveLdStructSI(), gem5::ArmISA::SveLdStructSS< Element, MicroopLdMemType, MicroopDeIntrlvType >::SveLdStructSS(), gem5::ArmISA::SveStStructSI< Element, MicroopStMemType, MicroopIntrlvType >::SveStStructSI(), gem5::ArmISA::SveStStructSS< Element, MicroopStMemType, MicroopIntrlvType >::SveStStructSS(), gem5::branch_prediction::TAGEBase::tagePredict(), gem5::FALRU::tagsInit(), gem5::o3::IEW::takeOverFrom(), gem5::BaseCPU::takeOverFrom(), gem5::ruby::TBEStorage::TBEStorage(), gem5::TCPIface::TCPIface(), gem5::VirtIO9PDiod::terminateDiod(), gem5::fastmodel::SCGIC::Terminator::Terminator(), TEST(), sc_dt::sc_uint_base::test(), sc_dt::sc_int_base::test(), TEST_F(), TEST_P(), gem5::ruby::testAndRead(), gem5::ruby::testAndReadMask(), gem5::ruby::testAndWrite(), gem5::branch_prediction::MultiperspectivePerceptron::ThreadData::ThreadData(), gem5::trace::ArmNativeTrace::ThreadState::ThreadState(), gem5::AtomicSimpleCPU::tick(), gem5::o3::Fetch::tick(), gem5::TimeBuffer< gem5::o3::FetchStruct >::TimeBuffer(), gem5::GenericTimerMem::timerCtrlRead(), gem5::GenericTimerMem::timerCtrlWrite(), gem5::AddrRange::to_string(), gem5::compression::Base::toChunks(), gem5::compression::DictionaryCompressor< uint64_t >::toDictionaryEntry(), gem5::ruby::Topology::Topology(), gem5::LinearEquation::toStr(), gem5::statistics::VectorBase< Vector, StatStor >::total(), gem5::statistics::VectorProxy< Stat >::total(), gem5::statistics::Vector2dBase< Vector2d, StatStor >::total(), gem5::statistics::ConstVectorNode< T >::total(), gem5::statistics::UnaryNode< Op >::total(), gem5::statistics::BinaryNode< Op >::total(), gem5::statistics::SumNode< Op >::total(), gem5::MinorCPU::totalInsts(), gem5::o3::CPU::totalInsts(), gem5::MinorCPU::totalOps(), gem5::o3::CPU::totalOps(), gem5::branch_prediction::TournamentBP::TournamentBP(), gem5::memory::AbstractMemory::trackLoadLocked(), gem5::branch_prediction::MultiperspectivePerceptron::train(), gem5::PacketQueue::trySatisfyFunctional(), gem5::SerialLink::SerialLinkRequestPort::trySatisfyFunctional(), gem5::Bridge::BridgeRequestPort::trySatisfyFunctional(), gem5::Packet::trySatisfyFunctional(), gem5::ruby::RubyPort::trySendRetries(), gem5::EtherBus::txDone(), gem5::ruby::PersistentTable::typeOfSmallest(), gem5::branch_prediction::MultiperspectivePerceptron::uncondBranch(), gem5::CxxConfigManager::unRename(), gem5::NoMaliGpu::unserialize(), gem5::PM4PacketProcessor::unserialize(), gem5::ArmISA::PMU::unserialize(), gem5::MemPools::unserialize(), gem5::X86ISA::I82094AA::unserialize(), gem5::Plic::unserialize(), gem5::Root::unserialize(), gem5::EtherSwitch::Interface::PortFifo::unserialize(), gem5::DVFSHandler::unserialize(), gem5::SDMAEngine::unserialize(), gem5::CpuLocalTimer::unserialize(), gem5::EmulationPageTable::unserialize(), gem5::MemState::unserialize(), gem5::PacketFifo::unserialize(), gem5::ArmSemihosting::unserialize(), gem5::memory::PhysicalMemory::unserialize(), gem5::GenericTimer::unserialize(), gem5::sinic::Device::unserialize(), gem5::AMDGPUVM::unserialize(), gem5::loader::SymbolTable::unserialize(), gem5::PciDevice::unserialize(), gem5::BaseCPU::unserialize(), gem5::DistIface::RecvScheduler::unserialize(), gem5::GicV2::unserialize(), gem5::RegisterBank< BankByteOrder >::RegisterLBuf< 0x80 >::unserialize(), gem5::VirtIODeviceBase::unserialize(), gem5::trace::X86NativeTrace::ThreadState::update(), gem5::trace::ArmNativeTrace::ThreadState::update(), sc_core::sc_signal_rv< W >::update(), gem5::Gicv3Distributor::update(), gem5::branch_prediction::MultiperspectivePerceptron::update(), tlm::tlm_generic_payload::update_extensions_from(), tlm::tlm_generic_payload::update_original_from(), gem5::branch_prediction::MultiperspectivePerceptron::ThreadData::updateAcyclic(), gem5::ArmISA::PMU::updateAllCounters(), gem5::branch_prediction::TAGEBase::updateGHist(), gem5::branch_prediction::MultiperspectivePerceptronTAGE::updateHistories(), gem5::branch_prediction::TAGEBase::updateHistories(), gem5::Plic::updateInt(), gem5::VGic::updateIntState(), gem5::ArmV8KvmCPU::updateKvmState(), gem5::updateKvmStateFPUCommon(), gem5::o3::DynInst::updateMiscRegs(), gem5::ruby::TimerTable::updateNext(), gem5::branch_prediction::MultiperspectivePerceptronTAGE::updatePartial(), gem5::branch_prediction::MPP_TAGE::updatePathAndGlobalHistory(), gem5::branch_prediction::TAGE_SC_L_TAGE::updatePathAndGlobalHistory(), gem5::TLBCoalescer::updatePhysAddresses(), gem5::VegaTLBCoalescer::updatePhysAddresses(), gem5::trace::TarmacTracerRecordV8::TraceRegEntryV8::updatePred(), gem5::ruby::PerfectSwitch::updatePriorityGroups(), gem5::GicV2::updateRunPri(), gem5::ArmV8KvmCPU::updateThreadContext(), gem5::updateThreadContextFPUCommon(), gem5::X86KvmCPU::updateThreadContextMSRs(), gem5::StackDistCalc::updateTree(), gem5::trace::TarmacTracerRecordV8::TraceRegEntryV8::updateVec(), gem5::ActivityRecorder::validate(), gem5::Checker< gem5::RefCountingPtr >::validateExecution(), gem5::Memoizer< int, gem5::ThreadContext *, bool, bool, TCR, ExceptionLevel >::validateMemoizer(), gem5::o3::Rename::validInsts(), gem5::statistics::VectorBase< Vector, StatStor >::value(), sc_core::sc_port_b< tlm_nonblocking_put_if< T > >::vbind(), sc_gem5::VcdTraceFile::VcdTraceFile(), sc_dt::vec_add_small(), sc_dt::vec_complement(), sc_dt::vec_copy(), sc_dt::vec_sub_small(), sc_dt::vec_to_char(), gem5::VirtQueue::VirtQueue(), gem5::Gicv3CPUInterface::virtualDropPriority(), gem5::Gicv3CPUInterface::virtualHighestActivePriority(), gem5::statistics::Text::visit(), gem5::ArmISA::VldMultOp::VldMultOp(), gem5::ArmISA::VldMultOp64::VldMultOp64(), gem5::ArmISA::VldSingleOp::VldSingleOp(), gem5::ArmISA::VldSingleOp64::VldSingleOp64(), gem5::ArmISA::VstMultOp::VstMultOp(), gem5::ArmISA::VstMultOp64::VstMultOp64(), gem5::ArmISA::VstSingleOp::VstSingleOp(), gem5::ArmISA::VstSingleOp64::VstSingleOp64(), sc_core::sc_prim_channel::wait(), sc_core::sc_module::wait(), gem5::o3::MemDepUnit::wakeDependents(), gem5::WalkCache::WalkCache(), gem5::VectorRegisterFile::waveExecuteInst(), gem5::Wavefront::Wavefront(), tlm::circular_buffer< RSP >::write(), gem5::CowDiskImage::write(), gem5::Gicv3Redistributor::write(), gem5::Gicv3Distributor::write(), gem5::Gcn3ISA::ScalarOperand< DataType, Const, sizeof(DataType)/sizeof(VecElemU32) >::write(), gem5::VegaISA::ScalarOperand< DataType, Const, sizeof(DataType)/sizeof(VecElemU32) >::write(), gem5::VirtQueue::VirtRing< struct vring_used_elem >::write(), gem5::CowDiskImage::writeback(), gem5::o3::IEW::writebackInsts(), gem5::Packet::writeData(), gem5::Plic::writeEnable(), gem5::X86ISA::intelmp::FloatingPointer::writeOut(), gem5::X86ISA::intelmp::ConfigTable::writeOut(), gem5::X86ISA::smbios::SMBiosTable::writeOut(), gem5::writeOutString(), gem5::X86ISA::writePackedMem(), gem5::Plic::writePriority(), gem5::SDMAEngine::writeReadData(), gem5::X86ISA::E820Table::writeTo(), gem5::VGic::writeVCpu(), gem5::writevFunc(), gem5::PixelConverter::writeWord(), gem5::X86IdeController::X86IdeController(), gem5::X86ISA::X86MicroopBase::X86MicroopBase(), gem5::X86ISA::Cmos::X86RTC::X86RTC(), sc_dt::sc_unsigned_subref_r::xor_reduce(), sc_dt::sc_signed_subref_r::xor_reduce(), sc_dt::sc_unsigned::xor_reduce(), sc_dt::sc_signed::xor_reduce(), gem5::statistics::DataWrapVec2d< Derived, Vector2dInfoProxy >::ysubname(), gem5::statistics::DataWrapVec2d< Derived, Vector2dInfoProxy >::ysubnames(), gem5::HorizontalSlice< ElemType, Container, FromTile >::zero(), gem5::VerticalSlice< ElemType, Container, FromTile >::zero(), gem5::Tile< ElemType, Container >::zero(), gem5::statistics::VectorBase< Vector, StatStor >::zero(), gem5::statistics::VectorDistBase< VectorAverageDeviation, AvgSampleStor >::zero(), gem5::statistics::Formula::zero(), gem5::ArmISA::ISA::zeroSveVecRegUpperPart(), gem5::BaseGlobalEvent::~BaseGlobalEvent(), gem5::ruby::CacheMemory::~CacheMemory(), gem5::CheckTable::~CheckTable(), gem5::ComputeUnit::~ComputeUnit(), gem5::CowDiskImage::~CowDiskImage(), gem5::ruby::DirectoryMemory::~DirectoryMemory(), gem5::o3::DynInst::~DynInst(), gem5::minor::Execute::~Execute(), gem5::o3::FUPool::~FUPool(), gem5::IniFile::~IniFile(), tlm_utils::instance_specific_extension_container::~instance_specific_extension_container(), gem5::o3::MemDepUnit::MemDepEntry::~MemDepEntry(), gem5::PollQueue::~PollQueue(), gem5::ProtocolTester::~ProtocolTester(), gem5::RubyDirectedTester::~RubyDirectedTester(), gem5::RubyTester::~RubyTester(), gem5::minor::LSQ::SplitDataRequest::~SplitDataRequest(), and gem5::TimeBuffer< gem5::o3::FetchStruct >::~TimeBuffer().

◆ i16i64

Bitfield<55, 52> gem5::ArmISA::i16i64

Definition at line 224 of file misc_types.hh.

◆ i8i32

Bitfield<39, 36> gem5::ArmISA::i8i32

Definition at line 226 of file misc_types.hh.

◆ i8mm

Bitfield< 47, 44 > gem5::ArmISA::i8mm

Definition at line 90 of file misc_types.hh.

◆ iCacheLineSize

gem5::ArmISA::iCacheLineSize

Definition at line 697 of file misc_types.hh.

◆ id

Bitfield<33> gem5::ArmISA::id

Definition at line 305 of file misc_types.hh.

Referenced by gem5::ArmISA::PMU::addEventProbe(), gem5::memory::qos::MemCtrl::addRequestor(), gem5::ArmISA::PMU::addSoftwareIncrementEvent(), gem5::Request::createMemManagement(), gem5::ArmV8KvmCPU::dump(), gem5::memory::qos::MemCtrl::escalateQueues(), gem5::RegClassOps::flatten(), gem5::RegClass::flatten(), gem5::ruby::garnet::flit::flit(), gem5::ArmISA::PMU::getCounter(), gem5::BaseKvmCPU::getOneReg(), gem5::AMDGPUDevice::getSDMAById(), gem5::ruby::IDToInt(), gem5::o3::LSQUnit::init(), gem5::ArmProcess32::initState(), gem5::ArmProcess64::initState(), gem5::Iris::ThreadContext::installBp(), gem5::Iris::ThreadContext::instanceRegistryChanged(), gem5::ruby::intToID(), sc_dt::sc_fxval_fast::is_inf(), sc_dt::sc_fxval_fast::is_nan(), sc_dt::sc_fxval_fast::is_neg(), sc_dt::sc_fxnum_fast::is_neg(), sc_dt::sc_fxval_fast::is_normal(), sc_dt::sc_fxnum_fast::is_normal(), sc_dt::sc_fxval_fast::is_zero(), sc_dt::sc_fxnum_fast::is_zero(), gem5::Dueler::isSample(), gem5::memory::qos::MemCtrl::logRequest(), gem5::memory::qos::MemCtrl::logResponse(), gem5::System::lookupRequestorId(), gem5::PM4PacketProcessor::newQueue(), gem5::ruby::garnet::OutVcState::OutVcState(), gem5::TrafficGen::parseConfig(), sc_dt::sc_fxval_fast::print(), sc_dt::sc_fxnum_fast::print(), sc_core::sc_report::register_id(), tlm_utils::passthrough_target_socket_tagged_b< MODULE, 32, tlm::tlm_base_protocol_types, sc_core::SC_ZERO_OR_MORE_BOUND >::register_transport_dbg(), gem5::ArmISA::PMU::registerEvent(), gem5::ruby::RubySystem::registerRequestorIDs(), sc_core::sc_report_handler::report(), gem5::minor::Fetch1::FetchRequest::reportData(), gem5::BaseRemoteGDB::scheduleTrapEvent(), gem5::ThreadState::setContextId(), gem5::Iris::ThreadContext::setContextId(), gem5::BaseKvmCPU::setOneReg(), gem5::Dueler::setSample(), gem5::CacheBlk::setSrcRequestorId(), gem5::ThreadState::setThreadId(), gem5::Iris::ThreadContext::setThreadId(), gem5::Request::setVirt(), gem5::ruby::SimpleNetwork::SimpleNetwork(), gem5::BaseCPU::taskId(), gem5::Request::taskId(), gem5::System::Threads::thread(), sc_dt::scfx_rep::to_double(), and gem5::PM4PacketProcessor::unmapQueues().

◆ idc

Bitfield<7> gem5::ArmISA::idc

Definition at line 495 of file misc_types.hh.

◆ ide

Bitfield<15> gem5::ArmISA::ide

Definition at line 501 of file misc_types.hh.

Referenced by gem5::IGbE::TxDescCache::pktComplete().

◆ ids

Bitfield<39, 36> gem5::ArmISA::ids

Definition at line 178 of file misc_types.hh.

Referenced by gem5::Iris::ThreadContext::extractResourceMap().

◆ iesb

Bitfield<15, 12> gem5::ArmISA::iesb

Definition at line 184 of file misc_types.hh.

◆ ifsc

Bitfield< 5, 0 > gem5::ArmISA::ifsc

Definition at line 765 of file misc_types.hh.

◆ il

Bitfield< 25 > gem5::ArmISA::il

Definition at line 61 of file misc_types.hh.

◆ illegalExecution

Bitfield<61> gem5::ArmISA::illegalExecution

Definition at line 62 of file types.hh.

◆ imm

Bitfield<7, 0> gem5::ArmISA::imm

Definition at line 132 of file types.hh.

Referenced by AArch64AArch32SystemAccessTrap(), gem5::ArmISA::BigFpMemImmOp::BigFpMemImmOp(), gem5::ArmISA::BigFpMemLitOp::BigFpMemLitOp(), gem5::ArmISA::BigFpMemPostOp::BigFpMemPostOp(), gem5::ArmISA::BigFpMemPreOp::BigFpMemPreOp(), gem5::ArmISA::BigFpMemRegOp::BigFpMemRegOp(), gem5::ImmOp64::generateDisassembly(), gem5::ArmISAInst::TmeImmOp64::generateDisassembly(), gem5::MsrImmOp::generateDisassembly(), gem5::RegRegRegImmOp64::generateDisassembly(), gem5::ImmOp::generateDisassembly(), gem5::RegImmOp::generateDisassembly(), gem5::MiscRegImmOp64::generateDisassembly(), gem5::RegImmRegOp::generateDisassembly(), gem5::RegRegRegImmOp::generateDisassembly(), gem5::ArmISA::PredIntOp::generateDisassembly(), gem5::RegRegImmOp::generateDisassembly(), gem5::RegImmRegShiftOp::generateDisassembly(), mcrMrc15Trap(), mcrrMrrc15Trap(), gem5::MiscRegImmOp64::miscRegImm(), gem5::OperandInfo::OperandInfo(), gem5::ArmISA::PairMemOp::PairMemOp(), gem5::ArmISA::ArmStaticInst::printDataInst(), gem5::ArmISA::ArmStaticInst::softwareBreakpoint32(), sveDecodePredCount(), sveDisasmPredCountImm(), sveExpandFpImmAddSub(), sveExpandFpImmMaxMin(), sveExpandFpImmMul(), vfpFpToFixed(), vfpSFixedToFpD(), vfpSFixedToFpS(), vfpUFixedToFpD(), and vfpUFixedToFpS().

◆ immed11_0

Bitfield<11, 0> gem5::ArmISA::immed11_0

Definition at line 136 of file types.hh.

◆ immed23_0

Bitfield<23, 0> gem5::ArmISA::immed23_0

Definition at line 146 of file types.hh.

◆ immed7_0

Bitfield<7, 0> gem5::ArmISA::immed7_0

Definition at line 137 of file types.hh.

◆ immedHi11_8

Bitfield<11, 8> gem5::ArmISA::immedHi11_8

Definition at line 139 of file types.hh.

◆ immedLo3_0

Bitfield<3, 0> gem5::ArmISA::immedLo3_0

Definition at line 140 of file types.hh.

◆ imo

Bitfield<4> gem5::ArmISA::imo

Definition at line 335 of file misc_types.hh.

Referenced by gem5::ArmISA::Interrupts::checkInterrupts(), and gem5::ArmISA::Interrupts::getInterrupt().

◆ implementer

Bitfield<31, 24> gem5::ArmISA::implementer

Definition at line 824 of file misc_types.hh.

◆ instBits

uint32_t gem5::ArmISA::instBits

Definition at line 87 of file types.hh.

◆ intdis

Bitfield<23, 22> gem5::ArmISA::intdis

Definition at line 879 of file misc_types.hh.

◆ interptCtrlPresent

Bitfield<23> gem5::ArmISA::interptCtrlPresent

Definition at line 690 of file misc_types.hh.

◆ intRegClass

constexpr RegClass gem5::ArmISA::intRegClass
inlineconstexpr
Initial value:
=
RegClass(IntRegClass, IntRegClassName, int_reg::NumRegs, debug::IntRegs).
ops(intRegClassOps).
needsFlattening()

Definition at line 173 of file int.hh.

Referenced by gem5::PowerProcess::argsInit(), gem5::guest_abi::enable_if_t< std::is_integral_v< Integer > &&(sizeof(Integer)<=sizeof(uint32_t)) > >::get(), gem5::guest_abi::enable_if_t< std::is_integral_v< Integer > &&(sizeof(Integer)<=8)> >::get(), gem5::guest_abi::Argument< Aapcs32, Composite, typename std::enable_if_t< IsAapcs32CompositeV< Composite > > >::get(), gem5::guest_abi::Argument< Aapcs64, Composite, typename std::enable_if_t< IsAapcs64CompositeV< Composite > &&!IsAapcs64HxaV< Composite > > >::get(), gem5::Iris::ThreadContext::getIntRegRscId(), gem5::MipsISA::RemoteGDB::MipsGdbRegCache::getRegs(), gem5::RiscvISA::RemoteGDB::Riscv32GdbRegCache::getRegs(), gem5::RiscvISA::RemoteGDB::Riscv64GdbRegCache::getRegs(), gem5::guest_abi::Result< Aapcs32, Composite, typename std::enable_if_t< IsAapcs32CompositeV< Composite > > >::prepare(), gem5::trace::TarmacParserRecord::TarmacParserRecordEvent::process(), gem5::ArmISA::HTMCheckpoint::restore(), gem5::ArmISA::HTMCheckpoint::save(), gem5::Iris::ThreadContext::setIntRegFlat(), gem5::MipsISA::RemoteGDB::MipsGdbRegCache::setRegs(), gem5::RiscvISA::RemoteGDB::Riscv32GdbRegCache::setRegs(), gem5::RiscvISA::RemoteGDB::Riscv64GdbRegCache::setRegs(), gem5::ArmISAInst::Tstart64::Tstart64(), gem5::ArmISAInst::Ttest64::Ttest64(), gem5::trace::ArmNativeTrace::ThreadState::update(), gem5::ArmV8KvmCPU::updateKvmState(), gem5::ArmKvmCPU::updateTCStateCore(), gem5::ArmV8KvmCPU::updateThreadContext(), and gem5::ArmISA::int_reg::x().

◆ intRegClassOps

constexpr IntRegClassOps gem5::ArmISA::intRegClassOps
inlineconstexpr

Definition at line 171 of file int.hh.

◆ INTRLVREG0

const int gem5::ArmISA::INTRLVREG0 = NumVecV8ArchRegs + NumVecSpecialRegs

Definition at line 88 of file vec.hh.

Referenced by gem5::ArmISA::SveLdStructSI< Element, MicroopLdMemType, MicroopDeIntrlvType >::SveLdStructSI(), gem5::ArmISA::SveLdStructSS< Element, MicroopLdMemType, MicroopDeIntrlvType >::SveLdStructSS(), gem5::ArmISA::SveStStructSI< Element, MicroopStMemType, MicroopIntrlvType >::SveStStructSI(), and gem5::ArmISA::SveStStructSS< Element, MicroopStMemType, MicroopIntrlvType >::SveStStructSS().

◆ INTRLVREG1

const int gem5::ArmISA::INTRLVREG1 = INTRLVREG0 + 1

Definition at line 89 of file vec.hh.

◆ INTRLVREG2

const int gem5::ArmISA::INTRLVREG2 = INTRLVREG0 + 2

Definition at line 90 of file vec.hh.

◆ INTRLVREG3

const int gem5::ArmISA::INTRLVREG3 = INTRLVREG0 + 3

Definition at line 91 of file vec.hh.

◆ ioe

Bitfield<8> gem5::ArmISA::ioe

Definition at line 496 of file misc_types.hh.

◆ ips

Bitfield< 34, 32 > gem5::ArmISA::ips

Definition at line 564 of file misc_types.hh.

◆ ir0

gem5::ArmISA::ir0

Definition at line 656 of file misc_types.hh.

◆ ir1

Bitfield<3,2> gem5::ArmISA::ir1

Definition at line 657 of file misc_types.hh.

◆ ir2

Bitfield<5,4> gem5::ArmISA::ir2

Definition at line 658 of file misc_types.hh.

◆ ir3

Bitfield<7,6> gem5::ArmISA::ir3

Definition at line 659 of file misc_types.hh.

◆ ir4

Bitfield<9,8> gem5::ArmISA::ir4

Definition at line 660 of file misc_types.hh.

◆ ir5

Bitfield<11,10> gem5::ArmISA::ir5

Definition at line 661 of file misc_types.hh.

◆ ir6

Bitfield<13,12> gem5::ArmISA::ir6

Definition at line 662 of file misc_types.hh.

◆ ir7

Bitfield<15,14> gem5::ArmISA::ir7

Definition at line 663 of file misc_types.hh.

◆ irgn0

Bitfield< 9, 8 > gem5::ArmISA::irgn0

Definition at line 553 of file misc_types.hh.

◆ irgn1

Bitfield< 25, 24 > gem5::ArmISA::irgn1

Definition at line 560 of file misc_types.hh.

◆ irq

Bitfield<1> gem5::ArmISA::irq

Definition at line 387 of file misc_types.hh.

Referenced by gem5::trace::TarmacParserRecord::advanceTrace(), gem5::LupioTTY::lupioTTYUpdateIRQ(), gem5::fastmodel::PL330::PL330(), gem5::KvmKernelGic::setIntState(), and gem5::KvmVM::setIRQLine().

◆ isMisc

Bitfield<32> gem5::ArmISA::isMisc

Definition at line 85 of file types.hh.

◆ iss

Bitfield< 19, 0 > gem5::ArmISA::iss

Definition at line 729 of file misc_types.hh.

Referenced by gem5::ArmISA::ArmStaticInst::checkAdvSIMDOrFPEnabled32(), gem5::ArmISA::ArmStaticInst::checkForWFxTrap32(), gem5::ArmISA::ArmStaticInst::checkForWFxTrap64(), gem5::memory::DRAMSim2Wrapper::extractConfig(), gem5::MiscRegOp64::generateTrap(), mcrMrc14TrapToHyp(), mcrMrc15TrapToHyp(), mcrMrcIssExtract(), mcrrMrrc15TrapToHyp(), gem5::ArmISA::ArmStaticInst::smeAccessTrap(), and gem5::Random::unserialize().

◆ isv

Bitfield< 24 > gem5::ArmISA::isv

Definition at line 743 of file misc_types.hh.

◆ it1

Bitfield<26, 25> gem5::ArmISA::it1

Definition at line 56 of file misc_types.hh.

Referenced by gem5::FutexMap::requeue().

◆ it2

Bitfield<15, 10> gem5::ArmISA::it2

Definition at line 63 of file misc_types.hh.

Referenced by gem5::FutexMap::requeue().

◆ itd

Bitfield<7> gem5::ArmISA::itd

Definition at line 439 of file misc_types.hh.

Referenced by getRestoredITBits().

◆ itstate

Bitfield<55, 48> gem5::ArmISA::itstate

Definition at line 70 of file types.hh.

Referenced by gem5::ArmISA::ArmFault::invoke32(), and gem5::ArmISA::ArmFault::invoke64().

◆ itstateCond

Bitfield<55, 52> gem5::ArmISA::itstateCond

Definition at line 71 of file types.hh.

◆ itstateMask

Bitfield<51, 48> gem5::ArmISA::itstateMask

Definition at line 72 of file types.hh.

◆ ixc

Bitfield<4> gem5::ArmISA::ixc

Definition at line 494 of file misc_types.hh.

◆ ixe

Bitfield<12> gem5::ArmISA::ixe

Definition at line 500 of file misc_types.hh.

◆ j

Bitfield<24> gem5::ArmISA::j

Definition at line 57 of file misc_types.hh.

Referenced by gem5::memory::DRAMInterface::activateBank(), gem5::ruby::Histogram::add(), gem5::ArmISA::Crypto::aesInvMixColumns(), gem5::ArmISA::Crypto::aesMixColumns(), gem5::Aapcs32Vfp::State::allocate(), gem5::ruby::Set::broadcast(), gem5::FALRU::CacheTracking::check(), gem5::ruby::garnet::SwitchAllocator::check_for_wakeup(), gem5::ScheduleStage::checkRfOperandReadComplete(), gem5::MipsISA::ISA::clear(), gem5::ruby::CacheMemory::clearLockedAll(), gem5::ruby::Profiler::collateStats(), gem5::ruby::garnet::GarnetNetwork::collateStats(), gem5::ruby::garnet::Router::collateStats(), gem5::ArmISA::WatchPoint::compareAddress(), gem5::MemChecker::completeRead(), gem5::branch_prediction::MultiperspectivePerceptron::computeOutput(), gem5::BaseTags::computeStats(), gem5::LdsState::countBankConflicts(), gem5::crc32(), gem5::ruby::Topology::createLinks(), gem5::compression::DictionaryCompressor< uint64_t >::decompress(), gem5::ComputeUnit::dispWorkgroup(), gem5::memory::DRAMInterface::doBurstAccess(), gem5::ObjectMatch::domatch(), gem5::trace::Logger::dump(), gem5::dumpFpuCommon(), SimpleLTInitiator2_dmi::end_of_simulation(), SimpleLTInitiator1_dmi::end_of_simulation(), SimpleLTInitiator_ext::end_of_simulation(), gem5::FetchStage::exec(), gem5::FetchUnit::exec(), gem5::ScheduleStage::exec(), gem5::ruby::Topology::extend_shortest_path(), gem5::FetchStage::FetchStage(), gem5::ScheduleStage::fillDispatchList(), gem5::minor::FUPipeline::FUPipeline(), gem5::o3::FUPool::FUPool(), sc_dt::scfx_rep::get_slice(), sc_dt::sc_fxnum::get_slice(), gem5::ruby::NetDest::getAllDest(), gem5::branch_prediction::MultiperspectivePerceptron::PATH::getHash(), gem5::branch_prediction::MultiperspectivePerceptron::GHISTPATH::getHash(), gem5::branch_prediction::MultiperspectivePerceptron::SGHISTPATH::getHash(), gem5::ruby::RubyPrefetcher::getPrefetchEntry(), gem5::ArmISA::RemoteGDB::AArch64GdbRegCache::getRegs(), gem5::branch_prediction::TAGE_SC_L_TAGE_8KB::handleAllocAndUReset(), gem5::branch_prediction::TAGE_SC_L_TAGE_64KB::handleAllocAndUReset(), gem5::branch_prediction::MPP_TAGE::handleUReset(), gem5::branch_prediction::TAGE_SC_L_TAGE::handleUReset(), gem5::branch_prediction::TAGEBase::handleUReset(), gem5::ComputeUnit::hasDispResources(), gem5::ruby::CacheMemory::htmAbortTransaction(), gem5::ruby::CacheMemory::htmCommitTransaction(), gem5::FetchStage::init(), gem5::ScheduleStage::init(), gem5::ruby::CacheMemory::init(), gem5::Plic::PlicRegisters::init(), gem5::FALRU::CacheTracking::init(), gem5::branch_prediction::MPP_StatisticalCorrector::initBias(), gem5::branch_prediction::StatisticalCorrector::initBias(), gem5::branch_prediction::StatisticalCorrector::initGEHLTable(), gem5::branch_prediction::MultiperspectivePerceptron::insertModhistSpec(), gem5::branch_prediction::MultiperspectivePerceptron::insertModpathSpec(), gem5::branch_prediction::MultiperspectivePerceptron::ThreadData::insertRecency(), SimpleLTInitiator2_dmi::invalidate_direct_mem_ptr(), SimpleLTInitiator1_dmi::invalidate_direct_mem_ptr(), SimpleLTInitiator_ext::invalidate_direct_mem_ptr(), gem5::ruby::VIPERCoalescer::issueRequest(), gem5::DmaThread::issueStoreOps(), gem5::GpuWavefront::issueStoreOps(), gem5::memory::qos::MemCtrl::logRequest(), gem5::memory::qos::MemCtrl::logResponse(), gem5::ArmISA::MacroVFPMemOp::MacroVFPMemOp(), gem5::memory::DRAMInterface::minBankPrep(), sc_dt::sc_fxnum::operator()(), sc_dt::sc_unsigned::operator()(), sc_dt::sc_fxnum_fast::operator()(), sc_dt::sc_signed::operator()(), gem5::TrafficGen::parseConfig(), gem5::ruby::Profiler::ProfilerStats::PerRequestTypeMachineTypeStats::PerRequestTypeMachineTypeStats(), gem5::PortTerminator::PortTerminator(), gem5::ruby::NetDest::print(), gem5::ruby::CacheMemory::print(), gem5::ruby::printSorted(), sc_dt::sc_fxnum::range(), sc_dt::sc_unsigned::range(), sc_dt::sc_fxnum_fast::range(), sc_dt::sc_signed::range(), gem5::SimpleDisk::read(), gem5::ruby::CacheMemory::recordCacheContents(), gem5::memory::qos::MemCtrl::MemCtrlStats::regStats(), gem5::BaseXBar::regStats(), gem5::System::regStats(), gem5::ComputeUnit::releaseWFsFromBarrier(), gem5::ScheduleStage::reserveResources(), gem5::ruby::Sequencer::resetStats(), gem5::ruby::garnet::InputUnit::resetStats(), gem5::ruby::GPUCoalescer::resetStats(), sc_dt::scfx_rep::resize(), gem5::ScheduleStage::scheduleRfDestOperands(), gem5::ScheduleStage::ScheduleStage(), sc_dt::scfx_rep::set_slice(), sc_dt::sc_fxnum::set_slice(), gem5::branch_prediction::MultiperspectivePerceptron::ACYCLIC::setBitRequirements(), gem5::branch_prediction::MultiperspectivePerceptron::BLURRYPATH::setBitRequirements(), gem5::ArmISA::RemoteGDB::AArch64GdbRegCache::setRegs(), TwoDifferentMatRegs::SetUp(), gem5::ruby::NetDest::smallestElement(), syncVecElemsToRegs(), syncVecRegsToElems(), TEST(), TEST_F(), gem5::branch_prediction::MultiperspectivePerceptron::ThreadData::ThreadData(), gem5::branch_prediction::MultiperspectivePerceptron::train(), gem5::branch_prediction::MultiperspectivePerceptron::update(), gem5::branch_prediction::MultiperspectivePerceptronTAGE::updateHistories(), gem5::ArmV8KvmCPU::updateKvmState(), gem5::ruby::PerfectSwitch::updatePriorityGroups(), gem5::ArmV8KvmCPU::updateThreadContext(), sc_dt::vec_from_char(), gem5::statistics::Text::visit(), gem5::ruby::CacheMemory::~CacheMemory(), gem5::ComputeUnit::~ComputeUnit(), gem5::Shader::~Shader(), and gem5::System::~System().

◆ jscvt

Bitfield< 15, 12 > gem5::ArmISA::jscvt

Definition at line 96 of file misc_types.hh.

◆ l1IndexPolicy

Bitfield<15,14> gem5::ArmISA::l1IndexPolicy

Definition at line 699 of file misc_types.hh.

◆ l2rstDISABLE_monitor

Bitfield<31> gem5::ArmISA::l2rstDISABLE_monitor

Definition at line 693 of file misc_types.hh.

◆ lbn

Bitfield< 19, 16 > gem5::ArmISA::lbn

Definition at line 847 of file misc_types.hh.

◆ len

Bitfield< 3, 0 > gem5::ArmISA::len

Definition at line 502 of file misc_types.hh.

Referenced by gem5::ArmISA::RemoteGDB::acc(), gem5::ArmISA::ArmStaticInst::extendReg64(), gem5::ArmISA::ISA::getCurSmeVecLenInBits(), gem5::ArmISA::ISA::getCurSveVecLenInBits(), gem5::ArmISA::Decoder::setSmeLen(), and gem5::ArmISA::Decoder::setSveLen().

◆ lo

Bitfield<19, 16> gem5::ArmISA::lo

Definition at line 165 of file misc_types.hh.

Referenced by gem5::trace::TarmacParserRecord::advanceTrace(), and gem5::RiscvISA::mulhu_64().

◆ loadOp

Bitfield<20> gem5::ArmISA::loadOp

Definition at line 127 of file types.hh.

◆ lookUpMiscReg

std::vector< struct MiscRegLUTEntry > gem5::ArmISA::lookUpMiscReg

Definition at line 1627 of file misc.hh.

Referenced by canReadCoprocReg(), canWriteCoprocReg(), checkFaultAccessAArch64SysReg(), gem5::ArmISA::ISA::clear(), gem5::ArmISA::ISA::flattenMiscIndex(), gem5::ArmISA::ISA::getMiscIndices(), gem5::ArmV8KvmCPU::getSysRegMap(), gem5::ArmISA::ISA::InitReg(), preUnflattenMiscReg(), gem5::ArmISA::ISA::readMiscReg(), gem5::ArmISA::ISA::readMiscRegNoEffect(), gem5::ArmISA::ISA::readMiscRegReset(), gem5::ArmISA::ISA::setMiscReg(), gem5::ArmISA::ISA::setMiscRegNoEffect(), snsBankedIndex(), gem5::ArmISA::ISA::snsBankedIndex64(), and gem5::ArmISA::ISA::unserialize().

◆ lpae

Bitfield< 11 > gem5::ArmISA::lpae

Definition at line 482 of file misc_types.hh.

Referenced by gem5::ArmISA::TlbEntry::setAttributes().

◆ lrcpc

Bitfield<23, 20> gem5::ArmISA::lrcpc

Definition at line 136 of file misc_types.hh.

◆ lsm

Bitfield<11, 8> gem5::ArmISA::lsm

Definition at line 185 of file misc_types.hh.

◆ lsv

Bitfield<4, 3> gem5::ArmISA::lsv

Definition at line 866 of file misc_types.hh.

◆ ltcoproc

Bitfield<11, 8> gem5::ArmISA::ltcoproc

Definition at line 202 of file types.hh.

◆ ltopcode11_8

Bitfield<11, 8> gem5::ArmISA::ltopcode11_8

Definition at line 196 of file types.hh.

◆ ltopcode15

Bitfield<15> gem5::ArmISA::ltopcode15

Definition at line 195 of file types.hh.

◆ ltopcode4

Bitfield<4> gem5::ArmISA::ltopcode4

Definition at line 199 of file types.hh.

◆ ltopcode7_4

Bitfield<7, 4> gem5::ArmISA::ltopcode7_4

Definition at line 198 of file types.hh.

◆ ltopcode7_6

Bitfield<7, 6> gem5::ArmISA::ltopcode7_6

Definition at line 197 of file types.hh.

◆ ltrd

Bitfield<11, 8> gem5::ArmISA::ltrd

Definition at line 201 of file types.hh.

◆ m

Bitfield<0> gem5::ArmISA::m

Definition at line 451 of file misc_types.hh.

◆ m5Func

Bitfield<15, 8> gem5::ArmISA::m5Func

Definition at line 156 of file types.hh.

◆ mask

Bitfield< 28, 24 > gem5::ArmISA::mask

Definition at line 63 of file pcstate.hh.

Referenced by addPAC(), gem5::ArmISA::ISA::addressTranslation(), gem5::ArmISA::ISA::addressTranslation64(), auth(), gem5::ArmISA::MMU::checkPermissions(), gem5::ArmISA::MMU::checkPermissions64(), gem5::ArmISA::TableWalker::checkVAddrSizeFaultAArch64(), gem5::ArmISA::WatchPoint::compareAddress(), sc_dt::sc_uint_subref_r::concat_get_ctrl(), sc_dt::sc_int_subref_r::concat_get_ctrl(), sc_dt::sc_uint_base::concat_get_ctrl(), sc_dt::sc_int_base::concat_get_ctrl(), sc_dt::sc_unsigned::concat_get_ctrl(), sc_dt::sc_signed::concat_get_ctrl(), sc_dt::sc_uint_subref_r::concat_get_data(), sc_dt::sc_int_subref_r::concat_get_data(), sc_dt::sc_uint_base::concat_get_data(), sc_dt::sc_int_base::concat_get_data(), sc_dt::sc_unsigned::concat_get_data(), sc_dt::sc_signed::concat_get_data(), sc_dt::sc_signed::concat_get_uint64(), gem5::ArmISA::ArmStaticInst::cpsrWriteByInstr(), gem5::RiscvISA::TLB::doTranslate(), gem5::ArmISA::ArmStaticInst::encoding(), gem5::ArmISA::ArmStaticInst::extendReg64(), finishVfp(), fixFpDFpSDest(), fixFpSFpDDest(), gem5::ArmISA::ISA::initializeMiscRegMetadata(), gem5::ArmISA::SelfDebug::isDebugEnabledForEL32(), gem5::ArmISA::SelfDebug::isDebugEnabledForEL64(), maskTaggedAddr(), gem5::ArmISA::Stage2LookUp::mergeTe(), mul62x62(), MultiSocketSimpleSwitchAT::MultiSocketSimpleSwitchAT(), sc_dt::sc_uint_subref::operator=(), sc_dt::sc_int_subref::operator=(), gem5::ArmISA::V7LPageTableOps::pageMask(), gem5::ArmISA::V8PageTableOps4k::pageMask(), gem5::ArmISA::V8PageTableOps16k::pageMask(), gem5::ArmISA::V8PageTableOps64k::pageMask(), gem5::ArmISA::MiscRegLUTEntryInitializer::rao(), gem5::ArmISA::MiscRegLUTEntryInitializer::raz(), gem5::ArmISA::ISA::readMiscRegNoEffect(), gem5::ArmISA::MiscRegLUTEntryInitializer::res0(), gem5::ArmISA::MiscRegLUTEntryInitializer::res1(), gem5::ArmISA::SelfDebug::setDebugMask(), gem5::ArmISA::ISA::setMiscReg(), gem5::ArmISA::ArmStaticInst::shiftReg64(), gem5::ArmISA::ArmStaticInst::spsrWriteByInstr(), stripPAC(), gem5::ArmISA::Interrupts::takeInt(), sc_dt::sc_concatref::to_uint64(), gem5::ArmISA::MMU::translateFs(), gem5::ArmISA::MMU::translateMmuOn(), gem5::ArmISA::MMU::translateSe(), gem5::RiscvISA::TLB::translateWithTLB(), gem5::ArmISA::TlbEntry::updateAttributes(), vcvtFpFpH(), vcvtFpHFp(), sc_dt::vec_to_char(), vfpFpToFixed(), gem5::ArmISA::PageTableOps::walkMask(), gem5::X86ISA::ACPI::RXSDT< uint64_t >::writeBuf(), sc_dt::sc_uint_base::xor_reduce(), and sc_dt::sc_int_base::xor_reduce().

◆ matRegClass

constexpr RegClass gem5::ArmISA::matRegClass
inlineconstexpr
Initial value:
=
RegClass(MatRegClass, MatRegClassName, NumMatrixRegs, debug::MatRegs).
ops(matRegClassOps).
regType<MatRegContainer>()

Definition at line 92 of file mat.hh.

Referenced by gem5::ArmISA::ISA::copyRegsFrom(), gem5::X86ISA::ISA::ISA(), gem5::PowerISA::ISA::ISA(), gem5::RiscvISA::ISA::ISA(), gem5::MipsISA::ISA::ISA(), gem5::SparcISA::ISA::ISA(), and gem5::ArmISA::ISA::ISA().

◆ matRegClassOps

TypedRegClassOps<ArmISA::MatRegContainer> gem5::ArmISA::matRegClassOps
inlinestatic

Definition at line 90 of file mat.hh.

◆ MaxPhysAddrRange

const unsigned gem5::ArmISA::MaxPhysAddrRange = 52

Definition at line 73 of file pagetable.hh.

Referenced by gem5::ArmSystem::ArmSystem().

◆ MaxSmeVecLenInBits

constexpr unsigned gem5::ArmISA::MaxSmeVecLenInBits = 2048
constexpr

Definition at line 476 of file types.hh.

◆ MaxSmeVecLenInBytes

constexpr unsigned gem5::ArmISA::MaxSmeVecLenInBytes = MaxSmeVecLenInBits >> 3
constexpr

Definition at line 484 of file types.hh.

◆ MaxSmeVecLenInDWords

constexpr unsigned gem5::ArmISA::MaxSmeVecLenInDWords = MaxSmeVecLenInBits >> 6
constexpr

Definition at line 486 of file types.hh.

◆ MaxSmeVecLenInWords

constexpr unsigned gem5::ArmISA::MaxSmeVecLenInWords = MaxSmeVecLenInBits >> 5
constexpr

Definition at line 485 of file types.hh.

◆ MaxSveVecLenInBits

constexpr unsigned gem5::ArmISA::MaxSveVecLenInBits = 2048
constexpr

Definition at line 464 of file types.hh.

◆ MaxSveVecLenInBytes

constexpr unsigned gem5::ArmISA::MaxSveVecLenInBytes = MaxSveVecLenInBits >> 3
constexpr

Definition at line 469 of file types.hh.

◆ MaxSveVecLenInDWords

constexpr unsigned gem5::ArmISA::MaxSveVecLenInDWords = MaxSveVecLenInBits >> 6
constexpr

Definition at line 471 of file types.hh.

◆ MaxSveVecLenInWords

constexpr unsigned gem5::ArmISA::MaxSveVecLenInWords = MaxSveVecLenInBits >> 5
constexpr

Definition at line 470 of file types.hh.

◆ md

Bitfield<12> gem5::ArmISA::md

Definition at line 909 of file misc_types.hh.

Referenced by gem5::ArmISA::SelfDebug::testDebug().

◆ mdbgen

Bitfield<15> gem5::ArmISA::mdbgen

Definition at line 886 of file misc_types.hh.

◆ mediaOpcode

Bitfield<24, 20> gem5::ArmISA::mediaOpcode

Definition at line 93 of file types.hh.

◆ mf

Bitfield<15> gem5::ArmISA::mf

Definition at line 906 of file misc_types.hh.

◆ mi

Bitfield<14> gem5::ArmISA::mi

Definition at line 907 of file misc_types.hh.

Referenced by gem5::trace::InstPBTrace::getInstRecord().

◆ miocnce

Bitfield<38> gem5::ArmISA::miocnce

Definition at line 300 of file misc_types.hh.

◆ miscOpcode

Bitfield<7, 4> gem5::ArmISA::miscOpcode

Definition at line 105 of file types.hh.

◆ miscRegClass

constexpr RegClass gem5::ArmISA::miscRegClass
inlineconstexpr
Initial value:
=
RegClass(MiscRegClass, MiscRegClassName, NUM_MISCREGS,
debug::MiscRegs).
ops(miscRegClassOps)

Definition at line 2810 of file misc.hh.

Referenced by gem5::Iris::ThreadContext::getMiscRegRscId(), gem5::ArmISA::ISA::ISA(), and gem5::trace::TarmacTracerRecord::mergeCCEntry().

◆ miscRegClassOps

MiscRegClassOps gem5::ArmISA::miscRegClassOps
inlinestatic

Definition at line 2808 of file misc.hh.

◆ miscRegName

const char* const gem5::ArmISA::miscRegName[]

Definition at line 1748 of file misc.hh.

Referenced by gem5::Gicv3Registers::copyCpuRegister(), gem5::ArmV8KvmCPU::dump(), gem5::ArmKvmCPU::dumpKvmStateCoProc(), gem5::ArmKvmCPU::dumpKvmStateCore(), gem5::ArmKvmCPU::dumpKvmStateVFP(), gem5::getMiscRegName(), gem5::ArmV8KvmCPU::getSysRegMap(), gem5::ArmISA::ArmStaticInst::printMiscReg(), gem5::ArmISA::DummyISADevice::readMiscReg(), gem5::ArmISA::PMU::readMiscReg(), gem5::ArmISA::ISA::readMiscReg(), gem5::GenericTimer::readMiscReg(), gem5::Gicv3CPUInterface::readMiscReg(), gem5::GenericTimerISA::readMiscReg(), gem5::ArmISA::PMU::readMiscRegInt(), gem5::ArmISA::ISA::readMiscRegNoEffect(), gem5::ArmISA::MiscRegClassOps::regName(), gem5::ArmISA::ISA::serialize(), gem5::ArmISA::DummyISADevice::setMiscReg(), gem5::ArmISA::PMU::setMiscReg(), gem5::ArmISA::ISA::setMiscReg(), gem5::GenericTimer::setMiscReg(), gem5::Gicv3CPUInterface::setMiscReg(), gem5::GenericTimerISA::setMiscReg(), gem5::ArmISA::ISA::setMiscRegNoEffect(), gem5::ArmISA::ISA::unserialize(), gem5::ArmKvmCPU::updateKvmStateCoProc(), gem5::ArmKvmCPU::updateKvmStateVFP(), gem5::trace::TarmacTracerRecord::TraceRegEntry::updateMisc(), gem5::ArmKvmCPU::updateTCStateCoProc(), and gem5::ArmKvmCPU::updateTCStateVFP().

◆ mode

Bitfield<4, 0> gem5::ArmISA::mode

Definition at line 74 of file misc_types.hh.

Referenced by gem5::accessFunc(), gem5::accessImpl(), gem5::ArmISA::ISA::addressTranslation(), gem5::ArmISA::ISA::addressTranslation64(), badMode(), badMode32(), gem5::ArmSemihosting::callOpen(), gem5::ArmISA::MMU::checkPAN(), gem5::RiscvISA::TLB::checkPermissions(), gem5::ArmISA::MMU::checkPermissions(), gem5::ArmISA::MMU::checkPermissions64(), gem5::ArmISA::TLB::checkPromotion(), gem5::chmodFunc(), gem5::OutputDirectory::create(), gem5::ArmSemihosting::FileBase::create(), gem5::PMP::createAddrfault(), gem5::RiscvISA::TLB::createPagefault(), gem5::VegaISA::GpuTLB::createPagefault(), decodeMrsMsrBankedReg(), gem5::RiscvISA::TLB::doTranslate(), EndBitUnion(), gem5::faccessatFunc(), gem5::fallocateFunc(), gem5::ArmISA::MMU::faultPAN(), gem5::fchmodatFunc(), gem5::fchmodFunc(), gem5::BaseMMU::finalizePhysical(), gem5::ArmISA::MMU::finalizePhysical(), gem5::o3::Fetch::FetchTranslation::finish(), gem5::DataTranslation< ExecContextPtr >::finish(), gem5::SETranslatingPortProxy::fixupRange(), flattenIntRegModeIndex(), fp16_add(), fp16_compare_eq(), fp16_compare_ge(), fp16_compare_gt(), fp16_compare_un(), fp16_cvtf(), fp16_div(), fp16_mul(), fp16_muladd(), fp16_process_NaN(), fp16_process_NaNs(), fp16_process_NaNs3(), fp16_round(), fp16_round_(), fp16_scale(), fp16_sqrt(), fp16_unpack(), fp32_add(), fp32_compare_eq(), fp32_compare_ge(), fp32_compare_gt(), fp32_compare_un(), fp32_cvtf(), fp32_div(), fp32_mul(), fp32_muladd(), fp32_process_NaN(), fp32_process_NaNs(), fp32_process_NaNs3(), fp32_round(), fp32_round_(), fp32_scale(), fp32_sqrt(), fp32_unpack(), fp64_add(), fp64_compare_eq(), fp64_compare_ge(), fp64_compare_gt(), fp64_compare_un(), fp64_cvtf(), fp64_div(), fp64_mul(), fp64_muladd(), fp64_process_NaN(), fp64_process_NaNs(), fp64_process_NaNs3(), fp64_round(), fp64_round_(), fp64_scale(), fp64_sqrt(), fp64_unpack(), fplibCompare(), fplibConvert(), fplibMax(), fplibMin(), fplibMulX(), fplibRecipEstimate(), fplibRecipStepFused(), fplibRecpX(), fplibRoundInt(), fplibRSqrtEstimate(), fplibRSqrtStepFused(), fplibTrigSMul(), gem5::ArmISA::FpRegImmOp::FpRegImmOp(), gem5::ArmISA::FpRegRegImmOp::FpRegRegImmOp(), gem5::ArmISA::FpRegRegOp::FpRegRegOp(), gem5::ArmISA::FpRegRegRegCondOp::FpRegRegRegCondOp(), gem5::ArmISA::FpRegRegRegImmOp::FpRegRegRegImmOp(), gem5::ArmISA::FpRegRegRegOp::FpRegRegRegOp(), gem5::ArmISA::FpRegRegRegRegOp::FpRegRegRegRegOp(), gem5::Shader::functionalTLBAccess(), gem5::RiscvISA::TLB::getMemPriv(), gem5::ArmISA::MMU::getResultTe(), gem5::ArmSemihosting::getSTDIO(), gem5::ArmISA::MMU::getTableWalker(), gem5::ArmISA::MMU::getTE(), gem5::ArmISA::MMU::getTlb(), gem5::BaseMMU::getTlb(), gem5::VegaISA::GpuTLB::handleFuncTranslationReturn(), gem5::VegaISA::GpuTLB::handleTranslationReturn(), gem5::ruby::HTMSequencer::htmCallback(), illegalExceptionReturn(), gem5::TimingSimpleCPU::initiateMemAMO(), gem5::TimingSimpleCPU::initiateMemRead(), gem5::VegaISA::Walker::WalkerState::initState(), gem5::ArmISA::ArmFault::invoke64(), gem5::RiscvISA::TLB::lookup(), gem5::ArmISA::TLB::lookup(), gem5::ArmISA::MMU::lookup(), gem5::mkdiratFunc(), gem5::mkdirFunc(), gem5::mkdirImpl(), gem5::mknodatFunc(), gem5::mknodFunc(), gem5::mknodImpl(), gem5::RawDiskImage::open(), gem5::OutputDirectory::open(), gem5::openatFunc(), gem5::FDArray::openFile(), gem5::openFunc(), gem5::ArmSemihosting::File::openImpl(), opModeIsH(), opModeIsT(), opModeToEL(), gem5::VegaISA::Walker::WalkerState::pageFault(), gem5::VegaISA::GpuTLB::pagingProtectionChecks(), gem5::ArmISA::PairMemOp::PairMemOp(), gem5::TrafficGen::parseConfig(), gem5::PMP::pmpCheck(), gem5::trace::TarmacTracerRecordV8::TraceInstEntryV8::print(), gem5::trace::TarmacTracerRecord::TraceInstEntry::print(), gem5::ArmISA::int_reg::regInMode(), gem5::ArmISA::MMU::s1PermBits64(), SC_MODULE(), sc_core::sc_set_stop_mode(), gem5::ArmSemihosting::FileBase::serialize(), gem5::FileFDEntry::setFileMode(), gem5::System::setMemoryMode(), setVfpMicroFlags(), gem5::VegaISA::Walker::startFunctional(), gem5::VegaISA::Walker::startTiming(), gem5::ArmISA::SelfDebug::testDebug(), gem5::ArmISA::MMU::testTranslation(), gem5::ArmISA::MMU::testWalk(), gem5::BaseMMU::MMUTranslationGen::translate(), gem5::RiscvISA::TLB::translate(), gem5::Iris::TLB::translateAtomic(), gem5::BaseMMU::translateAtomic(), gem5::SparcISA::TLB::translateAtomic(), gem5::ArmISA::MMU::translateAtomic(), gem5::ArmISA::MMU::translateComplete(), gem5::ArmISA::MMU::translateFs(), gem5::PowerISA::MMU::translateFunctional(), gem5::Iris::MMU::translateFunctional(), gem5::SparcISA::MMU::translateFunctional(), gem5::ArmISA::MMU::translateFunctional(), gem5::BaseMMU::translateFunctional(), gem5::SparcISA::TLB::translateFunctional(), gem5::ArmISA::MMU::translateMmuOff(), gem5::ArmISA::MMU::translateMmuOn(), gem5::ArmISA::MMU::translateSe(), gem5::Iris::TLB::translateTiming(), gem5::BaseMMU::translateTiming(), gem5::SparcISA::TLB::translateTiming(), gem5::ArmISA::MMU::translateTiming(), gem5::ArmISA::TableWalker::Stage2Walk::translateTiming(), gem5::RiscvISA::TLB::translateWithTLB(), gem5::TranslatingPortProxy::tryMemsetBlob(), gem5::TranslatingPortProxy::tryOnBlob(), gem5::TranslatingPortProxy::tryReadBlob(), gem5::TranslatingPortProxy::tryWriteBlob(), unknownMode(), unknownMode32(), gem5::FDArray::unserialize(), gem5::trace::TarmacTracerRecord::TraceRegEntry::updateInt(), gem5::WriteAllocator::updateMode(), vcvtFpFpH(), gem5::VegaISA::Walker::WalkerState::walkStateMachine(), and gem5::TimingSimpleCPU::writeMem().

◆ moe

Bitfield<5, 2> gem5::ArmISA::moe

Definition at line 893 of file misc_types.hh.

◆ mp

Bitfield<11> gem5::ArmISA::mp

Definition at line 910 of file misc_types.hh.

Referenced by gem5::GlobalMemPipeline::acqCoalescerToken(), gem5::GlobalMemPipeline::coalescerReady(), gem5::ScalarMemPipeline::exec(), gem5::GlobalMemPipeline::exec(), gem5::ScheduleStage::fillDispatchList(), and gem5::GlobalMemPipeline::outstandingReqsCheck().

◆ mpam

Bitfield<43, 40> gem5::ArmISA::mpam

Definition at line 195 of file misc_types.hh.

◆ ms

Bitfield<10> gem5::ArmISA::ms

Definition at line 911 of file misc_types.hh.

◆ n

gem5::ArmISA::n

Definition at line 513 of file misc_types.hh.

Referenced by sc_core::sc_port_b< tlm_nonblocking_put_if< T > >::_gem5Interface(), gem5::ThermalModel::addNode(), gem5::memory::NVMInterface::addRankToRankDelay(), gem5::memory::DRAMInterface::addRankToRankDelay(), gem5::ruby::TBETable< MiscNode_TBE >::areNSlotsAvailable(), gem5::ruby::TBEStorage::areNSlotsAvailable(), gem5::ruby::MessageBuffer::areNSlotsAvailable(), gem5::ruby::MN_TBEStorage< RetryEntry >::areNSlotsAvailable(), gem5::atomic_read(), gem5::atomic_write(), sc_dt::b_or_assign_(), tlm::circular_buffer< RSP >::buf_free(), tlm::circular_buffer< RSP >::buf_write(), gem5::ceilLog2(), gem5::DVFSHandler::clkPeriodAtPerfLevel(), sc_dt::convert_to_bin(), gem5::memory::NVMInterface::doBurstAccess(), gem5::ThermalModel::doStep(), SimpleLTInitiator2_dmi::end_of_simulation(), SimpleLTInitiator1_dmi::end_of_simulation(), SimpleLTInitiator_ext::end_of_simulation(), gem5::MathExpr::eval(), gem5::CxxConfigManager::findObject(), sc_dt::sc_bitref_r< T >::get_bit(), sc_dt::sc_subref_r< X >::get_bit(), sc_dt::sc_subref_r< X >::get_cword(), sc_dt::sc_subref_r< X >::get_word(), gem5::ThermalResistor::getEquation(), gem5::ThermalDomain::getEquation(), gem5::ThermalCapacitor::getEquation(), gem5::ThermalModel::getTemperature(), gem5::MathExpr::getVariables(), gem5::ArmISA::V7LPageTableOps::index(), SimpleLTInitiator2_dmi::invalidate_direct_mem_ptr(), SimpleLTInitiator1_dmi::invalidate_direct_mem_ptr(), SimpleLTInitiator_ext::invalidate_direct_mem_ptr(), gem5::ruby::NetDest::isEqual(), gem5::isPowerOf2(), sc_gem5::listContains(), sc_dt::sc_proxy< sc_bv_base >::lrotate(), sc_dt::lrotate(), sc_dt::scfx_rep::lshift(), SwitchingFiber::main(), tlm::tlm_fifo< RSP >::nb_peek(), sc_gem5::Object::Object(), sc_core::sc_vector_iter< Element, AccessPolicy >::operator+(), sc_core::sc_vector_iter< Element, AccessPolicy >::operator+=(), sc_core::sc_vector_iter< Element, AccessPolicy >::operator-(), sc_core::sc_vector_iter< Element, AccessPolicy >::operator-=(), sc_dt::operator==(), sc_dt::sc_proxy< sc_bv_base >::operator>>(), sc_core::sc_port_b< tlm_nonblocking_put_if< T > >::operator[](), sc_core::sc_vector_iter< Element, AccessPolicy >::operator[](), sc_dt::operator^(), gem5::stl_helpers::opExtract_impl::opExtractPrimDisp(), gem5::MathExpr::parse(), gem5::ArmISA::TableWalker::pendingChange(), gem5::linux::printk(), gem5::StackDistCalc::printStack(), gem5::prlimitFunc(), gem5::ArmISA::TableWalker::processWalkLPAE(), sc_dt::quantization_scfx_rep(), gem5::X86ISA::smbios::SMBiosStructure::readString(), gem5::ArmISA::HTMCheckpoint::restore(), gem5::RiscvRTC::RTC::RTC(), gem5::statistics::DistBase< Distribution, DistStor >::sample(), gem5::statistics::DistProxy< Stat >::sample(), gem5::statistics::SparseHistBase< SparseHistogram, SparseHistStor >::sample(), gem5::ArmISA::HTMCheckpoint::save(), sc_dt::scfx_string::scfx_string(), sc_dt::sc_bitref< X >::set_bit(), gem5::fastmodel::CortexR52::set_evs_param(), gem5::fastmodel::CortexA76::set_evs_param(), gem5::fastmodel::CortexR52Cluster::set_evs_param(), gem5::fastmodel::CortexA76Cluster::set_evs_param(), sc_dt::scfx_rep::set_hex(), sc_dt::scfx_rep::set_oct(), sc_dt::sc_subref_r< X >::set_word(), gem5::ThermalDomain::setNode(), gem5::ThermalReference::setNode(), gem5::X86ISA::smbios::SMBiosStructure::setString(), sc_dt::scfx_rep::shift_left(), sc_dt::scfx_rep::shift_right(), gem5::ThermalModel::startup(), testPredicate(), sc_dt::sc_proxy< sc_bv_base >::to_string(), gem5::MathExpr::toStr(), gem5::DVFSHandler::voltageAtPerfLevel(), sc_core::wait(), gem5::X86ISA::Cmos::X86RTC::X86RTC(), sc_dt::sc_uint_base::xor_reduce(), and sc_dt::sc_int_base::xor_reduce().

◆ nEt

Bitfield<6> gem5::ArmISA::nEt

Definition at line 382 of file misc_types.hh.

◆ nmea

Bitfield<20> gem5::ArmISA::nmea

Definition at line 367 of file misc_types.hh.

◆ nmfi

Bitfield<27> gem5::ArmISA::nmfi

Definition at line 397 of file misc_types.hh.

Referenced by gem5::ArmISA::ArmStaticInst::cpsrWriteByInstr().

◆ nos0

Bitfield<24> gem5::ArmISA::nos0

Definition at line 645 of file misc_types.hh.

◆ nos1

Bitfield<25> gem5::ArmISA::nos1

Definition at line 646 of file misc_types.hh.

◆ nos2

Bitfield<26> gem5::ArmISA::nos2

Definition at line 647 of file misc_types.hh.

◆ nos3

Bitfield<27> gem5::ArmISA::nos3

Definition at line 648 of file misc_types.hh.

◆ nos4

Bitfield<28> gem5::ArmISA::nos4

Definition at line 649 of file misc_types.hh.

◆ nos5

Bitfield<29> gem5::ArmISA::nos5

Definition at line 650 of file misc_types.hh.

◆ nos6

Bitfield<30> gem5::ArmISA::nos6

Definition at line 651 of file misc_types.hh.

◆ nos7

Bitfield<31> gem5::ArmISA::nos7

Definition at line 652 of file misc_types.hh.

◆ ns

Bitfield< 18 > gem5::ArmISA::ns

Definition at line 388 of file misc_types.hh.

Referenced by EL2Enabled(), gem5::Gicv3CPUInterface::generateSGI(), gem5::ArmISA::TLB::insert(), isSecureBelowEL3(), sc_gem5::Process::needsStart(), gem5::pseudo_inst::quiesceNs(), gem5::Gicv3Redistributor::sendSGI(), snsBankedIndex(), gem5::ArmISA::ISA::snsBankedIndex64(), and gem5::BaseKvmTimer::ticksFromHostNs().

◆ ns0

Bitfield<18> gem5::ArmISA::ns0

Definition at line 643 of file misc_types.hh.

◆ ns1

Bitfield<19> gem5::ArmISA::ns1

Definition at line 644 of file misc_types.hh.

◆ nsasedis

Bitfield<15> gem5::ArmISA::nsasedis

Definition at line 345 of file misc_types.hh.

◆ nsd

Bitfield<28> gem5::ArmISA::nsd

Definition at line 901 of file misc_types.hh.

◆ nsd32dis

Bitfield<14> gem5::ArmISA::nsd32dis

Definition at line 346 of file misc_types.hh.

◆ nsi

Bitfield<30> gem5::ArmISA::nsi

Definition at line 899 of file misc_types.hh.

◆ nsp

Bitfield<27> gem5::ArmISA::nsp

Definition at line 902 of file misc_types.hh.

◆ nss

Bitfield<26> gem5::ArmISA::nss

Definition at line 903 of file misc_types.hh.

◆ nsu

Bitfield<25> gem5::ArmISA::nsu

Definition at line 904 of file misc_types.hh.

◆ nTT

Bitfield<2> gem5::ArmISA::nTT

Definition at line 839 of file misc_types.hh.

◆ ntwe

Bitfield<18> gem5::ArmISA::ntwe

Definition at line 417 of file misc_types.hh.

◆ ntwi

Bitfield<16> gem5::ArmISA::ntwi

Definition at line 420 of file misc_types.hh.

◆ NumArgumentRegs

constexpr size_t gem5::ArmISA::NumArgumentRegs = 4
inlineconstexpr

Definition at line 645 of file int.hh.

◆ NumArgumentRegs64

constexpr size_t gem5::ArmISA::NumArgumentRegs64 = 8
inlineconstexpr

Definition at line 646 of file int.hh.

◆ numCPUs

Bitfield<25,24> gem5::ArmISA::numCPUs

Definition at line 691 of file misc_types.hh.

◆ NumFloatV7ArchRegs

const int gem5::ArmISA::NumFloatV7ArchRegs = 64

Definition at line 78 of file vec.hh.

◆ NumMatrixRegs

const int gem5::ArmISA::NumMatrixRegs = 1

Definition at line 88 of file mat.hh.

◆ NumVecElemPerNeonVecReg

constexpr unsigned gem5::ArmISA::NumVecElemPerNeonVecReg = 4
constexpr

Definition at line 59 of file vec.hh.

Referenced by gem5::ArmISA::RemoteGDB::AArch64GdbRegCache::getRegs(), and gem5::ArmISA::RemoteGDB::AArch64GdbRegCache::setRegs().

◆ NumVecElemPerVecReg

constexpr unsigned gem5::ArmISA::NumVecElemPerVecReg = MaxSveVecLenInWords
constexpr

Definition at line 61 of file vec.hh.

Referenced by gem5::GPUDynInst::allLanesZero(), gem5::GPUDynInst::GPUDynInst(), gem5::ruby::GPUCoalescer::makeRequest(), gem5::VectorRegisterFile::printReg(), gem5::GPUDynInst::printStatusVector(), gem5::GPUDynInst::resetEntireStatusVector(), syncVecElemsToRegs(), and syncVecRegsToElems().

◆ NumVecIntrlvRegs

const int gem5::ArmISA::NumVecIntrlvRegs = 4

Definition at line 82 of file vec.hh.

◆ NumVecPredRegs

const int gem5::ArmISA::NumVecPredRegs = 18

Definition at line 84 of file vec.hh.

Referenced by gem5::ArmISA::HTMCheckpoint::reset(), gem5::ArmISA::HTMCheckpoint::restore(), and gem5::ArmISA::HTMCheckpoint::save().

◆ NumVecRegs

const int gem5::ArmISA::NumVecRegs = NumVecV8ArchRegs + NumVecSpecialRegs + NumVecIntrlvRegs

Definition at line 83 of file vec.hh.

Referenced by gem5::ArmISA::HTMCheckpoint::reset(), gem5::ArmISA::HTMCheckpoint::restore(), gem5::ArmISA::HTMCheckpoint::save(), syncVecElemsToRegs(), and syncVecRegsToElems().

◆ NumVecSpecialRegs

const int gem5::ArmISA::NumVecSpecialRegs = 8

Definition at line 81 of file vec.hh.

◆ NumVecV7ArchRegs

const int gem5::ArmISA::NumVecV7ArchRegs = 16

Definition at line 79 of file vec.hh.

Referenced by gem5::trace::ArmNativeTrace::ThreadState::update().

◆ NumVecV8ArchRegs

const int gem5::ArmISA::NumVecV8ArchRegs = 32

Definition at line 80 of file vec.hh.

Referenced by gem5::ArmISA::RemoteGDB::AArch64GdbRegCache::getRegs(), gem5::ArmISA::RemoteGDB::AArch64GdbRegCache::setRegs(), gem5::ArmISA::VldMultOp64::VldMultOp64(), gem5::ArmISA::VldSingleOp64::VldSingleOp64(), gem5::ArmISA::VstMultOp64::VstMultOp64(), and gem5::ArmISA::VstSingleOp64::VstSingleOp64().

◆ nv

Bitfield< 42 > gem5::ArmISA::nv

Definition at line 181 of file misc_types.hh.

◆ nv1

Bitfield<43> gem5::ArmISA::nv1

Definition at line 296 of file misc_types.hh.

◆ nv2

Bitfield<45> gem5::ArmISA::nv2

Definition at line 294 of file misc_types.hh.

◆ nz

gem5::ArmISA::nz

Definition at line 52 of file misc_types.hh.

Referenced by fplibFPToFixedJS(), and testPredicate().

◆ ofc

Bitfield<2> gem5::ArmISA::ofc

Definition at line 492 of file misc_types.hh.

◆ ofe

Bitfield<10> gem5::ArmISA::ofe

Definition at line 498 of file misc_types.hh.

◆ offset

Bitfield<23, 0> gem5::ArmISA::offset

Definition at line 144 of file types.hh.

Referenced by gem5::_llseekFunc(), gem5::IdeController::Channel::accessBMI(), gem5::IdeController::Channel::accessCommand(), gem5::IdeController::Channel::accessControl(), gem5::IniFile::Section::add(), gem5::IniFile::add(), gem5::loader::DtbFile::addBootData(), gem5::prefetch::STeMS::ActiveGenerationTableEntry::addOffset(), gem5::RegisterBank< ByteOrder::little >::addRegisters(), gem5::ruby::addressOffset(), gem5::ArmISA::VfpMacroOp::addStride(), gem5::TraceCPU::ElasticDataGen::adjustInitTraceOffset(), gem5::ruby::DMASequencer::atomicCallback(), gem5::AddressManager::AtomicStruct::AtomicStruct(), gem5::ArmISA::BigFpMemRegOp::BigFpMemRegOp(), gem5::o3::LSQ::SplitDataRequest::buildPackets(), gem5::VegaISA::Inst_SMEM::calcAddr(), gem5::Gcn3ISA::Inst_SMEM::calcAddr(), gem5::VegaISA::Inst_FLAT::calcAddr(), gem5::VegaISA::Inst_FLAT::calcAddrSgpr(), gem5::VegaISA::Inst_FLAT::calcAddrVgpr(), gem5::BaseXBar::calcPacketTiming(), gem5::VirtDescriptor::chainRead(), gem5::VirtDescriptor::chainWrite(), gem5::BaseCache::cmpAndSwap(), gem5::PacketFifo::copyout(), gem5::ruby::DataBlock::copyPartial(), gem5::ruby::WriteMask::count(), gem5::GenericTimerMem::counterCtrlRead(), gem5::GenericTimerMem::counterCtrlWrite(), gem5::linux::ThreadInfo::curTaskInfo(), gem5::linux::ThreadInfo::curTaskMmFromTaskStruct(), gem5::linux::ThreadInfo::curTaskNameFromTaskStruct(), gem5::linux::ThreadInfo::curTaskPIDFromTaskStruct(), gem5::linux::ThreadInfo::curTaskStartFromTaskStruct(), gem5::linux::ThreadInfo::curTaskTGIDFromTaskStruct(), gem5::ruby::DMASequencer::dataCallback(), gem5::GenericPciHost::decodeAddress(), gem5::pseudo_inst::decodeAddrOffset(), gem5::IdeController::dispatchAccess(), gem5::BaseRemoteGDB::encodeXferResponse(), gem5::Gcn3ISA::Inst_SOPK__S_SETREG_B32::execute(), gem5::Gcn3ISA::Inst_SOPK__S_SETREG_IMM32_B32::execute(), gem5::VegaISA::Inst_SOPK__S_GETREG_B32::execute(), gem5::VegaISA::Inst_SOPK__S_SETREG_B32::execute(), gem5::VegaISA::Inst_SOPK__S_SETREG_IMM32_B32::execute(), gem5::Gcn3ISA::Inst_SMEM__S_LOAD_DWORD::execute(), gem5::Gcn3ISA::Inst_SMEM__S_LOAD_DWORDX2::execute(), gem5::VegaISA::Inst_SMEM__S_LOAD_DWORD::execute(), gem5::Gcn3ISA::Inst_SMEM__S_LOAD_DWORDX4::execute(), gem5::VegaISA::Inst_SMEM__S_LOAD_DWORDX2::execute(), gem5::Gcn3ISA::Inst_SMEM__S_LOAD_DWORDX8::execute(), gem5::VegaISA::Inst_SMEM__S_LOAD_DWORDX4::execute(), gem5::Gcn3ISA::Inst_SMEM__S_LOAD_DWORDX16::execute(), gem5::VegaISA::Inst_SMEM__S_LOAD_DWORDX8::execute(), gem5::Gcn3ISA::Inst_SMEM__S_BUFFER_LOAD_DWORD::execute(), gem5::VegaISA::Inst_SMEM__S_LOAD_DWORDX16::execute(), gem5::Gcn3ISA::Inst_SMEM__S_BUFFER_LOAD_DWORDX2::execute(), gem5::VegaISA::Inst_SMEM__S_BUFFER_LOAD_DWORD::execute(), gem5::Gcn3ISA::Inst_SMEM__S_BUFFER_LOAD_DWORDX4::execute(), gem5::VegaISA::Inst_SMEM__S_BUFFER_LOAD_DWORDX2::execute(), gem5::Gcn3ISA::Inst_SMEM__S_BUFFER_LOAD_DWORDX8::execute(), gem5::VegaISA::Inst_SMEM__S_BUFFER_LOAD_DWORDX4::execute(), gem5::Gcn3ISA::Inst_SMEM__S_BUFFER_LOAD_DWORDX16::execute(), gem5::VegaISA::Inst_SMEM__S_BUFFER_LOAD_DWORDX8::execute(), gem5::Gcn3ISA::Inst_SMEM__S_STORE_DWORD::execute(), gem5::VegaISA::Inst_SMEM__S_BUFFER_LOAD_DWORDX16::execute(), gem5::Gcn3ISA::Inst_SMEM__S_STORE_DWORDX2::execute(), gem5::VegaISA::Inst_SMEM__S_STORE_DWORD::execute(), gem5::Gcn3ISA::Inst_SMEM__S_STORE_DWORDX4::execute(), gem5::VegaISA::Inst_SMEM__S_STORE_DWORDX2::execute(), gem5::VegaISA::Inst_SMEM__S_STORE_DWORDX4::execute(), gem5::Gcn3ISA::Inst_MUBUF__BUFFER_LOAD_UBYTE::execute(), gem5::Gcn3ISA::Inst_MUBUF__BUFFER_LOAD_USHORT::execute(), gem5::Gcn3ISA::Inst_MUBUF__BUFFER_LOAD_DWORD::execute(), gem5::Gcn3ISA::Inst_MUBUF__BUFFER_LOAD_DWORDX2::execute(), gem5::Gcn3ISA::Inst_MUBUF__BUFFER_LOAD_DWORDX3::execute(), gem5::Gcn3ISA::Inst_MUBUF__BUFFER_LOAD_DWORDX4::execute(), gem5::Gcn3ISA::Inst_MUBUF__BUFFER_STORE_BYTE::execute(), gem5::Gcn3ISA::Inst_MUBUF__BUFFER_STORE_SHORT::execute(), gem5::Gcn3ISA::Inst_MUBUF__BUFFER_STORE_DWORD::execute(), gem5::Gcn3ISA::Inst_MUBUF__BUFFER_STORE_DWORDX2::execute(), gem5::Gcn3ISA::Inst_MUBUF__BUFFER_STORE_DWORDX3::execute(), gem5::Gcn3ISA::Inst_MUBUF__BUFFER_STORE_DWORDX4::execute(), gem5::VegaISA::Inst_MUBUF__BUFFER_LOAD_UBYTE::execute(), gem5::VegaISA::Inst_MUBUF__BUFFER_LOAD_USHORT::execute(), gem5::VegaISA::Inst_MUBUF__BUFFER_LOAD_DWORD::execute(), gem5::VegaISA::Inst_MUBUF__BUFFER_LOAD_DWORDX2::execute(), gem5::VegaISA::Inst_MUBUF__BUFFER_LOAD_DWORDX3::execute(), gem5::VegaISA::Inst_MUBUF__BUFFER_LOAD_DWORDX4::execute(), gem5::VegaISA::Inst_MUBUF__BUFFER_STORE_BYTE::execute(), gem5::VegaISA::Inst_MUBUF__BUFFER_STORE_SHORT::execute(), gem5::VegaISA::Inst_MUBUF__BUFFER_STORE_DWORD::execute(), gem5::VegaISA::Inst_MUBUF__BUFFER_STORE_DWORDX2::execute(), gem5::VegaISA::Inst_MUBUF__BUFFER_STORE_DWORDX3::execute(), gem5::VegaISA::Inst_MUBUF__BUFFER_STORE_DWORDX4::execute(), gem5::fallocateFunc(), gem5::NonCachingSimpleCPU::fetchInstMem(), gem5::VMA::fillMemPages(), gem5::SectorTags::findBlock(), gem5::loader::DtbFile::findReleaseAddr(), gem5::CompressedTags::findVictim(), gem5::ruby::WriteMask::firstBitSet(), gem5::Gcn3ISA::Inst_DS::generateDisassembly(), gem5::VegaISA::Inst_DS::generateDisassembly(), gem5::guest_abi::Argument< Aapcs32, Composite, typename std::enable_if_t< IsAapcs32CompositeV< Composite > > >::get(), gem5::ruby::SubBlock::getByte(), gem5::ruby::DataBlock::getData(), gem5::ruby::DataBlock::getDataMod(), gem5::KvmKernelGicV2::getGicReg(), gem5::KvmKernelGicV3::getGicReg(), gem5::BaseKvmCPU::getGuestData(), gem5::ruby::UncoalescedTable::getInstPackets(), gem5::ruby::WriteMask::getMask(), gem5::PM4PacketProcessor::getQueue(), gem5::AMDGPUDevice::getSDMAEngine(), gem5::o3::LSQ::SplitDataRequest::handleLocalAccess(), gem5::VegaISA::Inst_DS::initAtomicAccess(), gem5::Gcn3ISA::Inst_DS__DS_WRITE_B32::initiateAcc(), gem5::VegaISA::Inst_DS__DS_ADD_U32::initiateAcc(), gem5::Gcn3ISA::Inst_DS__DS_WRITE_B8::initiateAcc(), gem5::Gcn3ISA::Inst_DS__DS_WRITE_B16::initiateAcc(), gem5::VegaISA::Inst_DS__DS_OR_B32::initiateAcc(), gem5::VegaISA::Inst_DS__DS_WRITE_B32::initiateAcc(), gem5::VegaISA::Inst_DS__DS_ADD_F32::initiateAcc(), gem5::VegaISA::Inst_DS__DS_WRITE_B8::initiateAcc(), gem5::VegaISA::Inst_DS__DS_WRITE_B8_D16_HI::initiateAcc(), gem5::VegaISA::Inst_DS__DS_WRITE_B16::initiateAcc(), gem5::Gcn3ISA::Inst_DS__DS_READ_B32::initiateAcc(), gem5::Gcn3ISA::Inst_DS__DS_READ_U8::initiateAcc(), gem5::Gcn3ISA::Inst_DS__DS_READ_U16::initiateAcc(), gem5::VegaISA::Inst_DS__DS_READ_B32::initiateAcc(), gem5::VegaISA::Inst_DS__DS_READ_I8::initiateAcc(), gem5::VegaISA::Inst_DS__DS_READ_U8::initiateAcc(), gem5::Gcn3ISA::Inst_DS__DS_WRITE_B64::initiateAcc(), gem5::VegaISA::Inst_DS__DS_READ_U16::initiateAcc(), gem5::VegaISA::Inst_DS__DS_ADD_U64::initiateAcc(), gem5::VegaISA::Inst_DS__DS_WRITE_B64::initiateAcc(), gem5::Gcn3ISA::Inst_DS__DS_READ_B64::initiateAcc(), gem5::VegaISA::Inst_DS__DS_READ_B64::initiateAcc(), gem5::Gcn3ISA::Inst_DS__DS_WRITE_B96::initiateAcc(), gem5::Gcn3ISA::Inst_DS__DS_WRITE_B128::initiateAcc(), gem5::Gcn3ISA::Inst_DS__DS_READ_B96::initiateAcc(), gem5::Gcn3ISA::Inst_DS__DS_READ_B128::initiateAcc(), gem5::VegaISA::Inst_DS__DS_WRITE_B96::initiateAcc(), gem5::VegaISA::Inst_DS__DS_WRITE_B128::initiateAcc(), gem5::VegaISA::Inst_DS__DS_READ_B96::initiateAcc(), gem5::VegaISA::Inst_DS__DS_READ_B128::initiateAcc(), gem5::Gcn3ISA::Inst_DS::initMemRead(), gem5::VegaISA::Inst_DS::initMemRead(), gem5::Gcn3ISA::Inst_DS::initMemWrite(), gem5::VegaISA::Inst_DS::initMemWrite(), gem5::Shader::initShHiddenPrivateBase(), gem5::ArmISA::FsFreebsd::initState(), gem5::ArmISA::FsLinux::initState(), gem5::SparcISA::ISA::installGlobals(), gem5::SparcISA::ISA::installWindow(), gem5::ruby::SubBlock::internalMergeFrom(), gem5::ruby::SubBlock::internalMergeTo(), gem5::EmulationPageTable::isUnmapped(), gem5::ArmISA::MacroVFPMemOp::MacroVFPMemOp(), gem5::ruby::DMASequencer::makeRequest(), gem5::UFSHostDevice::manageReadTransfer(), gem5::UFSHostDevice::manageWriteTransfer(), gem5::MultiLevelPageTable< EntryTypes >::map(), gem5::PM4PacketProcessor::mapKiq(), gem5::VMA::MappedFileBuffer::MappedFileBuffer(), gem5::PM4PacketProcessor::mapPq(), gem5::MemState::mapRegion(), gem5::GPUComputeDriver::mmap(), gem5::mmap2Func(), gem5::mmapFunc(), gem5::PM4PacketProcessor::newQueue(), gem5::CowDiskImage::open(), gem5::TimeBuffer< T >::wire::operator+=(), gem5::TimeBuffer< T >::wire::operator-=(), gem5::statistics::Vector2dBase< Vector2d, StatStor >::operator[](), gem5::CircleBuf< char >::peek(), gem5::ruby::WriteMask::performAtomic(), gem5::WalkCache::pickSetIdx(), gem5::pread64Func(), gem5::prefetch::Base::PrefetchInfo::PrefetchInfo(), gem5::memory::SharedMemoryServer::ClientSocketEvent::process(), gem5::PM4PacketProcessor::processMQD(), gem5::pwrite64Func(), gem5::BaseRemoteGDB::queryXfer(), gem5::MmioVirtIO::read(), gem5::PciVirtIO::read(), gem5::RiscvISA::MmioVirtIO::read(), gem5::qemu::FwCfgItemFixed::read(), gem5::RawDiskImage::read(), gem5::Gicv2m::read(), gem5::CowDiskImage::read(), gem5::Uart8250::Registers::BankedRegister::read(), gem5::VirtIOBlock::read(), gem5::AMDGPUDevice::read(), gem5::Uart8250::Registers::RWSwitchedRegister::read(), gem5::VirtDescriptor::read(), gem5::RegisterBank< BankByteOrder >::RegisterRoFill::read(), gem5::GenericTimerFrame::read(), gem5::RegisterBank< BankByteOrder >::RegisterBuf::read(), gem5::RegisterBank< BankByteOrder >::Register< BackingType >::read(), gem5::IdeDisk::readCommand(), gem5::AMDGPUDevice::readConfig(), gem5::IdeController::readConfig(), gem5::PciDevice::readConfig(), gem5::SMMUv3::readControl(), gem5::IdeDisk::readControl(), gem5::AMDGPUDevice::readDoorbell(), gem5::pseudo_inst::readfile(), gem5::UFSHostDevice::UFSSCSIDevice::readFlash(), gem5::AMDGPUDevice::readFrame(), gem5::AMDGPUNbio::readFrame(), gem5::AMDMMIOReader::readFromTrace(), gem5::scmi::AgentChannel::readLength(), gem5::scmi::AgentChannel::readMessage(), gem5::AMDGPUDevice::readMMIO(), gem5::AMDGPUNbio::readMMIO(), gem5::AMDGPUVM::readMMIO(), gem5::scmi::AgentChannel::readStatus(), gem5::Iris::ThreadContext::readVecPredReg(), gem5::AMDMMIOReader::recordMtrace(), gem5::memory::HeteroMemCtrl::recvTimingReq(), gem5::memory::HBMCtrl::recvTimingReq(), gem5::memory::MemCtrl::recvTimingReq(), gem5::HWScheduler::registerNewQueue(), gem5::MultiLevelPageTable< EntryTypes >::remap(), gem5::RangeAddrMapper::remapAddr(), gem5::GPUDynInst::resolveFlatSegment(), gem5::BaseCache::satisfyRequest(), gem5::DmaPort::sendAtomicBdReq(), gem5::PM4PacketProcessor::serialize(), gem5::networking::TcpPtr::set(), gem5::networking::UdpPtr::set(), gem5::ruby::SubBlock::setByte(), gem5::ruby::DataBlock::setData(), gem5::HSAPacketProcessor::setDeviceQueueDesc(), gem5::AMDGPUDevice::setDoorbellType(), gem5::KvmKernelGicV2::setGicReg(), gem5::KvmKernelGicV3::setGicReg(), gem5::ruby::WriteMask::setMask(), gem5::AMDGPUDevice::setSDMAEngine(), gem5::split_first(), gem5::split_last(), gem5::GUPSGen::startup(), gem5::Intel8254Timer::Counter::startup(), subArr(), gem5::ruby::WriteMask::test(), TEST(), gem5::MemTest::tick(), gem5::memory::SharedMemoryServer::BaseShmPollEvent::tryReadAll(), gem5::MultiLevelPageTable< EntryTypes >::unmap(), gem5::PM4PacketProcessor::unserialize(), gem5::Intel8254Timer::Counter::unserialize(), gem5::MemState::unserialize(), gem5::PM4PacketProcessor::updateReadIndex(), gem5::MSHR::TargetList::updateWriteFlags(), gem5::ArmISA::VldSingleOp::VldSingleOp(), gem5::ArmISA::VstSingleOp::VstSingleOp(), gem5::PciVirtIO::write(), gem5::MmioVirtIO::write(), gem5::RiscvISA::MmioVirtIO::write(), gem5::RawDiskImage::write(), gem5::Gicv2m::write(), gem5::CowDiskImage::write(), gem5::Uart8250::Registers::BankedRegister::write(), gem5::VirtIOBlock::write(), gem5::AMDGPUDevice::write(), gem5::Uart8250::Registers::RWSwitchedRegister::write(), gem5::Intel8254Timer::Counter::write(), gem5::memory::CfiMemory::ProgramBuffer::write(), gem5::VirtDescriptor::write(), gem5::GenericTimerFrame::write(), gem5::RegisterBank< BankByteOrder >::RegisterBuf::write(), gem5::RegisterBank< BankByteOrder >::Register< BackingType >::write(), gem5::IdeDisk::writeCommand(), gem5::AMDGPUDevice::writeConfig(), gem5::IdeController::writeConfig(), gem5::PciDevice::writeConfig(), gem5::NSGigE::writeConfig(), gem5::IGbE::writeConfig(), gem5::SMMUv3::writeControl(), gem5::IdeDisk::writeControl(), gem5::GicV2::writeDistributor(), gem5::AMDGPUDevice::writeDoorbell(), gem5::pseudo_inst::writefile(), gem5::UFSHostDevice::UFSSCSIDevice::writeFlash(), gem5::AMDGPUDevice::writeFrame(), gem5::AMDGPUNbio::writeFrame(), gem5::AMDMMIOReader::writeFromTrace(), gem5::AMDGPUDevice::writeMMIO(), gem5::AMDGPUNbio::writeMMIO(), and gem5::AMDGPUVM::writeMMIO().

◆ opc2

Bitfield<7,5> gem5::ArmISA::opc2

Definition at line 106 of file types.hh.

Referenced by gem5::ArmKvmCPU::decodeCoProcReg(), decodeCP14Reg(), decodeCP15Reg(), mcrMrc14TrapToHyp(), mcrMrc15TrapToHyp(), mcrMrcIssBuild(), mcrMrcIssExtract(), and mcrrMrrc15TrapToHyp().

◆ opcode

Bitfield<24, 21> gem5::ArmISA::opcode

Definition at line 92 of file types.hh.

Referenced by gem5::SDMAEngine::decodeHeader(), gem5::trace::TarmacTracerRecordV8::TraceInstEntryV8::print(), gem5::trace::TarmacTracerRecord::TraceInstEntry::print(), gem5::X86ISA::Decoder::processOpcode(), and SC_MODULE().

◆ opcode15

Bitfield<15> gem5::ArmISA::opcode15

Definition at line 104 of file types.hh.

◆ opcode15_12

Bitfield<15, 12> gem5::ArmISA::opcode15_12

Definition at line 103 of file types.hh.

◆ opcode18

Bitfield<18> gem5::ArmISA::opcode18

Definition at line 102 of file types.hh.

◆ opcode19

Bitfield<19> gem5::ArmISA::opcode19

Definition at line 101 of file types.hh.

◆ opcode19_16

Bitfield<19, 16> gem5::ArmISA::opcode19_16

Definition at line 100 of file types.hh.

◆ opcode20

Bitfield<20> gem5::ArmISA::opcode20

Definition at line 98 of file types.hh.

◆ opcode22

Bitfield<22> gem5::ArmISA::opcode22

Definition at line 99 of file types.hh.

◆ opcode23_20

Bitfield<23, 20> gem5::ArmISA::opcode23_20

Definition at line 96 of file types.hh.

◆ opcode23_21

Bitfield<23, 21> gem5::ArmISA::opcode23_21

Definition at line 97 of file types.hh.

◆ opcode24

Bitfield<24> gem5::ArmISA::opcode24

Definition at line 94 of file types.hh.

◆ opcode24_23

Bitfield<24, 23> gem5::ArmISA::opcode24_23

Definition at line 95 of file types.hh.

◆ opcode4

Bitfield<4> gem5::ArmISA::opcode4

Definition at line 109 of file types.hh.

◆ opcode6

Bitfield<6> gem5::ArmISA::opcode6

Definition at line 108 of file types.hh.

◆ opcode7

Bitfield<7> gem5::ArmISA::opcode7

Definition at line 107 of file types.hh.

◆ or0

Bitfield<17,16> gem5::ArmISA::or0

Definition at line 664 of file misc_types.hh.

◆ or1

Bitfield<19,18> gem5::ArmISA::or1

Definition at line 665 of file misc_types.hh.

◆ or2

Bitfield<21,20> gem5::ArmISA::or2

Definition at line 666 of file misc_types.hh.

◆ or3

Bitfield<23,22> gem5::ArmISA::or3

Definition at line 667 of file misc_types.hh.

◆ or4

Bitfield<25,24> gem5::ArmISA::or4

Definition at line 668 of file misc_types.hh.

◆ or5

Bitfield<27,26> gem5::ArmISA::or5

Definition at line 669 of file misc_types.hh.

◆ or6

Bitfield<29,28> gem5::ArmISA::or6

Definition at line 670 of file misc_types.hh.

◆ or7

Bitfield<31,30> gem5::ArmISA::or7

Definition at line 671 of file misc_types.hh.

◆ orgn0

Bitfield< 11, 10 > gem5::ArmISA::orgn0

Definition at line 554 of file misc_types.hh.

◆ orgn1

Bitfield< 27, 26 > gem5::ArmISA::orgn1

Definition at line 561 of file misc_types.hh.

◆ oslk

Bitfield<1> gem5::ArmISA::oslk

Definition at line 840 of file misc_types.hh.

◆ oslm_0

Bitfield<0> gem5::ArmISA::oslm_0

Definition at line 841 of file misc_types.hh.

◆ oslm_3

Bitfield<3> gem5::ArmISA::oslm_3

Definition at line 838 of file misc_types.hh.

◆ pa

Bitfield<39, 12> gem5::ArmISA::pa

Definition at line 714 of file misc_types.hh.

Referenced by gem5::ArmISA::Stage2LookUp::mergeTe(), gem5::ArmISA::TableWalker::LongDescriptor::nextDescAddr(), gem5::ArmISA::MMU::testWalk(), gem5::ArmISA::TableWalker::testWalk(), gem5::ArmISA::MMU::translateFunctional(), gem5::ArmISA::MMU::translateMmuOn(), and gem5::SMMUTranslationProcess::walkCacheUpdate().

◆ pac

Bitfield<2, 1> gem5::ArmISA::pac

Definition at line 867 of file misc_types.hh.

Referenced by gem5::ArmISA::WatchPoint::isEnabled().

◆ PageBytes

const Addr gem5::ArmISA::PageBytes = 1ULL << PageShift

Definition at line 53 of file page_size.hh.

Referenced by gem5::ArmISA::RemoteGDB::acc(), gem5::ArmProcess::argsInit(), gem5::ArmLinuxProcess32::initState(), roundPage(), gem5::Iris::MMU::translateFunctional(), gem5::ArmISA::MMU::translateFunctional(), and truncPage().

◆ PageShift

const Addr gem5::ArmISA::PageShift = 12

Definition at line 52 of file page_size.hh.

Referenced by gem5::ArmISA::TlbEntry::pageStart(), and gem5::ArmISA::TlbEntry::updateVaddr().

◆ pan

Bitfield< 23, 20 > gem5::ArmISA::pan

Definition at line 59 of file misc_types.hh.

Referenced by gem5::ArmISA::ISA::setMiscReg().

◆ parange

Bitfield<3, 0> gem5::ArmISA::parange

Definition at line 157 of file misc_types.hh.

◆ pcsample

Bitfield<3,0> gem5::ArmISA::pcsample

Definition at line 931 of file misc_types.hh.

◆ pd0

Bitfield<4> gem5::ArmISA::pd0

Definition at line 547 of file misc_types.hh.

◆ pd1

Bitfield<5> gem5::ArmISA::pd1

Definition at line 548 of file misc_types.hh.

◆ pmc

Bitfield<2, 1> gem5::ArmISA::pmc

Definition at line 853 of file misc_types.hh.

Referenced by gem5::ArmISA::BrkPoint::isEnabled().

◆ pmsver

Bitfield<35, 32> gem5::ArmISA::pmsver

Definition at line 102 of file misc_types.hh.

◆ pmuver

Bitfield<11, 8> gem5::ArmISA::pmuver

Definition at line 106 of file misc_types.hh.

◆ PREDREG_FFR

const int gem5::ArmISA::PREDREG_FFR = 16

Definition at line 93 of file vec.hh.

◆ PREDREG_UREG0

const int gem5::ArmISA::PREDREG_UREG0 = 17

Definition at line 94 of file vec.hh.

◆ priority

Bitfield<3, 0> gem5::ArmISA::priority

Definition at line 833 of file misc_types.hh.

Referenced by gem5::prefetch::Queued::alreadyInQueue(), gem5::EventQueue::debugVerify(), gem5::memory::qos::FixedPriorityPolicy::initRequestorName(), gem5::memory::qos::FixedPriorityPolicy::initRequestorObj(), gem5::prefetch::Queued::insert(), gem5::MathExpr::parse(), and gem5::MinorCPU::roundRobinPriority().

◆ privSyscallDescs32

SyscallDescTable<EmuLinux::SyscallABI32> gem5::ArmISA::privSyscallDescs32
static
Initial value:
= {
{ 0xf0001, "breakpoint" },
{ 0xf0002, "cacheflush" },
{ 0xf0003, "usr26" },
{ 0xf0004, "usr32" },
{ 0xf0005, "set_tls", setTLSFunc32 },
}

Definition at line 851 of file se_workload.cc.

Referenced by gem5::ArmISA::EmuLinux::syscall().

◆ privSyscallDescs64

SyscallDescTable<EmuLinux::SyscallABI64> gem5::ArmISA::privSyscallDescs64
static
Initial value:
= {
{ 0x1002, "cacheflush" },
{ 0x1005, "set_tls", setTLSFunc64 }
}

Definition at line 860 of file se_workload.cc.

Referenced by gem5::ArmISA::EmuLinux::syscall().

◆ procid

Bitfield<31,8> gem5::ArmISA::procid

Definition at line 676 of file misc_types.hh.

◆ ps

Bitfield< 18, 16 > gem5::ArmISA::ps

Definition at line 571 of file misc_types.hh.

Referenced by gem5::GenericISA::PCStateWithNext::equals(), gem5::GenericISA::DelaySlotPCState< 4 >::equals(), gem5::SparcISA::TLB::MakeTsbPtr(), gem5::BasePixelPump::nextLine(), and gem5::ArmISA::TableWalker::processWalkAArch64().

◆ psruser

Bitfield<22> gem5::ArmISA::psruser

Definition at line 125 of file types.hh.

◆ ptw

Bitfield< 8 > gem5::ArmISA::ptw

Definition at line 337 of file misc_types.hh.

◆ pubwl

gem5::ArmISA::pubwl

Definition at line 130 of file types.hh.

◆ punwl

Bitfield<24, 20> gem5::ArmISA::punwl

Definition at line 154 of file types.hh.

◆ q

Bitfield<27> gem5::ArmISA::q

Definition at line 55 of file misc_types.hh.

Referenced by gem5::SDMAEngine::atomic(), gem5::SDMAEngine::atomicData(), gem5::SDMAEngine::atomicDone(), gem5::SDMAEngine::copy(), gem5::SDMAEngine::copyDone(), gem5::SDMAEngine::copyReadData(), gem5::curEventQueue(), gem5::PM4PacketProcessor::decodeHeader(), gem5::SDMAEngine::decodeHeader(), gem5::PM4PacketProcessor::decodeNext(), gem5::SDMAEngine::decodeNext(), gem5::ruby::AbstractController::dequeueMemRespQueue(), gem5::BaseGlobalEvent::deschedule(), gem5::PowerISA::IntArithOp::divide(), gem5::SparcISA::TlbMap::erase(), gem5::AddrRangeMap< gem5::MemBackdoor, 1 >::erase(), gem5::memory::qos::MemCtrl::escalate(), gem5::SDMAEngine::fence(), gem5::SDMAEngine::fenceDone(), gem5::PM4PacketProcessor::indirectBuffer(), gem5::SDMAEngine::indirectBuffer(), gem5::PM4PacketProcessor::mapProcessGfx9(), gem5::PM4PacketProcessor::mapProcessGfx90a(), gem5::PM4PacketProcessor::mapQueues(), gem5::PM4PacketProcessor::newQueue(), gem5::SDMAEngine::SDMAQueue::parent(), gem5::SDMAEngine::pollRegMem(), gem5::SDMAEngine::pollRegMemRead(), gem5::PM4PacketProcessor::process(), gem5::SDMAEngine::ptePde(), gem5::SDMAEngine::ptePdeDone(), gem5::pybind_init_event(), gem5::PM4PacketProcessor::queryStatus(), gem5::PM4PacketProcessor::queryStatusDone(), recipEstimate(), gem5::PM4PacketProcessor::releaseMem(), gem5::PM4PacketProcessor::releaseMemDone(), gem5::PM4PacketProcessor::runList(), SC_MODULE(), gem5::memory::qos::LrgQueuePolicy::selectPacket(), gem5::PM4PacketProcessor::serialize(), Gem5SystemC::ControlExtension::setQos(), gem5::PM4PacketProcessor::setUconfigReg(), gem5::Event::setWhen(), gem5::SDMAEngine::srbmWrite(), gem5::PM4PacketProcessor::switchBuffer(), gem5::TracingExtension::TracingExtension(), gem5::SDMAEngine::trap(), gem5::PM4PacketProcessor::unmapQueues(), sc_dt::vec_div_small(), sc_dt::vec_mul_small_on(), gem5::PM4PacketProcessor::waitRegMem(), gem5::SDMAEngine::write(), gem5::PM4PacketProcessor::writeData(), gem5::PM4PacketProcessor::writeDataDone(), gem5::SDMAEngine::writeDone(), and gem5::SDMAEngine::writeReadData().

◆ qc

Bitfield<27> gem5::ArmISA::qc

Definition at line 509 of file misc_types.hh.

◆ rao2

Bitfield<18> gem5::ArmISA::rao2

Definition at line 419 of file misc_types.hh.

◆ rao3

Bitfield<16> gem5::ArmISA::rao3

Definition at line 422 of file misc_types.hh.

◆ rao4

Bitfield<6, 3> gem5::ArmISA::rao4

Definition at line 441 of file misc_types.hh.

◆ ras

Bitfield<31, 28> gem5::ArmISA::ras

Definition at line 198 of file misc_types.hh.

◆ raz

Bitfield<31, 28> gem5::ArmISA::raz

Definition at line 541 of file misc_types.hh.

Referenced by TEST_F().

◆ raz_13_4

Bitfield<13,4> gem5::ArmISA::raz_13_4

Definition at line 698 of file misc_types.hh.

◆ raz_28

Bitfield<28> gem5::ArmISA::raz_28

Definition at line 703 of file misc_types.hh.

◆ razwi_8_4

Bitfield<8, 4> gem5::ArmISA::razwi_8_4

Definition at line 812 of file misc_types.hh.

◆ rd

Bitfield<15, 12> gem5::ArmISA::rd

Definition at line 114 of file types.hh.

Referenced by gem5::ArmISA::ArmStaticInst::printDataInst().

◆ rdm

Bitfield< 31, 28 > gem5::ArmISA::rdm

Definition at line 80 of file misc_types.hh.

◆ recip_sqrt_estimate

const uint8_t gem5::ArmISA::recip_sqrt_estimate[256]
static
Initial value:
= {
255, 253, 251, 249, 247, 245, 243, 242, 240, 238, 236, 234, 233, 231, 229, 228,
226, 224, 223, 221, 219, 218, 216, 215, 213, 212, 210, 209, 207, 206, 204, 203,
201, 200, 198, 197, 196, 194, 193, 192, 190, 189, 188, 186, 185, 184, 183, 181,
180, 179, 178, 176, 175, 174, 173, 172, 170, 169, 168, 167, 166, 165, 164, 163,
162, 160, 159, 158, 157, 156, 155, 154, 153, 152, 151, 150, 149, 148, 147, 146,
145, 144, 143, 142, 141, 140, 140, 139, 138, 137, 136, 135, 134, 133, 132, 131,
131, 130, 129, 128, 127, 126, 126, 125, 124, 123, 122, 121, 121, 120, 119, 118,
118, 117, 116, 115, 114, 114, 113, 112, 111, 111, 110, 109, 109, 108, 107, 106,
105, 104, 103, 101, 100, 99, 97, 96, 95, 93, 92, 91, 90, 88, 87, 86,
85, 84, 82, 81, 80, 79, 78, 77, 76, 75, 74, 72, 71, 70, 69, 68,
67, 66, 65, 64, 63, 62, 61, 60, 60, 59, 58, 57, 56, 55, 54, 53,
52, 51, 51, 50, 49, 48, 47, 46, 46, 45, 44, 43, 42, 42, 41, 40,
39, 38, 38, 37, 36, 35, 35, 34, 33, 33, 32, 31, 30, 30, 29, 28,
28, 27, 26, 26, 25, 24, 24, 23, 22, 22, 21, 20, 20, 19, 19, 18,
17, 17, 16, 16, 15, 14, 14, 13, 13, 12, 11, 11, 10, 10, 9, 9,
8, 8, 7, 6, 6, 5, 5, 4, 4, 3, 3, 2, 2, 1, 1, 0
}

Definition at line 3510 of file fplib.cc.

Referenced by fplibRSqrtEstimate().

◆ regList

Bitfield<15, 0> gem5::ArmISA::regList

Definition at line 142 of file types.hh.

◆ res0

gem5::ArmISA::res0

Definition at line 837 of file misc_types.hh.

Referenced by TEST_F().

◆ res0_

Bitfield<13> gem5::ArmISA::res0_

Definition at line 888 of file misc_types.hh.

◆ res0_0

Bitfield< 0 > gem5::ArmISA::res0_0

Definition at line 852 of file misc_types.hh.

◆ res0_1

Bitfield< 5 > gem5::ArmISA::res0_1

Definition at line 850 of file misc_types.hh.

◆ res0_14_12

Bitfield<14, 12> gem5::ArmISA::res0_14_12

Definition at line 827 of file misc_types.hh.

◆ res0_2

Bitfield< 9, 8 > gem5::ArmISA::res0_2

Definition at line 845 of file misc_types.hh.

◆ res0_3

Bitfield< 13 > gem5::ArmISA::res0_3

Definition at line 881 of file misc_types.hh.

◆ res0_30_9

Bitfield<30, 9> gem5::ArmISA::res0_30_9

Definition at line 811 of file misc_types.hh.

◆ res0_4

Bitfield< 24, 16 > gem5::ArmISA::res0_4

Definition at line 878 of file misc_types.hh.

◆ res0_5

Bitfield< 29 > gem5::ArmISA::res0_5

Definition at line 875 of file misc_types.hh.

◆ res0_63_2

gem5::ArmISA::res0_63_2

Definition at line 817 of file misc_types.hh.

◆ res0_63_32

gem5::ArmISA::res0_63_32

Definition at line 809 of file misc_types.hh.

◆ res0_63_4

gem5::ArmISA::res0_63_4

Definition at line 832 of file misc_types.hh.

◆ res1_12_el2

Bitfield<12, 12> gem5::ArmISA::res1_12_el2

Definition at line 793 of file misc_types.hh.

◆ res1_13_el2

Bitfield<13, 13> gem5::ArmISA::res1_13_el2

Definition at line 792 of file misc_types.hh.

◆ res1_7_0_el2

Bitfield<7, 0> gem5::ArmISA::res1_7_0_el2

Definition at line 801 of file misc_types.hh.

◆ res1_8_el2

Bitfield<8> gem5::ArmISA::res1_8_el2

Definition at line 798 of file misc_types.hh.

◆ res1_9_el2

Bitfield<9> gem5::ArmISA::res1_9_el2

Definition at line 797 of file misc_types.hh.

◆ reserved_20_13

Bitfield<20,13> gem5::ArmISA::reserved_20_13

Definition at line 687 of file misc_types.hh.

◆ reserved_22

Bitfield<22> gem5::ArmISA::reserved_22

Definition at line 689 of file misc_types.hh.

◆ reserved_30_26

Bitfield<30,26> gem5::ArmISA::reserved_30_26

Definition at line 692 of file misc_types.hh.

◆ reserved_4_3

Bitfield<4,3> gem5::ArmISA::reserved_4_3

Definition at line 681 of file misc_types.hh.

◆ ReturnAddressReg

constexpr auto & gem5::ArmISA::ReturnAddressReg = int_reg::Lr

Definition at line 655 of file int.hh.

Referenced by gem5::ArmISA::ArmStaticInst::printIntReg(), gem5::ArmISA::SkipFunc::returnFromFuncIn(), gem5::trace::TarmacTracerRecordV8::TraceRegEntryV8::updateInt(), and gem5::trace::TarmacTracerRecord::TraceRegEntry::updateInt().

◆ ReturnValueReg

constexpr auto& gem5::ArmISA::ReturnValueReg = int_reg::X0
inlineconstexpr

Definition at line 648 of file int.hh.

Referenced by gem5::guest_abi::Result< ABI, SyscallReturn, typename std::enable_if_t< std::is_base_of_v< ArmISA::EmuLinux::BaseSyscallABI, ABI > > >::store(), and gem5::guest_abi::Result< ABI, SyscallReturn, typename std::enable_if_t< std::is_base_of_v< ArmISA::EmuFreebsd::BaseSyscallABI, ABI > > >::store().

◆ ReturnValueReg1

constexpr auto & gem5::ArmISA::ReturnValueReg1 = int_reg::X1

Definition at line 649 of file int.hh.

◆ revision

Bitfield<23, 16> gem5::ArmISA::revision

Definition at line 825 of file misc_types.hh.

Referenced by EndBitUnion().

◆ rfr

Bitfield<19> gem5::ArmISA::rfr

Definition at line 344 of file misc_types.hh.

◆ rm

Bitfield<3, 0> gem5::ArmISA::rm

Definition at line 118 of file types.hh.

Referenced by fp16_round_(), fp32_round_(), fp64_round_(), gem5::getFpRound(), gem5::ArmISA::ArmStaticInst::printDataInst(), gem5::ArmISA::ArmStaticInst::printExtendOperand(), gem5::ArmISA::ArmStaticInst::printShiftOperand(), gem5::setFpRound(), gem5::ArmISA::VldMultOp::VldMultOp(), gem5::ArmISA::VldMultOp64::VldMultOp64(), gem5::ArmISA::VldSingleOp::VldSingleOp(), gem5::ArmISA::VldSingleOp64::VldSingleOp64(), gem5::ArmISA::VstMultOp::VstMultOp(), gem5::ArmISA::VstMultOp64::VstMultOp64(), gem5::ArmISA::VstSingleOp::VstSingleOp(), and gem5::ArmISA::VstSingleOp64::VstSingleOp64().

◆ rMode

Bitfield<23, 22> gem5::ArmISA::rMode

Definition at line 505 of file misc_types.hh.

Referenced by gem5::ArmISA::FpOp::binaryOp(), prepFpState(), gem5::ArmISA::FpOp::ternaryOp(), gem5::ArmISA::FpOp::unaryOp(), vcvtFpDFpH(), vcvtFpFpH(), and vcvtFpSFpH().

◆ rn

Bitfield<19, 16> gem5::ArmISA::rn

Definition at line 113 of file types.hh.

Referenced by gem5::ArmISA::MacroMemOp::MacroMemOp(), gem5::ArmISA::MacroVFPMemOp::MacroVFPMemOp(), gem5::ArmISA::PairMemOp::PairMemOp(), gem5::ArmISA::ArmStaticInst::printDataInst(), gem5::ArmISA::VldMultOp::VldMultOp(), gem5::ArmISA::VldMultOp64::VldMultOp64(), gem5::ArmISA::VldSingleOp::VldSingleOp(), gem5::ArmISA::VldSingleOp64::VldSingleOp64(), gem5::ArmISA::VstMultOp::VstMultOp(), gem5::ArmISA::VstMultOp64::VstMultOp64(), gem5::ArmISA::VstSingleOp::VstSingleOp(), and gem5::ArmISA::VstSingleOp64::VstSingleOp64().

◆ rndr

gem5::ArmISA::rndr

Definition at line 112 of file misc_types.hh.

◆ rotate

Bitfield<11, 8> gem5::ArmISA::rotate

Definition at line 134 of file types.hh.

Referenced by gem5::ArmISA::PredIntOp::generateDisassembly().

◆ roundingModes

Bitfield<31, 28> gem5::ArmISA::roundingModes

Definition at line 530 of file misc_types.hh.

◆ rr

Bitfield<14> gem5::ArmISA::rr

Definition at line 425 of file misc_types.hh.

◆ rs

Bitfield< 11, 8 > gem5::ArmISA::rs

Definition at line 433 of file misc_types.hh.

Referenced by gem5::ruby::garnet::GarnetNetwork::collateStats(), gem5::Gicv3CPUInterface::generateSGI(), gem5::ruby::RubyPort::MemResponsePort::hitCallback(), gem5::ruby::Sequencer::hitCallback(), gem5::IGbE::TxDescCache::pktComplete(), gem5::ArmISA::ArmStaticInst::printDataInst(), gem5::ArmISA::ArmStaticInst::printShiftOperand(), gem5::ruby::RubyPort::MemResponsePort::recvAtomic(), gem5::ruby::RubyPort::MemResponsePort::recvFunctional(), gem5::ruby::RubyPort::MemResponsePort::recvTimingReq(), and gem5::statistics::BinaryNode< Op >::size().

◆ rsvd

Bitfield<29, 28> gem5::ArmISA::rsvd

Definition at line 472 of file misc_types.hh.

◆ rt

Bitfield<15, 12> gem5::ArmISA::rt

Definition at line 115 of file types.hh.

Referenced by mcrMrc14TrapToHyp(), mcrMrc15TrapToHyp(), mcrMrcIssBuild(), mcrMrcIssExtract(), mcrrMrrc15TrapToHyp(), mcrrMrrcIssBuild(), gem5::ArmISA::PairMemOp::PairMemOp(), and gem5::ArmISA::HTMCheckpoint::restore().

◆ rw

Bitfield< 10 > gem5::ArmISA::rw

Definition at line 307 of file misc_types.hh.

Referenced by gem5::Pl111::pixelConverter().

◆ rxfull

Bitfield<30> gem5::ArmISA::rxfull

Definition at line 873 of file misc_types.hh.

◆ rxo

Bitfield<27> gem5::ArmISA::rxo

Definition at line 876 of file misc_types.hh.

◆ s

Bitfield< 9 > gem5::ArmISA::s

Definition at line 619 of file misc_types.hh.

Referenced by gem5::ArmISA::TableWalker::memAttrs(), gem5::ArmISA::ArmStaticInst::printDataInst(), recipEstimate(), and recipSqrtEstimate().

◆ s1ptw

Bitfield< 7 > gem5::ArmISA::s1ptw

Definition at line 754 of file misc_types.hh.

Referenced by gem5::ArmISA::AbortFault< DataAbort >::annotate().

◆ sa

Bitfield<3> gem5::ArmISA::sa

Definition at line 448 of file misc_types.hh.

Referenced by gem5::acceptFunc(), gem5::getsocknameFunc(), gem5::installSignalHandler(), gem5::recvfromFunc(), gem5::sendtoFunc(), and gem5::BaseKvmCPU::setupSignalHandler().

◆ sa0

Bitfield<4> gem5::ArmISA::sa0

Definition at line 446 of file misc_types.hh.

◆ sas

Bitfield<23, 22> gem5::ArmISA::sas

Definition at line 745 of file misc_types.hh.

◆ sataRAMLatency

gem5::ArmISA::sataRAMLatency

Definition at line 680 of file misc_types.hh.

◆ sb

Bitfield< 39, 36 > gem5::ArmISA::sb

Definition at line 93 of file misc_types.hh.

Referenced by gem5::prefetch::SBOOE::access().

◆ sc2

Bitfield<19> gem5::ArmISA::sc2

Definition at line 882 of file misc_types.hh.

Referenced by addPACDA(), addPACDB(), addPACIA(), addPACIB(), authDA(), authDB(), authIA(), and authIB().

◆ scd

Bitfield<7> gem5::ArmISA::scd

Definition at line 380 of file misc_types.hh.

◆ sd

Bitfield<4> gem5::ArmISA::sd

Definition at line 916 of file misc_types.hh.

Referenced by gem5::ArmISA::ArmStaticInst::activateBreakpoint(), gem5::DebugStep::execute(), gem5::ArmISA::ArmStaticInst::getPSTATEFromPSR(), gem5::StackDistProbe::handleRequest(), and gem5::ArmISA::MMU::translateFs().

◆ sed

Bitfield<8> gem5::ArmISA::sed

Definition at line 436 of file misc_types.hh.

Referenced by gem5::ArmISA::ArmStaticInst::checkSETENDEnabled().

◆ sel

gem5::ArmISA::sel

Definition at line 708 of file misc_types.hh.

Referenced by gem5::AddrRange::contains(), gem5::Gcn3ISA::Inst_VOP3__V_PERM_B32::permute(), gem5::VegaISA::Inst_VOP3__V_PERM_B32::permute(), gem5::Gcn3ISA::sdwaInstDstImpl(), gem5::VegaISA::sdwaInstDstImpl(), gem5::Gcn3ISA::sdwaInstDstImpl_helper(), gem5::VegaISA::sdwaInstDstImpl_helper(), gem5::Gcn3ISA::sdwaInstSrcImpl(), gem5::VegaISA::sdwaInstSrcImpl(), gem5::Gcn3ISA::sdwaInstSrcImpl_helper(), and gem5::VegaISA::sdwaInstSrcImpl_helper().

◆ sel2

Bitfield<39, 36> gem5::ArmISA::sel2

Definition at line 196 of file misc_types.hh.

◆ set

Bitfield<12, 11> gem5::ArmISA::set

Definition at line 760 of file misc_types.hh.

Referenced by gem5::NoMaliGpu::_interrupt(), gem5::ruby::CacheMemory::allocate(), gem5::ARMArchTLB::ARMArchTLB(), gem5::minor::BranchData::BranchData(), gem5::minor::Fetch1::changeStream(), gem5::SimpleThread::clearArchRegs(), gem5::ruby::CacheMemory::clearLockedAll(), gem5::o3::Fetch::clearStates(), gem5::o3::Commit::commit(), gem5::o3::Commit::commitInsts(), gem5::ConfigCache::ConfigCache(), gem5::GicV2::copyGicState(), gem5::minor::Decode::DecodeThreadInfo::DecodeThreadInfo(), gem5::VegaISA::GpuTLB::demapPage(), gem5::X86ISA::GpuTLB::demapPage(), gem5::o3::Fetch::doSquash(), gem5::o3::DynInst::DynInst(), gem5::minor::Decode::evaluate(), gem5::minor::Fetch2::evaluate(), gem5::Wavefront::exec(), gem5::o3::Fetch::fetch(), gem5::minor::Fetch2::Fetch2ThreadInfo::Fetch2ThreadInfo(), gem5::BaseTags::findBlockBySetAndWay(), gem5::FALRU::findBlockBySetAndWay(), sc_core::sc_time::from_seconds(), gem5::ruby::CacheMemory::getAddressAtIdx(), gem5::BaseIndexingPolicy::getEntry(), gem5::ruby::CacheMemory::getReplacementWeight(), gem5::ruby::CacheMemory::htmAbortTransaction(), gem5::ruby::CacheMemory::htmCommitTransaction(), gem5::X86ISA::GpuTLB::insert(), gem5::VegaISA::GpuTLB::insert(), gem5::MemFootprintProbe::insertAddr(), gem5::SMMUTLB::invalidateAll(), gem5::ARMArchTLB::invalidateAll(), gem5::IPACache::invalidateAll(), gem5::ConfigCache::invalidateAll(), gem5::WalkCache::invalidateAll(), gem5::SMMUTLB::invalidateASID(), gem5::ARMArchTLB::invalidateASID(), gem5::WalkCache::invalidateASID(), gem5::IPACache::invalidateIPA(), gem5::IPACache::invalidateIPAA(), gem5::SMMUTLB::invalidateSID(), gem5::ConfigCache::invalidateSID(), gem5::SMMUTLB::invalidateSSID(), gem5::ConfigCache::invalidateSSID(), gem5::SMMUTLB::invalidateVA(), gem5::ARMArchTLB::invalidateVA(), gem5::WalkCache::invalidateVA(), gem5::SMMUTLB::invalidateVAA(), gem5::ARMArchTLB::invalidateVAA(), gem5::WalkCache::invalidateVAA(), gem5::SMMUTLB::invalidateVMID(), gem5::ARMArchTLB::invalidateVMID(), gem5::IPACache::invalidateVMID(), gem5::WalkCache::invalidateVMID(), sc_dt::sc_unsigned::invert(), sc_dt::sc_signed::invert(), gem5::IPACache::IPACache(), gem5::branch_prediction::SimpleIndirectPredictor::lookup(), gem5::VegaISA::GpuTLB::lookup(), gem5::X86ISA::GpuTLB::lookup(), gem5::SMMUTLB::lookup(), gem5::ARMArchTLB::lookup(), gem5::IPACache::lookup(), gem5::ConfigCache::lookup(), gem5::WalkCache::lookup(), gem5::SMMUTLB::lookupAnyVA(), gem5::X86ISA::GpuTLB::lookupIt(), gem5::VegaISA::GpuTLB::lookupIt(), gem5::NoMaliGpu::onInterrupt(), gem5::minor::BranchData::operator=(), gem5::minor::ForwardLineData::operator=(), gem5::SimpleThread::pcState(), gem5::o3::Commit::pcState(), gem5::o3::DynInst::pcState(), gem5::SimpleThread::pcStateNoRecord(), gem5::SMMUTLB::pickEntryIdxToReplace(), gem5::ARMArchTLB::pickEntryIdxToReplace(), gem5::IPACache::pickEntryIdxToReplace(), gem5::ConfigCache::pickEntryIdxToReplace(), gem5::WalkCache::pickEntryIdxToReplace(), gem5::branch_prediction::BPredUnit::predict(), gem5::minor::Fetch2::predictBranch(), gem5::branch_prediction::BPredUnit::PredictorHistory::PredictorHistory(), gem5::BaseSimpleCPU::preExecute(), gem5::minor::Fetch1::processResponse(), gem5::branch_prediction::ReturnAddrStack::push(), gem5::CheckerCPU::recordPCChange(), gem5::branch_prediction::SimpleIndirectPredictor::recordTarget(), gem5::o3::Fetch::resetStage(), gem5::branch_prediction::ReturnAddrStack::restore(), sc_core::sc_time::sc_time(), sc_dt::sc_unsigned::set(), sc_dt::sc_signed::set(), gem5::Gicv3Redistributor::setClrLPI(), gem5::BaseIndexingPolicy::setEntry(), gem5::ruby::NetDest::setNetDest(), gem5::ReplaceableEntry::setPosition(), gem5::SectorBlk::setPosition(), gem5::o3::DynInst::setPredTarg(), gem5::PollQueue::setupAsyncIO(), sc_gem5::Process::signalReset(), gem5::SMMUTLB::SMMUTLB(), gem5::o3::Decode::squash(), gem5::o3::Commit::squashAll(), gem5::o3::IEW::squashDueToBranch(), gem5::o3::IEW::squashDueToMemOrder(), gem5::SMMUTLB::store(), gem5::ARMArchTLB::store(), gem5::IPACache::store(), gem5::ConfigCache::store(), gem5::WalkCache::store(), TEST(), gem5::branch_prediction::DefaultBTB::update(), gem5::Checker< gem5::RefCountingPtr >::verify(), gem5::minor::Fetch1::wakeupFetch(), and gem5::WalkCache::WalkCache().

◆ sevenAndFour

Bitfield<33> gem5::ArmISA::sevenAndFour

Definition at line 84 of file types.hh.

◆ sevl

Bitfield<3, 0> gem5::ArmISA::sevl

Definition at line 85 of file misc_types.hh.

◆ sf

Bitfield< 7 > gem5::ArmISA::sf

Definition at line 748 of file misc_types.hh.

◆ sField

Bitfield<20> gem5::ArmISA::sField

Definition at line 112 of file types.hh.

◆ sh

Bitfield<8, 7> gem5::ArmISA::sh

Definition at line 718 of file misc_types.hh.

Referenced by gem5::ArmSemihosting::SemiCall::buildDispatcher(), gem5::branch_prediction::MPP_StatisticalCorrector_8KB::gPredictions(), gem5::branch_prediction::MPP_StatisticalCorrector_64KB::gPredictions(), gem5::branch_prediction::TAGE_SC_L_8KB_StatisticalCorrector::gPredictions(), gem5::branch_prediction::TAGE_SC_L_64KB_StatisticalCorrector::gPredictions(), gem5::branch_prediction::MPP_StatisticalCorrector_8KB::gUpdates(), gem5::branch_prediction::MPP_StatisticalCorrector_64KB::gUpdates(), gem5::branch_prediction::TAGE_SC_L_8KB_StatisticalCorrector::gUpdates(), gem5::branch_prediction::TAGE_SC_L_64KB_StatisticalCorrector::gUpdates(), gem5::branch_prediction::MPP_StatisticalCorrector_8KB::makeThreadHistory(), gem5::branch_prediction::MPP_StatisticalCorrector_64KB::makeThreadHistory(), gem5::branch_prediction::TAGE_SC_L_8KB_StatisticalCorrector::makeThreadHistory(), gem5::branch_prediction::TAGE_SC_L_64KB_StatisticalCorrector::makeThreadHistory(), gem5::ArmISA::TableWalker::memAttrsAArch64(), gem5::ArmISA::TableWalker::memAttrsLPAE(), gem5::branch_prediction::MPP_StatisticalCorrector_8KB::scHistoryUpdate(), gem5::branch_prediction::MPP_StatisticalCorrector_64KB::scHistoryUpdate(), gem5::branch_prediction::TAGE_SC_L_8KB_StatisticalCorrector::scHistoryUpdate(), gem5::branch_prediction::TAGE_SC_L_64KB_StatisticalCorrector::scHistoryUpdate(), and gem5::ArmSemihosting::SemiCall::wrapImpl().

◆ sh0

Bitfield< 13, 12 > gem5::ArmISA::sh0

Definition at line 62 of file int.hh.

◆ sh1

Bitfield< 29, 28 > gem5::ArmISA::sh1

Definition at line 61 of file int.hh.

◆ sha1

Bitfield< 11, 8 > gem5::ArmISA::sha1

Definition at line 83 of file misc_types.hh.

◆ sha2

Bitfield< 15, 12 > gem5::ArmISA::sha2

Definition at line 82 of file misc_types.hh.

◆ sha3

Bitfield< 35, 32 > gem5::ArmISA::sha3

Definition at line 119 of file misc_types.hh.

◆ shift

Bitfield<6, 5> gem5::ArmISA::shift

Definition at line 117 of file types.hh.

Referenced by gem5::MipsISA::bitrev(), gem5::divideFromConf(), gem5::X86ISA::X86StaticInst::divideStep(), gem5::findCarry(), gem5::findOverflow(), fp128_normalise(), fp16_normalise(), fp32_normalise(), fp64_normalise(), gem5::MipsISA::getCondCode(), gem5::branch_prediction::MultiperspectivePerceptron::ACYCLIC::getHash(), gem5::branch_prediction::MultiperspectivePerceptron::RECENCY::getHash(), gem5::branch_prediction::MultiperspectivePerceptron::PATH::getHash(), gem5::branch_prediction::MultiperspectivePerceptron::MODPATH::getHash(), gem5::branch_prediction::MultiperspectivePerceptron::GHISTPATH::getHash(), gem5::branch_prediction::MultiperspectivePerceptron::GHISTMODPATH::getHash(), gem5::branch_prediction::MultiperspectivePerceptron::BLURRYPATH::getHash(), gem5::branch_prediction::MultiperspectivePerceptron::SGHISTPATH::getHash(), gem5::branch_prediction::StatisticalCorrector::SCThreadHistory::initLocalHistory(), gem5::ps2::keySymToPs2(), lsl128(), lsl16(), lsl32(), lsl64(), lsr128(), lsr16(), lsr32(), lsr64(), sc_dt::scfx_rep::normalize(), gem5::Cycles::operator<<(), sc_dt::operator<<(), gem5::GenericSatCounter< uint8_t >::operator<<=(), gem5::Cycles::operator>>(), sc_dt::operator>>(), gem5::GenericSatCounter< uint8_t >::operator>>=(), sc_dt::scfx_rep::resize(), gem5::ArmISA::Crypto::ror(), gem5::PowerISA::IntRotateOp::rotate(), gem5::PowerISA::IntConcatRotateOp::rotate(), SC_MODULE(), sc_dt::sc_concref_r< X, Y >::set_cword(), sc_dt::sc_concref_r< X, Y >::set_word(), gem5::RiscvISA::Walker::WalkerState::setupWalk(), gem5::RiscvISA::Walker::WalkerState::stepWalk(), gem5::prefetch::IndirectMemory::trackMissIndex1(), gem5::prefetch::IndirectMemory::trackMissIndex2(), and gem5::X86ISA::X86MicroopBase::X86MicroopBase().

◆ shiftSize

Bitfield<11, 7> gem5::ArmISA::shiftSize

Definition at line 116 of file types.hh.

◆ shortVectors

Bitfield<27, 24> gem5::ArmISA::shortVectors

Definition at line 529 of file misc_types.hh.

◆ si

Bitfield<6> gem5::ArmISA::si

Definition at line 914 of file misc_types.hh.

Referenced by gem5::RiscvISA::Decoder::decode(), gem5::MipsISA::Decoder::decode(), gem5::SparcISA::Decoder::decode(), gem5::ArmISA::Decoder::decode(), gem5::trace::InstPBTrace::getInstRecord(), gem5::minor::ExecContext::getRegOperand(), gem5::CheckerCPU::getRegOperand(), gem5::SimpleExecContext::getRegOperand(), gem5::MathExprPowerModel::getStatValue(), gem5::minor::ExecContext::getWritableRegOperand(), gem5::CheckerCPU::getWritableRegOperand(), gem5::SimpleExecContext::getWritableRegOperand(), gem5::SimpleExecContext::readMiscRegOperand(), gem5::minor::ExecContext::readMiscRegOperand(), gem5::CheckerCPU::readMiscRegOperand(), gem5::o3::DynInst::readMiscRegOperand(), gem5::SimpleExecContext::setMiscRegOperand(), gem5::minor::ExecContext::setMiscRegOperand(), gem5::CheckerCPU::setMiscRegOperand(), gem5::o3::DynInst::setMiscRegOperand(), gem5::minor::ExecContext::setRegOperand(), gem5::CheckerCPU::setRegOperand(), gem5::SimpleExecContext::setRegOperand(), gem5::trace::InstPBTrace::traceInst(), and gem5::trace::InstPBTrace::traceMem().

◆ sif

Bitfield<9> gem5::ArmISA::sif

Definition at line 378 of file misc_types.hh.

◆ singlePrecision

Bitfield<7, 4> gem5::ArmISA::singlePrecision

Definition at line 524 of file misc_types.hh.

◆ sl0

Bitfield<7, 6> gem5::ArmISA::sl0

Definition at line 621 of file misc_types.hh.

Referenced by gem5::ArmISA::V8PageTableOps4k::firstS2Level(), gem5::ArmISA::V8PageTableOps16k::firstS2Level(), and gem5::ArmISA::V8PageTableOps64k::firstS2Level().

◆ sm

Bitfield<0, 0> gem5::ArmISA::sm

Definition at line 819 of file misc_types.hh.

◆ sm3

Bitfield<39, 36> gem5::ArmISA::sm3

Definition at line 118 of file misc_types.hh.

◆ sm4

Bitfield< 43, 40 > gem5::ArmISA::sm4

Definition at line 117 of file misc_types.hh.

◆ smd

Bitfield<7> gem5::ArmISA::smd

Definition at line 381 of file misc_types.hh.

◆ smen

Bitfield< 25, 24 > gem5::ArmISA::smen

Definition at line 469 of file misc_types.hh.

◆ smEver

Bitfield<59, 56> gem5::ArmISA::smEver

Definition at line 223 of file misc_types.hh.

◆ smps

Bitfield<15, 15> gem5::ArmISA::smps

Definition at line 826 of file misc_types.hh.

◆ snsmem

Bitfield<15, 12> gem5::ArmISA::snsmem

Definition at line 154 of file misc_types.hh.

◆ sp

Bitfield< 3 > gem5::ArmISA::sp

Definition at line 75 of file misc_types.hh.

Referenced by gem5::RiscvProcess::argsInit(), gem5::SparcISA::SEWorkload::flushWindows(), gem5::SparcISA::SpillNNormal::invoke(), gem5::SparcISA::FillNNormal::invoke(), gem5::SparcISA::TrapInstruction::invoke(), gem5::statistics::ScalarProxy< Stat >::operator=(), gem5::statistics::VectorProxy< Stat >::operator=(), gem5::statistics::DistProxy< Stat >::operator=(), gem5::ArmISA::HTMCheckpoint::restore(), gem5::ArmISA::HTMCheckpoint::save(), and gem5::ArmISA::ISA::setMiscReg().

◆ span

Bitfield<23> gem5::ArmISA::span

Definition at line 405 of file misc_types.hh.

Referenced by gem5::SMMUTranslationProcess::doReadSTE().

◆ specres

Bitfield< 43, 40 > gem5::ArmISA::specres

Definition at line 92 of file misc_types.hh.

◆ specsei

Bitfield<27, 24> gem5::ArmISA::specsei

Definition at line 163 of file misc_types.hh.

◆ spiddis

Bitfield<16> gem5::ArmISA::spiddis

Definition at line 885 of file misc_types.hh.

◆ spniddis

Bitfield<17> gem5::ArmISA::spniddis

Definition at line 884 of file misc_types.hh.

◆ squareRoot

Bitfield<23, 20> gem5::ArmISA::squareRoot

Definition at line 528 of file misc_types.hh.

◆ srt

Bitfield<20, 16> gem5::ArmISA::srt

Definition at line 747 of file misc_types.hh.

◆ ss

Bitfield< 2 > gem5::ArmISA::ss

Definition at line 60 of file misc_types.hh.

Referenced by gem5::MrsOp::generateDisassembly(), gem5::ImmOp64::generateDisassembly(), gem5::ArmISA::DataXImmOp::generateDisassembly(), gem5::ArmISA::BranchImm::generateDisassembly(), gem5::ArmISA::SmeAddOp::generateDisassembly(), gem5::ArmISA::BranchImm64::generateDisassembly(), gem5::ArmISA::SysDC64::generateDisassembly(), gem5::ArmISAInst::MicroTmeBasic64::generateDisassembly(), gem5::RegOp64::generateDisassembly(), gem5::ArmISA::SveMemVecFillSpill::generateDisassembly(), gem5::ArmISA::SveIndexIIOp::generateDisassembly(), gem5::ArmISA::DataXImmOnlyOp::generateDisassembly(), gem5::ArmISAInst::TmeImmOp64::generateDisassembly(), gem5::ArmISA::BranchImmCond64::generateDisassembly(), gem5::MsrImmOp::generateDisassembly(), gem5::ArmISA::SmeAddVlOp::generateDisassembly(), gem5::RegImmImmOp64::generateDisassembly(), gem5::ArmISA::SveIndexIROp::generateDisassembly(), gem5::ArmISA::BranchReg::generateDisassembly(), gem5::ArmISA::DataXSRegOp::generateDisassembly(), gem5::ArmISAInst::TmeRegNone64::generateDisassembly(), gem5::MsrRegOp::generateDisassembly(), gem5::ArmISA::SveMemPredFillSpill::generateDisassembly(), gem5::ArmISA::SveLdStructSS< Element, MicroopLdMemType, MicroopDeIntrlvType >::generateDisassembly(), gem5::ArmISA::BranchRegReg64::generateDisassembly(), gem5::ArmISA::SmeLd1xSt1xOp::generateDisassembly(), gem5::ArmISA::SveIndexRIOp::generateDisassembly(), gem5::RegRegImmImmOp64::generateDisassembly(), gem5::ArmISA::BranchReg64::generateDisassembly(), gem5::ArmISA::DataXERegOp::generateDisassembly(), gem5::MrrcOp::generateDisassembly(), gem5::ArmISA::BranchRegReg::generateDisassembly(), gem5::ArmISA::SveIndexRROp::generateDisassembly(), gem5::ArmISA::SveContigMemSS::generateDisassembly(), gem5::ArmISA::SmeLdrStrOp::generateDisassembly(), gem5::ArmISA::BranchRet64::generateDisassembly(), gem5::RegRegRegImmOp64::generateDisassembly(), gem5::ArmISA::DataX1RegOp::generateDisassembly(), gem5::ArmISA::RfeOp::generateDisassembly(), gem5::McrrOp::generateDisassembly(), gem5::ArmISA::BranchRetA64::generateDisassembly(), gem5::ArmISA::SvePredCountOp::generateDisassembly(), gem5::ArmISA::DataX1RegImmOp::generateDisassembly(), gem5::ArmISA::SmeMovExtractOp::generateDisassembly(), gem5::ImmOp::generateDisassembly(), gem5::ArmISA::SveContigMemSI::generateDisassembly(), gem5::ArmISA::BranchEret64::generateDisassembly(), gem5::ArmISA::SvePredCountPredOp::generateDisassembly(), gem5::ArmISA::DataX1Reg2ImmOp::generateDisassembly(), gem5::RegImmOp::generateDisassembly(), gem5::ArmISA::MemoryImm64::generateDisassembly(), gem5::ArmISA::BranchEretA64::generateDisassembly(), gem5::ArmISA::SmeMovInsertOp::generateDisassembly(), gem5::ArmISA::SveStStructSS< Element, MicroopStMemType, MicroopIntrlvType >::generateDisassembly(), gem5::ArmISA::SrsOp::generateDisassembly(), gem5::ArmISA::DataX2RegOp::generateDisassembly(), gem5::ArmISA::SveWhileOp::generateDisassembly(), gem5::RegRegOp::generateDisassembly(), gem5::ArmISA::MemoryDImm64::generateDisassembly(), gem5::ArmISA::SmeOPOp::generateDisassembly(), gem5::ArmISA::BranchImmReg64::generateDisassembly(), gem5::RegOp::generateDisassembly(), gem5::ArmISA::DataX2RegImmOp::generateDisassembly(), gem5::ArmISA::MemoryDImmEx64::generateDisassembly(), gem5::MiscRegImmOp64::generateDisassembly(), gem5::ArmISA::SvePselOp::generateDisassembly(), gem5::ArmISA::SmeRdsvlOp::generateDisassembly(), gem5::ArmISA::MemoryPreIndex64::generateDisassembly(), gem5::ArmISA::DataX3RegOp::generateDisassembly(), gem5::RegImmRegOp::generateDisassembly(), gem5::ArmISA::BranchImmImmReg64::generateDisassembly(), gem5::ArmISA::SveCompTermOp::generateDisassembly(), gem5::MiscRegRegImmOp64::generateDisassembly(), gem5::ArmISA::SmeZeroOp::generateDisassembly(), gem5::ArmISA::MemoryPostIndex64::generateDisassembly(), gem5::ArmISA::ArmStaticInst::generateDisassembly(), gem5::ArmISA::DataXCondCompImmOp::generateDisassembly(), gem5::ArmISA::SveUnaryPredOp::generateDisassembly(), gem5::RegRegRegImmOp::generateDisassembly(), gem5::RegMiscRegImmOp64::generateDisassembly(), gem5::ArmISA::MemoryReg64::generateDisassembly(), gem5::ArmISA::SveLdStructSI< Element, MicroopLdMemType, MicroopDeIntrlvType >::generateDisassembly(), gem5::ArmISA::DataXCondCompRegOp::generateDisassembly(), gem5::ArmISA::SveUnaryUnpredOp::generateDisassembly(), gem5::RegRegRegRegOp::generateDisassembly(), gem5::ArmISA::MemoryRaw64::generateDisassembly(), gem5::ArmISA::PredImmOp::generateDisassembly(), gem5::ArmISA::DataXCondSelOp::generateDisassembly(), gem5::ArmISA::SveUnaryWideImmUnpredOp::generateDisassembly(), gem5::ArmISA::MemoryEx64::generateDisassembly(), gem5::RegRegRegOp::generateDisassembly(), gem5::ArmISA::PredIntOp::generateDisassembly(), gem5::RegNone::generateDisassembly(), gem5::ArmISA::MemoryLiteral64::generateDisassembly(), gem5::ArmISA::SveUnaryWideImmPredOp::generateDisassembly(), gem5::RegRegImmOp::generateDisassembly(), gem5::ArmISA::DataImmOp::generateDisassembly(), gem5::ArmISA::MicroSetPCCPSR::generateDisassembly(), gem5::ArmISA::MemoryAtomicPair64::generateDisassembly(), gem5::ArmISA::SveBinImmUnpredConstrOp::generateDisassembly(), gem5::MiscRegRegImmOp::generateDisassembly(), gem5::ArmISA::DataRegOp::generateDisassembly(), gem5::ArmISA::MicroIntMov::generateDisassembly(), gem5::ArmISA::SveStStructSI< Element, MicroopStMemType, MicroopIntrlvType >::generateDisassembly(), gem5::ArmISA::SveBinImmPredOp::generateDisassembly(), gem5::RegMiscRegImmOp::generateDisassembly(), gem5::ArmISA::DataRegRegOp::generateDisassembly(), gem5::ArmISA::MicroIntImmOp::generateDisassembly(), gem5::ArmISA::SveBinWideImmUnpredOp::generateDisassembly(), gem5::RegImmImmOp::generateDisassembly(), gem5::ArmISA::MicroIntImmXOp::generateDisassembly(), gem5::ArmISA::SveBinDestrPredOp::generateDisassembly(), gem5::RegRegImmImmOp::generateDisassembly(), gem5::ArmISA::MicroIntOp::generateDisassembly(), gem5::ArmISA::SveBinConstrPredOp::generateDisassembly(), gem5::ArmISA::PredMacroOp::generateDisassembly(), gem5::RegImmRegShiftOp::generateDisassembly(), gem5::ArmISA::SveBinUnpredOp::generateDisassembly(), gem5::ArmISA::MicroIntRegXOp::generateDisassembly(), gem5::ArmISA::MemoryOffset< Base >::generateDisassembly(), gem5::ArmISA::SveBinIdxUnpredOp::generateDisassembly(), gem5::ArmISA::SveIndexedMemVI< RegElemType, MemElemType, MicroopType, FirstFaultWritebackMicroopType >::generateDisassembly(), gem5::ArmISA::SvePredLogicalOp::generateDisassembly(), gem5::ArmISA::MicroMemOp::generateDisassembly(), gem5::ArmISA::SvePredBinPermOp::generateDisassembly(), gem5::ArmISA::MemoryPreIndex< Base >::generateDisassembly(), gem5::ArmISA::MicroMemPairOp::generateDisassembly(), gem5::ArmISA::SveCmpOp::generateDisassembly(), gem5::ArmISA::SveCmpImmOp::generateDisassembly(), gem5::ArmISA::SveTerPredOp::generateDisassembly(), gem5::ArmISA::MemoryPostIndex< Base >::generateDisassembly(), gem5::ArmISA::SveTerUnpredOp::generateDisassembly(), gem5::ArmISA::SveIndexedMemSV< RegElemType, MemElemType, MicroopType, FirstFaultWritebackMicroopType >::generateDisassembly(), gem5::ArmISA::SveTerImmUnpredOp::generateDisassembly(), gem5::ArmISA::SveReducOp::generateDisassembly(), gem5::ArmISA::SveOrdReducOp::generateDisassembly(), gem5::ArmISA::SvePtrueOp::generateDisassembly(), gem5::ArmISA::SveIntCmpOp::generateDisassembly(), gem5::ArmISA::SveIntCmpImmOp::generateDisassembly(), gem5::ArmISA::SveAdrOp::generateDisassembly(), gem5::ArmISA::SveElemCountOp::generateDisassembly(), gem5::ArmISA::SvePartBrkOp::generateDisassembly(), gem5::ArmISA::SvePartBrkPropOp::generateDisassembly(), gem5::ArmISA::SveSelectOp::generateDisassembly(), gem5::ArmISA::SveUnaryPredPredOp::generateDisassembly(), gem5::ArmISA::SveTblOp::generateDisassembly(), gem5::ArmISA::SveUnpackOp::generateDisassembly(), gem5::ArmISA::SvePredTestOp::generateDisassembly(), gem5::ArmISA::SvePredUnaryWImplicitSrcOp::generateDisassembly(), gem5::ArmISA::SvePredUnaryWImplicitSrcPredOp::generateDisassembly(), gem5::ArmISA::SvePredUnaryWImplicitDstOp::generateDisassembly(), gem5::ArmISA::SveWImplicitSrcDstOp::generateDisassembly(), gem5::ArmISA::SveBinImmUnpredDestrOp::generateDisassembly(), gem5::ArmISA::SveBinImmIdxUnpredOp::generateDisassembly(), gem5::ArmISA::SveUnarySca2VecUnpredOp::generateDisassembly(), gem5::ArmISA::FpCondCompRegOp::generateDisassembly(), gem5::ArmISA::SveDotProdIdxOp::generateDisassembly(), gem5::ArmISA::FpCondSelOp::generateDisassembly(), gem5::ArmISA::FpRegRegOp::generateDisassembly(), gem5::ArmISA::SveDotProdOp::generateDisassembly(), gem5::ArmISA::FpRegImmOp::generateDisassembly(), gem5::ArmISA::SveComplexOp::generateDisassembly(), gem5::ArmISA::FpRegRegImmOp::generateDisassembly(), gem5::ArmISA::SveComplexIdxOp::generateDisassembly(), gem5::ArmISA::FpRegRegRegOp::generateDisassembly(), gem5::ArmISA::SveClampOp::generateDisassembly(), gem5::ArmISA::FpRegRegRegCondOp::generateDisassembly(), gem5::ArmISA::FpRegRegRegRegOp::generateDisassembly(), gem5::ArmISA::FpRegRegRegImmOp::generateDisassembly(), and gem5::ArmISA::ArmStaticInst::getPSTATEFromPSR().

◆ ssc

Bitfield< 15, 14 > gem5::ArmISA::ssc

Definition at line 848 of file misc_types.hh.

Referenced by gem5::ArmISA::BrkPoint::isEnabled(), gem5::ArmISA::WatchPoint::isEnabled(), and gem5::ArmISA::SelfDebug::securityStateMatch().

◆ sse

Bitfield<21> gem5::ArmISA::sse

Definition at line 746 of file misc_types.hh.

◆ st

Bitfield< 11 > gem5::ArmISA::st

Definition at line 180 of file misc_types.hh.

Referenced by gem5::OutputDirectory::isFile(), and gem5::EventQueue::name().

◆ StackPointerReg

constexpr auto & gem5::ArmISA::StackPointerReg = int_reg::Sp

Definition at line 654 of file int.hh.

Referenced by gem5::PowerProcess::argsInit(), gem5::RiscvProcess::argsInit(), gem5::SparcProcess::argsInit(), gem5::ArmISA::ArmStaticInst::printIntReg(), gem5::trace::TarmacTracerRecordV8::TraceRegEntryV8::updateInt(), and gem5::trace::TarmacTracerRecord::TraceRegEntry::updateInt().

◆ status

Bitfield<5, 0> gem5::ArmISA::status

Definition at line 480 of file misc_types.hh.

Referenced by gem5::o3::CPU::addThreadToExitingList(), gem5::MipsISA::MipsFaultBase::base(), gem5::fastmodel::ScxEvsCortexA76< Types >::before_end_of_elaboration(), gem5::bindFunc(), gem5::ArmSemihosting::callIsError(), gem5::MipsISA::Interrupts::checkInterrupts(), gem5::RiscvISA::TLB::checkPermissions(), gem5::RiscvISA::ISA::clear(), gem5::FDArray::closeFDEntry(), gem5::MipsISA::ISA::configCP(), gem5::connectFunc(), gem5::RiscvISA::TLB::doTranslate(), gem5::o3::CPU::drainResume(), EndBitUnion(), gem5::scmi::EndBitUnion(), gem5::exitFunc(), gem5::exitGroupFunc(), gem5::exitImpl(), gem5::MipsISA::forkThread(), gem5::MipsISA::Interrupts::getInterrupt(), gem5::RiscvISA::TLB::getMemPriv(), gem5::getsocknameFunc(), gem5::getsockoptFunc(), gem5::fastmodel::GIC::GIC(), gem5::RiscvISA::Interrupts::globalMask(), gem5::RiscvISA::Walker::WalkerState::initState(), gem5::RiscvISA::RiscvFault::invoke(), gem5::MipsISA::ResetFault::invoke(), gem5::RiscvISA::Reset::invoke(), gem5::ioctlFunc(), gem5::listenFunc(), main(), gem5::ruby::Sequencer::makeRequest(), gem5::System::Threads::numRunning(), gem5::MipsISA::TlbRefillFault::offset(), gem5::VirtIOBlock::RequestQueue::onNotifyDescriptor(), gem5::IGbE::RxDescCache::pktComplete(), gem5::fastmodel::PL330::PL330(), gem5::pollFunc(), gem5::Pl050::read(), gem5::RiscvISA::ISA::readMiscReg(), gem5::ps2::PS2Mouse::recv(), sc_gem5::Gem5ToTlmBridge< BITWIDTH >::recvTimingReq(), gem5::AMDGPUMemoryManager::GPUMemPort::recvTimingResp(), gem5::sinic::Device::rxKick(), sc_gem5::TlmToGem5Bridge< BITWIDTH >::sendBeginResp(), sc_gem5::TlmToGem5Bridge< BITWIDTH >::sendEndReq(), gem5::ps2::PS2Mouse::serialize(), gem5::Pl050::serialize(), gem5::IdeController::Channel::serialize(), gem5::VirtIODeviceBase::setDeviceStatus(), gem5::MipsISA::MipsFaultBase::setExceptionState(), gem5::setsockoptFunc(), gem5::fastmodel::SignalReceiverInt::SignalReceiverInt(), gem5::socketpairFunc(), gem5::UFSHostDevice::UFSSCSIDevice::statusCheck(), gem5::RiscvISA::Walker::WalkerState::stepWalk(), gem5::DrainManager::tryDrain(), gem5::ps2::PS2Mouse::unserialize(), gem5::Pl050::unserialize(), gem5::IdeController::Channel::unserialize(), gem5::MipsISA::updateStatusView(), gem5::MipsISA::updateTCStatusView(), gem5::MinorCPU::wakeup(), gem5::o3::CPU::wakeup(), and gem5::PciVirtIO::write().

◆ stride

Bitfield<21, 20> gem5::ArmISA::stride

Definition at line 504 of file misc_types.hh.

Referenced by gem5::ruby::RubyPrefetcher::accessNonunitFilter(), gem5::ruby::RubyPrefetcher::accessUnitFilter(), gem5::ArmISA::VfpMacroOp::addStride(), gem5::Gcn3ISA::Inst_MUBUF::calcAddr(), gem5::VegaISA::Inst_MUBUF::calcAddr(), gem5::prefetch::AccessMapPatternMatching::calculatePrefetch(), gem5::prefetch::SignaturePath::calculatePrefetch(), gem5::prefetch::AccessMapPatternMatching::checkCandidate(), gem5::prefetch::SignaturePath::PatternEntry::findStride(), gem5::prefetch::SignaturePath::getSignatureEntry(), gem5::prefetch::SignaturePath::PatternEntry::getStrideEntry(), gem5::ruby::RubyPrefetcher::initializeStream(), gem5::prefetch::Queued::insert(), gem5::prefetch::Stride::StrideEntry::invalidate(), gem5::ruby::makeNextStrideAddress(), gem5::ArmISA::TableWalker::LongDescriptor::nextDescAddr(), gem5::ArmISA::VfpMacroOp::nextIdxs(), gem5::ComputeUnit::DTLBPort::recvTimingResp(), gem5::prefetch::SignaturePath::updatePatternTable(), and gem5::ArmISA::TableWalker::walkAddresses().

◆ su

Bitfield<1> gem5::ArmISA::su

Definition at line 919 of file misc_types.hh.

◆ subArchDefined

Bitfield<29, 0> gem5::ArmISA::subArchDefined

Definition at line 519 of file misc_types.hh.

◆ sve

Bitfield<35, 32> gem5::ArmISA::sve

Definition at line 197 of file misc_types.hh.

◆ sveLen

Bitfield<59, 56> gem5::ArmISA::sveLen

Definition at line 67 of file types.hh.

◆ sveVer

Bitfield<3, 0> gem5::ArmISA::sveVer

Definition at line 218 of file misc_types.hh.

◆ sw

Bitfield< 10 > gem5::ArmISA::sw

Definition at line 64 of file int.hh.

◆ swio

Bitfield<1> gem5::ArmISA::swio

Definition at line 338 of file misc_types.hh.

◆ syscallDescs32

SyscallDescTable<EmuFreebsd::SyscallABI32> gem5::ArmISA::syscallDescs32({})
static

Referenced by gem5::ArmISA::EmuFreebsd::syscall().

◆ syscallDescs32High

SyscallTable32 gem5::ArmISA::syscallDescs32High(0x900000)

◆ syscallDescs32Low

SyscallTable32 gem5::ArmISA::syscallDescs32Low(0)
static

Referenced by gem5::ArmISA::EmuLinux::syscall().

◆ syscallDescs64

SyscallDescTable<EmuFreebsd::SyscallABI64> gem5::ArmISA::syscallDescs64
static
Initial value:
= {
{ 1, "exit", exitFunc },
{ 3, "read", readFunc<ArmFreebsd64> },
{ 4, "write", writeFunc<ArmFreebsd64> },
{ 17, "obreak", brkFunc },
{ 54, "ioctl", ioctlFunc<ArmFreebsd64> },
{ 58, "readlink", readlinkFunc<ArmFreebsd64> },
{ 117, "getrusage", getrusageFunc<ArmFreebsd64> },
{ 189, "fstat", fstatFunc<ArmFreebsd64> },
{ 202, "sysctl", sysctlFunc },
{ 253, "issetugid", issetugidFunc },
{ 477, "mmap", mmapFunc<ArmFreebsd64> }
}

Definition at line 133 of file se_workload.cc.

Referenced by gem5::ArmISA::EmuFreebsd::syscall().

◆ syscallDescs64High

SyscallTable64 gem5::ArmISA::syscallDescs64High(0x900000)

◆ syscallDescs64Low

SyscallTable64 gem5::ArmISA::syscallDescs64Low(0)
static

Referenced by gem5::ArmISA::EmuLinux::syscall().

◆ SyscallNumReg

constexpr auto & gem5::ArmISA::SyscallNumReg = ReturnValueReg

Definition at line 657 of file int.hh.

◆ SyscallPseudoReturnReg

constexpr auto & gem5::ArmISA::SyscallPseudoReturnReg = ReturnValueReg

Definition at line 658 of file int.hh.

Referenced by gem5::guest_abi::Result< ABI, SyscallReturn, typename std::enable_if_t< std::is_base_of_v< ArmISA::EmuLinux::BaseSyscallABI, ABI > > >::store(), and gem5::guest_abi::Result< ABI, SyscallReturn, typename std::enable_if_t< std::is_base_of_v< ArmISA::EmuFreebsd::BaseSyscallABI, ABI > > >::store().

◆ SyscallSuccessReg

constexpr auto & gem5::ArmISA::SyscallSuccessReg = ReturnValueReg

Definition at line 659 of file int.hh.

◆ t

Bitfield<5> gem5::ArmISA::t

Definition at line 71 of file misc_types.hh.

Referenced by addPAC().

◆ t0

Bitfield<0> gem5::ArmISA::t0

Definition at line 283 of file misc_types.hh.

Referenced by fp16_sqrt(), fp32_sqrt(), fp64_muladd(), mul64x32(), and gem5::QARMA::PACMult().

◆ t0sz

gem5::ArmISA::t0sz

Definition at line 550 of file misc_types.hh.

◆ t0sz64

Bitfield<5, 0> gem5::ArmISA::t0sz64

Definition at line 620 of file misc_types.hh.

◆ t1

Bitfield<1> gem5::ArmISA::t1

Definition at line 282 of file misc_types.hh.

Referenced by gem5::ArmISA::Crypto::aesMixColumns(), gem5::ThreadContext::compare(), fp16_sqrt(), fp32_sqrt(), fp64_muladd(), gem5::igbreg::txd_op::isTypes(), mul64x32(), sc_core::operator/(), gem5::QARMA::PACMult(), gem5::PMP::pmpDecodeNapot(), gem5::Shader::sampleInstRoundTrip(), and TEST().

◆ t10

Bitfield<10> gem5::ArmISA::t10

Definition at line 273 of file misc_types.hh.

◆ t11

Bitfield<11> gem5::ArmISA::t11

Definition at line 272 of file misc_types.hh.

◆ t12

Bitfield<12> gem5::ArmISA::t12

Definition at line 271 of file misc_types.hh.

◆ t13

Bitfield<13> gem5::ArmISA::t13

Definition at line 270 of file misc_types.hh.

◆ t15

Bitfield<15> gem5::ArmISA::t15

Definition at line 269 of file misc_types.hh.

◆ t1sz

Bitfield< 21, 16 > gem5::ArmISA::t1sz

Definition at line 557 of file misc_types.hh.

◆ t2

Bitfield<2> gem5::ArmISA::t2

Definition at line 281 of file misc_types.hh.

Referenced by gem5::ThreadContext::compare(), gem5::igbreg::txd_op::isTypes(), sc_core::operator/(), gem5::QARMA::PACMult(), gem5::Shader::sampleInstRoundTrip(), and TEST().

◆ t2e

Bitfield<6> gem5::ArmISA::t2e

Definition at line 551 of file misc_types.hh.

◆ t3

Bitfield<3> gem5::ArmISA::t3

Definition at line 280 of file misc_types.hh.

Referenced by gem5::QARMA::PACMult(), gem5::Shader::sampleInstRoundTrip(), and TEST().

◆ t4

Bitfield<4> gem5::ArmISA::t4

Definition at line 279 of file misc_types.hh.

Referenced by gem5::Shader::sampleInstRoundTrip().

◆ t5

Bitfield<5> gem5::ArmISA::t5

Definition at line 278 of file misc_types.hh.

Referenced by gem5::Shader::sampleInstRoundTrip().

◆ t6

Bitfield<6> gem5::ArmISA::t6

Definition at line 277 of file misc_types.hh.

◆ t7

Bitfield<7> gem5::ArmISA::t7

Definition at line 276 of file misc_types.hh.

◆ t8

Bitfield<8> gem5::ArmISA::t8

Definition at line 275 of file misc_types.hh.

◆ t9

Bitfield<9> gem5::ArmISA::t9

Definition at line 274 of file misc_types.hh.

◆ tac

Bitfield<21> gem5::ArmISA::tac

Definition at line 317 of file misc_types.hh.

◆ tacr

Bitfield<21> gem5::ArmISA::tacr

Definition at line 318 of file misc_types.hh.

◆ tagRAMLatency

Bitfield<8,6> gem5::ArmISA::tagRAMLatency

Definition at line 683 of file misc_types.hh.

◆ tagRAMSetup

Bitfield<9> gem5::ArmISA::tagRAMSetup

Definition at line 684 of file misc_types.hh.

◆ tagRAMSlice

Bitfield<12> gem5::ArmISA::tagRAMSlice

Definition at line 686 of file misc_types.hh.

◆ tam

Bitfield<30> gem5::ArmISA::tam

Definition at line 786 of file misc_types.hh.

◆ tase

Bitfield<15> gem5::ArmISA::tase

Definition at line 247 of file misc_types.hh.

◆ tbi

Bitfield< 20 > gem5::ArmISA::tbi

Definition at line 572 of file misc_types.hh.

Referenced by addPAC(), auth(), calculateTBI(), computeAddrTop(), gem5::branch_prediction::TAGE_SC_L_TAGE::getUseAltIdx(), and stripPAC().

◆ tbi0

Bitfield< 37 > gem5::ArmISA::tbi0

Definition at line 566 of file misc_types.hh.

◆ tbi1

Bitfield< 38 > gem5::ArmISA::tbi1

Definition at line 567 of file misc_types.hh.

◆ tbid

Bitfield<29> gem5::ArmISA::tbid

Definition at line 595 of file misc_types.hh.

Referenced by computeAddrTop().

◆ tbid0

Bitfield<51> gem5::ArmISA::tbid0

Definition at line 605 of file misc_types.hh.

◆ tbid1

Bitfield<52> gem5::ArmISA::tbid1

Definition at line 606 of file misc_types.hh.

◆ tcp0

Bitfield<0> gem5::ArmISA::tcp0

Definition at line 263 of file misc_types.hh.

◆ tcp1

Bitfield<1> gem5::ArmISA::tcp1

Definition at line 262 of file misc_types.hh.

◆ tcp10

Bitfield<10> gem5::ArmISA::tcp10

Definition at line 251 of file misc_types.hh.

◆ tcp11

Bitfield<11> gem5::ArmISA::tcp11

Definition at line 250 of file misc_types.hh.

◆ tcp12

Bitfield<12> gem5::ArmISA::tcp12

Definition at line 249 of file misc_types.hh.

◆ tcp13

Bitfield<13> gem5::ArmISA::tcp13

Definition at line 248 of file misc_types.hh.

◆ tcp2

Bitfield<2> gem5::ArmISA::tcp2

Definition at line 261 of file misc_types.hh.

◆ tcp3

Bitfield<3> gem5::ArmISA::tcp3

Definition at line 260 of file misc_types.hh.

◆ tcp4

Bitfield<4> gem5::ArmISA::tcp4

Definition at line 259 of file misc_types.hh.

◆ tcp5

Bitfield<5> gem5::ArmISA::tcp5

Definition at line 258 of file misc_types.hh.

◆ tcp6

Bitfield<6> gem5::ArmISA::tcp6

Definition at line 257 of file misc_types.hh.

◆ tcp7

Bitfield<7> gem5::ArmISA::tcp7

Definition at line 256 of file misc_types.hh.

◆ tcp8

Bitfield<8> gem5::ArmISA::tcp8

Definition at line 254 of file misc_types.hh.

◆ tcp9

Bitfield<9> gem5::ArmISA::tcp9

Definition at line 253 of file misc_types.hh.

◆ tda

Bitfield< 21 > gem5::ArmISA::tda

Definition at line 236 of file misc_types.hh.

◆ tdcc

Bitfield<12> gem5::ArmISA::tdcc

Definition at line 890 of file misc_types.hh.

◆ tde

Bitfield<8> gem5::ArmISA::tde

Definition at line 237 of file misc_types.hh.

◆ tdosa

Bitfield<10> gem5::ArmISA::tdosa

Definition at line 235 of file misc_types.hh.

◆ tdra

Bitfield<11> gem5::ArmISA::tdra

Definition at line 234 of file misc_types.hh.

◆ tdz

Bitfield<28> gem5::ArmISA::tdz

Definition at line 310 of file misc_types.hh.

◆ te

Bitfield<30> gem5::ArmISA::te

Definition at line 394 of file misc_types.hh.

Referenced by gem5::ArmISA::MMU::checkPermissions(), gem5::ArmISA::MMU::checkPermissions64(), gem5::ArmISA::TableWalker::doL1Descriptor(), gem5::ArmISA::TableWalker::doL2Descriptor(), gem5::ArmISA::TableWalker::doLongDescriptor(), gem5::ArmISA::TLB::flush(), gem5::ArmISA::TLB::flushAll(), gem5::ArmISA::MMU::getResultTe(), gem5::ArmISA::MMU::getTE(), gem5::ArmISA::TableWalker::insertPartialTableEntry(), gem5::ArmISA::TableWalker::insertTableEntry(), gem5::ArmISA::TLBIALL::match(), gem5::ArmISA::ITLBIALL::match(), gem5::ArmISA::DTLBIALL::match(), gem5::ArmISA::TLBIALLEL::match(), gem5::ArmISA::TLBIVMALL::match(), gem5::ArmISA::TLBIASID::match(), gem5::ArmISA::ITLBIASID::match(), gem5::ArmISA::DTLBIASID::match(), gem5::ArmISA::TLBIALLN::match(), gem5::ArmISA::TLBIMVAA::match(), gem5::ArmISA::TLBIMVA::match(), gem5::ArmISA::ITLBIMVA::match(), gem5::ArmISA::DTLBIMVA::match(), gem5::ArmISA::TableWalker::memAttrs(), gem5::ArmISA::TableWalker::memAttrsAArch64(), gem5::ArmISA::TableWalker::memAttrsLPAE(), gem5::ArmISA::TLB::multiLookup(), gem5::ArmISA::TLB::printTlb(), gem5::ArmISA::TableWalker::processWalkWrapper(), gem5::ArmISA::MMU::s1PermBits64(), gem5::ArmISA::MMU::s2PermBits64(), and gem5::ArmISA::MMU::translateMmuOn().

◆ tea

Bitfield<37> gem5::ArmISA::tea

Definition at line 301 of file misc_types.hh.

◆ teer

Bitfield<15> gem5::ArmISA::teer

Definition at line 372 of file misc_types.hh.

◆ terr

Bitfield<36> gem5::ArmISA::terr

Definition at line 302 of file misc_types.hh.

◆ tfp

Bitfield< 10 > gem5::ArmISA::tfp

Definition at line 252 of file misc_types.hh.

◆ tg0

Bitfield< 15, 14 > gem5::ArmISA::tg0

Definition at line 556 of file misc_types.hh.

◆ tg1

Bitfield< 31, 30 > gem5::ArmISA::tg1

Definition at line 563 of file misc_types.hh.

◆ tge

Bitfield<27> gem5::ArmISA::tge

Definition at line 311 of file misc_types.hh.

◆ tgran16

Bitfield<23, 20> gem5::ArmISA::tgran16

Definition at line 152 of file misc_types.hh.

◆ tgran16_2

Bitfield<35, 32> gem5::ArmISA::tgran16_2

Definition at line 149 of file misc_types.hh.

◆ tgran4

Bitfield<31, 28> gem5::ArmISA::tgran4

Definition at line 150 of file misc_types.hh.

◆ tgran4_2

Bitfield<43, 40> gem5::ArmISA::tgran4_2

Definition at line 147 of file misc_types.hh.

◆ tgran64

Bitfield<27, 24> gem5::ArmISA::tgran64

Definition at line 151 of file misc_types.hh.

◆ tgran64_2

Bitfield<39, 36> gem5::ArmISA::tgran64_2

Definition at line 148 of file misc_types.hh.

◆ thee

Bitfield<6> gem5::ArmISA::thee

Definition at line 442 of file misc_types.hh.

◆ thumb

Bitfield<36> gem5::ArmISA::thumb

Definition at line 79 of file types.hh.

Referenced by gem5::ArmISA::BrkPoint::testAddrMatch(), and gem5::ArmISA::BrkPoint::testAddrMissMatch().

◆ ticab

Bitfield<50> gem5::ArmISA::ticab

Definition at line 290 of file misc_types.hh.

◆ tid0

Bitfield<15> gem5::ArmISA::tid0

Definition at line 324 of file misc_types.hh.

◆ tid1

Bitfield<16> gem5::ArmISA::tid1

Definition at line 323 of file misc_types.hh.

◆ tid2

Bitfield<17> gem5::ArmISA::tid2

Definition at line 322 of file misc_types.hh.

◆ tid3

Bitfield<18> gem5::ArmISA::tid3

Definition at line 321 of file misc_types.hh.

◆ tid4

Bitfield<49> gem5::ArmISA::tid4

Definition at line 291 of file misc_types.hh.

◆ tidcp

Bitfield<20> gem5::ArmISA::tidcp

Definition at line 319 of file misc_types.hh.

◆ tlb

Bitfield<59, 56> gem5::ArmISA::tlb

Definition at line 113 of file misc_types.hh.

Referenced by gem5::ArmISA::MMU::checkWalkCache(), gem5::ArmISA::MMU::dflush(), gem5::X86ISA::TLB::evictLRU(), gem5::BaseMMU::flushAll(), gem5::ArmISA::MMU::flushStage1(), gem5::ArmISA::MMU::iflush(), gem5::BaseMMU::init(), gem5::AMDGPUVM::invalidateTLBs(), gem5::ArmISA::MMU::lookup(), gem5::ArmISA::TLB::multiLookup(), gem5::AMDGPUVM::registerTLB(), gem5::RiscvISA::TLB::remove(), gem5::ArmISA::MMU::translateFunctional(), and gem5::ArmISA::MMU::updateMiscReg().

◆ tlor

Bitfield< 14 > gem5::ArmISA::tlor

Definition at line 303 of file misc_types.hh.

◆ tme

Bitfield<27, 24> gem5::ArmISA::tme

Definition at line 121 of file misc_types.hh.

◆ tocu

Bitfield<52> gem5::ArmISA::tocu

Definition at line 289 of file misc_types.hh.

◆ top6

Bitfield<7, 2> gem5::ArmISA::top6

Definition at line 65 of file pcstate.hh.

◆ topcode10_8

Bitfield<10, 8> gem5::ArmISA::topcode10_8

Definition at line 166 of file types.hh.

◆ topcode10_9

Bitfield<10, 9> gem5::ArmISA::topcode10_9

Definition at line 165 of file types.hh.

◆ topcode11_8

Bitfield<11, 8> gem5::ArmISA::topcode11_8

Definition at line 164 of file types.hh.

◆ topcode11_9

Bitfield<11, 9> gem5::ArmISA::topcode11_9

Definition at line 163 of file types.hh.

◆ topcode12_10

Bitfield<12, 10> gem5::ArmISA::topcode12_10

Definition at line 162 of file types.hh.

◆ topcode12_11

Bitfield<12, 11> gem5::ArmISA::topcode12_11

Definition at line 161 of file types.hh.

◆ topcode13_11

Bitfield<13, 11> gem5::ArmISA::topcode13_11

Definition at line 160 of file types.hh.

◆ topcode15_13

Bitfield<15, 13> gem5::ArmISA::topcode15_13

Definition at line 159 of file types.hh.

◆ topcode3_0

Bitfield<3, 0> gem5::ArmISA::topcode3_0

Definition at line 172 of file types.hh.

◆ topcode7

Bitfield<7> gem5::ArmISA::topcode7

Definition at line 168 of file types.hh.

◆ topcode7_4

Bitfield<7, 4> gem5::ArmISA::topcode7_4

Definition at line 171 of file types.hh.

◆ topcode7_5

Bitfield<7, 5> gem5::ArmISA::topcode7_5

Definition at line 170 of file types.hh.

◆ topcode7_6

Bitfield<7, 6> gem5::ArmISA::topcode7_6

Definition at line 169 of file types.hh.

◆ topcode9_6

Bitfield<9, 6> gem5::ArmISA::topcode9_6

Definition at line 167 of file types.hh.

◆ tpc

Bitfield<23> gem5::ArmISA::tpc

Definition at line 315 of file misc_types.hh.

◆ tpm

Bitfield<6> gem5::ArmISA::tpm

Definition at line 239 of file misc_types.hh.

◆ tpmcr

Bitfield<5> gem5::ArmISA::tpmcr

Definition at line 240 of file misc_types.hh.

◆ tpu

Bitfield<24> gem5::ArmISA::tpu

Definition at line 314 of file misc_types.hh.

◆ tr0

gem5::ArmISA::tr0

Definition at line 633 of file misc_types.hh.

◆ tr1

Bitfield<3,2> gem5::ArmISA::tr1

Definition at line 634 of file misc_types.hh.

◆ tr2

Bitfield<5,4> gem5::ArmISA::tr2

Definition at line 635 of file misc_types.hh.

◆ tr3

Bitfield<7,6> gem5::ArmISA::tr3

Definition at line 636 of file misc_types.hh.

◆ tr4

Bitfield<9,8> gem5::ArmISA::tr4

Definition at line 637 of file misc_types.hh.

◆ tr5

Bitfield<11,10> gem5::ArmISA::tr5

Definition at line 638 of file misc_types.hh.

◆ tr6

Bitfield<13,12> gem5::ArmISA::tr6

Definition at line 639 of file misc_types.hh.

◆ tr7

Bitfield<15,14> gem5::ArmISA::tr7

Definition at line 640 of file misc_types.hh.

◆ tracefilt

gem5::ArmISA::tracefilt

Definition at line 100 of file misc_types.hh.

◆ tracever

Bitfield<7, 4> gem5::ArmISA::tracever

Definition at line 107 of file misc_types.hh.

◆ tre

Bitfield<28> gem5::ArmISA::tre

Definition at line 396 of file misc_types.hh.

◆ trvm

Bitfield<30> gem5::ArmISA::trvm

Definition at line 308 of file misc_types.hh.

◆ ts

Bitfield<55, 52> gem5::ArmISA::ts

Definition at line 114 of file misc_types.hh.

Referenced by sc_gem5::Scheduler::acquireTimeSlot(), gem5::PosixKvmTimer::arm(), gem5::PosixKvmTimer::calcResolution(), sc_gem5::Scheduler::clear(), sc_gem5::Scheduler::completeTimeSlot(), sc_gem5::Scheduler::deschedule(), gem5::PosixKvmTimer::disarm(), gem5::floorLog2(), gem5::Time::operator=(), sc_gem5::Scheduler::releaseTimeSlot(), gem5::sleep(), and gem5::Time::Time().

◆ tsc

Bitfield<19> gem5::ArmISA::tsc

Definition at line 320 of file misc_types.hh.

◆ tsm

Bitfield<12> gem5::ArmISA::tsm

Definition at line 795 of file misc_types.hh.

◆ tsw

Bitfield<22> gem5::ArmISA::tsw

Definition at line 316 of file misc_types.hh.

◆ tta

Bitfield< 20 > gem5::ArmISA::tta

Definition at line 246 of file misc_types.hh.

◆ tta_e2h

Bitfield<28> gem5::ArmISA::tta_e2h

Definition at line 787 of file misc_types.hh.

◆ ttee

Bitfield<16> gem5::ArmISA::ttee

Definition at line 268 of file misc_types.hh.

◆ ttl

Bitfield<51, 48> gem5::ArmISA::ttl

Definition at line 176 of file misc_types.hh.

◆ ttlb

Bitfield<25> gem5::ArmISA::ttlb

Definition at line 313 of file misc_types.hh.

◆ ttlbis

Bitfield<54> gem5::ArmISA::ttlbis

Definition at line 288 of file misc_types.hh.

◆ tvm

Bitfield<26> gem5::ArmISA::tvm

Definition at line 312 of file misc_types.hh.

◆ twe

Bitfield< 13 > gem5::ArmISA::twe

Definition at line 325 of file misc_types.hh.

◆ twi

Bitfield< 12 > gem5::ArmISA::twi

Definition at line 326 of file misc_types.hh.

◆ txfull

Bitfield<29> gem5::ArmISA::txfull

Definition at line 874 of file misc_types.hh.

◆ txu

Bitfield<26> gem5::ArmISA::txu

Definition at line 877 of file misc_types.hh.

◆ tz

Bitfield< 8 > gem5::ArmISA::tz

Definition at line 255 of file misc_types.hh.

Referenced by gem5::mkutctime().

◆ u

Bitfield<22> gem5::ArmISA::u

Definition at line 409 of file misc_types.hh.

Referenced by gem5::bitsToFloat32(), gem5::bitsToFloat64(), sc_dt::div_by_zero(), gem5::floatToBits32(), gem5::floatToBits64(), fp16_cvtf(), fp32_cvtf(), fp64_cvtf(), fplibFixedToFP(), fplibFPToFixed(), FPToFixed_16(), FPToFixed_32(), FPToFixed_64(), sc_core::sc_time::from_value(), gem5::branch_prediction::MPP_TAGE::handleUReset(), gem5::branch_prediction::TAGE_SC_L_TAGE::handleUReset(), gem5::branch_prediction::TAGEBase::handleUReset(), gem5::ArmISA::MiscRegLUTEntryInitializer::mapsTo(), tlm_utils::callback_binder_bw< tlm::tlm_base_protocol_types >::nb_transport_bw(), sc_core::sc_prim_channel::next_trigger(), sc_core::sc_module::next_trigger(), sc_core::next_trigger(), sc_gem5::Event::notify(), sc_core::sc_event::notify(), sc_dt::operator!=(), sc_dt::operator%(), sc_dt::operator&(), sc_dt::operator*(), sc_dt::operator+(), sc_dt::operator-(), sc_dt::operator/(), sc_dt::operator<(), sc_dt::operator<<(), sc_dt::operator<=(), sc_dt::operator==(), sc_dt::operator>(), sc_dt::operator>=(), sc_dt::operator>>(), sc_dt::operator^(), sc_dt::operator|(), gem5::SparcISA::SparcStaticInst::passesFpCondition(), gem5::branch_prediction::TAGE_SC_L_TAGE_8KB::resetUctr(), gem5::branch_prediction::MPP_TAGE::resetUctr(), gem5::branch_prediction::TAGEBase::resetUctr(), BitUnionData::templatedFunction(), tlm::tlm_generic_payload::update_original_from(), sc_dt::vec_add_small(), sc_dt::vec_complement(), sc_dt::vec_copy(), sc_dt::vec_copy_and_zero(), sc_dt::vec_div_small(), sc_dt::vec_find_first_nonzero(), sc_dt::vec_from_char(), sc_dt::vec_mul_small_on(), sc_dt::vec_sub_on(), sc_dt::vec_sub_on2(), sc_dt::vec_sub_small(), sc_dt::vec_to_char(), sc_core::sc_prim_channel::wait(), sc_core::sc_module::wait(), and sc_core::wait().

◆ uao

Bitfield< 7, 4 > gem5::ArmISA::uao

Definition at line 58 of file misc_types.hh.

Referenced by gem5::ArmISA::ISA::setMiscReg().

◆ uci

Bitfield<26> gem5::ArmISA::uci

Definition at line 399 of file misc_types.hh.

◆ uct

Bitfield<15> gem5::ArmISA::uct

Definition at line 423 of file misc_types.hh.

◆ udccdis

Bitfield<12> gem5::ArmISA::udccdis

Definition at line 889 of file misc_types.hh.

◆ ufc

Bitfield<3> gem5::ArmISA::ufc

Definition at line 493 of file misc_types.hh.

◆ ufe

Bitfield<11> gem5::ArmISA::ufe

Definition at line 499 of file misc_types.hh.

◆ uh0

Bitfield<15, 0> gem5::ArmISA::uh0

Definition at line 60 of file int.hh.

◆ uh1

gem5::ArmISA::uh1

Definition at line 59 of file int.hh.

◆ uma

Bitfield<9> gem5::ArmISA::uma

Definition at line 435 of file misc_types.hh.

◆ unflattenResultMiscReg

int gem5::ArmISA::unflattenResultMiscReg[NUM_MISCREGS]

If the reg is a child reg of a banked set, then the parent is the last banked one in the list.

This is messy, and the wish is to eventually have the bitmap replaced with a better data structure. the preUnflatten function initializes a lookup table to speed up the search for these banked registers.

Definition at line 704 of file misc.cc.

Referenced by preUnflattenMiscReg(), and unflattenMiscReg().

◆ up

Bitfield<23> gem5::ArmISA::up

Definition at line 124 of file types.hh.

Referenced by gem5::ArmISA::MacroMemOp::MacroMemOp(), gem5::ArmISA::MacroVFPMemOp::MacroVFPMemOp(), gem5::branch_prediction::LoopPredictor::signedCtrUpdate(), gem5::branch_prediction::LoopPredictor::unsignedCtrUpdate(), and gem5::branch_prediction::TAGEBase::unsignedCtrUpdate().

◆ useImm

Bitfield<25> gem5::ArmISA::useImm

Definition at line 91 of file types.hh.

◆ uw

Bitfield<31, 0> gem5::ArmISA::uw

Definition at line 63 of file int.hh.

Referenced by gem5::ArmISA::MMU::s1PermBits64().

◆ uwxn

Bitfield<20> gem5::ArmISA::uwxn

Definition at line 412 of file misc_types.hh.

◆ v

Bitfield< 28 > gem5::ArmISA::v

Definition at line 54 of file misc_types.hh.

Referenced by gem5::ArmISA::MiscRegLUTEntryInitializer::allPrivileges(), gem5::ArmISA::MiscRegLUTEntryInitializer::banked(), gem5::ArmISA::MiscRegLUTEntryInitializer::banked64(), gem5::ArmISA::MiscRegLUTEntryInitializer::bankedChild(), gem5::ArmISA::WatchPoint::compareAddress(), gem5::ArmISA::RemoteGDB::AArch64GdbRegCache::getRegs(), gem5::ArmISA::MiscRegLUTEntryInitializer::hyp(), gem5::ArmISA::MiscRegLUTEntryInitializer::hypNonSecureRead(), gem5::ArmISA::MiscRegLUTEntryInitializer::hypNonSecureWrite(), gem5::ArmISA::MiscRegLUTEntryInitializer::hypRead(), gem5::ArmISA::MiscRegLUTEntryInitializer::hypSecure(), gem5::ArmISA::MiscRegLUTEntryInitializer::hypSecureRead(), gem5::ArmISA::MiscRegLUTEntryInitializer::hypSecureWrite(), gem5::ArmISA::MiscRegLUTEntryInitializer::hypWrite(), gem5::ArmISA::MiscRegLUTEntryInitializer::implemented(), gem5::ArmISA::BrkPoint::isEnabled(), gem5::ArmISA::WatchPoint::isEnabled(), gem5::ArmISA::TlbEntry::match(), gem5::ArmISA::MiscRegLUTEntryInitializer::mon(), gem5::ArmISA::MiscRegLUTEntryInitializer::monNonSecure(), gem5::ArmISA::MiscRegLUTEntryInitializer::monNonSecureRead(), gem5::ArmISA::MiscRegLUTEntryInitializer::monNonSecureWrite(), gem5::ArmISA::MiscRegLUTEntryInitializer::monSecure(), gem5::ArmISA::MiscRegLUTEntryInitializer::monSecureRead(), gem5::ArmISA::MiscRegLUTEntryInitializer::monSecureWrite(), gem5::ArmISA::MiscRegLUTEntryInitializer::mutex(), gem5::ArmISA::MiscRegLUTEntryInitializer::nonSecure(), gem5::ArmISA::MiscRegLUTEntryInitializer::priv(), gem5::ArmISA::MiscRegLUTEntryInitializer::privNonSecure(), gem5::ArmISA::MiscRegLUTEntryInitializer::privNonSecureRead(), gem5::ArmISA::MiscRegLUTEntryInitializer::privNonSecureWrite(), gem5::ArmISA::MiscRegLUTEntryInitializer::privRead(), gem5::ArmISA::MiscRegLUTEntryInitializer::privSecure(), gem5::ArmISA::MiscRegLUTEntryInitializer::privSecureRead(), gem5::ArmISA::MiscRegLUTEntryInitializer::privSecureWrite(), gem5::trace::TarmacParserRecord::TarmacParserRecordEvent::process(), gem5::ArmISA::MiscRegLUTEntryInitializer::reads(), gem5::ArmISA::MiscRegLUTEntryInitializer::secure(), gem5::ArmISA::ISA::setMiscReg(), gem5::ArmISA::ISA::setMiscRegNoEffect(), gem5::ArmISA::RemoteGDB::AArch64GdbRegCache::setRegs(), gem5::ArmISA::BrkPoint::test(), gem5::ArmISA::WatchPoint::test(), gem5::ArmISA::BrkPoint::testContextMatch(), testPredicate(), gem5::ArmISA::BrkPoint::testVMIDMatch(), gem5::ArmISA::MiscRegLUTEntryInitializer::unserialize(), gem5::ArmISA::MiscRegLUTEntryInitializer::unverifiable(), gem5::ArmISA::MiscRegLUTEntryInitializer::user(), gem5::ArmISA::MiscRegLUTEntryInitializer::userNonSecureRead(), gem5::ArmISA::MiscRegLUTEntryInitializer::userNonSecureWrite(), gem5::ArmISA::MiscRegLUTEntryInitializer::userSecureRead(), gem5::ArmISA::MiscRegLUTEntryInitializer::userSecureWrite(), gem5::ArmISA::MiscRegLUTEntryInitializer::warnNotFail(), gem5::ArmISA::MiscRegLUTEntryInitializer::writes(), and gem5::ArmISA::ISA::zeroSveVecRegUpperPart().

◆ va

Bitfield<8> gem5::ArmISA::va

Definition at line 330 of file misc_types.hh.

Referenced by gem5::ArmISA::RemoteGDB::acc(), gem5::X86ISA::TLB::demapPage(), gem5::VegaISA::GpuTLB::demapPage(), gem5::X86ISA::GpuTLB::demapPage(), gem5::SparcISA::TLB::demapPage(), gem5::SparcISA::TLB::doMmuRegRead(), gem5::SparcISA::TLB::doMmuRegWrite(), gem5::ArmISA::AbortFault< DataAbort >::getFaultVAddr(), getFaultVAddr(), gem5::ArmISA::V7LPageTableOps::index(), gem5::ArmISA::V8PageTableOps4k::index(), gem5::ArmISA::V8PageTableOps16k::index(), gem5::ArmISA::V8PageTableOps64k::index(), gem5::SparcISA::TLB::insert(), gem5::SMMUTLB::invalidateVA(), gem5::ARMArchTLB::invalidateVA(), gem5::WalkCache::invalidateVA(), gem5::SMMUTLB::invalidateVAA(), gem5::ARMArchTLB::invalidateVAA(), gem5::WalkCache::invalidateVAA(), gem5::X86ISA::TLB::lookup(), gem5::VegaISA::GpuTLB::lookup(), gem5::X86ISA::GpuTLB::lookup(), gem5::SparcISA::TLB::lookup(), gem5::SMMUTLB::lookup(), gem5::ARMArchTLB::lookup(), gem5::WalkCache::lookup(), gem5::ArmISA::MMU::lookup(), gem5::X86ISA::GpuTLB::lookupIt(), gem5::VegaISA::GpuTLB::lookupIt(), gem5::ArmISA::TableWalker::LongDescriptor::nextDescAddr(), gem5::ArmISA::TableWalker::L1Descriptor::paddr(), gem5::ArmISA::TlbEntry::pAddr(), gem5::ArmISA::TableWalker::L2Descriptor::paddr(), gem5::SMMUTLB::pickSetIdx(), gem5::ARMArchTLB::pickSetIdx(), gem5::IPACache::pickSetIdx(), gem5::WalkCache::pickSetIdx(), gem5::ArmISA::MMU::testWalk(), gem5::ArmISA::MMU::translateFunctional(), gem5::SparcISA::TLB::validVirtualAddress(), gem5::SMMUTranslationProcess::walkCacheUpdate(), and gem5::SparcISA::TLB::writeTagAccess().

◆ varange

Bitfield<19, 16> gem5::ArmISA::varange

Definition at line 183 of file misc_types.hh.

◆ vcma

gem5::ArmISA::vcma

Definition at line 79 of file misc_types.hh.

◆ vecElemClass

constexpr RegClass gem5::ArmISA::vecElemClass
inlineconstexpr
Initial value:
=
RegClass(VecElemClass, VecElemClassName, NumVecRegs * NumVecElemPerVecReg,
debug::VecRegs).
ops(vecRegElemClassOps)

Definition at line 105 of file vec.hh.

Referenced by gem5::ArmISA::ISA::copyRegsFrom(), gem5::guest_abi::Argument< Aapcs32Vfp, Float, typename std::enable_if_t< std::is_floating_point_v< Float > > >::get(), gem5::X86ISA::ISA::ISA(), gem5::PowerISA::ISA::ISA(), gem5::RiscvISA::ISA::ISA(), gem5::MipsISA::ISA::ISA(), gem5::SparcISA::ISA::ISA(), gem5::ArmISA::ISA::ISA(), gem5::trace::TarmacParserRecord::TarmacParserRecordEvent::process(), gem5::guest_abi::Result< Aapcs32Vfp, Float, typename std::enable_if_t< std::is_floating_point_v< Float > > >::store(), syncVecElemsToRegs(), and syncVecRegsToElems().

◆ vecPredRegClass

constexpr RegClass gem5::ArmISA::vecPredRegClass
inlineconstexpr
Initial value:
=
RegClass(VecPredRegClass, VecPredRegClassName, NumVecPredRegs,
debug::VecPredRegs).
ops(vecPredRegClassOps).
regType<VecPredRegContainer>()

Definition at line 109 of file vec.hh.

Referenced by gem5::X86ISA::ISA::ISA(), gem5::PowerISA::ISA::ISA(), gem5::RiscvISA::ISA::ISA(), gem5::MipsISA::ISA::ISA(), gem5::SparcISA::ISA::ISA(), gem5::ArmISA::ISA::ISA(), gem5::trace::TarmacParserRecord::TarmacParserRecordEvent::process(), gem5::Iris::ThreadContext::readVecPredRegFlat(), gem5::ArmISA::HTMCheckpoint::restore(), and gem5::ArmISA::HTMCheckpoint::save().

◆ vecPredRegClassOps

TypedRegClassOps<ArmISA::VecPredRegContainer> gem5::ArmISA::vecPredRegClassOps
inlinestatic

Definition at line 99 of file vec.hh.

◆ VecPredRegSizeBits

constexpr unsigned gem5::ArmISA::VecPredRegSizeBits = MaxSveVecLenInBytes
constexpr

Definition at line 474 of file types.hh.

◆ VECREG_UREG0

const int gem5::ArmISA::VECREG_UREG0 = 32

Definition at line 92 of file vec.hh.

Referenced by gem5::ArmISA::SveIndexedMemSV< RegElemType, MemElemType, MicroopType, FirstFaultWritebackMicroopType >::SveIndexedMemSV(), and gem5::ArmISA::SveIndexedMemVI< RegElemType, MemElemType, MicroopType, FirstFaultWritebackMicroopType >::SveIndexedMemVI().

◆ vecRegClass

constexpr RegClass gem5::ArmISA::vecRegClass
inlineconstexpr
Initial value:
=
RegClass(VecRegClass, VecRegClassName, NumVecRegs, debug::VecRegs).
ops(vecRegClassOps).
regType<VecRegContainer>()

Definition at line 101 of file vec.hh.

Referenced by gem5::ArmISA::ISA::copyRegsFrom(), gem5::guest_abi::Argument< Aapcs32Vfp, HA, typename std::enable_if_t< IsAapcs32HomogeneousAggregateV< HA > > >::get(), gem5::ArmISA::RemoteGDB::AArch64GdbRegCache::getRegs(), gem5::X86ISA::ISA::ISA(), gem5::PowerISA::ISA::ISA(), gem5::RiscvISA::ISA::ISA(), gem5::MipsISA::ISA::ISA(), gem5::SparcISA::ISA::ISA(), gem5::ArmISA::ISA::ISA(), gem5::trace::TarmacParserRecord::TarmacParserRecordEvent::process(), gem5::Iris::ThreadContext::readVecRegFlat(), gem5::ArmISA::HTMCheckpoint::restore(), gem5::ArmISA::HTMCheckpoint::save(), gem5::ArmISA::RemoteGDB::AArch64GdbRegCache::setRegs(), gem5::guest_abi::Result< Aapcs32Vfp, HA, typename std::enable_if_t< IsAapcs32HomogeneousAggregateV< HA > > >::store(), syncVecElemsToRegs(), syncVecRegsToElems(), gem5::trace::ArmNativeTrace::ThreadState::update(), gem5::ArmV8KvmCPU::updateKvmState(), and gem5::ArmV8KvmCPU::updateThreadContext().

◆ vecRegClassOps

TypedRegClassOps<ArmISA::VecRegContainer> gem5::ArmISA::vecRegClassOps
inlinestatic

Definition at line 98 of file vec.hh.

◆ vecRegElemClassOps

VecElemRegClassOps<RegVal> gem5::ArmISA::vecRegElemClassOps(NumVecElemPerVecReg)
inlinestatic

◆ VecRegSizeBytes

constexpr unsigned gem5::ArmISA::VecRegSizeBytes = MaxSveVecLenInBytes
constexpr

Definition at line 473 of file types.hh.

◆ VecSpecialElem

const int gem5::ArmISA::VecSpecialElem = NumVecV8ArchRegs * NumVecElemPerNeonVecReg

Definition at line 87 of file vec.hh.

Referenced by gem5::ArmISA::VldMultOp::VldMultOp(), gem5::ArmISA::VldSingleOp::VldSingleOp(), gem5::ArmISA::VstMultOp::VstMultOp(), and gem5::ArmISA::VstSingleOp::VstSingleOp().

◆ vectorcatch

Bitfield<15,12> gem5::ArmISA::vectorcatch

Definition at line 928 of file misc_types.hh.

◆ vf

Bitfield<6> gem5::ArmISA::vf

Definition at line 333 of file misc_types.hh.

◆ vfpExceptionTrapping

Bitfield<15, 12> gem5::ArmISA::vfpExceptionTrapping

Definition at line 526 of file misc_types.hh.

◆ vfpHalfPrecision

Bitfield<27, 24> gem5::ArmISA::vfpHalfPrecision

Definition at line 540 of file misc_types.hh.

◆ vh

Bitfield<11, 8> gem5::ArmISA::vh

Definition at line 167 of file misc_types.hh.

◆ vi

Bitfield<7> gem5::ArmISA::vi

Definition at line 332 of file misc_types.hh.

◆ virtextns

Bitfield<19,16> gem5::ArmISA::virtextns

Definition at line 927 of file misc_types.hh.

◆ vm

Bitfield<0> gem5::ArmISA::vm

Definition at line 339 of file misc_types.hh.

Referenced by gem5::MuxingKvmGic< Types >::drainResume(), gem5::MuxingKvmGic< Types >::MuxingKvmGic(), gem5::ArchTimerKvm::scheduleEvents(), gem5::System::setKvmVM(), gem5::MuxingKvmGic< Types >::startup(), gem5::AMDGPUVM::GARTTranslationGen::translate(), gem5::AMDGPUVM::MMHUBTranslationGen::translate(), gem5::AMDGPUVM::UserTranslationGen::translate(), gem5::ArmISA::MMU::translateFs(), and gem5::ArmISA::MMU::CachedState::updateMiscReg().

◆ vmidbits

Bitfield<7, 4> gem5::ArmISA::vmidbits

Definition at line 168 of file misc_types.hh.

◆ vncr

Bitfield< 13 > gem5::ArmISA::vncr

Definition at line 750 of file misc_types.hh.

◆ vs

Bitfield<19> gem5::ArmISA::vs

Definition at line 627 of file misc_types.hh.

Referenced by sc_dt::compare_unsigned(), gem5::ArmISA::BrkPoint::getVMIDfromReg(), sc_dt::operator%(), sc_dt::operator&(), sc_dt::operator+(), sc_dt::operator-(), sc_dt::operator<(), sc_dt::operator==(), sc_dt::operator^(), sc_dt::operator|(), and gem5::ArmISA::BrkPoint::testVMIDMatch().

◆ vse

Bitfield<8> gem5::ArmISA::vse

Definition at line 331 of file misc_types.hh.

◆ width

Bitfield< 4 > gem5::ArmISA::width

Definition at line 72 of file misc_types.hh.

Referenced by sc_gem5::VcdTraceFile::addNewTraceVal(), sc_gem5::VcdTraceFile::addTraceVal(), gem5::ArmISA::ArmStaticInst::extendReg64(), gem5::findCarry(), gem5::findNegative(), gem5::findOverflow(), gem5::findParity(), gem5::findZero(), gem5::Trie< Addr, TlbEntry >::insert(), sc_gem5::TlmToGem5Bridge< BITWIDTH >::nb_transport_fw(), gem5::linux::printk(), gem5::ArmISA::ArmStaticInst::satInt(), gem5::ArmISA::ArmStaticInst::saturateOp(), sc_core::sc_trace(), gem5::VncInput::setDirty(), gem5::ArmISA::ArmStaticInst::shiftReg64(), gem5::ArmISA::ArmStaticInst::uSatInt(), gem5::ArmISA::ArmStaticInst::uSaturateOp(), vfpFpToFixed(), vfpSFixedToFpD(), vfpSFixedToFpS(), vfpUFixedToFpD(), vfpUFixedToFpS(), and gem5::PngWriter::write().

◆ wnr

Bitfield< 6 > gem5::ArmISA::wnr

Definition at line 484 of file misc_types.hh.

◆ wpaddrmask

Bitfield<7,4> gem5::ArmISA::wpaddrmask

Definition at line 930 of file misc_types.hh.

◆ writeback

Bitfield<21> gem5::ArmISA::writeback

Definition at line 126 of file types.hh.

Referenced by gem5::ArmISA::MacroMemOp::MacroMemOp(), gem5::ArmISA::MacroVFPMemOp::MacroVFPMemOp(), gem5::ArmISA::PairMemOp::PairMemOp(), gem5::IGbE::TxDescCache::pktComplete(), gem5::IGbE::DescCache< igbreg::RxDesc >::wbComplete(), and gem5::memory::CfiMemory::write().

◆ wrps

Bitfield<23, 20> gem5::ArmISA::wrps

Definition at line 104 of file misc_types.hh.

◆ wt

Bitfield<20> gem5::ArmISA::wt

Definition at line 861 of file misc_types.hh.

◆ wxn

Bitfield<19> gem5::ArmISA::wxn

Definition at line 416 of file misc_types.hh.

Referenced by gem5::ArmISA::MMU::s1PermBits64().

◆ xnx

Bitfield<31, 28> gem5::ArmISA::xnx

Definition at line 162 of file misc_types.hh.

◆ xp

Bitfield<23> gem5::ArmISA::xp

Definition at line 407 of file misc_types.hh.

◆ z

Bitfield< 30 > gem5::ArmISA::z

Definition at line 431 of file misc_types.hh.

Referenced by gem5::ArmISA::HTMCheckpoint::restore(), gem5::ArmISA::HTMCheckpoint::save(), testPredicate(), and gem5::ArmISA::TableWalker::walkAddresses().

◆ za

Bitfield<1, 1> gem5::ArmISA::za

Definition at line 818 of file misc_types.hh.

◆ zen

Bitfield< 17, 16 > gem5::ArmISA::zen

Definition at line 464 of file misc_types.hh.

gem5::ArmISA::vecRegElemClassOps
static VecElemRegClassOps< RegVal > vecRegElemClassOps(NumVecElemPerVecReg)
gem5::ArmISA::NumVecElemPerVecReg
constexpr unsigned NumVecElemPerVecReg
Definition: vec.hh:61
gem5::ArmISA::vecRegClassOps
static TypedRegClassOps< ArmISA::VecRegContainer > vecRegClassOps
Definition: vec.hh:98
gem5::ArmISA::Grain64KB
@ Grain64KB
Definition: pagetable.hh:65
gem5::ArmISA::NumVecRegs
const int NumVecRegs
Definition: vec.hh:83
gem5::VecElemClass
@ VecElemClass
Vector Register Native Elem lane.
Definition: reg_class.hh:65
gem5::VecRegClassName
constexpr char VecRegClassName[]
Definition: reg_class.hh:76
gem5::CCRegClass
@ CCRegClass
Condition-code register.
Definition: reg_class.hh:68
gem5::VecPredRegClassName
constexpr char VecPredRegClassName[]
Definition: reg_class.hh:78
gem5::SparcISA::int_reg::NumRegs
const int NumRegs
Definition: int.hh:67
gem5::ArmISA::Grain16KB
@ Grain16KB
Definition: pagetable.hh:64
gem5::RiscvISA::NUM_MISCREGS
@ NUM_MISCREGS
Definition: misc.hh:240
gem5::ArmISA::NumMatrixRegs
const int NumMatrixRegs
Definition: mat.hh:88
gem5::brkFunc
SyscallReturn brkFunc(SyscallDesc *desc, ThreadContext *tc, VPtr<> new_brk)
Target brk() handler: set brk address.
Definition: syscall_emul.cc:258
gem5::ArmISA::miscRegClassOps
static MiscRegClassOps miscRegClassOps
Definition: misc.hh:2808
gem5::ArmISA::Grain4KB
@ Grain4KB
Definition: pagetable.hh:63
gem5::ArmISA::ccRegClassOps
static CCRegClassOps ccRegClassOps
Definition: cc.hh:85
gem5::VecPredRegClass
@ VecPredRegClass
Definition: reg_class.hh:66
gem5::ArmISA::matRegClassOps
static TypedRegClassOps< ArmISA::MatRegContainer > matRegClassOps
Definition: mat.hh:90
gem5::ArmISA::issetugidFunc
static SyscallReturn issetugidFunc(SyscallDesc *desc, ThreadContext *tc)
Definition: se_workload.cc:86
gem5::ArmISA::NumVecPredRegs
const int NumVecPredRegs
Definition: vec.hh:84
gem5::ArmISA::cc_reg::NumRegs
@ NumRegs
Definition: cc.hh:61
gem5::MatRegClass
@ MatRegClass
Matrix Register.
Definition: reg_class.hh:67
gem5::ArmISA::setTLSFunc32
static SyscallReturn setTLSFunc32(SyscallDesc *desc, ThreadContext *tc, uint32_t tlsPtr)
Target set_tls() handler.
Definition: se_workload.cc:131
gem5::ArmISA::ReservedGrain
@ ReservedGrain
Definition: pagetable.hh:66
gem5::IntRegClassName
constexpr char IntRegClassName[]
Definition: reg_class.hh:74
gem5::MatRegClassName
constexpr char MatRegClassName[]
Definition: reg_class.hh:79
gem5::ArmISA::sysctlFunc
static SyscallReturn sysctlFunc(SyscallDesc *desc, ThreadContext *tc, VPtr<> namep, size_t nameLen, VPtr<> oldp, VPtr<> oldlenp, VPtr<> newp, size_t newlen)
Definition: se_workload.cc:93
gem5::ArmISA::setTLSFunc64
static SyscallReturn setTLSFunc64(SyscallDesc *desc, ThreadContext *tc, uint32_t tlsPtr)
Definition: se_workload.cc:140
gem5::VecElemClassName
constexpr char VecElemClassName[]
Definition: reg_class.hh:77
gem5::X86ISA::intRegClassOps
constexpr IntRegClassOps intRegClassOps
Definition: int.hh:121
gem5::CCRegClassName
constexpr char CCRegClassName[]
Definition: reg_class.hh:80
gem5::IntRegClass
@ IntRegClass
Integer register.
Definition: reg_class.hh:60
gem5::MiscRegClassName
constexpr char MiscRegClassName[]
Definition: reg_class.hh:81
gem5::exitFunc
SyscallReturn exitFunc(SyscallDesc *desc, ThreadContext *tc, int status)
Target exit() handler: terminate current context.
Definition: syscall_emul.cc:239
gem5::MiscRegClass
@ MiscRegClass
Control (misc) register.
Definition: reg_class.hh:69
gem5::VecRegClass
@ VecRegClass
Vector Register.
Definition: reg_class.hh:63
gem5::ArmISA::vecPredRegClassOps
static TypedRegClassOps< ArmISA::VecPredRegContainer > vecPredRegClassOps
Definition: vec.hh:99
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