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Pages
gpu-compute
gpu_exec_context.cc
Go to the documentation of this file.
1
/*
2
* Copyright (c) 2015 Advanced Micro Devices, Inc.
3
* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
6
* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
9
* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
12
* this list of conditions and the following disclaimer in the documentation
13
* and/or other materials provided with the distribution.
14
*
15
* 3. Neither the name of the copyright holder nor the names of its
16
* contributors may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
23
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29
* POSSIBILITY OF SUCH DAMAGE.
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*/
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32
#include "
gpu-compute/gpu_exec_context.hh
"
33
#include "
gpu-compute/wavefront.hh
"
34
35
namespace
gem5
36
{
37
38
GPUExecContext::GPUExecContext
(
ComputeUnit
*_cu,
Wavefront
*_wf)
39
: cu(_cu), wf(_wf), gpuISA(_wf ? &_wf->gpuISA() : nullptr)
40
{
41
}
42
43
ComputeUnit
*
44
GPUExecContext::computeUnit
()
45
{
46
return
cu
;
47
}
48
49
Wavefront
*
50
GPUExecContext::wavefront
()
51
{
52
return
wf
;
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}
54
55
RegVal
56
GPUExecContext::readMiscReg
(
int
opIdx)
const
57
{
58
assert(
gpuISA
);
59
return
gpuISA
->readMiscReg(opIdx);
60
}
61
62
void
63
GPUExecContext::writeMiscReg
(
int
opIdx,
RegVal
val
)
64
{
65
assert(
gpuISA
);
66
gpuISA
->writeMiscReg(opIdx,
val
);
67
}
68
69
}
// namespace gem5
gem5::RegVal
uint64_t RegVal
Definition:
types.hh:173
gem5::GPUExecContext::writeMiscReg
void writeMiscReg(int opIdx, RegVal operandVal)
Definition:
gpu_exec_context.cc:63
gem5::Wavefront
Definition:
wavefront.hh:60
gem5::X86ISA::val
Bitfield< 63 > val
Definition:
misc.hh:776
gem5::GPUExecContext::wf
Wavefront * wf
Definition:
gpu_exec_context.hh:63
gem5::GPUExecContext::gpuISA
TheGpuISA::GPUISA * gpuISA
Definition:
gpu_exec_context.hh:64
wavefront.hh
gem5::GPUExecContext::computeUnit
ComputeUnit * computeUnit()
Definition:
gpu_exec_context.cc:44
gem5::ComputeUnit
Definition:
compute_unit.hh:201
gem5::GPUExecContext::GPUExecContext
GPUExecContext(ComputeUnit *_cu, Wavefront *_wf)
Definition:
gpu_exec_context.cc:38
gem5::GPUExecContext::readMiscReg
RegVal readMiscReg(int opIdx) const
Definition:
gpu_exec_context.cc:56
gem5::GPUExecContext::wavefront
Wavefront * wavefront()
Definition:
gpu_exec_context.cc:50
gpu_exec_context.hh
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition:
gpu_translation_state.hh:37
gem5::GPUExecContext::cu
ComputeUnit * cu
Definition:
gpu_exec_context.hh:62
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