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gem5
[DEVELOP-FOR-23.0]
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gem5
[DEVELOP-FOR-23.0]
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Go to the source code of this file.
Namespaces | |
| gem5 | |
| Reference material can be found at the JEDEC website: UFS standard http://www.jedec.org/standards-documents/results/jesd220 UFS HCI specification http://www.jedec.org/standards-documents/results/jesd223. | |
Macros | |
| #define | mmCP_RB0_BASE 0x1040 |
| #define | mmCP_RB0_CNTL 0x1041 |
| #define | mmCP_RB_WPTR_POLL_ADDR_LO 0x1046 |
| #define | mmCP_RB_WPTR_POLL_ADDR_HI 0x1047 |
| #define | mmCP_RB_VMID 0x1051 |
| #define | mmCP_RB0_RPTR_ADDR 0x1043 |
| #define | mmCP_RB0_RPTR_ADDR_HI 0x1044 |
| #define | mmCP_RB0_WPTR 0x1054 |
| #define | mmCP_RB0_WPTR_HI 0x1055 |
| #define | mmCP_RB_DOORBELL_CONTROL 0x1059 |
| #define | mmCP_RB_DOORBELL_RANGE_LOWER 0x105a |
| #define | mmCP_RB_DOORBELL_RANGE_UPPER 0x105b |
| #define | mmCP_RB0_BASE_HI 0x10b1 |
| #define | mmCP_HQD_ACTIVE 0x1247 |
| #define | mmCP_HQD_VMID 0x1248 |
| #define | mmCP_HQD_PQ_BASE 0x124d |
| #define | mmCP_HQD_PQ_BASE_HI 0x124e |
| #define | mmCP_HQD_PQ_DOORBELL_CONTROL 0x1254 |
| #define | mmCP_HQD_PQ_RPTR 0x124f |
| #define | mmCP_HQD_PQ_RPTR_REPORT_ADDR 0x1250 |
| #define | mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI 0x1251 |
| #define | mmCP_HQD_PQ_WPTR_POLL_ADDR 0x1252 |
| #define | mmCP_HQD_PQ_WPTR_POLL_ADDR_HI 0x1253 |
| #define | mmCP_HQD_PQ_CONTROL 0x1256 |
| #define | mmCP_HQD_IB_CONTROL 0x125a |
| #define | mmCP_HQD_PQ_WPTR_LO 0x127b |
| #define | mmCP_HQD_PQ_WPTR_HI 0x127c |
| #define mmCP_HQD_ACTIVE 0x1247 |
Definition at line 53 of file pm4_mmio.hh.
| #define mmCP_HQD_IB_CONTROL 0x125a |
Definition at line 64 of file pm4_mmio.hh.
| #define mmCP_HQD_PQ_BASE 0x124d |
Definition at line 55 of file pm4_mmio.hh.
| #define mmCP_HQD_PQ_BASE_HI 0x124e |
Definition at line 56 of file pm4_mmio.hh.
| #define mmCP_HQD_PQ_CONTROL 0x1256 |
Definition at line 63 of file pm4_mmio.hh.
| #define mmCP_HQD_PQ_DOORBELL_CONTROL 0x1254 |
Definition at line 57 of file pm4_mmio.hh.
| #define mmCP_HQD_PQ_RPTR 0x124f |
Definition at line 58 of file pm4_mmio.hh.
| #define mmCP_HQD_PQ_RPTR_REPORT_ADDR 0x1250 |
Definition at line 59 of file pm4_mmio.hh.
| #define mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI 0x1251 |
Definition at line 60 of file pm4_mmio.hh.
| #define mmCP_HQD_PQ_WPTR_HI 0x127c |
Definition at line 66 of file pm4_mmio.hh.
| #define mmCP_HQD_PQ_WPTR_LO 0x127b |
Definition at line 65 of file pm4_mmio.hh.
| #define mmCP_HQD_PQ_WPTR_POLL_ADDR 0x1252 |
Definition at line 61 of file pm4_mmio.hh.
| #define mmCP_HQD_PQ_WPTR_POLL_ADDR_HI 0x1253 |
Definition at line 62 of file pm4_mmio.hh.
| #define mmCP_HQD_VMID 0x1248 |
Definition at line 54 of file pm4_mmio.hh.
| #define mmCP_RB0_BASE 0x1040 |
Definition at line 39 of file pm4_mmio.hh.
| #define mmCP_RB0_BASE_HI 0x10b1 |
Definition at line 51 of file pm4_mmio.hh.
| #define mmCP_RB0_CNTL 0x1041 |
Definition at line 40 of file pm4_mmio.hh.
| #define mmCP_RB0_RPTR_ADDR 0x1043 |
Definition at line 44 of file pm4_mmio.hh.
| #define mmCP_RB0_RPTR_ADDR_HI 0x1044 |
Definition at line 45 of file pm4_mmio.hh.
| #define mmCP_RB0_WPTR 0x1054 |
Definition at line 46 of file pm4_mmio.hh.
| #define mmCP_RB0_WPTR_HI 0x1055 |
Definition at line 47 of file pm4_mmio.hh.
| #define mmCP_RB_DOORBELL_CONTROL 0x1059 |
Definition at line 48 of file pm4_mmio.hh.
| #define mmCP_RB_DOORBELL_RANGE_LOWER 0x105a |
Definition at line 49 of file pm4_mmio.hh.
| #define mmCP_RB_DOORBELL_RANGE_UPPER 0x105b |
Definition at line 50 of file pm4_mmio.hh.
| #define mmCP_RB_VMID 0x1051 |
Definition at line 43 of file pm4_mmio.hh.
| #define mmCP_RB_WPTR_POLL_ADDR_HI 0x1047 |
Definition at line 42 of file pm4_mmio.hh.
| #define mmCP_RB_WPTR_POLL_ADDR_LO 0x1046 |
Definition at line 41 of file pm4_mmio.hh.