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arch
riscv
pagetable.cc
Go to the documentation of this file.
1
/*
2
* Copyright (c) 2002-2005 The Regents of The University of Michigan
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* Copyright (c) 2007 MIPS Technologies, Inc.
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* Copyright (c) 2020 Barkhausen Institut
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
10
* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
12
* notice, this list of conditions and the following disclaimer in the
13
* documentation and/or other materials provided with the distribution;
14
* neither the name of the copyright holders nor the names of its
15
* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
19
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
20
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
21
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
22
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
25
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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31
#include "
arch/riscv/pagetable.hh
"
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33
#include "
sim/serialize.hh
"
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35
namespace
gem5
36
{
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38
namespace
RiscvISA
39
{
40
41
void
42
TlbEntry::serialize
(
CheckpointOut
&cp)
const
43
{
44
SERIALIZE_SCALAR
(
paddr
);
45
SERIALIZE_SCALAR
(
vaddr
);
46
SERIALIZE_SCALAR
(
logBytes
);
47
SERIALIZE_SCALAR
(
asid
);
48
SERIALIZE_SCALAR
(
pte
);
49
SERIALIZE_SCALAR
(
lruSeq
);
50
}
51
52
void
53
TlbEntry::unserialize
(
CheckpointIn
&cp)
54
{
55
UNSERIALIZE_SCALAR
(
paddr
);
56
UNSERIALIZE_SCALAR
(
vaddr
);
57
UNSERIALIZE_SCALAR
(
logBytes
);
58
UNSERIALIZE_SCALAR
(
asid
);
59
UNSERIALIZE_SCALAR
(
pte
);
60
UNSERIALIZE_SCALAR
(
lruSeq
);
61
}
62
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}
// namespace RiscvISA
64
}
// namespace gem5
serialize.hh
UNSERIALIZE_SCALAR
#define UNSERIALIZE_SCALAR(scalar)
Definition:
serialize.hh:575
gem5::CheckpointIn
Definition:
serialize.hh:68
gem5::RiscvISA::TlbEntry::pte
PTESv39 pte
Definition:
pagetable.hh:94
gem5::RiscvISA::TlbEntry::logBytes
unsigned logBytes
Definition:
pagetable.hh:90
gem5::RiscvISA::TlbEntry::vaddr
Addr vaddr
Definition:
pagetable.hh:88
gem5::RiscvISA::TlbEntry::asid
uint16_t asid
Definition:
pagetable.hh:92
SERIALIZE_SCALAR
#define SERIALIZE_SCALAR(scalar)
Definition:
serialize.hh:568
gem5::RiscvISA::TlbEntry::paddr
Addr paddr
Definition:
pagetable.hh:85
gem5::CheckpointOut
std::ostream CheckpointOut
Definition:
serialize.hh:66
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition:
gpu_translation_state.hh:37
gem5::RiscvISA::TlbEntry::serialize
void serialize(CheckpointOut &cp) const override
Serialize an object.
Definition:
pagetable.cc:42
gem5::RiscvISA::TlbEntry::lruSeq
uint64_t lruSeq
Definition:
pagetable.hh:99
pagetable.hh
gem5::RiscvISA::TlbEntry::unserialize
void unserialize(CheckpointIn &cp) override
Unserialize an object.
Definition:
pagetable.cc:53
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