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reg_abi.cc
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27 
28 #include "arch/riscv/reg_abi.hh"
29 #include "arch/riscv/regs/int.hh"
30 
31 namespace gem5
32 {
33 
34 namespace RiscvISA
35 {
36 
40 };
41 
45 };
46 
47 
48 } // namespace RiscvISA
49 } // namespace gem5
gem5::RiscvISA::RegABI64::ArgumentRegs
static const std::vector< RegId > ArgumentRegs
Definition: reg_abi.hh:44
reg_abi.hh
std::vector
STL vector class.
Definition: stl.hh:37
gem5::RiscvISA::int_reg::A2
constexpr RegId A2
Definition: int.hh:103
gem5::RiscvISA::int_reg::A6
constexpr RegId A6
Definition: int.hh:107
gem5::RiscvISA::int_reg::A1
constexpr RegId A1
Definition: int.hh:102
gem5::RiscvISA::int_reg::A0
constexpr RegId A0
Definition: int.hh:101
gem5::RiscvISA::int_reg::A5
constexpr RegId A5
Definition: int.hh:106
gem5::RiscvISA::RegABI32::ArgumentRegs
static const std::vector< RegId > ArgumentRegs
Definition: reg_abi.hh:49
gem5::RiscvISA::int_reg::A3
constexpr RegId A3
Definition: int.hh:104
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::RiscvISA::int_reg::A4
constexpr RegId A4
Definition: int.hh:105
int.hh

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