simple_cache.hh

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/*
 * Copyright (c) 2017 Jason Lowe-Power
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are
 * met: redistributions of source code must retain the above copyright
 * notice, this list of conditions and the following disclaimer;
 * redistributions in binary form must reproduce the above copyright
 * notice, this list of conditions and the following disclaimer in the
 * documentation and/or other materials provided with the distribution;
 * neither the name of the copyright holders nor the names of its
 * contributors may be used to endorse or promote products derived from
 * this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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#ifndef __LEARNING_GEM5_SIMPLE_CACHE_SIMPLE_CACHE_HH__
#define __LEARNING_GEM5_SIMPLE_CACHE_SIMPLE_CACHE_HH__
 
#include <unordered_map>
 
#include "base/statistics.hh"
#include "mem/port.hh"
#include "params/SimpleCache.hh"
#include "sim/clocked_object.hh"
 
namespace gem5
{
 
class SimpleCache : public ClockedObject
{
  private:
 
    class CPUSidePort : public ResponsePort
    {
      private:
        int id;
 
        SimpleCache *owner;
 
        bool needRetry;
 
        PacketPtr blockedPacket;
 
      public:
        CPUSidePort(const std::string& name, int id, SimpleCache *owner) :
            ResponsePort(name), id(id), owner(owner), needRetry(false),
            blockedPacket(nullptr)
        { }
 
        void sendPacket(PacketPtr pkt);
 
        AddrRangeList getAddrRanges() const override;
 
        void trySendRetry();
 
      protected:
        Tick recvAtomic(PacketPtr pkt) override
        { panic("recvAtomic unimpl."); }
 
        void recvFunctional(PacketPtr pkt) override;
 
        bool recvTimingReq(PacketPtr pkt) override;
 
        void recvRespRetry() override;
    };
 
    class MemSidePort : public RequestPort
    {
      private:
        SimpleCache *owner;
 
        PacketPtr blockedPacket;
 
      public:
        MemSidePort(const std::string& name, SimpleCache *owner) :
            RequestPort(name), owner(owner), blockedPacket(nullptr)
        { }
 
        void sendPacket(PacketPtr pkt);
 
      protected:
        bool recvTimingResp(PacketPtr pkt) override;
 
        void recvReqRetry() override;
 
        void recvRangeChange() override;
    };
 
    bool handleRequest(PacketPtr pkt, int port_id);
 
    bool handleResponse(PacketPtr pkt);
 
    void sendResponse(PacketPtr pkt);
 
    void handleFunctional(PacketPtr pkt);
 
    void accessTiming(PacketPtr pkt);
 
    bool accessFunctional(PacketPtr pkt);
 
    void insert(PacketPtr pkt);
 
    AddrRangeList getAddrRanges() const;
 
    void sendRangeChange() const;
 
    const Cycles latency;
 
    const unsigned blockSize;
 
    const unsigned capacity;
 
    std::vector<CPUSidePort> cpuPorts;
 
    MemSidePort memPort;
 
    bool blocked;
 
    PacketPtr originalPacket;
 
    int waitingPortId;
 
    Tick missTime;
 
    std::unordered_map<Addr, uint8_t*> cacheStore;
 
  protected:
    struct SimpleCacheStats : public statistics::Group
    {
        SimpleCacheStats(statistics::Group *parent);
        statistics::Scalar hits;
        statistics::Scalar misses;
        statistics::Histogram missLatency;
        statistics::Formula hitRatio;
    } stats;
 
  public:
 
    SimpleCache(const SimpleCacheParams &params);
 
    Port &getPort(const std::string &if_name,
                  PortID idx=InvalidPortID) override;
 
};
 
} // namespace gem5
 
#endif // __LEARNING_GEM5_SIMPLE_CACHE_SIMPLE_CACHE_HH__