gem5::Gcn3ISA::InFmt_SOPC Struct Reference

#include <gpu_decoder.hh>

Public Attributes
unsigned int	SSRC0: 8
unsigned int	SSRC1: 8
unsigned int	OP: 7
unsigned int	ENCODING: 9

Detailed Description

Definition at line 1521 of file gpu_decoder.hh.

Member Data Documentation

ENCODING

unsigned int gem5::Gcn3ISA::InFmt_SOPC::ENCODING

Definition at line 1526 of file gpu_decoder.hh.

OP

unsigned int gem5::Gcn3ISA::InFmt_SOPC::OP

Definition at line 1525 of file gpu_decoder.hh.

Referenced by gem5::Gcn3ISA::Decoder::subDecode_OP_SOPC().

SSRC0

unsigned int gem5::Gcn3ISA::InFmt_SOPC::SSRC0

Definition at line 1523 of file gpu_decoder.hh.

Referenced by gem5::Gcn3ISA::Inst_SOPC__S_CMP_EQ_I32::execute(), gem5::Gcn3ISA::Inst_SOPC__S_CMP_LG_I32::execute(), gem5::Gcn3ISA::Inst_SOPC__S_CMP_GT_I32::execute(), gem5::Gcn3ISA::Inst_SOPC__S_CMP_GE_I32::execute(), gem5::Gcn3ISA::Inst_SOPC__S_CMP_LT_I32::execute(), gem5::Gcn3ISA::Inst_SOPC__S_CMP_LE_I32::execute(), gem5::Gcn3ISA::Inst_SOPC__S_CMP_EQ_U32::execute(), gem5::Gcn3ISA::Inst_SOPC__S_CMP_LG_U32::execute(), gem5::Gcn3ISA::Inst_SOPC__S_CMP_GT_U32::execute(), gem5::Gcn3ISA::Inst_SOPC__S_CMP_GE_U32::execute(), gem5::Gcn3ISA::Inst_SOPC__S_CMP_LT_U32::execute(), gem5::Gcn3ISA::Inst_SOPC__S_CMP_LE_U32::execute(), gem5::Gcn3ISA::Inst_SOPC__S_BITCMP0_B32::execute(), gem5::Gcn3ISA::Inst_SOPC__S_BITCMP1_B32::execute(), gem5::Gcn3ISA::Inst_SOPC__S_BITCMP0_B64::execute(), gem5::Gcn3ISA::Inst_SOPC__S_BITCMP1_B64::execute(), gem5::Gcn3ISA::Inst_SOPC__S_CMP_EQ_U64::execute(), gem5::Gcn3ISA::Inst_SOPC__S_CMP_LG_U64::execute(), gem5::Gcn3ISA::Inst_SOPC::generateDisassembly(), gem5::Gcn3ISA::Inst_SOPC::hasSecondDword(), and gem5::Gcn3ISA::Inst_SOPC::initOperandInfo().

SSRC1

unsigned int gem5::Gcn3ISA::InFmt_SOPC::SSRC1

Definition at line 1524 of file gpu_decoder.hh.

Referenced by gem5::Gcn3ISA::Inst_SOPC__S_CMP_EQ_I32::execute(), gem5::Gcn3ISA::Inst_SOPC__S_CMP_LG_I32::execute(), gem5::Gcn3ISA::Inst_SOPC__S_CMP_GT_I32::execute(), gem5::Gcn3ISA::Inst_SOPC__S_CMP_GE_I32::execute(), gem5::Gcn3ISA::Inst_SOPC__S_CMP_LT_I32::execute(), gem5::Gcn3ISA::Inst_SOPC__S_CMP_LE_I32::execute(), gem5::Gcn3ISA::Inst_SOPC__S_CMP_EQ_U32::execute(), gem5::Gcn3ISA::Inst_SOPC__S_CMP_LG_U32::execute(), gem5::Gcn3ISA::Inst_SOPC__S_CMP_GT_U32::execute(), gem5::Gcn3ISA::Inst_SOPC__S_CMP_GE_U32::execute(), gem5::Gcn3ISA::Inst_SOPC__S_CMP_LT_U32::execute(), gem5::Gcn3ISA::Inst_SOPC__S_CMP_LE_U32::execute(), gem5::Gcn3ISA::Inst_SOPC__S_BITCMP0_B32::execute(), gem5::Gcn3ISA::Inst_SOPC__S_BITCMP1_B32::execute(), gem5::Gcn3ISA::Inst_SOPC__S_BITCMP0_B64::execute(), gem5::Gcn3ISA::Inst_SOPC__S_BITCMP1_B64::execute(), gem5::Gcn3ISA::Inst_SOPC__S_CMP_EQ_U64::execute(), gem5::Gcn3ISA::Inst_SOPC__S_CMP_LG_U64::execute(), gem5::Gcn3ISA::Inst_SOPC::generateDisassembly(), gem5::Gcn3ISA::Inst_SOPC::hasSecondDword(), and gem5::Gcn3ISA::Inst_SOPC::initOperandInfo().

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The documentation for this struct was generated from the following file:

• arch/amdgpu/gcn3/gpu_decoder.hh