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gem5::Gcn3ISA::InFmt_VOP_SDWA Struct Reference

#include <gpu_decoder.hh>

Public Attributes

unsigned int SRC0: 8
 
unsigned int DST_SEL: 3
 
unsigned int DST_UNUSED: 2
 
unsigned int CLAMP: 1
 
unsigned int pad_14_15: 2
 
unsigned int SRC0_SEL: 3
 
unsigned int SRC0_SEXT: 1
 
unsigned int SRC0_NEG: 1
 
unsigned int SRC0_ABS: 1
 
unsigned int pad_22_23: 2
 
unsigned int SRC1_SEL: 3
 
unsigned int SRC1_SEXT: 1
 
unsigned int SRC1_NEG: 1
 
unsigned int SRC1_ABS: 1
 

Detailed Description

Definition at line 1621 of file gpu_decoder.hh.

Member Data Documentation

◆ CLAMP

unsigned int gem5::Gcn3ISA::InFmt_VOP_SDWA::CLAMP

Definition at line 1626 of file gpu_decoder.hh.

Referenced by gem5::Gcn3ISA::Inst_VOP2__V_MUL_U32_U24::execute(), gem5::Gcn3ISA::Inst_VOP2__V_LSHLREV_B32::execute(), gem5::Gcn3ISA::Inst_VOP2__V_OR_B32::execute(), gem5::Gcn3ISA::Inst_VOP2__V_ADD_U32::execute(), and gem5::Gcn3ISA::processSDWA_dst().

◆ DST_SEL

unsigned int gem5::Gcn3ISA::InFmt_VOP_SDWA::DST_SEL

Definition at line 1624 of file gpu_decoder.hh.

Referenced by gem5::Gcn3ISA::Inst_VOP2__V_MUL_U32_U24::execute(), gem5::Gcn3ISA::Inst_VOP2__V_LSHLREV_B32::execute(), gem5::Gcn3ISA::Inst_VOP2__V_OR_B32::execute(), gem5::Gcn3ISA::Inst_VOP2__V_ADD_U32::execute(), and gem5::Gcn3ISA::processSDWA_dst().

◆ DST_UNUSED

unsigned int gem5::Gcn3ISA::InFmt_VOP_SDWA::DST_UNUSED

Definition at line 1625 of file gpu_decoder.hh.

Referenced by gem5::Gcn3ISA::Inst_VOP2__V_MUL_U32_U24::execute(), gem5::Gcn3ISA::Inst_VOP2__V_LSHLREV_B32::execute(), gem5::Gcn3ISA::Inst_VOP2__V_OR_B32::execute(), gem5::Gcn3ISA::Inst_VOP2__V_ADD_U32::execute(), and gem5::Gcn3ISA::processSDWA_dst().

◆ pad_14_15

unsigned int gem5::Gcn3ISA::InFmt_VOP_SDWA::pad_14_15

Definition at line 1627 of file gpu_decoder.hh.

◆ pad_22_23

unsigned int gem5::Gcn3ISA::InFmt_VOP_SDWA::pad_22_23

Definition at line 1632 of file gpu_decoder.hh.

◆ SRC0

unsigned int gem5::Gcn3ISA::InFmt_VOP_SDWA::SRC0

Definition at line 1623 of file gpu_decoder.hh.

Referenced by gem5::Gcn3ISA::Inst_VOP2__V_MUL_U32_U24::execute(), gem5::Gcn3ISA::Inst_VOP2__V_LSHLREV_B32::execute(), gem5::Gcn3ISA::Inst_VOP2__V_OR_B32::execute(), and gem5::Gcn3ISA::Inst_VOP2__V_ADD_U32::execute().

◆ SRC0_ABS

unsigned int gem5::Gcn3ISA::InFmt_VOP_SDWA::SRC0_ABS

Definition at line 1631 of file gpu_decoder.hh.

Referenced by gem5::Gcn3ISA::Inst_VOP2__V_MUL_U32_U24::execute(), gem5::Gcn3ISA::Inst_VOP2__V_LSHLREV_B32::execute(), gem5::Gcn3ISA::Inst_VOP2__V_OR_B32::execute(), gem5::Gcn3ISA::Inst_VOP2__V_ADD_U32::execute(), and gem5::Gcn3ISA::processSDWA_src().

◆ SRC0_NEG

unsigned int gem5::Gcn3ISA::InFmt_VOP_SDWA::SRC0_NEG

Definition at line 1630 of file gpu_decoder.hh.

Referenced by gem5::Gcn3ISA::Inst_VOP2__V_MUL_U32_U24::execute(), gem5::Gcn3ISA::Inst_VOP2__V_LSHLREV_B32::execute(), gem5::Gcn3ISA::Inst_VOP2__V_OR_B32::execute(), gem5::Gcn3ISA::Inst_VOP2__V_ADD_U32::execute(), and gem5::Gcn3ISA::processSDWA_src().

◆ SRC0_SEL

unsigned int gem5::Gcn3ISA::InFmt_VOP_SDWA::SRC0_SEL

Definition at line 1628 of file gpu_decoder.hh.

Referenced by gem5::Gcn3ISA::Inst_VOP2__V_MUL_U32_U24::execute(), gem5::Gcn3ISA::Inst_VOP2__V_LSHLREV_B32::execute(), gem5::Gcn3ISA::Inst_VOP2__V_OR_B32::execute(), gem5::Gcn3ISA::Inst_VOP2__V_ADD_U32::execute(), and gem5::Gcn3ISA::processSDWA_src().

◆ SRC0_SEXT

unsigned int gem5::Gcn3ISA::InFmt_VOP_SDWA::SRC0_SEXT

Definition at line 1629 of file gpu_decoder.hh.

Referenced by gem5::Gcn3ISA::Inst_VOP2__V_MUL_U32_U24::execute(), gem5::Gcn3ISA::Inst_VOP2__V_LSHLREV_B32::execute(), gem5::Gcn3ISA::Inst_VOP2__V_OR_B32::execute(), gem5::Gcn3ISA::Inst_VOP2__V_ADD_U32::execute(), and gem5::Gcn3ISA::processSDWA_src().

◆ SRC1_ABS

unsigned int gem5::Gcn3ISA::InFmt_VOP_SDWA::SRC1_ABS

Definition at line 1636 of file gpu_decoder.hh.

Referenced by gem5::Gcn3ISA::Inst_VOP2__V_MUL_U32_U24::execute(), gem5::Gcn3ISA::Inst_VOP2__V_LSHLREV_B32::execute(), gem5::Gcn3ISA::Inst_VOP2__V_OR_B32::execute(), gem5::Gcn3ISA::Inst_VOP2__V_ADD_U32::execute(), and gem5::Gcn3ISA::processSDWA_src().

◆ SRC1_NEG

unsigned int gem5::Gcn3ISA::InFmt_VOP_SDWA::SRC1_NEG

Definition at line 1635 of file gpu_decoder.hh.

Referenced by gem5::Gcn3ISA::Inst_VOP2__V_MUL_U32_U24::execute(), gem5::Gcn3ISA::Inst_VOP2__V_LSHLREV_B32::execute(), gem5::Gcn3ISA::Inst_VOP2__V_OR_B32::execute(), gem5::Gcn3ISA::Inst_VOP2__V_ADD_U32::execute(), and gem5::Gcn3ISA::processSDWA_src().

◆ SRC1_SEL

unsigned int gem5::Gcn3ISA::InFmt_VOP_SDWA::SRC1_SEL

Definition at line 1633 of file gpu_decoder.hh.

Referenced by gem5::Gcn3ISA::Inst_VOP2__V_MUL_U32_U24::execute(), gem5::Gcn3ISA::Inst_VOP2__V_LSHLREV_B32::execute(), gem5::Gcn3ISA::Inst_VOP2__V_OR_B32::execute(), gem5::Gcn3ISA::Inst_VOP2__V_ADD_U32::execute(), and gem5::Gcn3ISA::processSDWA_src().

◆ SRC1_SEXT

unsigned int gem5::Gcn3ISA::InFmt_VOP_SDWA::SRC1_SEXT

Definition at line 1634 of file gpu_decoder.hh.

Referenced by gem5::Gcn3ISA::Inst_VOP2__V_MUL_U32_U24::execute(), gem5::Gcn3ISA::Inst_VOP2__V_LSHLREV_B32::execute(), gem5::Gcn3ISA::Inst_VOP2__V_OR_B32::execute(), gem5::Gcn3ISA::Inst_VOP2__V_ADD_U32::execute(), and gem5::Gcn3ISA::processSDWA_src().

The documentation for this struct was generated from the following file:
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