gem5::VegaISA::InFmt_VOP_SDWA Struct Reference

#include <gpu_decoder.hh>

Public Attributes
unsigned int	SRC0: 8
unsigned int	DST_SEL: 3
unsigned int	DST_U: 2
unsigned int	CLMP: 1
unsigned int	OMOD: 2
unsigned int	SRC0_SEL: 3
unsigned int	SRC0_SEXT: 1
unsigned int	SRC0_NEG: 1
unsigned int	SRC0_ABS: 1
unsigned int	pad_22: 1
unsigned int	S0: 1
unsigned int	SRC1_SEL: 3
unsigned int	SRC1_SEXT: 1
unsigned int	SRC1_NEG: 1
unsigned int	SRC1_ABS: 1
unsigned int	pad_30: 1
unsigned int	S1: 1

Detailed Description

Definition at line 1855 of file gpu_decoder.hh.

Member Data Documentation

CLMP

unsigned int gem5::VegaISA::InFmt_VOP_SDWA::CLMP

Definition at line 1859 of file gpu_decoder.hh.

Referenced by gem5::VegaISA::Inst_VOP2__V_LSHLREV_B32::execute(), gem5::VegaISA::Inst_VOP2__V_OR_B32::execute(), gem5::VegaISA::Inst_VOP2__V_ADD_CO_U32::execute(), gem5::VegaISA::Inst_VOP2__V_ADD_U32::execute(), gem5::VegaISA::processSDWA_dst(), and gem5::VegaISA::Inst_VOP2::sdwaSrcHelper().

DST_SEL

unsigned int gem5::VegaISA::InFmt_VOP_SDWA::DST_SEL

Definition at line 1857 of file gpu_decoder.hh.

Referenced by gem5::VegaISA::Inst_VOP2__V_LSHLREV_B32::execute(), gem5::VegaISA::Inst_VOP2__V_OR_B32::execute(), gem5::VegaISA::Inst_VOP2__V_ADD_CO_U32::execute(), gem5::VegaISA::Inst_VOP2__V_ADD_U32::execute(), gem5::VegaISA::processSDWA_dst(), and gem5::VegaISA::Inst_VOP2::sdwaSrcHelper().

DST_U

unsigned int gem5::VegaISA::InFmt_VOP_SDWA::DST_U

Definition at line 1858 of file gpu_decoder.hh.

Referenced by gem5::VegaISA::Inst_VOP2__V_LSHLREV_B32::execute(), gem5::VegaISA::Inst_VOP2__V_OR_B32::execute(), gem5::VegaISA::Inst_VOP2__V_ADD_CO_U32::execute(), gem5::VegaISA::Inst_VOP2__V_ADD_U32::execute(), gem5::VegaISA::processSDWA_dst(), and gem5::VegaISA::Inst_VOP2::sdwaSrcHelper().

OMOD

unsigned int gem5::VegaISA::InFmt_VOP_SDWA::OMOD

Definition at line 1860 of file gpu_decoder.hh.

pad_22

unsigned int gem5::VegaISA::InFmt_VOP_SDWA::pad_22

Definition at line 1865 of file gpu_decoder.hh.

pad_30

unsigned int gem5::VegaISA::InFmt_VOP_SDWA::pad_30

Definition at line 1871 of file gpu_decoder.hh.

S0

unsigned int gem5::VegaISA::InFmt_VOP_SDWA::S0

Definition at line 1866 of file gpu_decoder.hh.

S1

unsigned int gem5::VegaISA::InFmt_VOP_SDWA::S1

Definition at line 1872 of file gpu_decoder.hh.

SRC0

unsigned int gem5::VegaISA::InFmt_VOP_SDWA::SRC0

Definition at line 1856 of file gpu_decoder.hh.

Referenced by gem5::VegaISA::Inst_VOP2__V_LSHLREV_B32::execute(), gem5::VegaISA::Inst_VOP2__V_OR_B32::execute(), gem5::VegaISA::Inst_VOP2__V_ADD_CO_U32::execute(), gem5::VegaISA::Inst_VOP2__V_ADD_U32::execute(), and gem5::VegaISA::Inst_VOP2::sdwaSrcHelper().

SRC0_ABS

unsigned int gem5::VegaISA::InFmt_VOP_SDWA::SRC0_ABS

Definition at line 1864 of file gpu_decoder.hh.

Referenced by gem5::VegaISA::Inst_VOP2__V_LSHLREV_B32::execute(), gem5::VegaISA::Inst_VOP2__V_OR_B32::execute(), gem5::VegaISA::Inst_VOP2__V_ADD_CO_U32::execute(), gem5::VegaISA::Inst_VOP2__V_ADD_U32::execute(), gem5::VegaISA::processSDWA_src(), and gem5::VegaISA::Inst_VOP2::sdwaSrcHelper().

SRC0_NEG

unsigned int gem5::VegaISA::InFmt_VOP_SDWA::SRC0_NEG

Definition at line 1863 of file gpu_decoder.hh.

Referenced by gem5::VegaISA::Inst_VOP2__V_LSHLREV_B32::execute(), gem5::VegaISA::Inst_VOP2__V_OR_B32::execute(), gem5::VegaISA::Inst_VOP2__V_ADD_CO_U32::execute(), gem5::VegaISA::Inst_VOP2__V_ADD_U32::execute(), gem5::VegaISA::processSDWA_src(), and gem5::VegaISA::Inst_VOP2::sdwaSrcHelper().

SRC0_SEL

unsigned int gem5::VegaISA::InFmt_VOP_SDWA::SRC0_SEL

Definition at line 1861 of file gpu_decoder.hh.

Referenced by gem5::VegaISA::Inst_VOP2__V_LSHLREV_B32::execute(), gem5::VegaISA::Inst_VOP2__V_OR_B32::execute(), gem5::VegaISA::Inst_VOP2__V_ADD_CO_U32::execute(), gem5::VegaISA::Inst_VOP2__V_ADD_U32::execute(), gem5::VegaISA::processSDWA_src(), and gem5::VegaISA::Inst_VOP2::sdwaSrcHelper().

SRC0_SEXT

unsigned int gem5::VegaISA::InFmt_VOP_SDWA::SRC0_SEXT

Definition at line 1862 of file gpu_decoder.hh.

Referenced by gem5::VegaISA::Inst_VOP2__V_LSHLREV_B32::execute(), gem5::VegaISA::Inst_VOP2__V_OR_B32::execute(), gem5::VegaISA::Inst_VOP2__V_ADD_CO_U32::execute(), gem5::VegaISA::Inst_VOP2__V_ADD_U32::execute(), gem5::VegaISA::processSDWA_src(), and gem5::VegaISA::Inst_VOP2::sdwaSrcHelper().

SRC1_ABS

unsigned int gem5::VegaISA::InFmt_VOP_SDWA::SRC1_ABS

Definition at line 1870 of file gpu_decoder.hh.

Referenced by gem5::VegaISA::Inst_VOP2__V_LSHLREV_B32::execute(), gem5::VegaISA::Inst_VOP2__V_OR_B32::execute(), gem5::VegaISA::Inst_VOP2__V_ADD_CO_U32::execute(), gem5::VegaISA::Inst_VOP2__V_ADD_U32::execute(), gem5::VegaISA::processSDWA_src(), and gem5::VegaISA::Inst_VOP2::sdwaSrcHelper().

SRC1_NEG

unsigned int gem5::VegaISA::InFmt_VOP_SDWA::SRC1_NEG

Definition at line 1869 of file gpu_decoder.hh.

Referenced by gem5::VegaISA::Inst_VOP2__V_LSHLREV_B32::execute(), gem5::VegaISA::Inst_VOP2__V_OR_B32::execute(), gem5::VegaISA::Inst_VOP2__V_ADD_CO_U32::execute(), gem5::VegaISA::Inst_VOP2__V_ADD_U32::execute(), gem5::VegaISA::processSDWA_src(), and gem5::VegaISA::Inst_VOP2::sdwaSrcHelper().

SRC1_SEL

unsigned int gem5::VegaISA::InFmt_VOP_SDWA::SRC1_SEL

Definition at line 1867 of file gpu_decoder.hh.

Referenced by gem5::VegaISA::Inst_VOP2__V_LSHLREV_B32::execute(), gem5::VegaISA::Inst_VOP2__V_OR_B32::execute(), gem5::VegaISA::Inst_VOP2__V_ADD_CO_U32::execute(), gem5::VegaISA::Inst_VOP2__V_ADD_U32::execute(), gem5::VegaISA::processSDWA_src(), and gem5::VegaISA::Inst_VOP2::sdwaSrcHelper().

SRC1_SEXT

unsigned int gem5::VegaISA::InFmt_VOP_SDWA::SRC1_SEXT

Definition at line 1868 of file gpu_decoder.hh.

Referenced by gem5::VegaISA::Inst_VOP2__V_LSHLREV_B32::execute(), gem5::VegaISA::Inst_VOP2__V_OR_B32::execute(), gem5::VegaISA::Inst_VOP2__V_ADD_CO_U32::execute(), gem5::VegaISA::Inst_VOP2__V_ADD_U32::execute(), gem5::VegaISA::processSDWA_src(), and gem5::VegaISA::Inst_VOP2::sdwaSrcHelper().

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The documentation for this struct was generated from the following file:

• arch/amdgpu/vega/gpu_decoder.hh