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isa.hh
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28 
29 #ifndef __ARCH_X86_ISA_HH__
30 #define __ARCH_X86_ISA_HH__
31 
32 #include <iostream>
33 #include <string>
34 
35 #include "arch/generic/isa.hh"
36 #include "arch/x86/pcstate.hh"
37 #include "arch/x86/regs/ccr.hh"
38 #include "arch/x86/regs/float.hh"
39 #include "arch/x86/regs/int.hh"
40 #include "arch/x86/regs/misc.hh"
41 #include "base/types.hh"
42 #include "cpu/reg_class.hh"
43 
44 namespace gem5
45 {
46 
47 class ThreadContext;
48 struct X86ISAParams;
49 
50 namespace X86ISA
51 {
52 
53 class ISA : public BaseISA
54 {
55  private:
57  void updateHandyM5Reg(Efer efer, CR0 cr0,
58  SegAttr csAttr, SegAttr ssAttr, RFLAGS rflags);
59 
60  std::string vendorString;
61 
62  public:
63  void clear() override;
64 
65  PCStateBase *
66  newPCState(Addr new_inst_addr=0) const override
67  {
68  return new PCState(new_inst_addr);
69  }
70 
71  using Params = X86ISAParams;
72 
73  ISA(const Params &p);
74 
75  RegVal readMiscRegNoEffect(RegIndex idx) const override;
76  RegVal readMiscReg(RegIndex idx) override;
77 
78  void setMiscRegNoEffect(RegIndex idx, RegVal val) override;
79  void setMiscReg(RegIndex idx, RegVal val) override;
80 
81  bool
82  inUserMode() const override
83  {
84  HandyM5Reg m5reg = readMiscRegNoEffect(misc_reg::M5Reg);
85  return m5reg.cpl == 3;
86  }
87 
88  void copyRegsFrom(ThreadContext *src) override;
89 
90  void serialize(CheckpointOut &cp) const override;
91  void unserialize(CheckpointIn &cp) override;
92 
93  void setThreadContext(ThreadContext *_tc) override;
94 
95  std::string getVendorString() const;
96 };
97 
98 } // namespace X86ISA
99 } // namespace gem5
100 
101 #endif
pcstate.hh
gem5::X86ISA::ISA::copyRegsFrom
void copyRegsFrom(ThreadContext *src) override
Definition: isa.cc:192
gem5::RegVal
uint64_t RegVal
Definition: types.hh:173
gem5::X86ISA::ISA
Definition: isa.hh:53
gem5::X86ISA::ISA::vendorString
std::string vendorString
Definition: isa.hh:60
gem5::CheckpointIn
Definition: serialize.hh:68
gem5::X86ISA::ISA::ISA
ISA(const Params &p)
Definition: isa.cc:154
ccr.hh
gem5::X86ISA::val
Bitfield< 63 > val
Definition: misc.hh:776
gem5::X86ISA::misc_reg::Efer
@ Efer
Definition: misc.hh:256
gem5::X86ISA::ISA::serialize
void serialize(CheckpointOut &cp) const override
Serialize an object.
Definition: isa.cc:482
gem5::X86ISA::ISA::unserialize
void unserialize(CheckpointIn &cp) override
Unserialize an object.
Definition: isa.cc:488
gem5::X86ISA::ISA::Params
X86ISAParams Params
Definition: isa.hh:71
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:88
gem5::X86ISA::ISA::newPCState
PCStateBase * newPCState(Addr new_inst_addr=0) const override
Definition: isa.hh:66
gem5::X86ISA::ISA::setThreadContext
void setThreadContext(ThreadContext *_tc) override
Definition: isa.cc:499
int.hh
gem5::MipsISA::PCState
GenericISA::DelaySlotPCState< 4 > PCState
Definition: pcstate.hh:40
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::X86ISA::ISA::clear
void clear() override
Definition: isa.cc:112
gem5::X86ISA::ISA::getVendorString
std::string getVendorString() const
Definition: isa.cc:506
gem5::X86ISA::ISA::setMiscReg
void setMiscReg(RegIndex idx, RegVal val) override
Definition: isa.cc:283
gem5::X86ISA::ISA::regVal
RegVal regVal[misc_reg::NumRegs]
Definition: isa.hh:56
gem5::X86ISA::ISA::setMiscRegNoEffect
void setMiscRegNoEffect(RegIndex idx, RegVal val) override
Definition: isa.cc:241
isa.hh
gem5::X86ISA::misc_reg::NumRegs
@ NumRegs
Definition: misc.hh:408
types.hh
gem5::X86ISA::ISA::updateHandyM5Reg
void updateHandyM5Reg(Efer efer, CR0 cr0, SegAttr csAttr, SegAttr ssAttr, RFLAGS rflags)
Definition: isa.cc:51
reg_class.hh
gem5::X86ISA::p
Bitfield< 0 > p
Definition: pagetable.hh:151
gem5::CheckpointOut
std::ostream CheckpointOut
Definition: serialize.hh:66
gem5::PCStateBase
Definition: pcstate.hh:57
gem5::BaseISA
Definition: isa.hh:58
gem5::RegIndex
uint16_t RegIndex
Definition: types.hh:176
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::X86ISA::misc_reg::M5Reg
@ M5Reg
Definition: misc.hh:148
gem5::X86ISA::ISA::readMiscReg
RegVal readMiscReg(RegIndex idx) override
Definition: isa.cc:219
misc.hh
float.hh
gem5::X86ISA::ISA::readMiscRegNoEffect
RegVal readMiscRegNoEffect(RegIndex idx) const override
Definition: isa.cc:208
gem5::X86ISA::ISA::inUserMode
bool inUserMode() const override
Definition: isa.hh:82

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