gem5  v22.0.0.2
ExplicitLTTarget.h
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19 
20 #ifndef __EXPLICIT_LT_TARGET_H__
21 #define __EXPLICIT_LT_TARGET_H__
22 
23 #include "tlm.h"
24 #include "tlm_utils/simple_target_socket.h"
25 //#include <systemc>
26 #include <cassert>
27 #include <vector>
28 #include <queue>
29 //#include <iostream>
30 
32 {
33 public:
35  typedef tlm::tlm_phase phase_type;
38 
39 public:
41 
42 public:
46  socket("socket")
47  {
48  // register nb_transport method
51  }
52 
54  {
55  sc_dt::uint64 address = trans.get_address();
56  assert(address < 400);
57 
58  unsigned int& data = *reinterpret_cast<unsigned int*>(trans.get_data_ptr());
59  if (trans.get_command() == tlm::TLM_WRITE_COMMAND) {
60  std::cout << name() << ": Received write request: A = 0x"
61  << std::hex << (unsigned int)address << ", D = 0x" << data
62  << std::dec << " @ " << sc_core::sc_time_stamp()
63  << std::endl;
64 
65  *reinterpret_cast<unsigned int*>(&mMem[address]) = data;
66 
67  // Synchronization on demand (eg need to assert an interrupt)
68  // Wait for passed timing annotation + wait for an extra 50 ns
71 
72  // We are synchronized, we can read/write sc_signals, wait,...
73 
74  *reinterpret_cast<unsigned int*>(trans.get_data_ptr()) =
75  *reinterpret_cast<unsigned int*>(&mMem[address]);
76 
77  } else {
78  std::cout << name() << ": Received read request: A = 0x"
79  << std::hex << (unsigned int)address
80  << std::dec << " @ " << sc_core::sc_time_stamp()
81  << std::endl;
82 
83  data = *reinterpret_cast<unsigned int*>(&mMem[address]);
84 
85  // Finish transaction (use timing annotation)
87  }
88 
90  }
91 
92  unsigned int transport_dbg(transaction_type& r)
93  {
94  if (r.get_address() >= 400) return 0;
95 
96  unsigned int tmp = (int)r.get_address();
97  unsigned int num_bytes;
98  if (tmp + r.get_data_length() >= 400) {
99  num_bytes = 400 - tmp;
100 
101  } else {
102  num_bytes = r.get_data_length();
103  }
104  if (!r.is_read() && !r.is_write()) {
105  return 0;
106  }
107  if (r.is_read()) {
108  for (unsigned int i = 0; i < num_bytes; ++i) {
109  r.get_data_ptr()[i] = mMem[i + tmp];
110  }
111 
112  } else {
113  for (unsigned int i = 0; i < num_bytes; ++i) {
114  mMem[i + tmp] = r.get_data_ptr()[i];
115  }
116  }
117  return num_bytes;
118  }
119 
120 private:
121  unsigned char mMem[400];
122 };
123 
124 #endif
data
const char data[]
Definition: circlebuf.test.cc:48
sc_core::sc_module
Definition: sc_module.hh:101
tlm_utils::simple_target_socket_b::register_b_transport
void register_b_transport(MODULE *mod, void(MODULE::*cb)(transaction_type &, sc_core::sc_time &))
Definition: simple_target_socket.h:117
tlm::tlm_phase
Definition: phase.hh:47
tlm::TLM_WRITE_COMMAND
@ TLM_WRITE_COMMAND
Definition: gp.hh:102
ExplicitLTTarget::socket
target_socket_type socket
Definition: ExplicitLTTarget.h:57
tlm::TLM_OK_RESPONSE
@ TLM_OK_RESPONSE
Definition: gp.hh:108
sc_core::SC_ZERO_TIME
const sc_time SC_ZERO_TIME
Definition: sc_time.cc:290
gem5::VegaISA::r
Bitfield< 5 > r
Definition: pagetable.hh:60
tlm_utils::simple_target_socket_b::register_transport_dbg
void register_transport_dbg(MODULE *mod, unsigned int(MODULE::*cb)(transaction_type &))
Definition: simple_target_socket.h:125
ExplicitLTTarget::ExplicitLTTarget
ExplicitLTTarget(sc_core::sc_module_name name)
Definition: ExplicitLTTarget.h:61
gem5::ArmISA::i
Bitfield< 7 > i
Definition: misc_types.hh:67
ExplicitLTTarget::transaction_type
tlm::tlm_generic_payload transaction_type
Definition: ExplicitLTTarget.h:51
ExplicitLTTarget::myBTransport
void myBTransport(transaction_type &trans, sc_core::sc_time &t)
Definition: ExplicitLTTarget.h:70
ExplicitLTTarget::phase_type
tlm::tlm_phase phase_type
Definition: ExplicitLTTarget.h:52
sc_core::SC_NS
@ SC_NS
Definition: sc_time.hh:43
tlm::tlm_generic_payload::get_command
tlm_command get_command() const
Definition: gp.hh:197
gem5::VegaISA::t
Bitfield< 51 > t
Definition: pagetable.hh:56
sc_dt::uint64
uint64_t uint64
Definition: sc_nbdefs.hh:206
ExplicitLTTarget
Definition: ExplicitLTTarget.h:31
sc_core::sc_time
Definition: sc_time.hh:49
ExplicitLTTarget::sync_enum_type
tlm::tlm_sync_enum sync_enum_type
Definition: ExplicitLTTarget.h:53
sc_core::sc_module_name
Definition: sc_module_name.hh:41
tlm_utils::simple_target_socket< ExplicitLTTarget >
ExplicitLTTarget::transport_dbg
unsigned int transport_dbg(transaction_type &r)
Definition: ExplicitLTTarget.h:109
tlm::tlm_generic_payload
Definition: gp.hh:133
sc_core::sc_object::name
const char * name() const
Definition: sc_object.cc:44
ExplicitLTTarget::target_socket_type
tlm_utils::simple_target_socket< ExplicitLTTarget > target_socket_type
Definition: ExplicitLTTarget.h:54
tlm::tlm_sync_enum
tlm_sync_enum
Definition: fw_bw_ifs.hh:48
ExplicitLTTarget::SC_HAS_PROCESS
SC_HAS_PROCESS(ExplicitLTTarget)
sc_core::sc_module::wait
void wait()
Definition: sc_module.cc:428
ExplicitLTTarget::mMem
unsigned char mMem[400]
Definition: ExplicitLTTarget.h:138
tlm::tlm_generic_payload::get_address
sc_dt::uint64 get_address() const
Definition: gp.hh:201
sc_core::sc_time_stamp
const sc_time & sc_time_stamp()
Definition: sc_main.cc:127
tlm::tlm_generic_payload::get_data_ptr
unsigned char * get_data_ptr() const
Definition: gp.hh:205
tlm::tlm_generic_payload::set_response_status
void set_response_status(const tlm_response_status response_status)
Definition: gp.hh:221

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