32#ifndef __SIMPLE_LT_INITIATOR1_H__
33#define __SIMPLE_LT_INITIATOR1_H__
56 unsigned int nrOfTransactions = 0x5,
57 unsigned int baseAddress = 0x0) :
100 std::cout <<
name() <<
": Send write request: A = 0x"
102 <<
", D = 0x" <<
mData << std::dec
106 std::cout <<
name() <<
": Send read request: A = 0x"
107 << std::hex << (
unsigned int)trans.
get_address() << std::dec
115 std::cout <<
name() <<
": Received error response @ "
119 std::cout <<
name() <<
": Received ok response";
121 std::cout <<
": D = 0x" << std::hex <<
mData << std::dec;
133 socket->b_transport(trans, t);
SC_HAS_PROCESS(SimpleLTInitiator1)
bool initTransaction(transaction_type &trans)
SimpleLTInitiator1(sc_core::sc_module_name name, unsigned int nrOfTransactions=0x5, unsigned int baseAddress=0x0)
tlm::tlm_sync_enum nb_transport_bw(transaction_type &, phase_type &, sc_core::sc_time &)
tlm::tlm_bw_transport_if bw_interface_type
tlm::tlm_sync_enum sync_enum_type
tlm::tlm_initiator_socket< 32 > initiator_socket_type
sc_core::sc_event mEndEvent
initiator_socket_type socket
unsigned int mNrOfTransactions
tlm::tlm_generic_payload transaction_type
void logStartTransation(transaction_type &trans)
void invalidate_direct_mem_ptr(sc_dt::uint64 start_range, sc_dt::uint64 end_range)
tlm::tlm_phase phase_type
unsigned int mTransactionCount
void logEndTransaction(transaction_type &trans)
unsigned int mBaseAddress
tlm::tlm_fw_transport_if fw_interface_type
const char * name() const
void set_data_ptr(unsigned char *data)
void set_dmi_allowed(bool dmi_allowed)
void set_response_status(const tlm_response_status response_status)
void set_address(const sc_dt::uint64 address)
void set_command(const tlm_command command)
sc_dt::uint64 get_address() const
tlm_response_status get_response_status() const
void set_data_length(const unsigned int length)
tlm_command get_command() const
void set_streaming_width(const unsigned int streaming_width)
const sc_time SC_ZERO_TIME
const sc_time & sc_time_stamp()
@ TLM_INCOMPLETE_RESPONSE