gem5 v24.0.0.0
Loading...
Searching...
No Matches
SimpleLTInitiator1.h
Go to the documentation of this file.
1/*****************************************************************************
2
3 Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
4 more contributor license agreements. See the NOTICE file distributed
5 with this work for additional information regarding copyright ownership.
6 Accellera licenses this file to you under the Apache License, Version 2.0
7 (the "License"); you may not use this file except in compliance with the
8 License. You may obtain a copy of the License at
9
10 http://www.apache.org/licenses/LICENSE-2.0
11
12 Unless required by applicable law or agreed to in writing, software
13 distributed under the License is distributed on an "AS IS" BASIS,
14 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
15 implied. See the License for the specific language governing
16 permissions and limitations under the License.
17
18 *****************************************************************************/
19
20//====================================================================
21// Nov 06, 2008
22//
23// Updated by:
24// Xiaopeng Qiu, JEDA Technologies, Inc
25// Email: qiuxp@jedatechnologies.net
26//
27// To fix violations of TLM2.0 rules, which are detected by JEDA
28// TLM2.0 checker.
29//
30//====================================================================
31
32#ifndef __SIMPLE_LT_INITIATOR1_H__
33#define __SIMPLE_LT_INITIATOR1_H__
34
35#include "tlm.h"
36#include <cassert>
37
39 public sc_core::sc_module,
40 public virtual tlm::tlm_bw_transport_if<>
41{
42public:
49
50public:
52
53public:
56 unsigned int nrOfTransactions = 0x5,
57 unsigned int baseAddress = 0x0) :
58 sc_core::sc_module(name),
59 socket("socket"),
60 mNrOfTransactions(nrOfTransactions),
61 mBaseAddress(baseAddress),
63 {
64 // Bind this initiator's interface to the initiator socket
65 socket(*this);
66
67 // Initiator thread
69 }
70
72 {
77
78 } else if (mTransactionCount < 2 * mNrOfTransactions) {
80 mData = 0;
82
83 } else {
84 return false;
85 }
86
87 trans.set_data_ptr(reinterpret_cast<unsigned char*>(&mData));
88 trans.set_data_length(4);
89 trans.set_streaming_width(4);
90 trans.set_dmi_allowed(false);
92
94 return true;
95 }
96
98 {
99 if (trans.get_command() == tlm::TLM_WRITE_COMMAND) {
100 std::cout << name() << ": Send write request: A = 0x"
101 << std::hex << (unsigned int)trans.get_address()
102 << ", D = 0x" << mData << std::dec
103 << " @ " << sc_core::sc_time_stamp() << std::endl;
104
105 } else {
106 std::cout << name() << ": Send read request: A = 0x"
107 << std::hex << (unsigned int)trans.get_address() << std::dec
108 << " @ " << sc_core::sc_time_stamp() << std::endl;
109 }
110 }
111
113 {
115 std::cout << name() << ": Received error response @ "
116 << sc_core::sc_time_stamp() << std::endl;
117
118 } else {
119 std::cout << name() << ": Received ok response";
120 if (trans.get_command() == tlm::TLM_READ_COMMAND) {
121 std::cout << ": D = 0x" << std::hex << mData << std::dec;
122 }
123 std::cout << " @ " << sc_core::sc_time_stamp() << std::endl;
124 }
125 }
126
127 void run()
128 {
129 transaction_type trans;
131 while (initTransaction(trans)) {
132 logStartTransation(trans);
133 socket->b_transport(trans, t);
134 wait(t);
135 logEndTransaction(trans);
137 }
138 wait();
139
140 }
141
143 {
144 assert(0); // should never happen
145 return tlm::TLM_COMPLETED;
146 }
147
149 sc_dt::uint64 end_range)
150 {
151 // No DMI support: ignore
152 }
153
154private:
156 unsigned int mNrOfTransactions;
157 unsigned int mBaseAddress;
158 unsigned int mTransactionCount;
159 unsigned int mData;
160};
161
162#endif
SC_HAS_PROCESS(SimpleLTInitiator1)
bool initTransaction(transaction_type &trans)
SimpleLTInitiator1(sc_core::sc_module_name name, unsigned int nrOfTransactions=0x5, unsigned int baseAddress=0x0)
tlm::tlm_sync_enum nb_transport_bw(transaction_type &, phase_type &, sc_core::sc_time &)
tlm::tlm_bw_transport_if bw_interface_type
tlm::tlm_sync_enum sync_enum_type
tlm::tlm_initiator_socket< 32 > initiator_socket_type
sc_core::sc_event mEndEvent
initiator_socket_type socket
unsigned int mNrOfTransactions
tlm::tlm_generic_payload transaction_type
void logStartTransation(transaction_type &trans)
void invalidate_direct_mem_ptr(sc_dt::uint64 start_range, sc_dt::uint64 end_range)
tlm::tlm_phase phase_type
unsigned int mTransactionCount
void logEndTransaction(transaction_type &trans)
tlm::tlm_fw_transport_if fw_interface_type
const char * name() const
Definition sc_object.cc:44
void set_data_ptr(unsigned char *data)
Definition gp.hh:189
void set_dmi_allowed(bool dmi_allowed)
Definition gp.hh:239
void set_response_status(const tlm_response_status response_status)
Definition gp.hh:204
void set_address(const sc_dt::uint64 address)
Definition gp.hh:185
void set_command(const tlm_command command)
Definition gp.hh:181
sc_dt::uint64 get_address() const
Definition gp.hh:184
tlm_response_status get_response_status() const
Definition gp.hh:199
void set_data_length(const unsigned int length)
Definition gp.hh:193
tlm_command get_command() const
Definition gp.hh:180
void set_streaming_width(const unsigned int streaming_width)
Definition gp.hh:213
const sc_time SC_ZERO_TIME
Definition sc_time.cc:290
const sc_time & sc_time_stamp()
Definition sc_main.cc:127
uint64_t uint64
Definition sc_nbdefs.hh:172
@ TLM_READ_COMMAND
Definition gp.hh:84
@ TLM_WRITE_COMMAND
Definition gp.hh:85
@ TLM_OK_RESPONSE
Definition gp.hh:91
@ TLM_INCOMPLETE_RESPONSE
Definition gp.hh:92
tlm_sync_enum
Definition fw_bw_ifs.hh:31
@ TLM_COMPLETED
Definition fw_bw_ifs.hh:31
#define SC_THREAD(name)
Definition sc_module.hh:313

Generated on Tue Jun 18 2024 16:24:07 for gem5 by doxygen 1.11.0