gem5  v21.2.1.1
SimpleLTInitiator1.h
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1 /*****************************************************************************
2 
3  Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
4  more contributor license agreements. See the NOTICE file distributed
5  with this work for additional information regarding copyright ownership.
6  Accellera licenses this file to you under the Apache License, Version 2.0
7  (the "License"); you may not use this file except in compliance with the
8  License. You may obtain a copy of the License at
9 
10  http://www.apache.org/licenses/LICENSE-2.0
11 
12  Unless required by applicable law or agreed to in writing, software
13  distributed under the License is distributed on an "AS IS" BASIS,
14  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
15  implied. See the License for the specific language governing
16  permissions and limitations under the License.
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18  *****************************************************************************/
19 
20 //====================================================================
21 // Nov 06, 2008
22 //
23 // Updated by:
24 // Xiaopeng Qiu, JEDA Technologies, Inc
25 // Email: qiuxp@jedatechnologies.net
26 //
27 // To fix violations of TLM2.0 rules, which are detected by JEDA
28 // TLM2.0 checker.
29 //
30 //====================================================================
31 
32 #ifndef __SIMPLE_LT_INITIATOR1_H__
33 #define __SIMPLE_LT_INITIATOR1_H__
34 
35 #include "tlm.h"
36 #include <cassert>
37 
39  public sc_core::sc_module,
40  public virtual tlm::tlm_bw_transport_if<>
41 {
42 public:
44  typedef tlm::tlm_phase phase_type;
49 
50 public:
52 
53 public:
56  unsigned int nrOfTransactions = 0x5,
57  unsigned int baseAddress = 0x0) :
59  socket("socket"),
60  mNrOfTransactions(nrOfTransactions),
61  mBaseAddress(baseAddress),
63  {
64  // Bind this initiator's interface to the initiator socket
65  socket(*this);
66 
67  // Initiator thread
69  }
70 
72  {
74  trans.set_address(mBaseAddress + 4*mTransactionCount);
76  trans.set_command(tlm::TLM_WRITE_COMMAND);
77 
78  } else if (mTransactionCount < 2 * mNrOfTransactions) {
79  trans.set_address(mBaseAddress + 4*(mTransactionCount - mNrOfTransactions));
80  mData = 0;
81  trans.set_command(tlm::TLM_READ_COMMAND);
82 
83  } else {
84  return false;
85  }
86 
87  trans.set_data_ptr(reinterpret_cast<unsigned char*>(&mData));
88  trans.set_data_length(4);
89  trans.set_streaming_width(4);
90  trans.set_dmi_allowed(false);
91  trans.set_response_status(tlm::TLM_INCOMPLETE_RESPONSE);
92 
94  return true;
95  }
96 
98  {
99  if (trans.get_command() == tlm::TLM_WRITE_COMMAND) {
100  std::cout << name() << ": Send write request: A = 0x"
101  << std::hex << (unsigned int)trans.get_address()
102  << ", D = 0x" << mData << std::dec
103  << " @ " << sc_core::sc_time_stamp() << std::endl;
104 
105  } else {
106  std::cout << name() << ": Send read request: A = 0x"
107  << std::hex << (unsigned int)trans.get_address() << std::dec
108  << " @ " << sc_core::sc_time_stamp() << std::endl;
109  }
110  }
111 
113  {
114  if (trans.get_response_status() != tlm::TLM_OK_RESPONSE) {
115  std::cout << name() << ": Received error response @ "
116  << sc_core::sc_time_stamp() << std::endl;
117 
118  } else {
119  std::cout << name() << ": Received ok response";
120  if (trans.get_command() == tlm::TLM_READ_COMMAND) {
121  std::cout << ": D = 0x" << std::hex << mData << std::dec;
122  }
123  std::cout << " @ " << sc_core::sc_time_stamp() << std::endl;
124  }
125  }
126 
127  void run()
128  {
131  while (initTransaction(trans)) {
132  logStartTransation(trans);
133  socket->b_transport(trans, t);
134  wait(t);
135  logEndTransaction(trans);
137  }
138  wait();
139 
140  }
141 
143  {
144  assert(0); // should never happen
145  return tlm::TLM_COMPLETED;
146  }
147 
148  void invalidate_direct_mem_ptr(sc_dt::uint64 start_range,
149  sc_dt::uint64 end_range)
150  {
151  // No DMI support: ignore
152  }
153 
154 private:
156  unsigned int mNrOfTransactions;
157  unsigned int mBaseAddress;
158  unsigned int mTransactionCount;
159  unsigned int mData;
160 };
161 
162 #endif
tlm::tlm_bw_transport_if
Definition: fw_bw_ifs.hh:231
tlm::TLM_INCOMPLETE_RESPONSE
@ TLM_INCOMPLETE_RESPONSE
Definition: gp.hh:109
SC_THREAD
#define SC_THREAD(name)
Definition: sc_module.hh:313
sc_core::sc_module
Definition: sc_module.hh:101
tlm::tlm_phase
Definition: phase.hh:47
SimpleLTInitiator1::run
void run()
Definition: SimpleLTInitiator1.h:144
SimpleLTInitiator1::mTransactionCount
unsigned int mTransactionCount
Definition: SimpleLTInitiator1.h:175
tlm::TLM_COMPLETED
@ TLM_COMPLETED
Definition: fw_bw_ifs.hh:65
tlm::tlm_initiator_socket< 32 >
tlm::TLM_WRITE_COMMAND
@ TLM_WRITE_COMMAND
Definition: gp.hh:102
SimpleLTInitiator1::initTransaction
bool initTransaction(transaction_type &trans)
Definition: SimpleLTInitiator1.h:88
tlm::TLM_OK_RESPONSE
@ TLM_OK_RESPONSE
Definition: gp.hh:108
sc_core::SC_ZERO_TIME
const sc_time SC_ZERO_TIME
Definition: sc_time.cc:290
SimpleLTInitiator1::sync_enum_type
tlm::tlm_sync_enum sync_enum_type
Definition: SimpleLTInitiator1.h:62
SimpleLTInitiator1::socket
initiator_socket_type socket
Definition: SimpleLTInitiator1.h:68
SimpleLTInitiator1::logStartTransation
void logStartTransation(transaction_type &trans)
Definition: SimpleLTInitiator1.h:114
tlm::tlm_fw_transport_if<>
SimpleLTInitiator1::mNrOfTransactions
unsigned int mNrOfTransactions
Definition: SimpleLTInitiator1.h:173
SimpleLTInitiator1::initiator_socket_type
tlm::tlm_initiator_socket< 32 > initiator_socket_type
Definition: SimpleLTInitiator1.h:65
sc_dt::uint64
uint64_t uint64
Definition: sc_nbdefs.hh:206
sc_core::sc_event
Definition: sc_event.hh:169
sc_core::sc_time
Definition: sc_time.hh:49
tlm::TLM_READ_COMMAND
@ TLM_READ_COMMAND
Definition: gp.hh:101
SimpleLTInitiator1::fw_interface_type
tlm::tlm_fw_transport_if fw_interface_type
Definition: SimpleLTInitiator1.h:63
SimpleLTInitiator1::bw_interface_type
tlm::tlm_bw_transport_if bw_interface_type
Definition: SimpleLTInitiator1.h:64
sc_core::sc_module_name
Definition: sc_module_name.hh:41
SimpleLTInitiator1::SC_HAS_PROCESS
SC_HAS_PROCESS(SimpleLTInitiator1)
SimpleLTInitiator1::nb_transport_bw
tlm::tlm_sync_enum nb_transport_bw(transaction_type &, phase_type &, sc_core::sc_time &)
Definition: SimpleLTInitiator1.h:159
gem5::ArmISA::t
Bitfield< 5 > t
Definition: misc_types.hh:71
SimpleLTInitiator1::mEndEvent
sc_core::sc_event mEndEvent
Definition: SimpleLTInitiator1.h:172
SimpleLTInitiator1::SimpleLTInitiator1
SimpleLTInitiator1(sc_core::sc_module_name name, unsigned int nrOfTransactions=0x5, unsigned int baseAddress=0x0)
Definition: SimpleLTInitiator1.h:72
tlm::tlm_generic_payload
Definition: gp.hh:133
SimpleLTInitiator1::invalidate_direct_mem_ptr
void invalidate_direct_mem_ptr(sc_dt::uint64 start_range, sc_dt::uint64 end_range)
Definition: SimpleLTInitiator1.h:165
sc_core::sc_object::name
const char * name() const
Definition: sc_object.cc:44
SimpleLTInitiator1::mData
unsigned int mData
Definition: SimpleLTInitiator1.h:176
SimpleLTInitiator1
TLM definitions.
Definition: SimpleLTInitiator1.h:38
tlm::tlm_sync_enum
tlm_sync_enum
Definition: fw_bw_ifs.hh:48
sc_core::sc_module::wait
void wait()
Definition: sc_module.cc:428
SimpleLTInitiator1::transaction_type
tlm::tlm_generic_payload transaction_type
Definition: SimpleLTInitiator1.h:60
SimpleLTInitiator1::phase_type
tlm::tlm_phase phase_type
Definition: SimpleLTInitiator1.h:61
SimpleLTInitiator1::logEndTransaction
void logEndTransaction(transaction_type &trans)
Definition: SimpleLTInitiator1.h:129
sc_core::sc_time_stamp
const sc_time & sc_time_stamp()
Definition: sc_main.cc:127
SimpleLTInitiator1::mBaseAddress
unsigned int mBaseAddress
Definition: SimpleLTInitiator1.h:174

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