gem5 v24.0.0.0
Loading...
Searching...
No Matches
types.hh
Go to the documentation of this file.
1/*
2 * Copyright (c) 2007 MIPS Technologies, Inc.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#ifndef __ARCH_MIPS_TYPES_HH__
30#define __ARCH_MIPS_TYPES_HH__
31
32#include <cstdint>
33
34#include "arch/mips/pcstate.hh"
35
36namespace gem5
37{
38
39namespace MipsISA
40{
41
42typedef uint32_t MachInst;
43typedef uint64_t ExtMachInst;
44
45//used in FP convert & round function
69
70//used in FP convert & round function
78
79struct CoreSpecific
80{
102
103 // MIPS CP0 State - First individual variables
104 // Page numbers refer to revision 2.50 (July 2005) of the MIPS32 ARM,
105 // Volume III (PRA)
106 unsigned CP0_IntCtl_IPTI; // Page 93, IP Timer Interrupt
107 unsigned CP0_IntCtl_IPPCI; // Page 94, IP Performance Counter Interrupt
108 unsigned CP0_SrsCtl_HSS; // Page 95, Highest Implemented Shadow Set
109 unsigned CP0_PRId_CompanyOptions; // Page 105, Manufacture options
110 unsigned CP0_PRId_CompanyID; // Page 105, Company ID - (0-255, 1=>MIPS)
111 unsigned CP0_PRId_ProcessorID; // Page 105
112 unsigned CP0_PRId_Revision; // Page 105
113 unsigned CP0_EBase_CPUNum; // Page 106, CPU Number in a multiprocessor
114 //system
115 unsigned CP0_Config_BE; // Page 108, Big/Little Endian mode
116 unsigned CP0_Config_AT; //Page 109
117 unsigned CP0_Config_AR; //Page 109
118 unsigned CP0_Config_MT; //Page 109
119 unsigned CP0_Config_VI; //Page 109
120 unsigned CP0_Config1_M; // Page 110
121 unsigned CP0_Config1_MMU; // Page 110
122 unsigned CP0_Config1_IS; // Page 110
123 unsigned CP0_Config1_IL; // Page 111
124 unsigned CP0_Config1_IA; // Page 111
125 unsigned CP0_Config1_DS; // Page 111
126 unsigned CP0_Config1_DL; // Page 112
127 unsigned CP0_Config1_DA; // Page 112
128 bool CP0_Config1_C2; // Page 112
129 bool CP0_Config1_MD;// Page 112 - Technically not used in MIPS32
130 bool CP0_Config1_PC;// Page 112
131 bool CP0_Config1_WR;// Page 113
132 bool CP0_Config1_CA;// Page 113
133 bool CP0_Config1_EP;// Page 113
134 bool CP0_Config1_FP;// Page 113
135 bool CP0_Config2_M; // Page 114
136 unsigned CP0_Config2_TU;// Page 114
137 unsigned CP0_Config2_TS;// Page 114
138 unsigned CP0_Config2_TL;// Page 115
139 unsigned CP0_Config2_TA;// Page 115
140 unsigned CP0_Config2_SU;// Page 115
141 unsigned CP0_Config2_SS;// Page 115
142 unsigned CP0_Config2_SL;// Page 116
143 unsigned CP0_Config2_SA;// Page 116
144 bool CP0_Config3_M;
145 bool CP0_Config3_DSPP;// Page 117
146 bool CP0_Config3_LPA;// Page 117
147 bool CP0_Config3_VEIC;// Page 118
148 bool CP0_Config3_VInt; // Page 118
149 bool CP0_Config3_SP;// Page 118
150 bool CP0_Config3_MT;// Page 119
151 bool CP0_Config3_SM;// Page 119
152 bool CP0_Config3_TL;// Page 119
153
154 bool CP0_WatchHi_M; // Page 124
155 bool CP0_PerfCtr_M; // Page 130
156 bool CP0_PerfCtr_W; // Page 130
157
158
159 // Then, whole registers
160 unsigned CP0_PRId;
161 unsigned CP0_Config;
162 unsigned CP0_Config1;
163 unsigned CP0_Config2;
164 unsigned CP0_Config3;
165};
166
167} // namespace MipsISA
168} // namespace gem5
169
170#endif
gem5::MipsISA::SINGLE_TO_DOUBLE
@ SINGLE_TO_DOUBLE
Definition types.hh:48
gem5::MipsISA::DOUBLE_TO_SINGLE
@ DOUBLE_TO_SINGLE
Definition types.hh:52
gem5::MipsISA::LONG_TO_DOUBLE
@ LONG_TO_DOUBLE
Definition types.hh:57
gem5::MipsISA::WORD_TO_DOUBLE
@ WORD_TO_DOUBLE
Definition types.hh:62
gem5::MipsISA::DOUBLE_TO_LONG
@ DOUBLE_TO_LONG
Definition types.hh:54
gem5::MipsISA::LONG_TO_SINGLE
@ LONG_TO_SINGLE
Definition types.hh:56
gem5::MipsISA::SINGLE_TO_WORD
@ SINGLE_TO_WORD
Definition types.hh:49
gem5::MipsISA::SINGLE_TO_LONG
@ SINGLE_TO_LONG
Definition types.hh:50
gem5::MipsISA::WORD_TO_SINGLE
@ WORD_TO_SINGLE
Definition types.hh:61
gem5::MipsISA::DOUBLE_TO_WORD
@ DOUBLE_TO_WORD
Definition types.hh:53
gem5::MipsISA::MachInst
uint32_t MachInst
Definition types.hh:42
gem5::MipsISA::ExtMachInst
uint64_t ExtMachInst
Definition types.hh:43
gem5
Copyright (c) 2024 - Pranith Kumar Copyright (c) 2020 Inria All rights reserved.
Definition binary32.hh:36
gem5::MipsISA::CoreSpecific::CP0_PRId_CompanyOptions
unsigned CP0_PRId_CompanyOptions
Definition types.hh:109
Generated on Tue Jun 18 2024 16:24:00 for gem5 by doxygen 1.11.0