gem5  v21.1.0.2
types.hh
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1 /*
2  * Copyright (c) 2007 MIPS Technologies, Inc.
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16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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28 
29 #ifndef __ARCH_MIPS_TYPES_HH__
30 #define __ARCH_MIPS_TYPES_HH__
31 
32 #include <cstdint>
33 
34 #include "arch/mips/pcstate.hh"
35 
36 namespace gem5
37 {
38 
39 namespace MipsISA
40 {
41 
42 typedef uint32_t MachInst;
43 typedef uint64_t ExtMachInst;
44 
45 //used in FP convert & round function
47 {
51 
55 
60 
65 
68 };
69 
70 //used in FP convert & round function
72 {
77 };
78 
80 {
90  CP0_Config1_MD(false), CP0_Config1_PC(false), CP0_Config1_WR(false),
91  CP0_Config1_CA(false), CP0_Config1_EP(false), CP0_Config1_FP(false),
95  CP0_Config3_M(false), CP0_Config3_DSPP(false), CP0_Config3_LPA(false),
96  CP0_Config3_VEIC(false), CP0_Config3_VInt(false),
97  CP0_Config3_SP(false), CP0_Config3_MT(false), CP0_Config3_SM(false),
98  CP0_Config3_TL(false), CP0_WatchHi_M(false), CP0_PerfCtr_M(false),
99  CP0_PerfCtr_W(false), CP0_PRId(0), CP0_Config(0), CP0_Config1(0),
100  CP0_Config2(0), CP0_Config3(0)
101  { }
102 
103  // MIPS CP0 State - First individual variables
104  // Page numbers refer to revision 2.50 (July 2005) of the MIPS32 ARM,
105  // Volume III (PRA)
106  unsigned CP0_IntCtl_IPTI; // Page 93, IP Timer Interrupt
107  unsigned CP0_IntCtl_IPPCI; // Page 94, IP Performance Counter Interrupt
108  unsigned CP0_SrsCtl_HSS; // Page 95, Highest Implemented Shadow Set
109  unsigned CP0_PRId_CompanyOptions; // Page 105, Manufacture options
110  unsigned CP0_PRId_CompanyID; // Page 105, Company ID - (0-255, 1=>MIPS)
111  unsigned CP0_PRId_ProcessorID; // Page 105
112  unsigned CP0_PRId_Revision; // Page 105
113  unsigned CP0_EBase_CPUNum; // Page 106, CPU Number in a multiprocessor
114  //system
115  unsigned CP0_Config_BE; // Page 108, Big/Little Endian mode
116  unsigned CP0_Config_AT; //Page 109
117  unsigned CP0_Config_AR; //Page 109
118  unsigned CP0_Config_MT; //Page 109
119  unsigned CP0_Config_VI; //Page 109
120  unsigned CP0_Config1_M; // Page 110
121  unsigned CP0_Config1_MMU; // Page 110
122  unsigned CP0_Config1_IS; // Page 110
123  unsigned CP0_Config1_IL; // Page 111
124  unsigned CP0_Config1_IA; // Page 111
125  unsigned CP0_Config1_DS; // Page 111
126  unsigned CP0_Config1_DL; // Page 112
127  unsigned CP0_Config1_DA; // Page 112
128  bool CP0_Config1_C2; // Page 112
129  bool CP0_Config1_MD;// Page 112 - Technically not used in MIPS32
130  bool CP0_Config1_PC;// Page 112
131  bool CP0_Config1_WR;// Page 113
132  bool CP0_Config1_CA;// Page 113
133  bool CP0_Config1_EP;// Page 113
134  bool CP0_Config1_FP;// Page 113
135  bool CP0_Config2_M; // Page 114
136  unsigned CP0_Config2_TU;// Page 114
137  unsigned CP0_Config2_TS;// Page 114
138  unsigned CP0_Config2_TL;// Page 115
139  unsigned CP0_Config2_TA;// Page 115
140  unsigned CP0_Config2_SU;// Page 115
141  unsigned CP0_Config2_SS;// Page 115
142  unsigned CP0_Config2_SL;// Page 116
143  unsigned CP0_Config2_SA;// Page 116
145  bool CP0_Config3_DSPP;// Page 117
146  bool CP0_Config3_LPA;// Page 117
147  bool CP0_Config3_VEIC;// Page 118
148  bool CP0_Config3_VInt; // Page 118
149  bool CP0_Config3_SP;// Page 118
150  bool CP0_Config3_MT;// Page 119
151  bool CP0_Config3_SM;// Page 119
152  bool CP0_Config3_TL;// Page 119
153 
154  bool CP0_WatchHi_M; // Page 124
155  bool CP0_PerfCtr_M; // Page 130
156  bool CP0_PerfCtr_W; // Page 130
157 
158 
159  // Then, whole registers
160  unsigned CP0_PRId;
161  unsigned CP0_Config;
162  unsigned CP0_Config1;
163  unsigned CP0_Config2;
164  unsigned CP0_Config3;
165 };
166 
167 } // namespace MipsISA
168 } // namespace gem5
169 
170 #endif
gem5::MipsISA::CoreSpecific::CP0_Config1
unsigned CP0_Config1
Definition: types.hh:162
gem5::MipsISA::CoreSpecific::CP0_Config1_DS
unsigned CP0_Config1_DS
Definition: types.hh:125
gem5::MipsISA::CoreSpecific::CP0_Config2_TA
unsigned CP0_Config2_TA
Definition: types.hh:139
gem5::MipsISA::CoreSpecific::CP0_Config3_SM
bool CP0_Config3_SM
Definition: types.hh:151
gem5::MipsISA::WORD_TO_DOUBLE
@ WORD_TO_DOUBLE
Definition: types.hh:62
gem5::MipsISA::CoreSpecific::CP0_Config_VI
unsigned CP0_Config_VI
Definition: types.hh:119
gem5::MipsISA::CoreSpecific::CP0_Config3_LPA
bool CP0_Config3_LPA
Definition: types.hh:146
gem5::MipsISA::CoreSpecific::CP0_Config1_IA
unsigned CP0_Config1_IA
Definition: types.hh:124
gem5::MipsISA::CoreSpecific::CP0_Config3_SP
bool CP0_Config3_SP
Definition: types.hh:149
gem5::MipsISA::LONG_TO_PS
@ LONG_TO_PS
Definition: types.hh:59
gem5::MipsISA::CoreSpecific::CP0_IntCtl_IPPCI
unsigned CP0_IntCtl_IPPCI
Definition: types.hh:107
gem5::MipsISA::CoreSpecific::CP0_Config2_SA
unsigned CP0_Config2_SA
Definition: types.hh:143
gem5::MipsISA::CoreSpecific::CP0_IntCtl_IPTI
unsigned CP0_IntCtl_IPTI
Definition: types.hh:106
gem5::MipsISA::LONG_TO_DOUBLE
@ LONG_TO_DOUBLE
Definition: types.hh:57
gem5::MipsISA::CoreSpecific::CP0_Config3_TL
bool CP0_Config3_TL
Definition: types.hh:152
gem5::MipsISA::RND_ZERO
@ RND_ZERO
Definition: types.hh:73
gem5::MipsISA::RoundMode
RoundMode
Definition: types.hh:71
gem5::MipsISA::CoreSpecific::CP0_Config1_MD
bool CP0_Config1_MD
Definition: types.hh:129
gem5::MipsISA::CoreSpecific::CP0_Config2
unsigned CP0_Config2
Definition: types.hh:163
gem5::MipsISA::CoreSpecific::CP0_Config1_CA
bool CP0_Config1_CA
Definition: types.hh:132
gem5::MipsISA::RND_DOWN
@ RND_DOWN
Definition: types.hh:74
gem5::MipsISA::CoreSpecific::CP0_Config1_M
unsigned CP0_Config1_M
Definition: types.hh:120
gem5::MipsISA::CoreSpecific::CP0_Config1_DA
unsigned CP0_Config1_DA
Definition: types.hh:127
gem5::MipsISA::CoreSpecific::CP0_SrsCtl_HSS
unsigned CP0_SrsCtl_HSS
Definition: types.hh:108
gem5::MipsISA::CoreSpecific::CP0_PRId
unsigned CP0_PRId
Definition: types.hh:160
gem5::MipsISA::DOUBLE_TO_SINGLE
@ DOUBLE_TO_SINGLE
Definition: types.hh:52
gem5::MipsISA::PL_TO_SINGLE
@ PL_TO_SINGLE
Definition: types.hh:66
gem5::MipsISA::CoreSpecific::CP0_Config2_SU
unsigned CP0_Config2_SU
Definition: types.hh:140
gem5::MipsISA::CoreSpecific::CP0_Config1_DL
unsigned CP0_Config1_DL
Definition: types.hh:126
gem5::MipsISA::CoreSpecific::CP0_Config3_M
bool CP0_Config3_M
Definition: types.hh:144
gem5::MipsISA::CoreSpecific::CP0_Config1_C2
bool CP0_Config1_C2
Definition: types.hh:128
gem5::MipsISA::LONG_TO_WORD
@ LONG_TO_WORD
Definition: types.hh:58
gem5::MipsISA::CoreSpecific::CP0_Config3
unsigned CP0_Config3
Definition: types.hh:164
gem5::MipsISA::DOUBLE_TO_WORD
@ DOUBLE_TO_WORD
Definition: types.hh:53
gem5::MipsISA::CoreSpecific::CP0_PerfCtr_M
bool CP0_PerfCtr_M
Definition: types.hh:155
gem5::MipsISA::ExtMachInst
uint64_t ExtMachInst
Definition: types.hh:43
gem5::MipsISA::CoreSpecific::CP0_WatchHi_M
bool CP0_WatchHi_M
Definition: types.hh:154
gem5::MipsISA::CoreSpecific::CP0_Config2_TU
unsigned CP0_Config2_TU
Definition: types.hh:136
gem5::MipsISA::LONG_TO_SINGLE
@ LONG_TO_SINGLE
Definition: types.hh:56
gem5::MipsISA::CoreSpecific::CP0_Config3_VInt
bool CP0_Config3_VInt
Definition: types.hh:148
gem5::MipsISA::CoreSpecific::CP0_Config3_VEIC
bool CP0_Config3_VEIC
Definition: types.hh:147
gem5::MipsISA::CoreSpecific::CP0_Config3_DSPP
bool CP0_Config3_DSPP
Definition: types.hh:145
gem5::MipsISA::WORD_TO_PS
@ WORD_TO_PS
Definition: types.hh:64
gem5::MipsISA::CoreSpecific::CP0_Config1_MMU
unsigned CP0_Config1_MMU
Definition: types.hh:121
gem5::MipsISA::CoreSpecific::CP0_Config2_M
bool CP0_Config2_M
Definition: types.hh:135
gem5::MipsISA::RND_NEAREST
@ RND_NEAREST
Definition: types.hh:76
gem5::MipsISA::CoreSpecific::CP0_Config1_IS
unsigned CP0_Config1_IS
Definition: types.hh:122
gem5::MipsISA::SINGLE_TO_DOUBLE
@ SINGLE_TO_DOUBLE
Definition: types.hh:48
gem5::MipsISA::CoreSpecific::CP0_Config
unsigned CP0_Config
Definition: types.hh:161
gem5::MipsISA::CoreSpecific::CP0_Config1_WR
bool CP0_Config1_WR
Definition: types.hh:131
gem5::MipsISA::CoreSpecific::CP0_PRId_ProcessorID
unsigned CP0_PRId_ProcessorID
Definition: types.hh:111
gem5::MipsISA::MachInst
uint32_t MachInst
Definition: types.hh:42
gem5::MipsISA::CoreSpecific
Definition: types.hh:79
gem5::MipsISA::CoreSpecific::CP0_PRId_Revision
unsigned CP0_PRId_Revision
Definition: types.hh:112
gem5::MipsISA::CoreSpecific::CoreSpecific
CoreSpecific()
Definition: types.hh:81
gem5::MipsISA::CoreSpecific::CP0_PRId_CompanyOptions
unsigned CP0_PRId_CompanyOptions
Definition: types.hh:109
gem5::MipsISA::SINGLE_TO_LONG
@ SINGLE_TO_LONG
Definition: types.hh:50
gem5::MipsISA::CoreSpecific::CP0_Config1_IL
unsigned CP0_Config1_IL
Definition: types.hh:123
gem5::MipsISA::ConvertType
ConvertType
Definition: types.hh:46
gem5::MipsISA::RND_UP
@ RND_UP
Definition: types.hh:75
gem5::MipsISA::CoreSpecific::CP0_Config1_PC
bool CP0_Config1_PC
Definition: types.hh:130
gem5::MipsISA::CoreSpecific::CP0_Config_AT
unsigned CP0_Config_AT
Definition: types.hh:116
gem5::MipsISA::SINGLE_TO_WORD
@ SINGLE_TO_WORD
Definition: types.hh:49
gem5::MipsISA::CoreSpecific::CP0_Config3_MT
bool CP0_Config3_MT
Definition: types.hh:150
gem5::MipsISA::CoreSpecific::CP0_Config_MT
unsigned CP0_Config_MT
Definition: types.hh:118
gem5::MipsISA::CoreSpecific::CP0_EBase_CPUNum
unsigned CP0_EBase_CPUNum
Definition: types.hh:113
gem5::MipsISA::CoreSpecific::CP0_Config_AR
unsigned CP0_Config_AR
Definition: types.hh:117
gem5::MipsISA::CoreSpecific::CP0_Config1_FP
bool CP0_Config1_FP
Definition: types.hh:134
gem5::MipsISA::CoreSpecific::CP0_Config_BE
unsigned CP0_Config_BE
Definition: types.hh:115
gem5::MipsISA::CoreSpecific::CP0_Config2_TS
unsigned CP0_Config2_TS
Definition: types.hh:137
gem5::MipsISA::CoreSpecific::CP0_PerfCtr_W
bool CP0_PerfCtr_W
Definition: types.hh:156
gem5::MipsISA::DOUBLE_TO_LONG
@ DOUBLE_TO_LONG
Definition: types.hh:54
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::MipsISA::WORD_TO_LONG
@ WORD_TO_LONG
Definition: types.hh:63
pcstate.hh
gem5::MipsISA::PU_TO_SINGLE
@ PU_TO_SINGLE
Definition: types.hh:67
gem5::MipsISA::CoreSpecific::CP0_Config2_SS
unsigned CP0_Config2_SS
Definition: types.hh:141
gem5::MipsISA::CoreSpecific::CP0_PRId_CompanyID
unsigned CP0_PRId_CompanyID
Definition: types.hh:110
gem5::MipsISA::CoreSpecific::CP0_Config2_TL
unsigned CP0_Config2_TL
Definition: types.hh:138
gem5::MipsISA::CoreSpecific::CP0_Config1_EP
bool CP0_Config1_EP
Definition: types.hh:133
gem5::MipsISA::WORD_TO_SINGLE
@ WORD_TO_SINGLE
Definition: types.hh:61
gem5::MipsISA::CoreSpecific::CP0_Config2_SL
unsigned CP0_Config2_SL
Definition: types.hh:142

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