gem5  v21.1.0.2
Classes | Typedefs | Enumerations | Functions | Variables
gem5::MipsISA Namespace Reference

Classes

class  AddressErrorFault
 
class  AddressFault
 
class  BreakpointFault
 
class  CoprocessorUnusableFault
 
struct  CoreSpecific
 
class  Decoder
 
class  DspStateDisabledFault
 
class  EmuLinux
 
class  IntegerOverflowFault
 
class  InterruptFault
 
class  Interrupts
 
class  ISA
 
class  MachineCheckFault
 
class  MipsFault
 
class  MipsFaultBase
 
class  MMU
 
class  NonMaskableInterrupt
 
struct  PTE
 
class  RemoteGDB
 
class  ReservedInstructionFault
 
class  ResetFault
 
class  SEWorkload
 
class  SoftResetFault
 
class  StackTrace
 
class  SystemCallFault
 
class  ThreadFault
 
class  TLB
 
struct  TlbEntry
 
class  TlbFault
 
class  TlbInvalidFault
 
class  TlbModifiedFault
 
class  TlbRefillFault
 
class  TrapFault
 

Typedefs

typedef MipsFaultBase::FaultVals FaultVals
 
typedef Addr FaultVect
 
typedef GenericISA::DelaySlotPCState< 4 > PCState
 
typedef uint32_t MachInst
 
typedef uint64_t ExtMachInst
 
using VecElem = ::gem5::DummyVecElem
 
using VecRegContainer = ::gem5::DummyVecRegContainer
 
using VecPredRegContainer = ::gem5::DummyVecPredRegContainer
 

Enumerations

enum  {
  SIMD_FMT_L, SIMD_FMT_W, SIMD_FMT_PH, SIMD_FMT_QB,
  SIMD_NUM_FMTS
}
 
enum  {
  DSP_POS, DSP_SCOUNT, DSP_C, DSP_OUFLAG,
  DSP_CCOND, DSP_EFI, DSP_NUM_FIELDS
}
 
enum  { CMP_EQ, CMP_LT, CMP_LE }
 
enum  {
  MODE_L, MODE_R, MODE_LA, MODE_RA,
  MODE_X
}
 
enum  { UNSIGNED, SIGNED }
 
enum  { NOSATURATE, SATURATE }
 
enum  { NOROUND, ROUND }
 
enum  ExcCode {
  ExcCodeDummy = 0, ExcCodeInt = 0, ExcCodeMod = 1, ExcCodeTlbL = 2,
  ExcCodeTlbS = 3, ExcCodeAdEL = 4, ExcCodeAdES = 5, ExcCodeIBE = 6,
  ExcCodeDBE = 7, ExcCodeSys = 8, ExcCodeBp = 9, ExcCodeRI = 10,
  ExcCodeCpU = 11, ExcCodeOv = 12, ExcCodeTr = 13, ExcCodeC2E = 18,
  ExcCodeMDMX = 22, ExcCodeWatch = 23, ExcCodeMCheck = 24, ExcCodeThread = 25,
  ExcCodeCacheErr = 30
}
 
enum  InterruptLevels {
  INTLEVEL_SOFTWARE_MIN = 4, INTLEVEL_SOFTWARE_MAX = 19, INTLEVEL_EXTERNAL_MIN = 20, INTLEVEL_EXTERNAL_MAX = 34,
  INTLEVEL_IRQ0 = 20, INTLEVEL_IRQ1 = 21, INTINDEX_ETHERNET = 0, INTINDEX_SCSI = 1,
  INTLEVEL_IRQ2 = 22, INTLEVEL_IRQ3 = 23, INTLEVEL_SERIAL = 33, NumInterruptLevels = INTLEVEL_EXTERNAL_MAX
}
 
enum  FPControlRegNums {
  FLOATREG_FIR = NumFloatArchRegs, FLOATREG_FCCR, FLOATREG_FEXR, FLOATREG_FENR,
  FLOATREG_FCSR
}
 
enum  FCSRBits {
  Inexact = 1, Underflow, Overflow, DivideByZero,
  Invalid, Unimplemented
}
 
enum  FCSRFields { Flag_Field = 1, Enable_Field = 6, Cause_Field = 11 }
 
enum  MiscIntRegNums {
  INTREG_LO = NumIntArchRegs, INTREG_DSP_LO0 = INTREG_LO, INTREG_HI, INTREG_DSP_HI0 = INTREG_HI,
  INTREG_DSP_ACX0, INTREG_DSP_LO1, INTREG_DSP_HI1, INTREG_DSP_ACX1,
  INTREG_DSP_LO2, INTREG_DSP_HI2, INTREG_DSP_ACX2, INTREG_DSP_LO3,
  INTREG_DSP_HI3, INTREG_DSP_ACX3, INTREG_DSP_CONTROL
}
 
enum  MiscRegIndex {
  MISCREG_INDEX = 0, MISCREG_MVP_CONTROL, MISCREG_MVP_CONF0, MISCREG_MVP_CONF1,
  MISCREG_CP0_RANDOM = 8, MISCREG_VPE_CONTROL, MISCREG_VPE_CONF0, MISCREG_VPE_CONF1,
  MISCREG_YQMASK, MISCREG_VPE_SCHEDULE, MISCREG_VPE_SCHEFBACK, MISCREG_VPE_OPT,
  MISCREG_ENTRYLO0 = 16, MISCREG_TC_STATUS, MISCREG_TC_BIND, MISCREG_TC_RESTART,
  MISCREG_TC_HALT, MISCREG_TC_CONTEXT, MISCREG_TC_SCHEDULE, MISCREG_TC_SCHEFBACK,
  MISCREG_ENTRYLO1 = 24, MISCREG_CONTEXT = 32, MISCREG_CONTEXT_CONFIG, MISCREG_PAGEMASK = 40,
  MISCREG_PAGEGRAIN = 41, MISCREG_WIRED = 48, MISCREG_SRS_CONF0, MISCREG_SRS_CONF1,
  MISCREG_SRS_CONF2, MISCREG_SRS_CONF3, MISCREG_SRS_CONF4, MISCREG_HWRENA = 56,
  MISCREG_BADVADDR = 64, MISCREG_COUNT = 72, MISCREG_ENTRYHI = 80, MISCREG_COMPARE = 88,
  MISCREG_STATUS = 96, MISCREG_INTCTL, MISCREG_SRSCTL, MISCREG_SRSMAP,
  MISCREG_CAUSE = 104, MISCREG_EPC = 112, MISCREG_PRID = 120, MISCREG_EBASE,
  MISCREG_CONFIG = 128, MISCREG_CONFIG1, MISCREG_CONFIG2, MISCREG_CONFIG3,
  MISCREG_CONFIG4, MISCREG_CONFIG5, MISCREG_CONFIG6, MISCREG_CONFIG7,
  MISCREG_LLADDR = 136, MISCREG_WATCHLO0 = 144, MISCREG_WATCHLO1, MISCREG_WATCHLO2,
  MISCREG_WATCHLO3, MISCREG_WATCHLO4, MISCREG_WATCHLO5, MISCREG_WATCHLO6,
  MISCREG_WATCHLO7, MISCREG_WATCHHI0 = 152, MISCREG_WATCHHI1, MISCREG_WATCHHI2,
  MISCREG_WATCHHI3, MISCREG_WATCHHI4, MISCREG_WATCHHI5, MISCREG_WATCHHI6,
  MISCREG_WATCHHI7, MISCREG_XCCONTEXT64 = 160, MISCREG_DEBUG = 184, MISCREG_TRACE_CONTROL1,
  MISCREG_TRACE_CONTROL2, MISCREG_USER_TRACE_DATA, MISCREG_TRACE_BPC, MISCREG_DEPC = 192,
  MISCREG_PERFCNT0 = 200, MISCREG_PERFCNT1, MISCREG_PERFCNT2, MISCREG_PERFCNT3,
  MISCREG_PERFCNT4, MISCREG_PERFCNT5, MISCREG_PERFCNT6, MISCREG_PERFCNT7,
  MISCREG_ERRCTL = 208, MISCREG_CACHEERR0 = 216, MISCREG_CACHEERR1, MISCREG_CACHEERR2,
  MISCREG_CACHEERR3, MISCREG_TAGLO0 = 224, MISCREG_DATALO1, MISCREG_TAGLO2,
  MISCREG_DATALO3, MISCREG_TAGLO4, MISCREG_DATALO5, MISCREG_TAGLO6,
  MISCREG_DATALO7, MISCREG_TAGHI0 = 232, MISCREG_DATAHI1, MISCREG_TAGHI2,
  MISCREG_DATAHI3, MISCREG_TAGHI4, MISCREG_DATAHI5, MISCREG_TAGHI6,
  MISCREG_DATAHI7, MISCREG_ERROR_EPC = 240, MISCREG_DESAVE = 248, MISCREG_LLFLAG = 257,
  MISCREG_TP_VALUE, MISCREG_NUMREGS
}
 
enum  ConvertType {
  SINGLE_TO_DOUBLE, SINGLE_TO_WORD, SINGLE_TO_LONG, DOUBLE_TO_SINGLE,
  DOUBLE_TO_WORD, DOUBLE_TO_LONG, LONG_TO_SINGLE, LONG_TO_DOUBLE,
  LONG_TO_WORD, LONG_TO_PS, WORD_TO_SINGLE, WORD_TO_DOUBLE,
  WORD_TO_LONG, WORD_TO_PS, PL_TO_SINGLE, PU_TO_SINGLE
}
 
enum  RoundMode { RND_ZERO, RND_DOWN, RND_UP, RND_NEAREST }
 

Functions

int32_t bitrev (int32_t value)
 
uint64_t dspSaturate (uint64_t value, int32_t fmt, int32_t sign, uint32_t *overflow)
 
uint64_t checkOverflow (uint64_t value, int32_t fmt, int32_t sign, uint32_t *overflow)
 
uint64_t signExtend (uint64_t value, int32_t signpos)
 
uint64_t addHalfLsb (uint64_t value, int32_t lsbpos)
 
int32_t dspAbs (int32_t a, int32_t fmt, uint32_t *dspctl)
 
int32_t dspAdd (int32_t a, int32_t b, int32_t fmt, int32_t saturate, int32_t sign, uint32_t *dspctl)
 
int32_t dspAddh (int32_t a, int32_t b, int32_t fmt, int32_t round, int32_t sign)
 
int32_t dspSub (int32_t a, int32_t b, int32_t fmt, int32_t saturate, int32_t sign, uint32_t *dspctl)
 
int32_t dspSubh (int32_t a, int32_t b, int32_t fmt, int32_t round, int32_t sign)
 
int32_t dspShll (int32_t a, uint32_t sa, int32_t fmt, int32_t saturate, int32_t sign, uint32_t *dspctl)
 
int32_t dspShrl (int32_t a, uint32_t sa, int32_t fmt, int32_t sign)
 
int32_t dspShra (int32_t a, uint32_t sa, int32_t fmt, int32_t round, int32_t sign, uint32_t *dspctl)
 
int32_t dspMul (int32_t a, int32_t b, int32_t fmt, int32_t saturate, uint32_t *dspctl)
 
int32_t dspMulq (int32_t a, int32_t b, int32_t fmt, int32_t saturate, int32_t round, uint32_t *dspctl)
 
int32_t dspMuleu (int32_t a, int32_t b, int32_t mode, uint32_t *dspctl)
 
int32_t dspMuleq (int32_t a, int32_t b, int32_t mode, uint32_t *dspctl)
 
int64_t dspDpaq (int64_t dspac, int32_t a, int32_t b, int32_t ac, int32_t infmt, int32_t outfmt, int32_t postsat, int32_t mode, uint32_t *dspctl)
 
int64_t dspDpsq (int64_t dspac, int32_t a, int32_t b, int32_t ac, int32_t infmt, int32_t outfmt, int32_t postsat, int32_t mode, uint32_t *dspctl)
 
int64_t dspDpa (int64_t dspac, int32_t a, int32_t b, int32_t ac, int32_t fmt, int32_t sign, int32_t mode)
 
int64_t dspDps (int64_t dspac, int32_t a, int32_t b, int32_t ac, int32_t fmt, int32_t sign, int32_t mode)
 
int64_t dspMaq (int64_t dspac, int32_t a, int32_t b, int32_t ac, int32_t fmt, int32_t mode, int32_t saturate, uint32_t *dspctl)
 
int64_t dspMulsa (int64_t dspac, int32_t a, int32_t b, int32_t ac, int32_t fmt)
 
int64_t dspMulsaq (int64_t dspac, int32_t a, int32_t b, int32_t ac, int32_t fmt, uint32_t *dspctl)
 
void dspCmp (int32_t a, int32_t b, int32_t fmt, int32_t sign, int32_t op, uint32_t *dspctl)
 
int32_t dspCmpg (int32_t a, int32_t b, int32_t fmt, int32_t sign, int32_t op)
 
int32_t dspCmpgd (int32_t a, int32_t b, int32_t fmt, int32_t sign, int32_t op, uint32_t *dspctl)
 
int32_t dspPrece (int32_t a, int32_t infmt, int32_t insign, int32_t outfmt, int32_t outsign, int32_t mode)
 
int32_t dspPrecrqu (int32_t a, int32_t b, uint32_t *dspctl)
 
int32_t dspPrecrq (int32_t a, int32_t b, int32_t fmt, uint32_t *dspctl)
 
int32_t dspPrecrSra (int32_t a, int32_t b, int32_t sa, int32_t fmt, int32_t round)
 
int32_t dspPick (int32_t a, int32_t b, int32_t fmt, uint32_t *dspctl)
 
int32_t dspPack (int32_t a, int32_t b, int32_t fmt)
 
int32_t dspExtr (int64_t dspac, int32_t fmt, int32_t sa, int32_t round, int32_t saturate, uint32_t *dspctl)
 
int32_t dspExtp (int64_t dspac, int32_t size, uint32_t *dspctl)
 
int32_t dspExtpd (int64_t dspac, int32_t size, uint32_t *dspctl)
 
void simdPack (uint64_t *values_ptr, int32_t *reg, int32_t fmt)
 
void simdUnpack (int32_t reg, uint64_t *values_ptr, int32_t fmt, int32_t sign)
 
void writeDSPControl (uint32_t *dspctl, uint32_t value, uint32_t mask)
 
uint32_t readDSPControl (uint32_t *dspctl, uint32_t mask)
 
 BitUnion32 (DebugReg) Bitfield< 31 > dbd
 
 SubBitUnion (ejtagVer, 17, 15) Bitfield< 17 > ejtagVer2
 
 EndSubBitUnion (ejtagVer) Bitfield< 14
 
 EndBitUnion (DebugReg) BitUnion32(TraceControlReg) Bitfield< 31 > ts
 
 EndBitUnion (TraceControlReg) BitUnion32(TraceControl2Reg) Bitfield< 29 > cpuidv
 
 EndBitUnion (TraceControl2Reg) BitUnion32(TraceBPCReg) Bitfield< 31 > mb
 
 EndBitUnion (TraceBPCReg) BitUnion32(TraceBPC2Reg) Bitfield< 17
 
 EndBitUnion (TraceBPC2Reg) BitUnion32(Debug2Reg) Bitfield< 3 > prm
 
static uint8_t getCauseIP (ThreadContext *tc)
 
static void setCauseIP (ThreadContext *tc, uint8_t val)
 
static SyscallReturn unameFunc (SyscallDesc *desc, ThreadContext *tc, VPtr< Linux::utsname > name)
 Target uname() handler. More...
 
static SyscallReturn sys_getsysinfoFunc (SyscallDesc *desc, ThreadContext *tc, unsigned op, unsigned bufPtr, unsigned nbytes)
 Target sys_getsysyinfo() handler. More...
 
static SyscallReturn sys_setsysinfoFunc (SyscallDesc *desc, ThreadContext *tc, unsigned op, VPtr<> bufPtr, unsigned nbytes)
 Target sys_setsysinfo() handler. More...
 
static SyscallReturn setThreadAreaFunc (SyscallDesc *desc, ThreadContext *tc, VPtr<> addr)
 
template<class XC >
void handleLockedSnoop (XC *xc, PacketPtr pkt, Addr cacheBlockMask)
 
template<class XC >
void handleLockedRead (XC *xc, const RequestPtr &req)
 
template<class XC >
void handleLockedSnoopHit (XC *xc)
 
template<class XC >
bool handleLockedWrite (XC *xc, const RequestPtr &req, Addr cacheBlockMask)
 
template<class XC >
void globalClearExclusive (XC *xc)
 
static RegVal readRegOtherThread (ThreadContext *tc, const RegId &reg, ThreadID tid=InvalidThreadID)
 
static void setRegOtherThread (ThreadContext *tc, const RegId &reg, RegVal val, ThreadID tid=InvalidThreadID)
 
static RegVal readRegOtherThread (ExecContext *xc, const RegId &reg, ThreadID tid=InvalidThreadID)
 
static void setRegOtherThread (ExecContext *xc, const RegId &reg, RegVal val, ThreadID tid=InvalidThreadID)
 
template<class TC >
unsigned getVirtProcNum (TC *tc)
 
template<class TC >
unsigned getTargetThread (TC *tc)
 
template<class TC >
void haltThread (TC *tc)
 
template<class TC >
void restoreThread (TC *tc)
 
template<class TC >
void forkThread (TC *tc, Fault &fault, int Rd_bits, int Rs, int Rt)
 
template<class TC >
int yieldThread (TC *tc, Fault &fault, int src_reg, uint32_t yield_mask)
 
template<class TC >
void updateStatusView (TC *tc)
 
template<class TC >
void updateTCStatusView (TC *tc)
 
 BitUnion32 (MVPControlReg) Bitfield< 3 > cpa
 
 EndBitUnion (MVPControlReg) BitUnion32(MVPConf0Reg) Bitfield< 31 > m
 
 EndBitUnion (MVPConf0Reg) BitUnion32(VPEControlReg) Bitfield< 21 > ysi
 
 EndBitUnion (VPEControlReg) BitUnion32(VPEConf0Reg) Bitfield< 31 > m
 
 EndBitUnion (VPEConf0Reg) BitUnion32(TCBindReg) Bitfield< 28
 
 EndBitUnion (TCBindReg) BitUnion32(TCStatusReg) Bitfield< 31
 
 EndBitUnion (TCStatusReg) BitUnion32(TCHaltReg) Bitfield< 0 > h
 
 BitUnion32 (IndexReg) Bitfield< 31 > p
 
 EndBitUnion (IndexReg) BitUnion32(RandomReg) Bitfield< 30
 
 EndBitUnion (RandomReg) BitUnion64(EntryLoReg) Bitfield< 63
 
 EndBitUnion (EntryLoReg) BitUnion64(ContextReg) Bitfield< 63
 
 EndBitUnion (ContextReg) BitUnion32(PageMaskReg) Bitfield< 28
 
 EndBitUnion (PageMaskReg) BitUnion32(PageGrainReg) Bitfield< 31
 
 EndBitUnion (PageGrainReg) BitUnion32(WiredReg) Bitfield< 30
 
 EndBitUnion (WiredReg) BitUnion32(HWREnaReg) Bitfield< 31
 
 EndBitUnion (HWREnaReg) BitUnion64(EntryHiReg) Bitfield< 63
 
 EndBitUnion (EntryHiReg) BitUnion32(StatusReg) SubBitUnion(cu
 
 EndSubBitUnion (cu) Bitfield< 27 > rp
 
 SubBitUnion (im, 15, 8) Bitfield< 15 > im7
 
 EndSubBitUnion (im) Bitfield< 7 > kx
 
 EndBitUnion (StatusReg) BitUnion32(IntCtlReg) Bitfield< 31
 
 EndBitUnion (IntCtlReg) BitUnion32(SRSCtlReg) Bitfield< 29
 
 EndBitUnion (SRSCtlReg) BitUnion32(SRSMapReg) Bitfield< 31
 
 EndBitUnion (SRSMapReg) BitUnion32(CauseReg) Bitfield< 31 > bd
 
 SubBitUnion (ip, 15, 8) Bitfield< 15 > ip7
 
 EndSubBitUnion (ip)
 
 EndBitUnion (CauseReg) BitUnion32(PRIdReg) Bitfield< 31
 
 EndBitUnion (PRIdReg) BitUnion32(EBaseReg) Bitfield< 29
 
 EndBitUnion (EBaseReg) BitUnion32(ConfigReg) Bitfield< 31 > m
 
 EndBitUnion (ConfigReg) BitUnion32(Config1Reg) Bitfield< 31 > m
 
 EndBitUnion (Config1Reg) BitUnion32(Config2Reg) Bitfield< 31 > m
 
 EndBitUnion (Config2Reg) BitUnion32(Config3Reg) Bitfield< 31 > m
 
 EndBitUnion (Config3Reg) BitUnion64(WatchLoReg) Bitfield< 63
 
 EndBitUnion (WatchLoReg) BitUnion32(WatchHiReg) Bitfield< 31 > m
 
 EndBitUnion (WatchHiReg) BitUnion32(PerfCntCtlReg) Bitfield< 31 > m
 
 EndBitUnion (PerfCntCtlReg) BitUnion32(CacheErrReg) Bitfield< 31 > er
 
 EndBitUnion (CacheErrReg) BitUnion32(TagLoReg) Bitfield< 31
 
uint64_t fpConvert (ConvertType cvt_type, double fp_val)
 
double roundFP (double val, int digits)
 
double truncFP (double val)
 
bool getCondCode (uint32_t fcsr, int cc_idx)
 
uint32_t genCCVector (uint32_t fcsr, int cc_num, uint32_t cc_val)
 
uint32_t genInvalidVector (uint32_t fcsr_bits)
 
bool isNan (void *val_ptr, int size)
 
bool isQnan (void *val_ptr, int size)
 
bool isSnan (void *val_ptr, int size)
 
Addr TruncPage (Addr addr)
 
Addr RoundPage (Addr addr)
 

Variables

const uint32_t DSP_CTL_POS [DSP_NUM_FIELDS] = { 0, 7, 13, 16, 24, 14 }
 
const uint32_t DSP_CTL_MASK [DSP_NUM_FIELDS]
 
const uint32_t SIMD_MAX_VALS = 4
 
const uint32_t SIMD_NVALS [SIMD_NUM_FMTS] = { 1, 1, 2, 4 }
 
const uint32_t SIMD_NBITS [SIMD_NUM_FMTS] = { 64, 32, 16, 8 }
 
const uint32_t SIMD_LOG2N [SIMD_NUM_FMTS] = { 6, 5, 4, 3 }
 
const uint64_t FIXED_L_SMAX = 0x7fffffffffffffffULL
 
const uint64_t FIXED_W_SMAX = 0x000000007fffffffULL
 
const uint64_t FIXED_H_SMAX = 0x0000000000007fffULL
 
const uint64_t FIXED_B_SMAX = 0x000000000000007fULL
 
const uint64_t FIXED_L_UMAX = 0xffffffffffffffffULL
 
const uint64_t FIXED_W_UMAX = 0x00000000ffffffffULL
 
const uint64_t FIXED_H_UMAX = 0x000000000000ffffULL
 
const uint64_t FIXED_B_UMAX = 0x00000000000000ffULL
 
const uint64_t FIXED_SMAX [SIMD_NUM_FMTS]
 
const uint64_t FIXED_UMAX [SIMD_NUM_FMTS]
 
const uint64_t FIXED_L_SMIN = 0x8000000000000000ULL
 
const uint64_t FIXED_W_SMIN = 0xffffffff80000000ULL
 
const uint64_t FIXED_H_SMIN = 0xffffffffffff8000ULL
 
const uint64_t FIXED_B_SMIN = 0xffffffffffffff80ULL
 
const uint64_t FIXED_L_UMIN = 0x0000000000000000ULL
 
const uint64_t FIXED_W_UMIN = 0x0000000000000000ULL
 
const uint64_t FIXED_H_UMIN = 0x0000000000000000ULL
 
const uint64_t FIXED_B_UMIN = 0x0000000000000000ULL
 
const uint64_t FIXED_SMIN [SIMD_NUM_FMTS]
 
const uint64_t FIXED_UMIN [SIMD_NUM_FMTS]
 
Bitfield< 30 > dm
 
Bitfield< 29 > nodcr
 
Bitfield< 28 > lsnm
 
Bitfield< 27 > doze
 
Bitfield< 26 > halt
 
Bitfield< 25 > conutdm
 
Bitfield< 24 > ibusep
 
Bitfield< 23 > mcheckep
 
Bitfield< 22 > cacheep
 
Bitfield< 21 > dbusep
 
Bitfield< 20, 19 > iexi
 
Bitfield< 19 > ddbsImpr
 
Bitfield< 18 > ddblImpr
 
Bitfield< 16 > ejtagVer1
 
Bitfield< 15 > ejtagVer0
 
 dexcCode
 
Bitfield< 9 > nosst
 
Bitfield< 8 > sst
 
Bitfield< 7 > offline
 
Bitfield< 6 > dibimpr
 
Bitfield< 5 > dint
 
Bitfield< 4 > dib
 
Bitfield< 3 > ddbs
 
Bitfield< 2 > ddbl
 
Bitfield< 1 > dbp
 
Bitfield< 0 > dss
 
Bitfield< 30 > ut
 
Bitfield< 27 > tb
 
Bitfield< 26 > io
 
Bitfield< 25 > d
 
Bitfield< 24 > e
 
Bitfield< 23 > k
 
Bitfield< 22 > s
 
Bitfield< 21 > u
 
Bitfield< 20, 13 > asidM
 
Bitfield< 12, 5 > asid
 
Bitfield< 4 > g
 
Bitfield< 3 > tfcr
 
Bitfield< 2 > tlsm
 
Bitfield< 1 > tim
 
Bitfield< 0 > on
 
Bitfield< 28, 21 > cpuid
 
Bitfield< 20 > tcv
 
Bitfield< 19, 12 > tcnum
 
Bitfield< 11, 7 > mode
 
Bitfield< 6, 5 > validModes
 
Bitfield< 4 > tbi
 
Bitfield< 3 > tbu
 
Bitfield< 2, 0 > syp
 
Bitfield< 27 > ate
 
Bitfield< 26, 24 > bpc8
 
Bitfield< 23, 21 > bpc7
 
Bitfield< 20, 18 > bpc6
 
Bitfield< 17, 15 > bpc5
 
Bitfield< 14, 12 > bpc4
 
Bitfield< 11, 9 > bpc3
 
Bitfield< 8, 6 > bpc2
 
Bitfield< 5, 3 > bpc1
 
Bitfield< 2, 0 > bpc0
 
 bpc14
 
Bitfield< 14, 12 > bpc13
 
Bitfield< 11, 9 > bpc12
 
Bitfield< 8, 6 > bpc11
 
Bitfield< 5, 3 > bpc10
 
Bitfield< 2, 0 > bpc9
 
Bitfield< 2 > dq
 
Bitfield< 1 > tup
 
Bitfield< 0 > paco
 
Bitfield< 2 > stlb
 
Bitfield< 1 > vpc
 
Bitfield< 0 > evp
 
Bitfield< 29 > tlbs
 
Bitfield< 28 > gs
 
Bitfield< 27 > pcp
 
Bitfield< 25, 16 > ptlbe
 
Bitfield< 15 > tca
 
Bitfield< 13, 10 > pvpe
 
Bitfield< 7, 0 > ptc
 
Bitfield< 18, 16 > excpt
 
Bitfield< 15 > te
 
Bitfield< 7, 0 > targTC
 
Bitfield< 28, 21 > xtc
 
Bitfield< 19 > tcs
 
Bitfield< 18 > scs
 
Bitfield< 17 > dcs
 
Bitfield< 16 > ics
 
Bitfield< 1 > mvp
 
Bitfield< 0 > vpa
 
 curTC
 
Bitfield< 20, 18 > a0
 
Bitfield< 17 > tbe
 
Bitfield< 3, 0 > curVPE
 
 tcu
 
Bitfield< 27 > tmx
 
Bitfield< 24, 23 > rnst
 
Bitfield< 21 > tds
 
Bitfield< 20 > dt
 
Bitfield< 19, 16 > impl
 
Bitfield< 15 > da
 
Bitfield< 13 > a
 
Bitfield< 12, 11 > tksu
 
Bitfield< 10 > ixmt
 
const Addr PageShift = 13
 
const Addr PageBytes = 1ULL << PageShift
 
Bitfield< 30, 0 > index
 
 random
 
 fill
 
Bitfield< 29, 6 > pfn
 
Bitfield< 5, 3 > c
 
Bitfield< 1 > v
 
 pteBase
 
Bitfield< 22, 4 > badVPN2
 
 mask
 
Bitfield< 12, 11 > maskx
 
 aseUp
 
Bitfield< 29 > elpa
 
Bitfield< 28 > esp
 
Bitfield< 12, 8 > aseDn
 
 wired
 
 r
 
Bitfield< 39, 13 > vpn2
 
Bitfield< 12, 11 > vpn2x
 
Bitfield< 31 > cu3
 
Bitfield< 30 > cu2
 
Bitfield< 29 > cu1
 
Bitfield< 28 > cu0
 
Bitfield< 26 > fr
 
Bitfield< 25 > re
 
Bitfield< 24 > mx
 
Bitfield< 23 > px
 
Bitfield< 22 > bev
 
Bitfield< 21 > ts
 
Bitfield< 20 > sr
 
Bitfield< 19 > nmi
 
Bitfield< 15, 10 > ipl
 
Bitfield< 14 > im6
 
Bitfield< 13 > im5
 
Bitfield< 12 > im4
 
Bitfield< 11 > im3
 
Bitfield< 10 > im2
 
Bitfield< 9 > im1
 
Bitfield< 8 > im0
 
Bitfield< 6 > sx
 
Bitfield< 5 > ux
 
Bitfield< 4, 3 > ksu
 
Bitfield< 4 > um
 
Bitfield< 3 > r0
 
Bitfield< 2 > erl
 
Bitfield< 1 > exl
 
Bitfield< 0 > ie
 
 ipti
 
Bitfield< 28, 26 > ippci
 
Bitfield< 9, 5 > vs
 
 hss
 
Bitfield< 21, 18 > eicss
 
Bitfield< 15, 12 > ess
 
Bitfield< 9, 6 > pss
 
Bitfield< 3, 0 > css
 
 ssv7
 
Bitfield< 27, 24 > ssv6
 
Bitfield< 23, 20 > ssv5
 
Bitfield< 19, 16 > ssv4
 
Bitfield< 15, 12 > ssv3
 
Bitfield< 11, 8 > ssv2
 
Bitfield< 7, 4 > ssv1
 
Bitfield< 3, 0 > ssv0
 
Bitfield< 30 > ti
 
Bitfield< 29, 28 > ce
 
Bitfield< 27 > dc
 
Bitfield< 26 > pci
 
Bitfield< 23 > iv
 
Bitfield< 22 > wp
 
Bitfield< 15, 10 > ripl
 
Bitfield< 14 > ip6
 
Bitfield< 13 > ip5
 
Bitfield< 12 > ip4
 
Bitfield< 11 > ip3
 
Bitfield< 10 > ip2
 
Bitfield< 9 > ip1
 
Bitfield< 8 > ip0
 
Bitfield< 6, 2 > excCode
 
 coOp
 
Bitfield< 23, 16 > coId
 
Bitfield< 15, 8 > procId
 
Bitfield< 7, 0 > rev
 
 exceptionBase
 
Bitfield< 9, 9 > cpuNum
 
Bitfield< 30, 28 > k23
 
Bitfield< 27, 25 > ku
 
Bitfield< 15 > be
 
Bitfield< 14, 13 > at
 
Bitfield< 12, 10 > ar
 
Bitfield< 9, 7 > mt
 
Bitfield< 3 > vi
 
Bitfield< 2, 0 > k0
 
Bitfield< 30, 25 > mmuSize
 
Bitfield< 24, 22 > is
 
Bitfield< 21, 19 > il
 
Bitfield< 18, 16 > ia
 
Bitfield< 15, 13 > ds
 
Bitfield< 12, 10 > dl
 
Bitfield< 6 > c2
 
Bitfield< 5 > md
 
Bitfield< 4 > pc
 
Bitfield< 3 > wr
 
Bitfield< 2 > ca
 
Bitfield< 1 > ep
 
Bitfield< 0 > fp
 
Bitfield< 30, 28 > tu
 
Bitfield< 23, 20 > tl
 
Bitfield< 19, 16 > ta
 
Bitfield< 15, 12 > su
 
Bitfield< 11, 8 > ss
 
Bitfield< 7, 4 > sl
 
Bitfield< 3, 0 > sa
 
Bitfield< 10 > dspp
 
Bitfield< 7 > lpa
 
Bitfield< 6 > veic
 
Bitfield< 5 > vint
 
Bitfield< 4 > sp
 
Bitfield< 1 > sm
 
 vaddr
 
Bitfield< 2 > i
 
Bitfield< 0 > w
 
Bitfield< 10, 5 > event
 
Bitfield< 30 > ec
 
Bitfield< 29 > ed
 
Bitfield< 28 > et
 
Bitfield< 27 > es
 
Bitfield< 26 > ee
 
Bitfield< 25 > eb
 
 pTagLo
 
Bitfield< 7, 6 > pState
 
Bitfield< 5 > l
 
Bitfield< 0 > p
 
const int NumFloatArchRegs = 32
 
const int NumFloatSpecialRegs = 5
 
const int NumFloatRegs = NumFloatArchRegs + NumFloatSpecialRegs
 
const uint32_t MIPS32_QNAN = 0x7fbfffff
 
const uint64_t MIPS64_QNAN = 0x7ff7ffffffffffffULL
 
const int NumIntArchRegs = 32
 
const int NumIntSpecialRegs = 9
 
const int MaxShadowRegSets = 16
 
const int NumIntRegs = NumIntArchRegs + NumIntSpecialRegs
 
const int SyscallSuccessReg = 7
 
const int FirstArgumentReg = 4
 
const int ReturnValueReg = 2
 
const int StackPointerReg = 29
 
const int SyscallPseudoReturnReg = 3
 
constexpr unsigned NumVecElemPerVecReg = ::gem5::DummyNumVecElemPerVecReg
 

Typedef Documentation

◆ ExtMachInst

typedef uint64_t gem5::MipsISA::ExtMachInst

Definition at line 43 of file types.hh.

◆ FaultVals

Definition at line 46 of file faults.cc.

◆ FaultVect

Definition at line 47 of file faults.hh.

◆ MachInst

typedef uint32_t gem5::MipsISA::MachInst

Definition at line 42 of file types.hh.

◆ PCState

Definition at line 40 of file pcstate.hh.

◆ VecElem

Definition at line 43 of file vecregs.hh.

◆ VecPredRegContainer

Definition at line 48 of file vecregs.hh.

◆ VecRegContainer

Definition at line 44 of file vecregs.hh.

Enumeration Type Documentation

◆ anonymous enum

anonymous enum
Enumerator
UNSIGNED 
SIGNED 

Definition at line 84 of file dsp.hh.

◆ anonymous enum

anonymous enum
Enumerator
NOSATURATE 
SATURATE 

Definition at line 85 of file dsp.hh.

◆ anonymous enum

anonymous enum
Enumerator
NOROUND 
ROUND 

Definition at line 86 of file dsp.hh.

◆ anonymous enum

anonymous enum
Enumerator
SIMD_FMT_L 
SIMD_FMT_W 
SIMD_FMT_PH 
SIMD_FMT_QB 
SIMD_NUM_FMTS 

Definition at line 44 of file dsp.hh.

◆ anonymous enum

anonymous enum
Enumerator
DSP_POS 
DSP_SCOUNT 
DSP_C 
DSP_OUFLAG 
DSP_CCOND 
DSP_EFI 
DSP_NUM_FIELDS 

Definition at line 54 of file dsp.hh.

◆ anonymous enum

anonymous enum
Enumerator
CMP_EQ 
CMP_LT 
CMP_LE 

Definition at line 66 of file dsp.hh.

◆ anonymous enum

anonymous enum
Enumerator
MODE_L 
MODE_R 
MODE_LA 
MODE_RA 
MODE_X 

Definition at line 74 of file dsp.hh.

◆ ConvertType

Enumerator
SINGLE_TO_DOUBLE 
SINGLE_TO_WORD 
SINGLE_TO_LONG 
DOUBLE_TO_SINGLE 
DOUBLE_TO_WORD 
DOUBLE_TO_LONG 
LONG_TO_SINGLE 
LONG_TO_DOUBLE 
LONG_TO_WORD 
LONG_TO_PS 
WORD_TO_SINGLE 
WORD_TO_DOUBLE 
WORD_TO_LONG 
WORD_TO_PS 
PL_TO_SINGLE 
PU_TO_SINGLE 

Definition at line 46 of file types.hh.

◆ ExcCode

Enumerator
ExcCodeDummy 
ExcCodeInt 
ExcCodeMod 
ExcCodeTlbL 
ExcCodeTlbS 
ExcCodeAdEL 
ExcCodeAdES 
ExcCodeIBE 
ExcCodeDBE 
ExcCodeSys 
ExcCodeBp 
ExcCodeRI 
ExcCodeCpU 
ExcCodeOv 
ExcCodeTr 
ExcCodeC2E 
ExcCodeMDMX 
ExcCodeWatch 
ExcCodeMCheck 
ExcCodeThread 
ExcCodeCacheErr 

Definition at line 49 of file faults.hh.

◆ FCSRBits

Enumerator
Inexact 
Underflow 
Overflow 
DivideByZero 
Invalid 
Unimplemented 

Definition at line 59 of file float.hh.

◆ FCSRFields

Enumerator
Flag_Field 
Enable_Field 
Cause_Field 

Definition at line 69 of file float.hh.

◆ FPControlRegNums

Enumerator
FLOATREG_FIR 
FLOATREG_FCCR 
FLOATREG_FEXR 
FLOATREG_FENR 
FLOATREG_FCSR 

Definition at line 50 of file float.hh.

◆ InterruptLevels

Enumerator
INTLEVEL_SOFTWARE_MIN 
INTLEVEL_SOFTWARE_MAX 
INTLEVEL_EXTERNAL_MIN 
INTLEVEL_EXTERNAL_MAX 
INTLEVEL_IRQ0 
INTLEVEL_IRQ1 
INTINDEX_ETHERNET 
INTINDEX_SCSI 
INTLEVEL_IRQ2 
INTLEVEL_IRQ3 
INTLEVEL_SERIAL 
NumInterruptLevels 

Definition at line 43 of file interrupts.cc.

◆ MiscIntRegNums

Enumerator
INTREG_LO 
INTREG_DSP_LO0 
INTREG_HI 
INTREG_DSP_HI0 
INTREG_DSP_ACX0 
INTREG_DSP_LO1 
INTREG_DSP_HI1 
INTREG_DSP_ACX1 
INTREG_DSP_LO2 
INTREG_DSP_HI2 
INTREG_DSP_ACX2 
INTREG_DSP_LO3 
INTREG_DSP_HI3 
INTREG_DSP_ACX3 
INTREG_DSP_CONTROL 

Definition at line 46 of file int.hh.

◆ MiscRegIndex

Enumerator
MISCREG_INDEX 
MISCREG_MVP_CONTROL 
MISCREG_MVP_CONF0 
MISCREG_MVP_CONF1 
MISCREG_CP0_RANDOM 
MISCREG_VPE_CONTROL 
MISCREG_VPE_CONF0 
MISCREG_VPE_CONF1 
MISCREG_YQMASK 
MISCREG_VPE_SCHEDULE 
MISCREG_VPE_SCHEFBACK 
MISCREG_VPE_OPT 
MISCREG_ENTRYLO0 
MISCREG_TC_STATUS 
MISCREG_TC_BIND 
MISCREG_TC_RESTART 
MISCREG_TC_HALT 
MISCREG_TC_CONTEXT 
MISCREG_TC_SCHEDULE 
MISCREG_TC_SCHEFBACK 
MISCREG_ENTRYLO1 
MISCREG_CONTEXT 
MISCREG_CONTEXT_CONFIG 
MISCREG_PAGEMASK 
MISCREG_PAGEGRAIN 
MISCREG_WIRED 
MISCREG_SRS_CONF0 
MISCREG_SRS_CONF1 
MISCREG_SRS_CONF2 
MISCREG_SRS_CONF3 
MISCREG_SRS_CONF4 
MISCREG_HWRENA 
MISCREG_BADVADDR 
MISCREG_COUNT 
MISCREG_ENTRYHI 
MISCREG_COMPARE 
MISCREG_STATUS 
MISCREG_INTCTL 
MISCREG_SRSCTL 
MISCREG_SRSMAP 
MISCREG_CAUSE 
MISCREG_EPC 
MISCREG_PRID 
MISCREG_EBASE 
MISCREG_CONFIG 
MISCREG_CONFIG1 
MISCREG_CONFIG2 
MISCREG_CONFIG3 
MISCREG_CONFIG4 
MISCREG_CONFIG5 
MISCREG_CONFIG6 
MISCREG_CONFIG7 
MISCREG_LLADDR 
MISCREG_WATCHLO0 
MISCREG_WATCHLO1 
MISCREG_WATCHLO2 
MISCREG_WATCHLO3 
MISCREG_WATCHLO4 
MISCREG_WATCHLO5 
MISCREG_WATCHLO6 
MISCREG_WATCHLO7 
MISCREG_WATCHHI0 
MISCREG_WATCHHI1 
MISCREG_WATCHHI2 
MISCREG_WATCHHI3 
MISCREG_WATCHHI4 
MISCREG_WATCHHI5 
MISCREG_WATCHHI6 
MISCREG_WATCHHI7 
MISCREG_XCCONTEXT64 
MISCREG_DEBUG 
MISCREG_TRACE_CONTROL1 
MISCREG_TRACE_CONTROL2 
MISCREG_USER_TRACE_DATA 
MISCREG_TRACE_BPC 
MISCREG_DEPC 
MISCREG_PERFCNT0 
MISCREG_PERFCNT1 
MISCREG_PERFCNT2 
MISCREG_PERFCNT3 
MISCREG_PERFCNT4 
MISCREG_PERFCNT5 
MISCREG_PERFCNT6 
MISCREG_PERFCNT7 
MISCREG_ERRCTL 
MISCREG_CACHEERR0 
MISCREG_CACHEERR1 
MISCREG_CACHEERR2 
MISCREG_CACHEERR3 
MISCREG_TAGLO0 
MISCREG_DATALO1 
MISCREG_TAGLO2 
MISCREG_DATALO3 
MISCREG_TAGLO4 
MISCREG_DATALO5 
MISCREG_TAGLO6 
MISCREG_DATALO7 
MISCREG_TAGHI0 
MISCREG_DATAHI1 
MISCREG_TAGHI2 
MISCREG_DATAHI3 
MISCREG_TAGHI4 
MISCREG_DATAHI5 
MISCREG_TAGHI6 
MISCREG_DATAHI7 
MISCREG_ERROR_EPC 
MISCREG_DESAVE 
MISCREG_LLFLAG 
MISCREG_TP_VALUE 
MISCREG_NUMREGS 

Definition at line 46 of file misc.hh.

◆ RoundMode

Enumerator
RND_ZERO 
RND_DOWN 
RND_UP 
RND_NEAREST 

Definition at line 71 of file types.hh.

Function Documentation

◆ addHalfLsb()

uint64_t gem5::MipsISA::addHalfLsb ( uint64_t  value,
int32_t  lsbpos 
)

Definition at line 128 of file dsp.cc.

Referenced by dspAddh(), dspExtr(), dspMulq(), dspPrecrq(), dspPrecrSra(), dspShra(), and dspSubh().

◆ bitrev()

int32_t gem5::MipsISA::bitrev ( int32_t  value)

Definition at line 42 of file dsp.cc.

References i, and gem5::ArmISA::shift.

◆ BitUnion32() [1/3]

gem5::MipsISA::BitUnion32 ( DebugReg  )

◆ BitUnion32() [2/3]

gem5::MipsISA::BitUnion32 ( IndexReg  )

◆ BitUnion32() [3/3]

gem5::MipsISA::BitUnion32 ( MVPControlReg  )

◆ checkOverflow()

uint64_t gem5::MipsISA::checkOverflow ( uint64_t  value,
int32_t  fmt,
int32_t  sign,
uint32_t *  overflow 
)

Definition at line 90 of file dsp.cc.

References FIXED_SMAX, FIXED_SMIN, FIXED_UMAX, FIXED_UMIN, sc_dt::overflow(), SIGNED, and UNSIGNED.

Referenced by dspAdd(), dspExtr(), dspMul(), dspShll(), and dspSub().

◆ dspAbs()

int32_t gem5::MipsISA::dspAbs ( int32_t  a,
int32_t  fmt,
uint32_t *  dspctl 
)

◆ dspAdd()

int32_t gem5::MipsISA::dspAdd ( int32_t  a,
int32_t  b,
int32_t  fmt,
int32_t  saturate,
int32_t  sign,
uint32_t *  dspctl 
)

◆ dspAddh()

int32_t gem5::MipsISA::dspAddh ( int32_t  a,
int32_t  b,
int32_t  fmt,
int32_t  round,
int32_t  sign 
)

Definition at line 197 of file dsp.cc.

References a, addHalfLsb(), gem5::ArmISA::b, i, SIMD_MAX_VALS, SIMD_NVALS, simdPack(), and simdUnpack().

◆ dspCmp()

void gem5::MipsISA::dspCmp ( int32_t  a,
int32_t  b,
int32_t  fmt,
int32_t  sign,
int32_t  op,
uint32_t *  dspctl 
)

◆ dspCmpg()

int32_t gem5::MipsISA::dspCmpg ( int32_t  a,
int32_t  b,
int32_t  fmt,
int32_t  sign,
int32_t  op 
)

Definition at line 803 of file dsp.cc.

References a, gem5::ArmISA::b, CMP_EQ, CMP_LE, CMP_LT, i, gem5::X86ISA::op, SIMD_MAX_VALS, SIMD_NVALS, and simdUnpack().

◆ dspCmpgd()

int32_t gem5::MipsISA::dspCmpgd ( int32_t  a,
int32_t  b,
int32_t  fmt,
int32_t  sign,
int32_t  op,
uint32_t *  dspctl 
)

◆ dspDpa()

int64_t gem5::MipsISA::dspDpa ( int64_t  dspac,
int32_t  a,
int32_t  b,
int32_t  ac,
int32_t  fmt,
int32_t  sign,
int32_t  mode 
)

Definition at line 627 of file dsp.cc.

References a, gem5::ArmISA::b, i, mode, MODE_L, MODE_R, MODE_X, SIMD_MAX_VALS, SIMD_NVALS, and simdUnpack().

◆ dspDpaq()

int64_t gem5::MipsISA::dspDpaq ( int64_t  dspac,
int32_t  a,
int32_t  b,
int32_t  ac,
int32_t  infmt,
int32_t  outfmt,
int32_t  postsat,
int32_t  mode,
uint32_t *  dspctl 
)

◆ dspDps()

int64_t gem5::MipsISA::dspDps ( int64_t  dspac,
int32_t  a,
int32_t  b,
int32_t  ac,
int32_t  fmt,
int32_t  sign,
int32_t  mode 
)

Definition at line 655 of file dsp.cc.

References a, gem5::ArmISA::b, i, mode, MODE_L, MODE_R, MODE_X, SIMD_MAX_VALS, SIMD_NVALS, and simdUnpack().

◆ dspDpsq()

int64_t gem5::MipsISA::dspDpsq ( int64_t  dspac,
int32_t  a,
int32_t  b,
int32_t  ac,
int32_t  infmt,
int32_t  outfmt,
int32_t  postsat,
int32_t  mode,
uint32_t *  dspctl 
)

◆ dspExtp()

int32_t gem5::MipsISA::dspExtp ( int64_t  dspac,
int32_t  size,
uint32_t *  dspctl 
)

Definition at line 1083 of file dsp.cc.

References gem5::bits(), and gem5::insertBits().

◆ dspExtpd()

int32_t gem5::MipsISA::dspExtpd ( int64_t  dspac,
int32_t  size,
uint32_t *  dspctl 
)

Definition at line 1103 of file dsp.cc.

References gem5::bits(), and gem5::insertBits().

◆ dspExtr()

int32_t gem5::MipsISA::dspExtr ( int64_t  dspac,
int32_t  fmt,
int32_t  sa,
int32_t  round,
int32_t  saturate,
uint32_t *  dspctl 
)

◆ dspMaq()

int64_t gem5::MipsISA::dspMaq ( int64_t  dspac,
int32_t  a,
int32_t  b,
int32_t  ac,
int32_t  fmt,
int32_t  mode,
int32_t  saturate,
uint32_t *  dspctl 
)

◆ dspMul()

int32_t gem5::MipsISA::dspMul ( int32_t  a,
int32_t  b,
int32_t  fmt,
int32_t  saturate,
uint32_t *  dspctl 
)

◆ dspMuleq()

int32_t gem5::MipsISA::dspMuleq ( int32_t  a,
int32_t  b,
int32_t  mode,
uint32_t *  dspctl 
)

◆ dspMuleu()

int32_t gem5::MipsISA::dspMuleu ( int32_t  a,
int32_t  b,
int32_t  mode,
uint32_t *  dspctl 
)

◆ dspMulq()

int32_t gem5::MipsISA::dspMulq ( int32_t  a,
int32_t  b,
int32_t  fmt,
int32_t  saturate,
int32_t  round,
uint32_t *  dspctl 
)

◆ dspMulsa()

int64_t gem5::MipsISA::dspMulsa ( int64_t  dspac,
int32_t  a,
int32_t  b,
int32_t  ac,
int32_t  fmt 
)

Definition at line 727 of file dsp.cc.

References a, gem5::ArmISA::b, SIGNED, SIMD_MAX_VALS, and simdUnpack().

◆ dspMulsaq()

int64_t gem5::MipsISA::dspMulsaq ( int64_t  dspac,
int32_t  a,
int32_t  b,
int32_t  ac,
int32_t  fmt,
uint32_t *  dspctl 
)

◆ dspPack()

int32_t gem5::MipsISA::dspPack ( int32_t  a,
int32_t  b,
int32_t  fmt 
)

Definition at line 1021 of file dsp.cc.

References a, gem5::ArmISA::b, SIMD_MAX_VALS, simdPack(), simdUnpack(), and UNSIGNED.

◆ dspPick()

int32_t gem5::MipsISA::dspPick ( int32_t  a,
int32_t  b,
int32_t  fmt,
uint32_t *  dspctl 
)

◆ dspPrece()

int32_t gem5::MipsISA::dspPrece ( int32_t  a,
int32_t  infmt,
int32_t  insign,
int32_t  outfmt,
int32_t  outsign,
int32_t  mode 
)

Definition at line 872 of file dsp.cc.

References a, i, mode, MODE_L, MODE_LA, MODE_R, MODE_RA, sa, SIGNED, SIMD_MAX_VALS, SIMD_NBITS, SIMD_NVALS, simdPack(), simdUnpack(), and UNSIGNED.

◆ dspPrecrq()

int32_t gem5::MipsISA::dspPrecrq ( int32_t  a,
int32_t  b,
int32_t  fmt,
uint32_t *  dspctl 
)

◆ dspPrecrqu()

int32_t gem5::MipsISA::dspPrecrqu ( int32_t  a,
int32_t  b,
uint32_t *  dspctl 
)

◆ dspPrecrSra()

int32_t gem5::MipsISA::dspPrecrSra ( int32_t  a,
int32_t  b,
int32_t  sa,
int32_t  fmt,
int32_t  round 
)

Definition at line 968 of file dsp.cc.

References a, addHalfLsb(), gem5::ArmISA::b, i, sa, SIGNED, SIMD_MAX_VALS, SIMD_NVALS, simdPack(), and simdUnpack().

◆ dspSaturate()

uint64_t gem5::MipsISA::dspSaturate ( uint64_t  value,
int32_t  fmt,
int32_t  sign,
uint32_t *  overflow 
)

◆ dspShll()

int32_t gem5::MipsISA::dspShll ( int32_t  a,
uint32_t  sa,
int32_t  fmt,
int32_t  saturate,
int32_t  sign,
uint32_t *  dspctl 
)

◆ dspShra()

int32_t gem5::MipsISA::dspShra ( int32_t  a,
uint32_t  sa,
int32_t  fmt,
int32_t  round,
int32_t  sign,
uint32_t *  dspctl 
)

Definition at line 325 of file dsp.cc.

References a, addHalfLsb(), gem5::bits(), i, sa, SIGNED, SIMD_LOG2N, SIMD_MAX_VALS, SIMD_NVALS, simdPack(), and simdUnpack().

◆ dspShrl()

int32_t gem5::MipsISA::dspShrl ( int32_t  a,
uint32_t  sa,
int32_t  fmt,
int32_t  sign 
)

Definition at line 306 of file dsp.cc.

References a, gem5::bits(), i, sa, SIMD_LOG2N, SIMD_MAX_VALS, SIMD_NVALS, simdPack(), simdUnpack(), and UNSIGNED.

◆ dspSub()

int32_t gem5::MipsISA::dspSub ( int32_t  a,
int32_t  b,
int32_t  fmt,
int32_t  saturate,
int32_t  sign,
uint32_t *  dspctl 
)

◆ dspSubh()

int32_t gem5::MipsISA::dspSubh ( int32_t  a,
int32_t  b,
int32_t  fmt,
int32_t  round,
int32_t  sign 
)

Definition at line 252 of file dsp.cc.

References a, addHalfLsb(), gem5::ArmISA::b, i, SIMD_MAX_VALS, SIMD_NVALS, simdPack(), and simdUnpack().

◆ EndBitUnion() [1/35]

gem5::MipsISA::EndBitUnion ( CacheErrReg  )

◆ EndBitUnion() [2/35]

gem5::MipsISA::EndBitUnion ( CauseReg  )

◆ EndBitUnion() [3/35]

gem5::MipsISA::EndBitUnion ( Config1Reg  )

◆ EndBitUnion() [4/35]

gem5::MipsISA::EndBitUnion ( Config2Reg  )

◆ EndBitUnion() [5/35]

gem5::MipsISA::EndBitUnion ( Config3Reg  )

◆ EndBitUnion() [6/35]

gem5::MipsISA::EndBitUnion ( ConfigReg  )

◆ EndBitUnion() [7/35]

gem5::MipsISA::EndBitUnion ( ContextReg  )

◆ EndBitUnion() [8/35]

gem5::MipsISA::EndBitUnion ( DebugReg  )

◆ EndBitUnion() [9/35]

gem5::MipsISA::EndBitUnion ( EBaseReg  )

◆ EndBitUnion() [10/35]

gem5::MipsISA::EndBitUnion ( EntryHiReg  )

◆ EndBitUnion() [11/35]

gem5::MipsISA::EndBitUnion ( EntryLoReg  )

◆ EndBitUnion() [12/35]

gem5::MipsISA::EndBitUnion ( HWREnaReg  )

◆ EndBitUnion() [13/35]

gem5::MipsISA::EndBitUnion ( IndexReg  )

◆ EndBitUnion() [14/35]

gem5::MipsISA::EndBitUnion ( IntCtlReg  )

◆ EndBitUnion() [15/35]

gem5::MipsISA::EndBitUnion ( MVPConf0Reg  )

◆ EndBitUnion() [16/35]

gem5::MipsISA::EndBitUnion ( MVPControlReg  )

◆ EndBitUnion() [17/35]

gem5::MipsISA::EndBitUnion ( PageGrainReg  )

◆ EndBitUnion() [18/35]

gem5::MipsISA::EndBitUnion ( PageMaskReg  )

◆ EndBitUnion() [19/35]

gem5::MipsISA::EndBitUnion ( PerfCntCtlReg  )

◆ EndBitUnion() [20/35]

gem5::MipsISA::EndBitUnion ( PRIdReg  )

◆ EndBitUnion() [21/35]

gem5::MipsISA::EndBitUnion ( RandomReg  )

◆ EndBitUnion() [22/35]

gem5::MipsISA::EndBitUnion ( SRSCtlReg  )

◆ EndBitUnion() [23/35]

gem5::MipsISA::EndBitUnion ( SRSMapReg  )

◆ EndBitUnion() [24/35]

gem5::MipsISA::EndBitUnion ( StatusReg  )

◆ EndBitUnion() [25/35]

gem5::MipsISA::EndBitUnion ( TCBindReg  )

◆ EndBitUnion() [26/35]

gem5::MipsISA::EndBitUnion ( TCStatusReg  )

◆ EndBitUnion() [27/35]

gem5::MipsISA::EndBitUnion ( TraceBPC2Reg  )

◆ EndBitUnion() [28/35]

gem5::MipsISA::EndBitUnion ( TraceBPCReg  )

◆ EndBitUnion() [29/35]

gem5::MipsISA::EndBitUnion ( TraceControl2Reg  )

◆ EndBitUnion() [30/35]

gem5::MipsISA::EndBitUnion ( TraceControlReg  )

◆ EndBitUnion() [31/35]

gem5::MipsISA::EndBitUnion ( VPEConf0Reg  )

◆ EndBitUnion() [32/35]

gem5::MipsISA::EndBitUnion ( VPEControlReg  )

◆ EndBitUnion() [33/35]

gem5::MipsISA::EndBitUnion ( WatchHiReg  )

◆ EndBitUnion() [34/35]

gem5::MipsISA::EndBitUnion ( WatchLoReg  )

◆ EndBitUnion() [35/35]

gem5::MipsISA::EndBitUnion ( WiredReg  )

◆ EndSubBitUnion() [1/4]

gem5::MipsISA::EndSubBitUnion ( cu  )

◆ EndSubBitUnion() [2/4]

gem5::MipsISA::EndSubBitUnion ( ejtagVer  )

◆ EndSubBitUnion() [3/4]

gem5::MipsISA::EndSubBitUnion ( im  )

◆ EndSubBitUnion() [4/4]

gem5::MipsISA::EndSubBitUnion ( ip  )

◆ forkThread()

template<class TC >
void gem5::MipsISA::forkThread ( TC *  tc,
Fault fault,
int  Rd_bits,
int  Rs,
int  Rt 
)

◆ fpConvert()

uint64_t gem5::MipsISA::fpConvert ( ConvertType  cvt_type,
double  fp_val 
)

Definition at line 50 of file utility.cc.

References panic, SINGLE_TO_DOUBLE, SINGLE_TO_WORD, WORD_TO_DOUBLE, and WORD_TO_SINGLE.

◆ genCCVector()

uint32_t gem5::MipsISA::genCCVector ( uint32_t  fcsr,
int  cc_num,
uint32_t  cc_val 
)

Definition at line 120 of file utility.cc.

References gem5::bits().

◆ genInvalidVector()

uint32_t gem5::MipsISA::genInvalidVector ( uint32_t  fcsr_bits)

Definition at line 132 of file utility.cc.

References Cause_Field, Flag_Field, and Invalid.

◆ getCauseIP()

static uint8_t gem5::MipsISA::getCauseIP ( ThreadContext tc)
inlinestatic

◆ getCondCode()

bool gem5::MipsISA::getCondCode ( uint32_t  fcsr,
int  cc_idx 
)

Definition at line 112 of file utility.cc.

References gem5::ArmISA::shift.

◆ getTargetThread()

template<class TC >
unsigned gem5::MipsISA::getTargetThread ( TC *  tc)
inline

Definition at line 127 of file mt.hh.

References MISCREG_VPE_CONTROL.

◆ getVirtProcNum()

template<class TC >
unsigned gem5::MipsISA::getVirtProcNum ( TC *  tc)
inline

Definition at line 119 of file mt.hh.

References MISCREG_TC_BIND.

◆ globalClearExclusive()

template<class XC >
void gem5::MipsISA::globalClearExclusive ( XC *  xc)
inline

Definition at line 146 of file locked_mem.hh.

◆ haltThread()

template<class TC >
void gem5::MipsISA::haltThread ( TC *  tc)
inline

Definition at line 135 of file mt.hh.

References gem5::curTick(), MISCREG_TC_RESTART, pc, and warn.

Referenced by gem5::MipsISA::ISA::updateCPU().

◆ handleLockedRead()

template<class XC >
void gem5::MipsISA::handleLockedRead ( XC *  xc,
const RequestPtr req 
)
inline

Definition at line 80 of file locked_mem.hh.

References DPRINTF, MISCREG_LLADDR, and MISCREG_LLFLAG.

◆ handleLockedSnoop()

template<class XC >
void gem5::MipsISA::handleLockedSnoop ( XC *  xc,
PacketPtr  pkt,
Addr  cacheBlockMask 
)
inline

Definition at line 65 of file locked_mem.hh.

References gem5::Packet::getAddr(), MISCREG_LLADDR, and MISCREG_LLFLAG.

◆ handleLockedSnoopHit()

template<class XC >
void gem5::MipsISA::handleLockedSnoopHit ( XC *  xc)
inline

Definition at line 91 of file locked_mem.hh.

◆ handleLockedWrite()

template<class XC >
bool gem5::MipsISA::handleLockedWrite ( XC *  xc,
const RequestPtr req,
Addr  cacheBlockMask 
)
inline

Definition at line 97 of file locked_mem.hh.

References gem5::curTick(), DPRINTF, MISCREG_LLADDR, MISCREG_LLFLAG, and warn.

◆ isNan()

bool gem5::MipsISA::isNan ( void *  val_ptr,
int  size 
)

Definition at line 146 of file utility.cc.

References gem5::bits(), and panic.

◆ isQnan()

bool gem5::MipsISA::isQnan ( void *  val_ptr,
int  size 
)

Definition at line 169 of file utility.cc.

References gem5::bits(), and panic.

◆ isSnan()

bool gem5::MipsISA::isSnan ( void *  val_ptr,
int  size 
)

Definition at line 191 of file utility.cc.

References gem5::bits(), and panic.

◆ readDSPControl()

uint32_t gem5::MipsISA::readDSPControl ( uint32_t *  dspctl,
uint32_t  mask 
)

Definition at line 1178 of file dsp.cc.

References DSP_C, DSP_CCOND, DSP_CTL_MASK, DSP_EFI, DSP_OUFLAG, DSP_POS, DSP_SCOUNT, and mask.

◆ readRegOtherThread() [1/2]

static RegVal gem5::MipsISA::readRegOtherThread ( ExecContext xc,
const RegId reg,
ThreadID  tid = InvalidThreadID 
)
inlinestatic

Definition at line 104 of file mt.hh.

References readRegOtherThread(), gem5::X86ISA::reg, and gem5::ExecContext::tcBase().

◆ readRegOtherThread() [2/2]

static RegVal gem5::MipsISA::readRegOtherThread ( ThreadContext tc,
const RegId reg,
ThreadID  tid = InvalidThreadID 
)
inlinestatic

◆ restoreThread()

template<class TC >
void gem5::MipsISA::restoreThread ( TC *  tc)
inline

Definition at line 154 of file mt.hh.

References gem5::curTick(), MISCREG_TC_RESTART, and warn.

Referenced by gem5::MipsISA::ISA::updateCPU().

◆ roundFP()

double gem5::MipsISA::roundFP ( double  val,
int  digits 
)

Definition at line 94 of file utility.cc.

References gem5::X86ISA::val.

◆ RoundPage()

Addr gem5::MipsISA::RoundPage ( Addr  addr)
inline

Definition at line 75 of file utility.hh.

References gem5::X86ISA::addr, and PageBytes.

◆ setCauseIP()

static void gem5::MipsISA::setCauseIP ( ThreadContext tc,
uint8_t  val 
)
inlinestatic

◆ setRegOtherThread() [1/2]

static void gem5::MipsISA::setRegOtherThread ( ExecContext xc,
const RegId reg,
RegVal  val,
ThreadID  tid = InvalidThreadID 
)
inlinestatic

◆ setRegOtherThread() [2/2]

static void gem5::MipsISA::setRegOtherThread ( ThreadContext tc,
const RegId reg,
RegVal  val,
ThreadID  tid = InvalidThreadID 
)
inlinestatic

◆ setThreadAreaFunc()

static SyscallReturn gem5::MipsISA::setThreadAreaFunc ( SyscallDesc desc,
ThreadContext tc,
VPtr<>  addr 
)
static

◆ signExtend()

uint64_t gem5::MipsISA::signExtend ( uint64_t  value,
int32_t  signpos 
)

Definition at line 113 of file dsp.cc.

References SIMD_NBITS.

Referenced by simdUnpack().

◆ simdPack()

void gem5::MipsISA::simdPack ( uint64_t *  values_ptr,
int32_t *  reg,
int32_t  fmt 
)

◆ simdUnpack()

void gem5::MipsISA::simdUnpack ( int32_t  reg,
uint64_t *  values_ptr,
int32_t  fmt,
int32_t  sign 
)

◆ SubBitUnion() [1/3]

gem5::MipsISA::SubBitUnion ( ejtagVer  ,
17  ,
15   
)

◆ SubBitUnion() [2/3]

gem5::MipsISA::SubBitUnion ( im  ,
15  ,
 
)

◆ SubBitUnion() [3/3]

gem5::MipsISA::SubBitUnion ( ip  ,
15  ,
 
)

◆ sys_getsysinfoFunc()

static SyscallReturn gem5::MipsISA::sys_getsysinfoFunc ( SyscallDesc desc,
ThreadContext tc,
unsigned  op,
unsigned  bufPtr,
unsigned  nbytes 
)
static

Target sys_getsysyinfo() handler.

Even though this call is borrowed from Tru64, the subcases that get used appear to be different in practice from those used by Tru64 processes.

Definition at line 107 of file se_workload.cc.

References gem5::X86ISA::op.

◆ sys_setsysinfoFunc()

static SyscallReturn gem5::MipsISA::sys_setsysinfoFunc ( SyscallDesc desc,
ThreadContext tc,
unsigned  op,
VPtr<>  bufPtr,
unsigned  nbytes 
)
static

Target sys_setsysinfo() handler.

Definition at line 130 of file se_workload.cc.

References DPRINTFR, gem5::letoh(), and gem5::X86ISA::op.

◆ truncFP()

double gem5::MipsISA::truncFP ( double  val)

Definition at line 105 of file utility.cc.

References gem5::X86ISA::val.

◆ TruncPage()

Addr gem5::MipsISA::TruncPage ( Addr  addr)
inline

Definition at line 69 of file utility.hh.

References gem5::X86ISA::addr, and PageBytes.

◆ unameFunc()

static SyscallReturn gem5::MipsISA::unameFunc ( SyscallDesc desc,
ThreadContext tc,
VPtr< Linux::utsname name 
)
static

Target uname() handler.

Definition at line 90 of file se_workload.cc.

References gem5::ThreadContext::getProcessPtr(), and name().

◆ updateStatusView()

template<class TC >
void gem5::MipsISA::updateStatusView ( TC *  tc)
inline

Definition at line 305 of file mt.hh.

References MISCREG_STATUS, MISCREG_TC_STATUS, and gem5::ArmISA::status.

◆ updateTCStatusView()

template<class TC >
void gem5::MipsISA::updateTCStatusView ( TC *  tc)
inline

Definition at line 323 of file mt.hh.

References MISCREG_STATUS, MISCREG_TC_STATUS, and gem5::ArmISA::status.

◆ writeDSPControl()

void gem5::MipsISA::writeDSPControl ( uint32_t *  dspctl,
uint32_t  value,
uint32_t  mask 
)

◆ yieldThread()

template<class TC >
int gem5::MipsISA::yieldThread ( TC *  tc,
Fault fault,
int  src_reg,
uint32_t  yield_mask 
)

Variable Documentation

◆ a

Bitfield<13> gem5::MipsISA::a

◆ a0

Bitfield<20, 18> gem5::MipsISA::a0

◆ ar

Bitfield<12, 10> gem5::MipsISA::ar

Definition at line 225 of file pra_constants.hh.

◆ aseDn

Bitfield<12, 8> gem5::MipsISA::aseDn

Definition at line 83 of file pra_constants.hh.

◆ aseUp

gem5::MipsISA::aseUp

Definition at line 79 of file pra_constants.hh.

◆ asid

Bitfield< 23, 16 > gem5::MipsISA::asid

Definition at line 85 of file dt_constants.hh.

◆ asidM

Bitfield<20, 13> gem5::MipsISA::asidM

Definition at line 84 of file dt_constants.hh.

◆ at

Bitfield<14, 13> gem5::MipsISA::at

Definition at line 224 of file pra_constants.hh.

◆ ate

Bitfield<27> gem5::MipsISA::ate

Definition at line 108 of file dt_constants.hh.

◆ badVPN2

Bitfield<22, 4> gem5::MipsISA::badVPN2

Definition at line 67 of file pra_constants.hh.

◆ be

Bitfield<15> gem5::MipsISA::be

Definition at line 223 of file pra_constants.hh.

Referenced by gem5::Request::setByteEnable().

◆ bev

Bitfield<22> gem5::MipsISA::bev

Definition at line 117 of file pra_constants.hh.

◆ bpc0

Bitfield<2, 0> gem5::MipsISA::bpc0

Definition at line 117 of file dt_constants.hh.

◆ bpc1

Bitfield<5, 3> gem5::MipsISA::bpc1

Definition at line 116 of file dt_constants.hh.

◆ bpc10

Bitfield<5, 3> gem5::MipsISA::bpc10

Definition at line 125 of file dt_constants.hh.

◆ bpc11

Bitfield<8, 6> gem5::MipsISA::bpc11

Definition at line 124 of file dt_constants.hh.

◆ bpc12

Bitfield<11, 9> gem5::MipsISA::bpc12

Definition at line 123 of file dt_constants.hh.

◆ bpc13

Bitfield<14, 12> gem5::MipsISA::bpc13

Definition at line 122 of file dt_constants.hh.

◆ bpc14

gem5::MipsISA::bpc14

Definition at line 121 of file dt_constants.hh.

◆ bpc2

Bitfield<8, 6> gem5::MipsISA::bpc2

Definition at line 115 of file dt_constants.hh.

◆ bpc3

Bitfield<11, 9> gem5::MipsISA::bpc3

Definition at line 114 of file dt_constants.hh.

◆ bpc4

Bitfield<14, 12> gem5::MipsISA::bpc4

Definition at line 113 of file dt_constants.hh.

◆ bpc5

Bitfield<17, 15> gem5::MipsISA::bpc5

Definition at line 112 of file dt_constants.hh.

◆ bpc6

Bitfield<20, 18> gem5::MipsISA::bpc6

Definition at line 111 of file dt_constants.hh.

◆ bpc7

Bitfield<23, 21> gem5::MipsISA::bpc7

Definition at line 110 of file dt_constants.hh.

◆ bpc8

Bitfield<26, 24> gem5::MipsISA::bpc8

Definition at line 109 of file dt_constants.hh.

◆ bpc9

Bitfield<2, 0> gem5::MipsISA::bpc9

Definition at line 126 of file dt_constants.hh.

◆ c

Bitfield<5, 3> gem5::MipsISA::c

Definition at line 59 of file pra_constants.hh.

◆ c2

Bitfield<6> gem5::MipsISA::c2

Definition at line 241 of file pra_constants.hh.

Referenced by SC_MODULE().

◆ ca

Bitfield<2> gem5::MipsISA::ca

Definition at line 245 of file pra_constants.hh.

◆ cacheep

Bitfield<22> gem5::MipsISA::cacheep

Definition at line 51 of file dt_constants.hh.

◆ ce

Bitfield<29, 28> gem5::MipsISA::ce

◆ coId

Bitfield<23, 16> gem5::MipsISA::coId

Definition at line 205 of file pra_constants.hh.

◆ conutdm

Bitfield<25> gem5::MipsISA::conutdm

Definition at line 48 of file dt_constants.hh.

◆ coOp

gem5::MipsISA::coOp

Definition at line 204 of file pra_constants.hh.

◆ cpuid

Bitfield<28, 21> gem5::MipsISA::cpuid

◆ cpuNum

Bitfield<9, 9> gem5::MipsISA::cpuNum

Definition at line 215 of file pra_constants.hh.

◆ css

Bitfield<3, 0> gem5::MipsISA::css

Definition at line 163 of file pra_constants.hh.

◆ cu0

Bitfield<28> gem5::MipsISA::cu0

Definition at line 110 of file pra_constants.hh.

◆ cu1

Bitfield<29> gem5::MipsISA::cu1

Definition at line 109 of file pra_constants.hh.

◆ cu2

Bitfield<30> gem5::MipsISA::cu2

Definition at line 108 of file pra_constants.hh.

◆ cu3

Bitfield<31> gem5::MipsISA::cu3

Definition at line 106 of file pra_constants.hh.

◆ curTC

gem5::MipsISA::curTC

Definition at line 78 of file mt_constants.hh.

◆ curVPE

Bitfield<3, 0> gem5::MipsISA::curVPE

Definition at line 81 of file mt_constants.hh.

◆ d

Bitfield< 2 > gem5::MipsISA::d

Definition at line 79 of file dt_constants.hh.

◆ da

Bitfield< 9, 7 > gem5::MipsISA::da

Definition at line 91 of file mt_constants.hh.

◆ dbp

Bitfield<1> gem5::MipsISA::dbp

Definition at line 70 of file dt_constants.hh.

◆ dbusep

Bitfield<21> gem5::MipsISA::dbusep

Definition at line 52 of file dt_constants.hh.

◆ dc

Bitfield<27> gem5::MipsISA::dc

Definition at line 181 of file pra_constants.hh.

◆ dcs

Bitfield<17> gem5::MipsISA::dcs

Definition at line 71 of file mt_constants.hh.

◆ ddbl

Bitfield<2> gem5::MipsISA::ddbl

Definition at line 69 of file dt_constants.hh.

◆ ddblImpr

Bitfield<18> gem5::MipsISA::ddblImpr

Definition at line 55 of file dt_constants.hh.

◆ ddbs

Bitfield<3> gem5::MipsISA::ddbs

Definition at line 68 of file dt_constants.hh.

◆ ddbsImpr

Bitfield<19> gem5::MipsISA::ddbsImpr

Definition at line 54 of file dt_constants.hh.

◆ dexcCode

gem5::MipsISA::dexcCode

Definition at line 61 of file dt_constants.hh.

◆ dib

Bitfield<4> gem5::MipsISA::dib

Definition at line 67 of file dt_constants.hh.

◆ dibimpr

Bitfield<6> gem5::MipsISA::dibimpr

Definition at line 65 of file dt_constants.hh.

◆ dint

Bitfield<5> gem5::MipsISA::dint

Definition at line 66 of file dt_constants.hh.

◆ dl

Bitfield<12, 10> gem5::MipsISA::dl

Definition at line 239 of file pra_constants.hh.

◆ dm

Bitfield<30> gem5::MipsISA::dm

Definition at line 43 of file dt_constants.hh.

◆ doze

Bitfield<27> gem5::MipsISA::doze

Definition at line 46 of file dt_constants.hh.

◆ dq

Bitfield<2> gem5::MipsISA::dq

Definition at line 131 of file dt_constants.hh.

Referenced by gem5::ScheduleStage::ScheduleStage().

◆ ds

Bitfield<15, 13> gem5::MipsISA::ds

◆ DSP_CTL_MASK

const uint32_t gem5::MipsISA::DSP_CTL_MASK[DSP_NUM_FIELDS]
Initial value:
=
{ 0x0000003f, 0x00001f80, 0x00002000,
0x00ff0000, 0x0f000000, 0x00004000 }

Definition at line 90 of file dsp.hh.

Referenced by readDSPControl(), and writeDSPControl().

◆ DSP_CTL_POS

const uint32_t gem5::MipsISA::DSP_CTL_POS[DSP_NUM_FIELDS] = { 0, 7, 13, 16, 24, 14 }

Definition at line 89 of file dsp.hh.

Referenced by dspAbs(), dspAdd(), dspCmp(), dspCmpgd(), dspMul(), dspMuleq(), dspMuleu(), dspMulq(), dspPick(), dspShll(), and dspSub().

◆ dspp

Bitfield<10> gem5::MipsISA::dspp

Definition at line 265 of file pra_constants.hh.

◆ dss

Bitfield<0> gem5::MipsISA::dss

Definition at line 71 of file dt_constants.hh.

◆ dt

Bitfield<20> gem5::MipsISA::dt

Definition at line 89 of file mt_constants.hh.

◆ e

Bitfield< 28 > gem5::MipsISA::e

Definition at line 80 of file dt_constants.hh.

◆ eb

Bitfield<25> gem5::MipsISA::eb

Definition at line 315 of file pra_constants.hh.

◆ ec

Bitfield<30> gem5::MipsISA::ec

Definition at line 310 of file pra_constants.hh.

◆ ed

Bitfield<29> gem5::MipsISA::ed

Definition at line 311 of file pra_constants.hh.

◆ ee

Bitfield<26> gem5::MipsISA::ee

Definition at line 314 of file pra_constants.hh.

◆ eicss

Bitfield<21, 18> gem5::MipsISA::eicss

Definition at line 157 of file pra_constants.hh.

◆ ejtagVer0

Bitfield<15> gem5::MipsISA::ejtagVer0

Definition at line 59 of file dt_constants.hh.

◆ ejtagVer1

Bitfield<16> gem5::MipsISA::ejtagVer1

Definition at line 58 of file dt_constants.hh.

◆ elpa

Bitfield<29> gem5::MipsISA::elpa

Definition at line 80 of file pra_constants.hh.

◆ ep

Bitfield<1> gem5::MipsISA::ep

◆ erl

Bitfield<2> gem5::MipsISA::erl

Definition at line 140 of file pra_constants.hh.

◆ es

Bitfield<27> gem5::MipsISA::es

Definition at line 313 of file pra_constants.hh.

◆ esp

Bitfield<28> gem5::MipsISA::esp

Definition at line 81 of file pra_constants.hh.

◆ ess

Bitfield<15, 12> gem5::MipsISA::ess

Definition at line 159 of file pra_constants.hh.

◆ et

Bitfield<28> gem5::MipsISA::et

Definition at line 312 of file pra_constants.hh.

◆ event

Bitfield<10, 5> gem5::MipsISA::event

Definition at line 300 of file pra_constants.hh.

Referenced by gem5::FlashDevice::accessDevice(), sc_gem5::SensitivityEvents::addEvent(), gem5::ArmISA::PMU::addEventProbe(), gem5::EventQueue::asyncInsert(), gem5::ArmISA::PMU::CounterState::attach(), gem5::EventQueue::checkpointReschedule(), sc_gem5::SensitivityEvents::clear(), gem5::GPUComputeDriver::EventList::clearEvents(), gem5::ArmISA::TableWalker::Port::createPacket(), sc_gem5::Scheduler::deschedule(), gem5::EventQueue::deschedule(), gem5::EventManager::deschedule(), gem5::o3::ThreadContext::descheduleInstCountEvent(), gem5::CheckerThreadContext< TC >::descheduleInstCountEvent(), gem5::Iris::ThreadContext::descheduleInstCountEvent(), gem5::SimpleThread::descheduleInstCountEvent(), gem5::DmaPort::dmaAction(), gem5::DmaDevice::dmaRead(), gem5::DmaVirtDevice::dmaVirt(), gem5::DmaDevice::dmaWrite(), gem5::ArmISA::TableWalker::doLongDescriptor(), gem5::Trace::TarmacParserRecord::dump(), gem5::PCEventQueue::equal_range(), gem5::ArmISA::TableWalker::fetchDescriptor(), gem5::Pl111::fillFifo(), gem5::ArmISA::TableWalker::Stage2Walk::finish(), gem5::DmaReadFifo::handlePending(), gem5::BaseCPU::init(), gem5::EventQueue::insert(), gem5::Event::insertBefore(), gem5::Iris::ThreadContext::instanceRegistryChanged(), gem5::ruby::RubySystem::memWriteback(), sc_gem5::Gem5ToTlmBridge< BITWIDTH >::nb_transport_bw(), sc_gem5::newDynamicSensitivityEventAndList(), sc_gem5::newDynamicSensitivityEventOrList(), gem5::FlashDevice::readMemory(), sc_gem5::Gem5ToTlmBridge< BITWIDTH >::recvTimingReq(), gem5::ArmISA::PMU::regProbeListeners(), gem5::PollQueue::remove(), gem5::PCEventQueue::remove(), gem5::System::remove(), gem5::EventQueue::remove(), gem5::Event::removeItem(), gem5::EventQueue::reschedule(), gem5::EventManager::reschedule(), gem5::DmaReadFifo::resumeFillTiming(), gem5::PollQueue::schedule(), gem5::PCEventQueue::schedule(), gem5::System::schedule(), sc_gem5::Scheduler::schedule(), gem5::EventQueue::schedule(), gem5::EventManager::schedule(), gem5::o3::ThreadContext::scheduleInstCountEvent(), gem5::CheckerThreadContext< TC >::scheduleInstCountEvent(), gem5::Iris::ThreadContext::scheduleInstCountEvent(), gem5::SimpleThread::scheduleInstCountEvent(), gem5::BaseCPU::scheduleInstStop(), gem5::Uart8250::scheduleIntr(), gem5::ArmISA::TableWalker::Port::sendTimingReq(), gem5::BasePixelPump::serialize(), gem5::DVFSHandler::serialize(), gem5::Intel8254Timer::Counter::serialize(), gem5::IdeDisk::serialize(), gem5::EventQueue::serviceOne(), gem5::Intel8254Timer::Counter::startup(), gem5::DistEtherLink::Link::unserialize(), gem5::BasePixelPump::unserialize(), gem5::DVFSHandler::unserialize(), gem5::Intel8254Timer::Counter::unserialize(), gem5::IdeDisk::unserialize(), gem5::Intel8254Timer::Counter::write(), gem5::FlashDevice::writeMemory(), and sc_gem5::Object::~Object().

◆ evp

Bitfield<0> gem5::MipsISA::evp

Definition at line 45 of file mt_constants.hh.

◆ excCode

Bitfield<6, 2> gem5::MipsISA::excCode

◆ exceptionBase

gem5::MipsISA::exceptionBase

Definition at line 213 of file pra_constants.hh.

◆ excpt

Bitfield<18, 16> gem5::MipsISA::excpt

Definition at line 61 of file mt_constants.hh.

◆ exl

Bitfield< 0 > gem5::MipsISA::exl

Definition at line 141 of file pra_constants.hh.

◆ fill

Bitfield< 61, 40 > gem5::MipsISA::fill

◆ FirstArgumentReg

const int gem5::MipsISA::FirstArgumentReg = 4

Definition at line 67 of file int.hh.

Referenced by gem5::MipsProcess::argsInit().

◆ FIXED_B_SMAX

const uint64_t gem5::MipsISA::FIXED_B_SMAX = 0x000000000000007fULL

Definition at line 112 of file dsp.hh.

◆ FIXED_B_SMIN

const uint64_t gem5::MipsISA::FIXED_B_SMIN = 0xffffffffffffff80ULL

Definition at line 126 of file dsp.hh.

◆ FIXED_B_UMAX

const uint64_t gem5::MipsISA::FIXED_B_UMAX = 0x00000000000000ffULL

Definition at line 116 of file dsp.hh.

◆ FIXED_B_UMIN

const uint64_t gem5::MipsISA::FIXED_B_UMIN = 0x0000000000000000ULL

Definition at line 130 of file dsp.hh.

◆ FIXED_H_SMAX

const uint64_t gem5::MipsISA::FIXED_H_SMAX = 0x0000000000007fffULL

Definition at line 111 of file dsp.hh.

◆ FIXED_H_SMIN

const uint64_t gem5::MipsISA::FIXED_H_SMIN = 0xffffffffffff8000ULL

Definition at line 125 of file dsp.hh.

◆ FIXED_H_UMAX

const uint64_t gem5::MipsISA::FIXED_H_UMAX = 0x000000000000ffffULL

Definition at line 115 of file dsp.hh.

◆ FIXED_H_UMIN

const uint64_t gem5::MipsISA::FIXED_H_UMIN = 0x0000000000000000ULL

Definition at line 129 of file dsp.hh.

◆ FIXED_L_SMAX

const uint64_t gem5::MipsISA::FIXED_L_SMAX = 0x7fffffffffffffffULL

Definition at line 109 of file dsp.hh.

◆ FIXED_L_SMIN

const uint64_t gem5::MipsISA::FIXED_L_SMIN = 0x8000000000000000ULL

Definition at line 123 of file dsp.hh.

◆ FIXED_L_UMAX

const uint64_t gem5::MipsISA::FIXED_L_UMAX = 0xffffffffffffffffULL

Definition at line 113 of file dsp.hh.

◆ FIXED_L_UMIN

const uint64_t gem5::MipsISA::FIXED_L_UMIN = 0x0000000000000000ULL

Definition at line 127 of file dsp.hh.

◆ FIXED_SMAX

const uint64_t gem5::MipsISA::FIXED_SMAX[SIMD_NUM_FMTS]

◆ FIXED_SMIN

const uint64_t gem5::MipsISA::FIXED_SMIN[SIMD_NUM_FMTS]

◆ FIXED_UMAX

const uint64_t gem5::MipsISA::FIXED_UMAX[SIMD_NUM_FMTS]
Initial value:

Definition at line 119 of file dsp.hh.

Referenced by checkOverflow(), and dspSaturate().

◆ FIXED_UMIN

const uint64_t gem5::MipsISA::FIXED_UMIN[SIMD_NUM_FMTS]
Initial value:

Definition at line 133 of file dsp.hh.

Referenced by checkOverflow(), and dspSaturate().

◆ FIXED_W_SMAX

const uint64_t gem5::MipsISA::FIXED_W_SMAX = 0x000000007fffffffULL

Definition at line 110 of file dsp.hh.

◆ FIXED_W_SMIN

const uint64_t gem5::MipsISA::FIXED_W_SMIN = 0xffffffff80000000ULL

Definition at line 124 of file dsp.hh.

◆ FIXED_W_UMAX

const uint64_t gem5::MipsISA::FIXED_W_UMAX = 0x00000000ffffffffULL

Definition at line 114 of file dsp.hh.

◆ FIXED_W_UMIN

const uint64_t gem5::MipsISA::FIXED_W_UMIN = 0x0000000000000000ULL

Definition at line 128 of file dsp.hh.

◆ fp

Bitfield<0> gem5::MipsISA::fp

Definition at line 247 of file pra_constants.hh.

◆ fr

Bitfield<26> gem5::MipsISA::fr

Definition at line 113 of file pra_constants.hh.

◆ g

Bitfield< 30 > gem5::MipsISA::g

◆ gs

Bitfield<28> gem5::MipsISA::gs

Definition at line 51 of file mt_constants.hh.

◆ halt

Bitfield<26> gem5::MipsISA::halt

Definition at line 47 of file dt_constants.hh.

◆ hss

gem5::MipsISA::hss

Definition at line 155 of file pra_constants.hh.

◆ i

Bitfield< 2 > gem5::MipsISA::i

◆ ia

Bitfield<18, 16> gem5::MipsISA::ia

Definition at line 237 of file pra_constants.hh.

Referenced by gem5::networking::operator<<().

◆ ibusep

Bitfield<24> gem5::MipsISA::ibusep

Definition at line 49 of file dt_constants.hh.

◆ ics

Bitfield<16> gem5::MipsISA::ics

Definition at line 72 of file mt_constants.hh.

◆ ie

Bitfield< 4 > gem5::MipsISA::ie

Definition at line 142 of file pra_constants.hh.

◆ iexi

Bitfield<20, 19> gem5::MipsISA::iexi

Definition at line 53 of file dt_constants.hh.

◆ il

Bitfield<21, 19> gem5::MipsISA::il

Definition at line 236 of file pra_constants.hh.

◆ im0

Bitfield<8> gem5::MipsISA::im0

Definition at line 132 of file pra_constants.hh.

◆ im1

Bitfield<9> gem5::MipsISA::im1

Definition at line 131 of file pra_constants.hh.

◆ im2

Bitfield<10> gem5::MipsISA::im2

Definition at line 130 of file pra_constants.hh.

◆ im3

Bitfield<11> gem5::MipsISA::im3

Definition at line 129 of file pra_constants.hh.

◆ im4

Bitfield<12> gem5::MipsISA::im4

Definition at line 128 of file pra_constants.hh.

◆ im5

Bitfield<13> gem5::MipsISA::im5

Definition at line 127 of file pra_constants.hh.

◆ im6

Bitfield<14> gem5::MipsISA::im6

Definition at line 126 of file pra_constants.hh.

◆ impl

Bitfield< 4, 3 > gem5::MipsISA::impl

◆ index

Bitfield< 22, 0 > gem5::MipsISA::index

Definition at line 47 of file pra_constants.hh.

Referenced by gem5::FlashDevice::accessDevice(), gem5::ruby::Histogram::add(), gem5::ruby::Set::add(), gem5::prefetch::IndirectMemory::allocateOrUpdateIPDEntry(), sc_core::sc_vector< svp_gicv3_comms::gicv3_comms_target_socket<> >::at(), gem5::ruby::NetDest::bitIndex(), gem5::PowerISA::BranchRegCondOp::branchTarget(), gem5::branch_prediction::MPP_LoopPredictor::calcConf(), gem5::branch_prediction::TAGE_SC_L_LoopPredictor::calcConf(), gem5::branch_prediction::LoopPredictor::calcConf(), gem5::prefetch::IndirectMemory::calculatePrefetch(), gem5::minor::Scoreboard::canInstIssue(), gem5::o3::StoreSet::checkInst(), gem5::SparcISA::Interrupts::clear(), gem5::ArmISA::Interrupts::clear(), tlm_utils::instance_specific_extensions_per_accessor::clear_extension(), gem5::minor::Scoreboard::clearInstDests(), gem5::BaseCPU::clearInterrupt(), gem5::FlashDevice::clearUnknownPages(), gem5::compression::Multi::compress(), gem5::compression::FrequentValues::compress(), gem5::VirtQueue::consumeDescriptor(), gem5::minor::cyclicIndexDec(), gem5::minor::cyclicIndexInc(), gem5::statistics::VectorBase< Vector, StatStor >::data(), gem5::statistics::VectorProxy< Stat >::data(), gem5::statistics::Vector2dBase< Vector2d, StatStor >::data(), gem5::statistics::VectorDistBase< VectorAverageDeviation, AvgSampleStor >::data(), gem5::DVFSHandler::domainID(), gem5::SMMUTranslationProcess::doReadSTE(), gem5::ruby::NetDest::elementAt(), gem5::ruby::Set::elementAt(), gem5::minor::Scoreboard::execSeqNumToWaitFor(), gem5::Gcn3ISA::Inst_DS__DS_SWIZZLE_B32::execute(), gem5::Gcn3ISA::Inst_DS__DS_PERMUTE_B32::execute(), gem5::Gcn3ISA::Inst_DS__DS_BPERMUTE_B32::execute(), gem5::VegaISA::Inst_DS__DS_SWIZZLE_B32::execute(), gem5::VegaISA::Inst_DS__DS_PERMUTE_B32::execute(), gem5::VegaISA::Inst_DS__DS_BPERMUTE_B32::execute(), gem5::branch_prediction::LoopPredictor::finallindex(), gem5::branch_prediction::MultiperspectivePerceptron::findBest(), gem5::WholeTranslationState::finish(), gem5::SparcISA::SEWorkload::flushWindows(), gem5::SparcISA::Mem::generateDisassembly(), gem5::SparcISA::MemImm::generateDisassembly(), gem5::SparcISA::WrPriv::generateDisassembly(), gem5::SparcISA::WrPrivImm::generateDisassembly(), gem5::PowerISA::IntImmLogicOp::generateDisassembly(), gem5::PowerISA::IntTrapOp::generateDisassembly(), gem5::guest_abi::Argument< Aapcs32Vfp, Float, typename std::enable_if_t< std::is_floating_point< Float >::value > >::get(), gem5::guest_abi::Argument< Aapcs32Vfp, HA, typename std::enable_if_t< IsAapcs32HomogeneousAggregate< HA >::value > >::get(), tlm_utils::instance_specific_extensions_per_accessor::get_extension(), tlm::tlm_generic_payload::get_extension(), gem5::scmi::Platform::getAgent(), gem5::ArmISA::SelfDebug::getBrkPoint(), gem5::ruby::Histogram::getData(), gem5::ruby::AbstractController::getDelayVCHist(), gem5::VirtQueue::getDescriptor(), gem5::getEventQueue(), gem5::compression::Multi::MultiCompData::getIndex(), gem5::branch_prediction::MultiperspectivePerceptronTAGE::getIndex(), gem5::branch_prediction::MultiperspectivePerceptron::getIndex(), gem5::getMiscRegName(), gem5::X86KvmCPU::getMSR(), gem5::FlashDevice::getUnknownPages(), gem5::o3::ThreadContext::getWritableVecPredReg(), gem5::o3::ThreadContext::getWritableVecReg(), gem5::branch_prediction::TAGE_SC_L_TAGE::gindex(), gem5::branch_prediction::TAGEBase::gindex(), gem5::branch_prediction::TAGE_SC_L_TAGE_8KB::gindex_ext(), gem5::branch_prediction::TAGE_SC_L_TAGE_64KB::gindex_ext(), gem5::branch_prediction::StatisticalCorrector::gPredict(), gem5::branch_prediction::MPP_StatisticalCorrector::gUpdate(), gem5::branch_prediction::StatisticalCorrector::gUpdate(), gem5::o3::PhysRegFile::initFreeList(), gem5::ruby::RubyPrefetcher::initializeStream(), gem5::Check::initiateAction(), gem5::Check::initiateCheck(), gem5::Check::initiateFlush(), gem5::Check::initiatePrefetch(), gem5::o3::StoreSet::insertStore(), gem5::ArmISA::INTREG_ABT(), gem5::ArmISA::INTREG_FIQ(), gem5::ArmISA::INTREG_HYP(), gem5::ArmISA::INTREG_IRQ(), gem5::ArmISA::INTREG_MON(), gem5::ArmISA::INTREG_SVC(), gem5::ArmISA::INTREG_UND(), gem5::ArmISA::INTREG_USR(), gem5::replacement_policy::isRightSubtree(), gem5::o3::StoreSet::issued(), gem5::ruby::RubyPrefetcher::issueNextPrefetch(), gem5::replacement_policy::leftSubtreeIndex(), gem5::PowerISA::TLB::lookup(), gem5::ArmISA::MacroMemOp::MacroMemOp(), gem5::makeKvmCpuid(), gem5::minor::Scoreboard::markupInstDests(), gem5::System::markWorkItem(), gem5::ruby::RubyPrefetcher::observeMiss(), gem5::CircularQueue< T >::iterator::operator[](), gem5::CircularQueue< Tick >::operator[](), sc_core::sc_vector< svp_gicv3_comms::gicv3_comms_target_socket<> >::operator[](), gem5::statistics::VectorBase< Vector, StatStor >::operator[](), gem5::statistics::VectorProxy< Stat >::operator[](), gem5::statistics::Vector2dBase< Vector2d, StatStor >::operator[](), gem5::statistics::VectorDistBase< VectorAverageDeviation, AvgSampleStor >::operator[](), gem5::replacement_policy::parentIndex(), gem5::CxxConfigManager::parsePort(), gem5::PMP::pmpUpdateAddr(), gem5::pollFunc(), gem5::ArmISA::Interrupts::post(), gem5::SparcISA::Interrupts::post(), gem5::BaseCPU::postInterrupt(), gem5::sinic::Device::prepareIO(), gem5::sinic::Device::prepareRead(), gem5::sinic::Device::prepareWrite(), gem5::SparcISA::IntOp::printPseudoOps(), gem5::SparcISA::IntOpImm::printPseudoOps(), gem5::ComputeUnit::DataPort::processMemRespEvent(), gem5::LdsChunk::read(), gem5::sinic::Device::read(), gem5::Pl111::read(), gem5::o3::ThreadContext::readCCReg(), gem5::o3::ThreadContext::readFloatReg(), gem5::o3::ThreadContext::readIntReg(), gem5::Iob::readIob(), gem5::Iob::readJBus(), gem5::o3::ThreadContext::readReg(), gem5::ArmISA::readVecElem(), gem5::o3::ThreadContext::readVecElem(), gem5::o3::ThreadContext::readVecPredReg(), gem5::o3::ThreadContext::readVecReg(), gem5::ComputeUnit::DataPort::recvTimingResp(), gem5::ArmISA::PMU::regProbeListeners(), gem5::ruby::Set::remove(), gem5::replacement_policy::rightSubtreeIndex(), gem5::statistics::HistStor::sample(), gem5::ComputeUnit::sendRequest(), tlm_utils::instance_specific_extensions_per_accessor::set_extension(), gem5::o3::ThreadContext::setCCReg(), gem5::setContextSegment(), gem5::BaseIndexingPolicy::setEntry(), gem5::o3::ThreadContext::setFloatReg(), gem5::o3::ThreadContext::setIntReg(), gem5::setKvmDTableReg(), gem5::setKvmSegmentReg(), gem5::X86KvmCPU::setMSR(), gem5::o3::ThreadContext::setVecElem(), gem5::o3::ThreadContext::setVecPredReg(), gem5::o3::ThreadContext::setVecReg(), sc_core::sc_vector_base::size(), gem5::branch_prediction::LoopPredictor::specLoopUpdate(), gem5::statistics::DataWrapVec< VectorStandardDeviation, VectorDistInfoProxy >::subdesc(), gem5::statistics::DataWrapVec< VectorStandardDeviation, VectorDistInfoProxy >::subname(), TEST(), TEST_P(), sc_dt::scfx_rep::to_string(), gem5::ArmISA::SelfDebug::updateDBGBCR(), gem5::ArmISA::SelfDebug::updateDBGWCR(), gem5::branch_prediction::MPP_StatisticalCorrector::MPP_SCThreadHistory::updateHistoryStack(), gem5::LdsChunk::write(), gem5::sinic::Device::write(), gem5::Pl111::write(), gem5::Iob::writeIob(), gem5::Iob::writeJBus(), gem5::ArmISA::writeVecElem(), and gem5::statistics::DataWrapVec2d< Derived, Vector2dInfoProxy >::ysubname().

◆ io

Bitfield<26> gem5::MipsISA::io

Definition at line 78 of file dt_constants.hh.

◆ ip0

Bitfield<8> gem5::MipsISA::ip0

Definition at line 196 of file pra_constants.hh.

◆ ip1

Bitfield<9> gem5::MipsISA::ip1

Definition at line 195 of file pra_constants.hh.

◆ ip2

Bitfield<10> gem5::MipsISA::ip2

Definition at line 194 of file pra_constants.hh.

◆ ip3

Bitfield<11> gem5::MipsISA::ip3

Definition at line 193 of file pra_constants.hh.

◆ ip4

Bitfield<12> gem5::MipsISA::ip4

Definition at line 192 of file pra_constants.hh.

◆ ip5

Bitfield<13> gem5::MipsISA::ip5

Definition at line 191 of file pra_constants.hh.

◆ ip6

Bitfield<14> gem5::MipsISA::ip6

◆ ipl

Bitfield<15, 10> gem5::MipsISA::ipl

Definition at line 123 of file pra_constants.hh.

◆ ippci

Bitfield<28, 26> gem5::MipsISA::ippci

Definition at line 147 of file pra_constants.hh.

◆ ipti

gem5::MipsISA::ipti

Definition at line 146 of file pra_constants.hh.

◆ is

Bitfield<24, 22> gem5::MipsISA::is

◆ iv

Bitfield<23> gem5::MipsISA::iv

Definition at line 184 of file pra_constants.hh.

◆ ixmt

Bitfield<10> gem5::MipsISA::ixmt

Definition at line 94 of file mt_constants.hh.

◆ k

Bitfield< 1 > gem5::MipsISA::k

◆ k0

Bitfield<2, 0> gem5::MipsISA::k0

Definition at line 229 of file pra_constants.hh.

Referenced by gem5::ArmISA::addPAC(), and gem5::ArmISA::auth().

◆ k23

Bitfield<30, 28> gem5::MipsISA::k23

Definition at line 220 of file pra_constants.hh.

◆ ksu

Bitfield<4, 3> gem5::MipsISA::ksu

Definition at line 137 of file pra_constants.hh.

◆ ku

Bitfield<27, 25> gem5::MipsISA::ku

Definition at line 221 of file pra_constants.hh.

◆ l

Bitfield<5> gem5::MipsISA::l

Definition at line 323 of file pra_constants.hh.

Referenced by gem5::ProbePointArg< RequestPtr >::addListener(), gem5::ruby::PerfectSwitch::addOutPort(), sc_dt::sc_uint_base::check_range(), sc_dt::sc_int_base::check_range(), sc_dt::sc_unsigned::check_range(), sc_dt::sc_signed::check_range(), gem5::CacheBlk::checkWrite(), gem5::CacheBlk::clearLoadLocks(), gem5::ruby::Topology::createLinks(), sc_dt::scfx_rep::get_slice(), gem5::branch_prediction::MultiperspectivePerceptron::RECENCYPOS::hash(), sc_core::sc_inout< sc_dt::sc_logic >::initialize(), sc_dt::sc_uint_base::invalid_range(), sc_dt::sc_int_base::invalid_range(), sc_dt::sc_unsigned::invalid_range(), sc_dt::sc_signed::invalid_range(), gem5::BaseArmKvmCPU::ioctlRun(), gem5::MemChecker::ByteTracker::lastCompletedTransaction(), gem5::ruby::Topology::makeLink(), gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::mapsTo(), tlm_utils::callback_binder_bw< tlm::tlm_base_protocol_types >::nb_transport_bw(), gem5::ProbePointArg< RequestPtr >::notify(), gem5::operator!=(), gem5::PCEventQueue::MapCompare::operator()(), gem5::statistics::operator*(), gem5::operator+(), gem5::statistics::operator+(), gem5::operator-(), gem5::statistics::operator-(), gem5::statistics::operator/(), gem5::operator<(), gem5::operator<=(), sc_core::sc_out_resolved::operator=(), sc_core::sc_inout_resolved::operator=(), sc_core::sc_out_rv< W >::operator=(), sc_core::sc_inout_rv< W >::operator=(), sc_core::sc_signal_resolved::operator=(), sc_core::sc_signal_rv< W >::operator=(), sc_core::sc_inout< sc_dt::sc_logic >::operator=(), gem5::operator==(), gem5::ruby::operator>(), gem5::operator>(), gem5::operator>=(), gem5::MathExpr::parse(), gem5::SparcISA::SparcStaticInst::passesFpCondition(), gem5::AMDMMIOReader::readMMIOTrace(), gem5::ruby::RubyPort::PioResponsePort::recvAtomic(), gem5::ruby::RubyPort::PioResponsePort::recvTimingReq(), gem5::ProbePointArg< RequestPtr >::removeListener(), gem5::memory::PhysicalMemory::serialize(), sc_dt::sc_concref_r< X, Y >::set_cword(), sc_dt::scfx_rep::set_slice(), sc_dt::sc_concref_r< X, Y >::set_word(), gem5::o3::UnifiedRenameMap::switchMode(), TEST_F(), RegisterBankTest::TestReg::TestReg(), gem5::CacheBlk::trackLoadLocked(), gem5::WalkCache::WalkCacheStats::WalkCacheStats(), sc_core::sc_signal_resolved::write(), sc_core::sc_signal_rv< W >::write(), sc_core::sc_inout< sc_dt::sc_logic >::write(), gem5::CoherentXBar::~CoherentXBar(), gem5::NoncoherentXBar::~NoncoherentXBar(), and gem5::ProbeListenerObject::~ProbeListenerObject().

◆ lpa

Bitfield<7> gem5::MipsISA::lpa

Definition at line 267 of file pra_constants.hh.

◆ lsnm

Bitfield<28> gem5::MipsISA::lsnm

Definition at line 45 of file dt_constants.hh.

◆ mask

Bitfield< 11, 3 > gem5::MipsISA::mask

Definition at line 73 of file pra_constants.hh.

Referenced by gem5::MipsISA::ISA::configCP(), readDSPControl(), and writeDSPControl().

◆ maskx

Bitfield<12, 11> gem5::MipsISA::maskx

Definition at line 74 of file pra_constants.hh.

◆ MaxShadowRegSets

const int gem5::MipsISA::MaxShadowRegSets = 16

Definition at line 43 of file int.hh.

◆ mcheckep

Bitfield<23> gem5::MipsISA::mcheckep

Definition at line 50 of file dt_constants.hh.

◆ md

Bitfield<5> gem5::MipsISA::md

Definition at line 242 of file pra_constants.hh.

◆ MIPS32_QNAN

const uint32_t gem5::MipsISA::MIPS32_QNAN = 0x7fbfffff

Definition at line 47 of file float.hh.

◆ MIPS64_QNAN

const uint64_t gem5::MipsISA::MIPS64_QNAN = 0x7ff7ffffffffffffULL

Definition at line 48 of file float.hh.

◆ mmuSize

Bitfield<30, 25> gem5::MipsISA::mmuSize

Definition at line 234 of file pra_constants.hh.

◆ mode

Bitfield<11, 7> gem5::MipsISA::mode

Definition at line 98 of file dt_constants.hh.

Referenced by dspDpa(), dspDpaq(), dspDps(), dspDpsq(), dspMaq(), dspMuleq(), dspMuleu(), and dspPrece().

◆ mt

Bitfield< 2 > gem5::MipsISA::mt

Definition at line 226 of file pra_constants.hh.

◆ mvp

Bitfield<1> gem5::MipsISA::mvp

Definition at line 73 of file mt_constants.hh.

◆ mx

Bitfield<24> gem5::MipsISA::mx

Definition at line 115 of file pra_constants.hh.

◆ nmi

Bitfield<19> gem5::MipsISA::nmi

Definition at line 120 of file pra_constants.hh.

◆ nodcr

Bitfield<29> gem5::MipsISA::nodcr

Definition at line 44 of file dt_constants.hh.

◆ nosst

Bitfield<9> gem5::MipsISA::nosst

Definition at line 62 of file dt_constants.hh.

◆ NumFloatArchRegs

const int gem5::MipsISA::NumFloatArchRegs = 32

◆ NumFloatRegs

const int gem5::MipsISA::NumFloatRegs = NumFloatArchRegs + NumFloatSpecialRegs

Definition at line 45 of file float.hh.

Referenced by gem5::MipsISA::ISA::copyRegsFrom(), and gem5::MipsISA::ISA::ISA().

◆ NumFloatSpecialRegs

const int gem5::MipsISA::NumFloatSpecialRegs = 5

Definition at line 43 of file float.hh.

◆ NumIntArchRegs

const int gem5::MipsISA::NumIntArchRegs = 32

◆ NumIntRegs

const int gem5::MipsISA::NumIntRegs = NumIntArchRegs + NumIntSpecialRegs

Definition at line 44 of file int.hh.

Referenced by gem5::MipsISA::ISA::copyRegsFrom(), and gem5::MipsISA::ISA::ISA().

◆ NumIntSpecialRegs

const int gem5::MipsISA::NumIntSpecialRegs = 9

Definition at line 41 of file int.hh.

Referenced by gem5::PowerProcess::argsInit().

◆ NumVecElemPerVecReg

constexpr unsigned gem5::MipsISA::NumVecElemPerVecReg = ::gem5::DummyNumVecElemPerVecReg
constexpr

Definition at line 45 of file vecregs.hh.

◆ offline

Bitfield<7> gem5::MipsISA::offline

Definition at line 64 of file dt_constants.hh.

◆ on

Bitfield<0> gem5::MipsISA::on

◆ p

Bitfield<0> gem5::MipsISA::p

Definition at line 326 of file pra_constants.hh.

Referenced by gem5::_llseekFunc(), gem5::acceptFunc(), gem5::accessFunc(), gem5::ArmISA::SelfDebug::activateDebug(), sc_core::sc_join::add_process(), gem5::ProbeManager::addListener(), gem5::ProbeManager::addPoint(), gem5::memory::MemCtrl::addToReadQueue(), gem5::AMDGPUDevice::AMDGPUDevice(), gem5::ArmSemihosting::ArmSemihosting(), gem5::ArmSystem::ArmSystem(), gem5::atomic_read(), gem5::atomic_write(), gem5::BaseGic::BaseGic(), gem5::BaseGlobalEventTemplate< GlobalSyncEvent >::BaseGlobalEventTemplate(), gem5::BaseSetAssoc::BaseSetAssoc(), gem5::BaseSimpleCPU::BaseSimpleCPU(), gem5::ruby::BasicLink::BasicLink(), gem5::ruby::BasicRouter::BasicRouter(), gem5::EtherInt::bind(), sc_core::sc_port_base::bind(), sc_core::sc_in< sc_dt::sc_lv< W > >::bind(), sc_core::sc_port_b< tlm_nonblocking_put_if< T > >::bind(), sc_core::sc_in< bool >::bind(), sc_core::sc_in< sc_dt::sc_logic >::bind(), gem5::bindFunc(), gem5::brkFunc(), tlm::circular_buffer< RSP >::buf_free(), tlm::circular_buffer< RSP >::buf_write(), gem5::Cache::Cache(), gem5::ruby::CacheMemory::CacheMemory(), gem5::chdirFunc(), gem5::PacketQueue::checkConflict(), gem5::o3::Checker::Checker(), gem5::CheckerCPU::CheckerCPU(), gem5::ScheduleStage::checkRfOperandReadComplete(), sc_gem5::WriteChecker< sc_core::SC_ONE_WRITER >::checkWriter(), sc_gem5::WriteChecker< sc_core::SC_MANY_WRITERS >::checkWriter(), gem5::chownFunc(), gem5::ProfileNode::clear(), sc_gem5::Scheduler::clear(), gem5::ArmISA::ISA::clear(), gem5::ArmISA::ISA::clear32(), gem5::ClockedObject::ClockedObject(), gem5::cloneFunc(), gem5::closeFunc(), gem5::BaseRemoteGDB::cmdAsyncCont(), gem5::BaseRemoteGDB::cmdAsyncStep(), gem5::BaseRemoteGDB::cmdClrHwBkpt(), gem5::BaseRemoteGDB::cmdCont(), gem5::BaseRemoteGDB::cmdMemR(), gem5::BaseRemoteGDB::cmdMemW(), gem5::BaseRemoteGDB::cmdRegW(), gem5::BaseRemoteGDB::cmdSetHwBkpt(), gem5::BaseRemoteGDB::cmdSetThread(), gem5::BaseCache::CacheStats::cmdStats(), gem5::BaseRemoteGDB::cmdStep(), gem5::CoherentXBar::CoherentXBar(), gem5::connectFunc(), gem5::VirtIO9PSocket::connectSocket(), sc_dt::convert_to_bin(), gem5::CopyEngine::CopyEngine(), gem5::FrameBuffer::copyIn(), gem5::AtagHeader::copyOut(), gem5::FrameBuffer::copyOut(), gem5::fastmodel::CortexA76Cluster::CortexA76Cluster(), gem5::fastmodel::CortexR52Cluster::CortexR52Cluster(), gem5::CowDiskImage::CowDiskImage(), gem5::memory::qos::QueuePolicy::create(), gem5::StreamGen::create(), gem5::GenericTimer::createTimers(), gem5::CustomNoMaliGpu::CustomNoMaliGpu(), gem5::Packet::dataDynamic(), gem5::Packet::dataStatic(), gem5::Packet::dataStaticConst(), sc_gem5::DefaultReportMessages::DefaultReportMessages(), gem5::DirectedGenerator::DirectedGenerator(), sc_gem5::Process::disable(), gem5::DistEtherLink::DistEtherLink(), gem5::memory::DRAMInterface::doBurstAccess(), gem5::loader::doGzipLoad(), sc_core::sc_module::dont_initialize(), gem5::DumbTOD::DumbTOD(), gem5::DummyChecker::DummyChecker(), gem5::ProfileNode::dump(), gem5::FunctionProfile::dump(), gem5::dup2Func(), gem5::dupFunc(), gem5::DVFSHandler::DVFSHandler(), gem5::DynPoolManager::DynPoolManager(), sc_gem5::Process::enable(), sc_core::sc_in< sc_dt::sc_int< W > >::end_of_elaboration(), sc_core::sc_in< sc_dt::sc_uint< W > >::end_of_elaboration(), sc_core::sc_in< sc_dt::sc_biguint< W > >::end_of_elaboration(), sc_core::sc_in< sc_dt::sc_bigint< W > >::end_of_elaboration(), sc_core::sc_inout< sc_dt::sc_int< W > >::end_of_elaboration(), sc_core::sc_inout< sc_dt::sc_uint< W > >::end_of_elaboration(), sc_core::sc_inout< sc_dt::sc_biguint< W > >::end_of_elaboration(), sc_core::sc_inout< sc_dt::sc_bigint< W > >::end_of_elaboration(), gem5::PciIoBar::EndBitUnion(), gem5::AddressManager::AtomicStruct::endLocSelection(), gem5::SparcISA::TlbMap::erase(), gem5::AddrRangeMap< gem5::MemBackdoor, 1 >::erase(), gem5::EtherLink::EtherLink(), gem5::EtherSwitch::EtherSwitch(), gem5::EtherTapStub::EtherTapStub(), gem5::eventfdFunc(), gem5::execveFunc(), gem5::exitImpl(), gem5::fallocateFunc(), gem5::ruby::FaultModel::FaultModel(), gem5::fchmodFunc(), gem5::fchownFunc(), gem5::fcntl64Func(), gem5::fcntlFunc(), gem5::FetchStage::FetchStage(), gem5::FrameBuffer::fill(), gem5::VGic::findHighestPendingLR(), gem5::CoherentXBar::forwardAtomic(), gem5::CoherentXBar::forwardFunctional(), gem5::CoherentXBar::forwardTiming(), gem5::ArmISA::FsFreebsd::FsFreebsd(), gem5::fstat64Func(), gem5::fstatfsFunc(), gem5::fstatFunc(), gem5::ArmISA::FsWorkload::FsWorkload(), gem5::ftruncate64Func(), gem5::ftruncateFunc(), gem5::o3::FUPool::FUPool(), gem5::ruby::garnet::GarnetExtLink::GarnetExtLink(), gem5::ruby::garnet::GarnetIntLink::GarnetIntLink(), gem5::ruby::garnet::GarnetNetwork::GarnetNetwork(), gem5::GenericTimer::GenericTimer(), sc_core::sc_simcontext::get_curr_proc_info(), gem5::DRAMPower::getArchParams(), gem5::getcwdFunc(), gem5::DRAMPower::getDataRate(), gem5::DRAMPower::getMemSpec(), sc_gem5::Scheduler::getNextReady(), gem5::IGbE::TxDescCache::getPacketData(), gem5::IGbE::TxDescCache::getPacketSize(), gem5::getpeernameFunc(), gem5::DRAMPower::getPowerParams(), gem5::branch_prediction::SimpleIndirectPredictor::getSetIndex(), gem5::getsocknameFunc(), gem5::getsockoptFunc(), gem5::DRAMPower::getTimingParams(), gem5::GPUComputeDriver::GPUComputeDriver(), gem5::DRAMPower::hasTwoVDD(), gem5::HMCController::HMCController(), gem5::HSAPacketProcessor::HSAPacketProcessor(), gem5::I2CBus::I2CBus(), sc_core::sc_vector_base::implicitCast(), sc_gem5::Kernel::init(), gem5::CpuLocalTimer::init(), gem5::CoherentXBar::init(), sc_core::sc_vector< svp_gicv3_comms::gicv3_comms_target_socket<> >::init(), gem5::branch_prediction::MultiperspectivePerceptron::init(), gem5::ArmISA::ISA::initID32(), gem5::ArmISA::ISA::initID64(), sc_gem5::Scheduler::initPhase(), gem5::Trace::InstPBTrace::InstPBTrace(), gem5::InvalidateGenerator::InvalidateGenerator(), gem5::GenericPageTableFault::invoke(), gem5::SparcISA::FastInstructionAccessMMUMiss::invoke(), gem5::SparcISA::FastDataAccessMMUMiss::invoke(), gem5::SparcISA::SpillNNormal::invoke(), gem5::SparcISA::FillNNormal::invoke(), gem5::SparcISA::TrapInstruction::invoke(), gem5::Iob::Iob(), gem5::ioctlFunc(), gem5::ArmISA::ISA::ISA(), gem5::IsaFake::IsaFake(), gem5::KernelWorkload::KernelWorkload(), sc_gem5::Process::kill(), gem5::linkFunc(), gem5::listenFunc(), gem5::lseekFunc(), gem5::SnoopFilter::maskToPortList(), gem5::PowerState::matchPwrState(), gem5::MemFootprintProbe::MemFootprintProbe(), gem5::MemTraceProbe::MemTraceProbe(), gem5::memory::DRAMInterface::minBankPrep(), gem5::mkdirFunc(), gem5::mknodFunc(), gem5::mmapFunc(), gem5::mremapFunc(), gem5::bloom_filter::MultiBitSel::MultiBitSel(), gem5::munmapFunc(), gem5::MuxingKvmGic::MuxingKvmGic(), gem5::ruby::Network::Network(), gem5::ruby::garnet::NetworkBridge::NetworkBridge(), gem5::ruby::garnet::NetworkLink::NetworkLink(), sc_gem5::newCThreadProcess(), sc_gem5::newDynamicSensitivityEvent(), sc_gem5::newDynamicSensitivityEventAndList(), sc_gem5::newDynamicSensitivityEventOrList(), sc_gem5::newMethodProcess(), sc_gem5::newReset(), sc_gem5::newStaticSensitivityEvent(), sc_gem5::newStaticSensitivityExport(), sc_gem5::newStaticSensitivityFinder(), sc_gem5::newStaticSensitivityInterface(), sc_gem5::newStaticSensitivityPort(), sc_gem5::newThreadProcess(), sc_core::next_trigger(), gem5::HDLcd::PixelPump::nextPixel(), gem5::TrafficGen::nextState(), gem5::NoMaliGpu::NoMaliGpu(), gem5::NonCachingSimpleCPU::NonCachingSimpleCPU(), gem5::NoncoherentCache::NoncoherentCache(), gem5::NoncoherentXBar::NoncoherentXBar(), gem5::RawDiskImage::notifyFork(), gem5::openatFunc(), gem5::TypedAtomicOpFunctor< T >::operator()(), sc_core::sc_sensitive::operator()(), sc_core::sc_in< sc_dt::sc_lv< W > >::operator()(), sc_core::sc_module::operator()(), sc_core::sc_port_b< tlm_nonblocking_put_if< T > >::operator()(), gem5::FALRU::PairHash::operator()(), sc_core::sc_in< bool >::operator()(), sc_core::sc_in< sc_dt::sc_logic >::operator()(), sc_core::sc_sensitive::operator<<(), tlm::operator<<(), sc_core::sc_out_resolved::operator=(), sc_core::sc_inout_resolved::operator=(), sc_core::sc_out_rv< W >::operator=(), sc_core::sc_inout_rv< W >::operator=(), sc_dt::scfx_mant::operator=(), sc_core::sc_inout< sc_dt::sc_lv< W > >::operator=(), sc_core::sc_process_handle::operator=(), gem5::RefCountingPtr< MinorDynInst >::operator=(), sc_core::sc_inout< bool >::operator=(), sc_core::sc_inout< sc_dt::sc_logic >::operator=(), sc_gem5::VcdTraceScope::output(), gem5::MathExpr::parse(), gem5::PciDevice::PciDevice(), gem5::PciLegacyIoBar::PciLegacyIoBar(), gem5::PciMemBar::PciMemBar(), tlm_utils::peq_with_cb_and_phase< MultiSocketSimpleSwitchAT >::peq_with_cb_and_phase(), gem5::bloom_filter::Perfect::Perfect(), gem5::ruby::WriteMask::performAtomic(), sc_gem5::pickParentObj(), gem5::pipe2Func(), gem5::pollFunc(), gem5::PowerModel::PowerModel(), gem5::PowerState::PowerState(), gem5::pread64Func(), gem5::linux::printk(), gem5::Trace::TarmacParserRecord::TarmacParserRecordEvent::process(), gem5::SimPoint::profile(), gem5::ruby::Profiler::Profiler(), gem5::ProtocolTester::ProtocolTester(), gem5::ps2::PS2Keyboard::PS2Keyboard(), gem5::MemBackdoor::ptr(), gem5::pwrite64Func(), gem5::HDLcd::pxlNext(), gem5::RawDiskImage::RawDiskImage(), gem5::PortProxy::readBlob(), gem5::PortProxy::readBlobPhys(), gem5::memory::DRAMSim2::readComplete(), gem5::memory::DRAMsim3::readComplete(), gem5::pseudo_inst::readfile(), gem5::readFunc(), gem5::readlinkFunc(), gem5::readvFunc(), gem5::PixelConverter::readWord(), sc_gem5::Scheduler::ready(), gem5::RealViewOsc::RealViewOsc(), gem5::recvfromFunc(), gem5::NoncoherentXBar::recvFunctional(), gem5::memory::SimpleMemory::recvFunctional(), gem5::memory::CfiMemory::recvFunctional(), gem5::CoherentXBar::recvFunctional(), gem5::CoherentXBar::recvFunctionalSnoop(), gem5::recvmsgFunc(), gem5::BaseXBar::recvRangeChange(), gem5::RedirectPath::RedirectPath(), sc_gem5::Scheduler::reg(), sc_core::sc_report::register_id(), gem5::RegisterManager::RegisterManager(), gem5::BaseMemProbe::regProbeListeners(), sc_gem5::Kernel::regStats(), gem5::PowerState::PowerStateStats::regStats(), sc_core::sc_mempool::release(), gem5::ProbeManager::removeListener(), gem5::renameFunc(), sc_gem5::Process::reset(), gem5::ArmISA::HTMCheckpoint::restore(), sc_gem5::Process::resume(), sc_gem5::Scheduler::resume(), gem5::rmdirFunc(), gem5::ruby::RubyPort::ruby_eviction_callback(), gem5::ruby::RubyPort::RubyPort(), gem5::ruby::RubySystem::RubySystem(), sc_gem5::Scheduler::runNext(), sc_gem5::Scheduler::runNow(), gem5::ArmISA::HTMCheckpoint::save(), gem5::prefetch::SBOOE::SBOOE(), sc_core::sc_event_finder_t< sc_core::sc_signal_inout_if< bool > >::sc_event_finder_t(), sc_core::sc_gen_unique_name(), sc_core::sc_spawn(), sc_core::sc_start(), gem5::Scheduler::Scheduler(), gem5::ScheduleStage::ScheduleStage(), gem5::ScheduleToExecute::ScheduleToExecute(), gem5::ScoreboardCheckToSchedule::ScoreboardCheckToSchedule(), gem5::SectorTags::SectorTags(), gem5::selectFunc(), gem5::BaseRemoteGDB::send(), gem5::sendmsgFunc(), gem5::ComputeUnit::sendRequest(), gem5::sendtoFunc(), gem5::PowerState::set(), tlm_utils::passthrough_target_socket_b< MODULE, BUSWIDTH, TYPES, POL >::process::set_nb_transport_ptr(), sc_core::sc_spawn_options::set_sensitivity(), gem5::SnoopFilter::setCPUSidePorts(), gem5::Packet::setData(), gem5::statistics::Info::setName(), gem5::EtherInt::setPeer(), gem5::ThreadState::setProcessPtr(), gem5::o3::ThreadContext::setProcessPtr(), gem5::CheckerThreadContext< TC >::setProcessPtr(), gem5::SimpleThread::setProcessPtr(), gem5::setsockoptFunc(), gem5::CheckerCPU::setSystem(), gem5::OperandInfo::setVirtToPhysMapping(), gem5::shutdownFunc(), gem5::ruby::SimpleExtLink::SimpleExtLink(), gem5::ruby::SimpleIntLink::SimpleIntLink(), gem5::ruby::SimpleNetwork::SimpleNetwork(), gem5::SimPoint::SimPoint(), gem5::socketFunc(), gem5::socketpairFunc(), sc_gem5::spawnWork(), gem5::SrcClockDomain::SrcClockDomain(), gem5::StackDistProbe::StackDistProbe(), gem5::StackDistProbe::StackDistProbeStats::StackDistProbeStats(), gem5::VirtIO9PDiod::startDiod(), sc_gem5::Kernel::startup(), gem5::BaseKvmCPU::startup(), gem5::BaseKvmCPU::startupThread(), gem5::branch_prediction::StatisticalCorrector::StatisticalCorrector(), gem5::DmaReadFifo::stopFill(), sc_gem5::Kernel::stopWork(), gem5::SubSystem::SubSystem(), sc_gem5::Process::suspend(), sc_gem5::Scheduler::suspend(), gem5::ruby::Switch::Switch(), gem5::symlinkFunc(), sc_gem5::Process::syncResetOff(), sc_gem5::Process::syncResetOn(), gem5::Trace::TarmacParser::TarmacParser(), gem5::Terminal::Terminal(), gem5::Terminal::terminalDump(), gem5::ArmISA::SelfDebug::testBreakPoints(), gem5::ArmISA::SelfDebug::testWatchPoints(), sc_gem5::Process::throw_it(), sc_gem5::throw_it_wrapper(), sc_core::timed_out(), gem5::timeFunc(), gem5::ArmISA::TLB::TLB(), sc_dt::sc_logic::to_bool(), gem5::RiscvISA::TLB::translate(), gem5::truncateFunc(), gem5::Process::tryLoaders(), gem5::TranslatingPortProxy::tryReadBlob(), gem5::PortProxy::tryReadBlob(), gem5::TranslatingPortProxy::tryWriteBlob(), gem5::PortProxy::tryWriteBlob(), gem5::unlinkFunc(), gem5::TLBCoalescer::updatePhysAddresses(), sc_core::sc_port_b< tlm_nonblocking_put_if< T > >::vbind(), gem5::VncServer::VncServer(), vring_init(), sc_core::wait(), gem5::wait4Func(), gem5::Wavefront::Wavefront(), gem5::System::workItemBegin(), gem5::System::workItemEnd(), sc_core::sc_signal_resolved::write(), sc_core::sc_signal_rv< W >::write(), gem5::PortProxy::writeBlob(), gem5::PortProxy::writeBlobPhys(), gem5::memory::DRAMSim2::writeComplete(), gem5::memory::DRAMsim3::writeComplete(), gem5::Packet::writeData(), gem5::writeFunc(), gem5::writevFunc(), gem5::PixelConverter::writeWord(), gem5::CoherentXBar::~CoherentXBar(), gem5::DmaReadFifo::~DmaReadFifo(), and gem5::prefetch::Queued::~Queued().

◆ paco

Bitfield<0> gem5::MipsISA::paco

Definition at line 133 of file dt_constants.hh.

◆ PageBytes

const Addr gem5::MipsISA::PageBytes = 1ULL << PageShift

Definition at line 42 of file page_size.hh.

Referenced by gem5::MipsProcess::argsInit(), RoundPage(), and TruncPage().

◆ PageShift

const Addr gem5::MipsISA::PageShift = 13

Definition at line 41 of file page_size.hh.

◆ pc

Bitfield<4> gem5::MipsISA::pc

Definition at line 243 of file pra_constants.hh.

Referenced by gem5::GenericISA::M5DebugFault::advancePC(), gem5::ArmISA::SoftwareStep::advanceSS(), gem5::Trace::TarmacParser::advanceTraceToStartPc(), gem5::PowerProcess::argsInit(), gem5::ArmProcess::argsInit(), gem5::branch_prediction::TAGEBase::baseUpdate(), gem5::branch_prediction::MPP_TAGE::bindex(), gem5::branch_prediction::TAGE_SC_L_TAGE::bindex(), gem5::Iris::ThreadContext::breakpointHit(), gem5::branch_prediction::TAGE_SC_L_TAGE::calculateIndicesAndTags(), gem5::prefetch::DeltaCorrelatingPredictionTables::calculatePrefetch(), gem5::prefetch::IrregularStreamBuffer::calculatePrefetch(), gem5::prefetch::Stride::calculatePrefetch(), gem5::prefetch::PIF::calculatePrefetch(), gem5::prefetch::IndirectMemory::calculatePrefetch(), gem5::prefetch::STeMS::calculatePrefetch(), gem5::Trace::SparcNativeTrace::check(), gem5::Check::Check(), gem5::BaseSimpleCPU::checkPcEventQueue(), gem5::ArmISA::Decoder::decode(), gem5::PowerISA::PCDependentDisassembly::disassemble(), gem5::StaticInst::disassemble(), gem5::SparcISA::doNormalFault(), gem5::SparcISA::doREDFault(), gem5::PCEventQueue::doService(), gem5::Trace::IntelTraceRecord::dump(), gem5::FunctionProfile::dump(), gem5::ArmKvmCPU::dumpKvmStateCore(), gem5::PCEventQueue::equal_range(), gem5::DecoderFaultInst::execute(), gem5::VegaISA::Inst_SOP1__S_GETPC_B64::execute(), gem5::Gcn3ISA::Inst_SOP1__S_GETPC_B64::execute(), gem5::Gcn3ISA::Inst_SOP1__S_SWAPPC_B64::execute(), gem5::VegaISA::Inst_SOP1__S_SWAPPC_B64::execute(), gem5::Gcn3ISA::Inst_SOPP__S_BRANCH::execute(), gem5::VegaISA::Inst_SOPP__S_BRANCH::execute(), gem5::Gcn3ISA::Inst_SOPP__S_CBRANCH_SCC0::execute(), gem5::VegaISA::Inst_SOPP__S_CBRANCH_SCC0::execute(), gem5::VegaISA::Inst_SOPP__S_CBRANCH_SCC1::execute(), gem5::Gcn3ISA::Inst_SOPP__S_CBRANCH_SCC1::execute(), gem5::VegaISA::Inst_SOPP__S_CBRANCH_VCCZ::execute(), gem5::Gcn3ISA::Inst_SOPP__S_CBRANCH_VCCZ::execute(), gem5::Gcn3ISA::Inst_SOPP__S_CBRANCH_VCCNZ::execute(), gem5::VegaISA::Inst_SOPP__S_CBRANCH_VCCNZ::execute(), gem5::VegaISA::Inst_SOPP__S_CBRANCH_EXECZ::execute(), gem5::Gcn3ISA::Inst_SOPP__S_CBRANCH_EXECZ::execute(), gem5::VegaISA::Inst_SOPP__S_CBRANCH_EXECNZ::execute(), gem5::Gcn3ISA::Inst_SOPP__S_CBRANCH_EXECNZ::execute(), gem5::prefetch::StridePrefetcherHashedSetAssociative::extractSet(), gem5::SparcISA::IntOp::generateDisassembly(), gem5::ArmISA::BranchImm::generateDisassembly(), gem5::ArmISA::BranchImm64::generateDisassembly(), gem5::SparcISA::BranchDisp::generateDisassembly(), gem5::SparcISA::IntOpImm::generateDisassembly(), gem5::ArmISA::BranchImmCond64::generateDisassembly(), gem5::PowerISA::BranchOp::generateDisassembly(), gem5::PowerISA::BranchDispCondOp::generateDisassembly(), gem5::ArmISA::BranchImmReg64::generateDisassembly(), gem5::ArmISA::BranchImmImmReg64::generateDisassembly(), gem5::ArmISA::MemoryLiteral64::generateDisassembly(), gem5::branch_prediction::TAGE_SC_L_TAGE::getBimodePred(), gem5::SparcISA::FsWorkload::getEntry(), gem5::branch_prediction::StatisticalCorrector::SCThreadHistory::getEntry(), gem5::branch_prediction::MultiperspectivePerceptron::LOCAL::getHash(), gem5::Trace::IntelTrace::getInstRecord(), gem5::Trace::ExeTracer::getInstRecord(), gem5::Trace::NativeTrace::getInstRecord(), gem5::Trace::InstPBTrace::getInstRecord(), gem5::Trace::TarmacTracer::getInstRecord(), gem5::Trace::TarmacParser::getInstRecord(), gem5::branch_prediction::StatisticalCorrector::SCThreadHistory::getLocalHistory(), gem5::branch_prediction::LoopPredictor::getLoop(), gem5::Iris::ThreadContext::getOrAllocBp(), gem5::branch_prediction::TAGE_SC_L_TAGE::gindex(), gem5::branch_prediction::TAGEBase::gindex(), gem5::branch_prediction::MPP_StatisticalCorrector_8KB::gPredictions(), gem5::branch_prediction::MPP_StatisticalCorrector_64KB::gPredictions(), gem5::branch_prediction::TAGE_SC_L_TAGE_8KB::gtag(), gem5::branch_prediction::TAGE_SC_L_TAGE_64KB::gtag(), gem5::branch_prediction::TAGEBase::gtag(), gem5::branch_prediction::MPP_StatisticalCorrector_8KB::gUpdates(), gem5::branch_prediction::MPP_StatisticalCorrector_64KB::gUpdates(), gem5::branch_prediction::TAGE_SC_L_8KB_StatisticalCorrector::gUpdates(), gem5::branch_prediction::TAGE_SC_L_64KB_StatisticalCorrector::gUpdates(), haltThread(), gem5::SparcISA::SEWorkload::handleTrap(), gem5::StaticInst::hasBranchTarget(), gem5::branch_prediction::MultiperspectivePerceptron::RECENCYPOS::hash(), gem5::TimingSimpleCPU::htmSendAbortSignal(), gem5::branch_prediction::MultiperspectivePerceptron::LocalHistories::index(), gem5::TimingSimpleCPU::initiateHtmCmd(), gem5::TimingSimpleCPU::initiateMemAMO(), gem5::TimingSimpleCPU::initiateMemRead(), gem5::PowerProcess::initState(), gem5::RiscvProcess32::initState(), gem5::prefetch::PIF::CompactorEntry::inSameSpatialRegion(), gem5::branch_prediction::MultiperspectivePerceptron::ThreadData::insertRecency(), gem5::Iris::ThreadContext::installBp(), gem5::SparcISA::SparcFaultBase::invoke(), gem5::SESyscallFault::invoke(), gem5::SparcISA::PowerOnReset::invoke(), gem5::ArmISA::ArmFault::invoke(), gem5::SparcISA::TrapInstruction::invoke(), gem5::ArmISA::Reset::invoke(), gem5::ArmISA::SupervisorCall::invoke(), gem5::ArmISA::ArmFault::invoke64(), gem5::ruby::VIPERCoalescer::issueRequest(), gem5::ruby::Sequencer::issueRequest(), gem5::branch_prediction::LoopPredictor::lindex(), gem5::branch_prediction::LoopPredictor::loopUpdate(), gem5::PowerISA::Decoder::moreBytes(), gem5::ArmISA::Decoder::moreBytes(), gem5::prefetch::PIF::PrefetchListenerPC::notify(), gem5::prefetch::PIF::notifyRetiredInst(), gem5::PCEventQueue::MapCompare::operator()(), gem5::GenericISA::operator<<(), gem5::branch_prediction::MultiperspectivePerceptron::LocalHistories::operator[](), gem5::FetchUnit::FetchBufDesc::pcBuffered(), gem5::Iris::ThreadContext::pcState(), gem5::BaseSimpleCPU::postExecute(), gem5::branch_prediction::BPredUnit::predict(), gem5::Trace::TarmacParserRecord::printMismatchHeader(), gem5::BaseCPU::probeInstCommit(), gem5::Trace::TarmacParserRecord::TarmacParserRecordEvent::process(), gem5::ArmISA::ISA::readMiscReg(), gem5::Request::Request(), gem5::FunctionProfile::sample(), gem5::TraceCPU::FixedRetryGen::send(), gem5::PCEventQueue::service(), gem5::ArmISA::ArmStaticInst::setAIWNextPC(), gem5::MipsISA::MipsFaultBase::setExceptionState(), gem5::ArmISA::ArmStaticInst::setIWNextPC(), gem5::ArmISA::ISA::setMiscReg(), gem5::ArmISA::ArmStaticInst::setNextPC(), gem5::Request::setPC(), gem5::PowerISA::RemoteGDB::PowerGdbRegCache::setRegs(), gem5::PowerISA::RemoteGDB::Power64GdbRegCache::setRegs(), gem5::o3::LSQ::LSQRequest::setVirt(), gem5::Request::setVirt(), gem5::o3::IEW::squashDueToBranch(), gem5::o3::CPU::switchRenameMode(), gem5::branch_prediction::TAGEBase::tagePredict(), gem5::ArmISA::BrkPoint::test(), gem5::ArmISA::BrkPoint::testAddrMatch(), gem5::ArmISA::BrkPoint::testAddrMissMatch(), gem5::ArmISA::SelfDebug::testBreakPoints(), gem5::BaseCPU::traceFunctions(), gem5::BaseCPU::traceFunctionsInternal(), gem5::Trace::ExeTracerRecord::traceInst(), gem5::Trace::InstPBTrace::traceInst(), gem5::branch_prediction::MultiperspectivePerceptronTAGE::uncondBranch(), gem5::branch_prediction::MultiperspectivePerceptron::uncondBranch(), gem5::branch_prediction::BPredUnit::update(), gem5::branch_prediction::MultiperspectivePerceptron::LocalHistories::update(), gem5::branch_prediction::MultiperspectivePerceptronTAGE::updateHistories(), gem5::ArmKvmCPU::updateTCStateCore(), gem5::ArmV8KvmCPU::updateThreadContext(), and gem5::TimingSimpleCPU::writeMem().

◆ pci

Bitfield<26> gem5::MipsISA::pci

Definition at line 182 of file pra_constants.hh.

◆ pcp

Bitfield<27> gem5::MipsISA::pcp

Definition at line 52 of file mt_constants.hh.

◆ pfn

Bitfield<29, 6> gem5::MipsISA::pfn

Definition at line 58 of file pra_constants.hh.

Referenced by gem5::ArmISA::TLB::insert().

◆ procId

Bitfield<15, 8> gem5::MipsISA::procId

Definition at line 206 of file pra_constants.hh.

Referenced by gem5::MipsISA::ISA::configCP().

◆ pss

Bitfield<9, 6> gem5::MipsISA::pss

Definition at line 161 of file pra_constants.hh.

◆ pState

Bitfield<7, 6> gem5::MipsISA::pState

Definition at line 322 of file pra_constants.hh.

◆ pTagLo

gem5::MipsISA::pTagLo

Definition at line 321 of file pra_constants.hh.

◆ ptc

Bitfield<7, 0> gem5::MipsISA::ptc

◆ pteBase

gem5::MipsISA::pteBase

Definition at line 66 of file pra_constants.hh.

◆ ptlbe

Bitfield<25, 16> gem5::MipsISA::ptlbe

Definition at line 53 of file mt_constants.hh.

◆ pvpe

Bitfield<13, 10> gem5::MipsISA::pvpe

Definition at line 55 of file mt_constants.hh.

◆ px

Bitfield<23> gem5::MipsISA::px

◆ r

Bitfield< 1 > gem5::MipsISA::r

Definition at line 98 of file pra_constants.hh.

Referenced by gem5::__to_number(), sc_gem5::ScSignalBaseBinary::_signalReset(), gem5::ThermalModel::addReference(), gem5::ThermalModel::addResistor(), gem5::AddrRange::AddrRange(), gem5::memory::DRAMInterface::allRanksDrained(), gem5::ruby::Set::AND(), gem5::branch_prediction::BPredUnit::BPredUnit(), gem5::o3::LSQ::SplitDataRequest::buildPackets(), sc_dt::sc_uint_base::check_range(), sc_dt::sc_int_base::check_range(), sc_dt::sc_unsigned::check_range(), sc_dt::sc_signed::check_range(), gem5::AddrRangeMap< gem5::MemBackdoor, 1 >::contains(), gem5::ArmISA::decodeMrsMsrBankedIntRegIndex(), gem5::ArmISA::decodeMrsMsrBankedReg(), gem5::ruby::DirectoryMemory::DirectoryMemory(), gem5::PowerISA::IntArithOp::divide(), gem5::loader::doGzipLoad(), gem5::memory::DRAMInterface::drainRanks(), sc_gem5::Port::finalize(), gem5::SparcISA::TlbMap::find(), gem5::AddrRangeMap< gem5::MemBackdoor, 1 >::find(), gem5::statistics::Formula::Formula(), gem5::ArmISA::fp64_sqrt(), gem5::AMDGPUDevice::getAddrRanges(), gem5::ruby::RubyPort::PioResponsePort::getAddrRanges(), sc_gem5::Gem5ToTlmBridge< BITWIDTH >::getBackdoor(), gem5::memory::PhysicalMemory::getConfAddrRanges(), gem5::ruby::Sequencer::getHitTypeMachLatencyHist(), gem5::ruby::Sequencer::getMissTypeMachLatencyHist(), gem5::ruby::GPUCoalescer::getMissTypeMachLatencyHist(), gem5::MipsISA::RemoteGDB::MipsGdbRegCache::getRegs(), gem5::PowerISA::RemoteGDB::PowerGdbRegCache::getRegs(), gem5::ArmISA::RemoteGDB::AArch32GdbRegCache::getRegs(), gem5::X86ISA::RemoteGDB::X86GdbRegCache::getRegs(), gem5::PowerISA::RemoteGDB::Power64GdbRegCache::getRegs(), gem5::RiscvISA::RemoteGDB::RiscvGdbRegCache::getRegs(), gem5::X86ISA::RemoteGDB::AMD64GdbRegCache::getRegs(), gem5::o3::LSQ::SplitDataRequest::handleLocalAccess(), gem5::o3::LSQ::SplitDataRequest::initiateTranslation(), gem5::BaseCache::inRange(), gem5::SparcISA::TlbMap::insert(), gem5::AddrRangeMap< gem5::MemBackdoor, 1 >::insert(), gem5::SparcISA::TlbMap::intersect(), gem5::ruby::Set::intersectionIsEmpty(), gem5::VMA::intersects(), gem5::AddrRangeMap< gem5::MemBackdoor, 1 >::intersects(), gem5::AddrRange::intersects(), sc_dt::sc_uint_base::invalid_range(), sc_dt::sc_int_base::invalid_range(), sc_dt::sc_unsigned::invalid_range(), sc_dt::sc_signed::invalid_range(), sc_gem5::Gem5ToTlmBridge< BITWIDTH >::invalidate_direct_mem_ptr(), sc_dt::scfx_ieee_float::is_inf(), sc_dt::scfx_ieee_float::is_nan(), QTIsaac< ALPHA >::isaac(), gem5::memory::DRAMInterface::isBusy(), gem5::o3::LSQ::SplitDataRequest::isCacheBlockHit(), gem5::ruby::DirectoryMemory::isPresent(), gem5::VMA::isStrictSuperset(), gem5::VMA::isSubset(), gem5::AddrRange::isSubset(), gem5::ruby::Set::isSuperset(), gem5::ruby::lookupTraceForAddress(), sc_gem5::ScMainFiber::main(), gem5::ruby::DirectoryMemory::mapAddressToLocalIdx(), gem5::VMA::mergesWith(), gem5::AddrRange::mergesWith(), gem5::operator!=(), gem5::AddrRange::operator!=(), gem5::PCEventQueue::MapCompare::operator()(), gem5::statistics::operator*(), gem5::operator+(), gem5::statistics::operator+(), gem5::statistics::Formula::operator+=(), gem5::operator-(), gem5::statistics::operator-(), gem5::statistics::operator/(), gem5::statistics::Formula::operator/=(), gem5::operator<(), gem5::AddrRange::operator<(), gem5::operator<=(), sc_core::sc_report::operator=(), sc_core::sc_signal_resolved::operator=(), sc_core::sc_signal_rv< W >::operator=(), gem5::RefCountingPtr< MinorDynInst >::operator=(), gem5::statistics::Formula::operator=(), gem5::operator==(), gem5::AddrRange::operator==(), gem5::ruby::operator>(), gem5::operator>(), gem5::operator>=(), gem5::ruby::Set::OR(), gem5::MathExpr::parse(), gem5::ruby::PersistentTable::persistentRequestLock(), gem5::memory::PhysicalMemory::PhysicalMemory(), QTIsaac< ALPHA >::randinit(), gem5::MemBackdoor::range(), gem5::MemBackdoor::readable(), gem5::ArmISA::recipEstimate(), gem5::ArmISA::recipSqrtEstimate(), gem5::ruby::RubyPort::PioRequestPort::recvRangeChange(), gem5::BaseXBar::recvRangeChange(), gem5::RefCountingPtr< MinorDynInst >::RefCountingPtr(), sc_gem5::reportifyException(), gem5::ArmSemihosting::retOK(), QTIsaac< ALPHA >::rngstep(), SC_MODULE(), gem5::Cache::sendMSHRQueuePacket(), sc_dt::sc_concref_r< X, Y >::set_cword(), sc_dt::sc_concref_r< X, Y >::set_word(), gem5::ArmISA::ISA::setMiscReg(), gem5::MipsISA::RemoteGDB::MipsGdbRegCache::setRegs(), gem5::PowerISA::RemoteGDB::PowerGdbRegCache::setRegs(), gem5::ArmISA::RemoteGDB::AArch32GdbRegCache::setRegs(), gem5::X86ISA::RemoteGDB::X86GdbRegCache::setRegs(), gem5::PowerISA::RemoteGDB::Power64GdbRegCache::setRegs(), gem5::ArmISA::RemoteGDB::AArch64GdbRegCache::setRegs(), gem5::RiscvISA::RemoteGDB::RiscvGdbRegCache::setRegs(), gem5::X86ISA::RemoteGDB::AMD64GdbRegCache::setRegs(), gem5::o3::LSQUnit::LSQEntry::setRequest(), gem5::memory::DRAMInterface::startup(), gem5::memory::DRAMInterface::suspend(), gem5::o3::LSQ::LSQRequest::taskId(), TEST(), TEST_F(), RegisterBankTest::TestReg::TestReg(), gem5::LinearSystem::toStr(), sc_dt::vec_div_small(), gem5::VMA::VMA(), and gem5::o3::LSQ::LSQRequest::~LSQRequest().

◆ r0

Bitfield<3> gem5::MipsISA::r0

Definition at line 139 of file pra_constants.hh.

Referenced by gem5::ArmISA::lsl128(), and gem5::ArmISA::lsr128().

◆ random

gem5::MipsISA::random

◆ re

Bitfield<25> gem5::MipsISA::re

Definition at line 114 of file pra_constants.hh.

◆ ReturnValueReg

const int gem5::MipsISA::ReturnValueReg = 2

◆ rev

Bitfield<7, 0> gem5::MipsISA::rev

Definition at line 207 of file pra_constants.hh.

◆ ripl

Bitfield<15, 10> gem5::MipsISA::ripl

Definition at line 187 of file pra_constants.hh.

◆ rnst

Bitfield<24, 23> gem5::MipsISA::rnst

Definition at line 87 of file mt_constants.hh.

◆ s

Bitfield< 2 > gem5::MipsISA::s

Definition at line 82 of file dt_constants.hh.

◆ sa

Bitfield<3, 0> gem5::MipsISA::sa

Definition at line 259 of file pra_constants.hh.

Referenced by dspExtr(), dspMulq(), dspPrece(), dspPrecrSra(), dspShll(), dspShra(), and dspShrl().

◆ scs

Bitfield<18> gem5::MipsISA::scs

Definition at line 70 of file mt_constants.hh.

◆ SIMD_LOG2N

const uint32_t gem5::MipsISA::SIMD_LOG2N[SIMD_NUM_FMTS] = { 6, 5, 4, 3 }

Definition at line 105 of file dsp.hh.

Referenced by dspShll(), dspShra(), and dspShrl().

◆ SIMD_MAX_VALS

const uint32_t gem5::MipsISA::SIMD_MAX_VALS = 4

◆ SIMD_NBITS

const uint32_t gem5::MipsISA::SIMD_NBITS[SIMD_NUM_FMTS] = { 64, 32, 16, 8 }

Definition at line 103 of file dsp.hh.

Referenced by dspMulq(), dspPrece(), dspPrecrqu(), signExtend(), simdPack(), and simdUnpack().

◆ SIMD_NVALS

const uint32_t gem5::MipsISA::SIMD_NVALS[SIMD_NUM_FMTS] = { 1, 1, 2, 4 }

◆ sl

Bitfield<7, 4> gem5::MipsISA::sl

Definition at line 258 of file pra_constants.hh.

◆ sm

Bitfield<1> gem5::MipsISA::sm

Definition at line 273 of file pra_constants.hh.

◆ sp

Bitfield<4> gem5::MipsISA::sp

Definition at line 270 of file pra_constants.hh.

◆ sr

Bitfield<20> gem5::MipsISA::sr

Definition at line 119 of file pra_constants.hh.

Referenced by gem5::DistIface::SyncEvent::process().

◆ ss

Bitfield<11, 8> gem5::MipsISA::ss

Definition at line 257 of file pra_constants.hh.

◆ sst

Bitfield<8> gem5::MipsISA::sst

Definition at line 63 of file dt_constants.hh.

◆ ssv0

Bitfield<3, 0> gem5::MipsISA::ssv0

Definition at line 174 of file pra_constants.hh.

◆ ssv1

Bitfield<7, 4> gem5::MipsISA::ssv1

Definition at line 173 of file pra_constants.hh.

◆ ssv2

Bitfield<11, 8> gem5::MipsISA::ssv2

Definition at line 172 of file pra_constants.hh.

◆ ssv3

Bitfield<15, 12> gem5::MipsISA::ssv3

Definition at line 171 of file pra_constants.hh.

◆ ssv4

Bitfield<19, 16> gem5::MipsISA::ssv4

Definition at line 170 of file pra_constants.hh.

◆ ssv5

Bitfield<23, 20> gem5::MipsISA::ssv5

Definition at line 169 of file pra_constants.hh.

◆ ssv6

Bitfield<27, 24> gem5::MipsISA::ssv6

Definition at line 168 of file pra_constants.hh.

◆ ssv7

gem5::MipsISA::ssv7

Definition at line 167 of file pra_constants.hh.

◆ StackPointerReg

const int gem5::MipsISA::StackPointerReg = 29

Definition at line 70 of file int.hh.

◆ stlb

Bitfield<2> gem5::MipsISA::stlb

Definition at line 43 of file mt_constants.hh.

◆ su

Bitfield<15, 12> gem5::MipsISA::su

Definition at line 256 of file pra_constants.hh.

◆ sx

Bitfield<6> gem5::MipsISA::sx

Definition at line 135 of file pra_constants.hh.

◆ syp

Bitfield<2, 0> gem5::MipsISA::syp

Definition at line 102 of file dt_constants.hh.

◆ SyscallPseudoReturnReg

const int gem5::MipsISA::SyscallPseudoReturnReg = 3

◆ SyscallSuccessReg

const int gem5::MipsISA::SyscallSuccessReg = 7

◆ ta

Bitfield<19, 16> gem5::MipsISA::ta

Definition at line 255 of file pra_constants.hh.

◆ targTC

Bitfield<7, 0> gem5::MipsISA::targTC

Definition at line 63 of file mt_constants.hh.

◆ tb

Bitfield<27> gem5::MipsISA::tb

Definition at line 77 of file dt_constants.hh.

Referenced by SC_MODULE().

◆ tbe

Bitfield<17> gem5::MipsISA::tbe

Definition at line 80 of file mt_constants.hh.

Referenced by gem5::SparcISA::TLB::translateFunctional().

◆ tbi

Bitfield<4> gem5::MipsISA::tbi

Definition at line 100 of file dt_constants.hh.

◆ tbu

Bitfield<3> gem5::MipsISA::tbu

Definition at line 101 of file dt_constants.hh.

◆ tca

Bitfield<15> gem5::MipsISA::tca

Definition at line 54 of file mt_constants.hh.

◆ tcnum

Bitfield<19, 12> gem5::MipsISA::tcnum

Definition at line 97 of file dt_constants.hh.

◆ tcs

Bitfield<19> gem5::MipsISA::tcs

Definition at line 69 of file mt_constants.hh.

◆ tcu

gem5::MipsISA::tcu

Definition at line 85 of file mt_constants.hh.

◆ tcv

Bitfield<20> gem5::MipsISA::tcv

Definition at line 96 of file dt_constants.hh.

◆ tds

Bitfield<21> gem5::MipsISA::tds

Definition at line 88 of file mt_constants.hh.

◆ te

Bitfield<15> gem5::MipsISA::te

Definition at line 62 of file mt_constants.hh.

◆ tfcr

Bitfield<3> gem5::MipsISA::tfcr

Definition at line 87 of file dt_constants.hh.

◆ ti

Bitfield<30> gem5::MipsISA::ti

◆ tim

Bitfield<1> gem5::MipsISA::tim

Definition at line 89 of file dt_constants.hh.

◆ tksu

Bitfield<12, 11> gem5::MipsISA::tksu

Definition at line 93 of file mt_constants.hh.

◆ tl

Bitfield< 0 > gem5::MipsISA::tl

◆ tlbs

Bitfield<29> gem5::MipsISA::tlbs

Definition at line 50 of file mt_constants.hh.

◆ tlsm

Bitfield<2> gem5::MipsISA::tlsm

Definition at line 88 of file dt_constants.hh.

◆ tmx

Bitfield<27> gem5::MipsISA::tmx

Definition at line 86 of file mt_constants.hh.

◆ ts

Bitfield< 27, 24 > gem5::MipsISA::ts

Definition at line 118 of file pra_constants.hh.

◆ tu

Bitfield<30, 28> gem5::MipsISA::tu

◆ tup

Bitfield<1> gem5::MipsISA::tup

Definition at line 132 of file dt_constants.hh.

◆ u

Bitfield< 3 > gem5::MipsISA::u

Definition at line 83 of file dt_constants.hh.

◆ um

Bitfield<4> gem5::MipsISA::um

Definition at line 138 of file pra_constants.hh.

◆ ut

Bitfield<30> gem5::MipsISA::ut

Definition at line 76 of file dt_constants.hh.

◆ ux

Bitfield<5> gem5::MipsISA::ux

Definition at line 136 of file pra_constants.hh.

Referenced by gem5::floorLog2().

◆ v

Bitfield<1> gem5::MipsISA::v

Definition at line 61 of file pra_constants.hh.

◆ vaddr

gem5::MipsISA::vaddr

Definition at line 278 of file pra_constants.hh.

Referenced by gem5::Process::allocateMem(), gem5::Gcn3ISA::Inst_SMEM::calcAddr(), gem5::VegaISA::Inst_SMEM::calcAddr(), gem5::VegaISA::Inst_MUBUF::calcAddr(), gem5::Gcn3ISA::Inst_MUBUF::calcAddr(), gem5::RiscvISA::TLB::checkPermissions(), gem5::ArmISA::TLB::checkPermissions(), gem5::ArmISA::TLB::checkPermissions64(), gem5::Process::clone(), gem5::PMP::createAddrfault(), gem5::RiscvISA::TLB::createPagefault(), gem5::BaseMMU::demapPage(), gem5::SimpleThread::demapPage(), gem5::o3::CPU::demapPage(), gem5::minor::ExecContext::demapPage(), gem5::o3::DynInst::demapPage(), gem5::CheckerCPU::demapPage(), gem5::SimpleExecContext::demapPage(), gem5::RiscvISA::TLB::doTranslate(), gem5::o3::Fetch::fetchCacheLine(), gem5::FetchUnit::FetchBufDesc::fetchDone(), gem5::Process::fixupFault(), gem5::MemState::fixupFault(), gem5::ArmISA::TLB::getTE(), gem5::X86ISA::GpuTLB::handleFuncTranslationReturn(), gem5::X86ISA::GpuTLB::handleTranslationReturn(), gem5::Gcn3ISA::Inst_FLAT::initAtomicAccess(), gem5::FetchUnit::initiateFetch(), gem5::Gcn3ISA::Inst_DS::initMemRead(), gem5::VegaISA::Inst_DS::initMemRead(), gem5::Gcn3ISA::Inst_FLAT::initMemRead(), gem5::initMemReqHelper(), gem5::initMemReqScalarHelper(), gem5::VegaISA::Inst_DS::initMemWrite(), gem5::Gcn3ISA::Inst_DS::initMemWrite(), gem5::Gcn3ISA::Inst_FLAT::initMemWrite(), gem5::ArmISA::BrkPoint::isActive(), gem5::FetchUnit::FetchBufDesc::isReserved(), gem5::EmulationPageTable::isUnmapped(), gem5::EmulationPageTable::lookup(), gem5::EmulationPageTable::map(), gem5::Process::map(), gem5::MultiLevelPageTable< EntryTypes >::map(), gem5::PMP::pmpCheck(), gem5::X86ISA::LongModePTE::read(), gem5::BaseRemoteGDB::read(), gem5::ArmISA::TableWalker::readDataUntimed(), gem5::pseudo_inst::readfile(), gem5::X86ISA::GpuTLB::CpuSidePort::recvFunctional(), gem5::ComputeUnit::DTLBPort::recvReqRetry(), gem5::ComputeUnit::ITLBPort::recvReqRetry(), gem5::ComputeUnit::DTLBPort::recvTimingResp(), gem5::EmulationPageTable::remap(), gem5::MultiLevelPageTable< EntryTypes >::remap(), gem5::RiscvISA::TLB::remove(), gem5::Process::replicatePage(), gem5::Request::Request(), gem5::FetchUnit::FetchBufDesc::reserveBuf(), gem5::FetchUnit::FetchBufDesc::reservedBuf(), gem5::ComputeUnit::sendRequest(), gem5::X86ISA::Walker::WalkerState::setupWalk(), gem5::o3::LSQ::LSQRequest::setVirt(), gem5::Request::setVirt(), gem5::ArmISA::TableWalker::Stage2Walk::setVirt(), gem5::X86ISA::Walker::WalkerState::stepWalk(), gem5::ArmISA::SelfDebug::testBreakPoints(), gem5::ArmISA::BrkPoint::testLinkedBk(), gem5::ArmISA::SelfDebug::testWatchPoints(), gem5::SparcISA::TlbEntry::TlbEntry(), gem5::X86ISA::GpuTLB::tlbLookup(), gem5::X86ISA::TLB::translate(), gem5::EmulationPageTable::translate(), gem5::X86ISA::GpuTLB::translate(), gem5::SparcISA::PageTableEntry::translate(), gem5::fastmodel::CortexR52TC::translateAddress(), gem5::fastmodel::CortexA76TC::translateAddress(), gem5::Iris::ThreadContext::translateAddress(), gem5::ArmISA::TLB::translateFs(), gem5::Iris::TLB::translateFunctional(), gem5::ArmISA::MMU::translateFunctional(), gem5::X86ISA::TLB::translateFunctional(), gem5::SparcISA::TLB::translateFunctional(), gem5::SparcISA::TLB::translateInst(), gem5::X86ISA::TLB::translateInt(), gem5::X86ISA::GpuTLB::translateInt(), gem5::ArmISA::TLB::translateMmuOff(), gem5::ArmISA::TLB::translateMmuOn(), gem5::GPUCommandProcessor::translateOrDie(), gem5::HSAPacketProcessor::translateOrDie(), gem5::ArmISA::TLB::translateSe(), gem5::RiscvISA::TLB::translateWithTLB(), gem5::X86ISA::GpuTLB::translationReturn(), gem5::ArmISA::SelfDebug::triggerException(), gem5::ArmISA::SelfDebug::triggerWatchpointException(), gem5::EmulationPageTable::unmap(), gem5::MultiLevelPageTable< EntryTypes >::unmap(), gem5::EmulationPageTable::unserialize(), gem5::BaseRemoteGDB::write(), and gem5::pseudo_inst::writefile().

◆ validModes

Bitfield<6, 5> gem5::MipsISA::validModes

Definition at line 99 of file dt_constants.hh.

◆ veic

Bitfield<6> gem5::MipsISA::veic

Definition at line 268 of file pra_constants.hh.

◆ vi

Bitfield<3> gem5::MipsISA::vi

Definition at line 228 of file pra_constants.hh.

◆ vint

Bitfield<5> gem5::MipsISA::vint

Definition at line 269 of file pra_constants.hh.

◆ vpa

Bitfield<0> gem5::MipsISA::vpa

Definition at line 74 of file mt_constants.hh.

◆ vpc

Bitfield<1> gem5::MipsISA::vpc

Definition at line 44 of file mt_constants.hh.

◆ vpn2

Bitfield<39, 13> gem5::MipsISA::vpn2

Definition at line 100 of file pra_constants.hh.

◆ vpn2x

Bitfield<12, 11> gem5::MipsISA::vpn2x

Definition at line 101 of file pra_constants.hh.

◆ vs

Bitfield<9, 5> gem5::MipsISA::vs

Definition at line 149 of file pra_constants.hh.

◆ w

Bitfield< 30 > gem5::MipsISA::w

Definition at line 281 of file pra_constants.hh.

Referenced by gem5::StaticRegisterManagerPolicy::allocateRegisters(), gem5::RegisterManager::allocateRegisters(), sc_dt::sc_bitref< X >::b_not(), sc_dt::sc_proxy< sc_bv_base >::check_bounds(), gem5::ComputeUnit::deleteFromPipeMap(), gem5::ScheduleStage::deleteFromSch(), gem5::ComputeUnit::dispWorkgroup(), gem5::LocalMemPipeline::exec(), gem5::ScalarMemPipeline::exec(), gem5::GlobalMemPipeline::exec(), gem5::ComputeUnit::fillKernelState(), gem5::StaticRegisterManagerPolicy::freeRegisters(), gem5::RegisterManager::freeRegisters(), sc_dt::sc_subref_r< X >::get_cword(), sc_dt::sc_subref_r< X >::get_word(), gem5::PowerModel::getDynamicPower(), gem5::branch_prediction::MultiperspectivePerceptron::GHISTPATH::getHash(), gem5::branch_prediction::MultiperspectivePerceptron::SGHISTPATH::getHash(), gem5::PowerModel::getStaticPower(), gem5::branch_prediction::StatisticalCorrector::gPredict(), gem5::branch_prediction::StatisticalCorrector::gUpdate(), gem5::branch_prediction::StatisticalCorrector::initGEHLTable(), gem5::ComputeUnit::insertInPipeMap(), sc_dt::sc_bv_base::is_01(), gem5::StaticRegisterManagerPolicy::mapSgpr(), gem5::RegisterManager::mapSgpr(), gem5::StaticRegisterManagerPolicy::mapVgpr(), gem5::RegisterManager::mapVgpr(), gem5::ScoreboardCheckStage::mapWaveToExeUnit(), gem5::ComputeUnit::mapWaveToScalarAlu(), gem5::ComputeUnit::mapWaveToScalarAluGlobalIdx(), gem5::VectorRegisterFile::operandsReady(), gem5::ScalarRegisterFile::operandsReady(), sc_dt::sc_lv_base::operator=(), sc_gem5::VcdTraceScope::output(), sc_gem5::VcdTraceValFinite< T >::output(), sc_gem5::VcdTraceValFxnum< T >::output(), sc_gem5::VcdTraceValInt< T >::output(), gem5::ScoreboardCheckStage::ready(), gem5::ComputeUnit::DataPort::recvTimingResp(), gem5::ComputeUnit::DTLBPort::recvTimingResp(), gem5::ComputeUnit::ScalarDTLBPort::recvTimingResp(), gem5::FutexMap::requeue(), SC_MODULE(), sc_dt::sc_proxy< sc_bv_base >::scan(), sc_gem5::ScEvent::schedule(), sc_dt::sc_bitref< X >::set_bit(), sc_dt::sc_concref_r< X, Y >::set_cword(), sc_dt::sc_concref_r< X, Y >::set_word(), gem5::Packet::setUintX(), gem5::ComputeUnit::startWavefront(), sc_dt::sc_proxy< sc_bv_base >::to_uint64(), sc_dt::vec_mul_small_on(), sc_dt::vec_sub_on2(), gem5::VectorRegisterFile::waveExecuteInst(), sc_gem5::ScEvent::when(), gem5::MemBackdoor::writeable(), and gem5::VGic::writeVCpu().

◆ wired

gem5::MipsISA::wired

Definition at line 89 of file pra_constants.hh.

◆ wp

Bitfield<22> gem5::MipsISA::wp

Definition at line 185 of file pra_constants.hh.

◆ wr

Bitfield<3> gem5::MipsISA::wr

Definition at line 244 of file pra_constants.hh.

Referenced by SC_MODULE().

◆ xtc

Bitfield<28, 21> gem5::MipsISA::xtc

Definition at line 68 of file mt_constants.hh.

gem5::MipsISA::FIXED_W_UMIN
const uint64_t FIXED_W_UMIN
Definition: dsp.hh:128
gem5::MipsISA::FIXED_W_SMAX
const uint64_t FIXED_W_SMAX
Definition: dsp.hh:110
gem5::MipsISA::FIXED_H_SMAX
const uint64_t FIXED_H_SMAX
Definition: dsp.hh:111
gem5::MipsISA::FIXED_L_SMIN
const uint64_t FIXED_L_SMIN
Definition: dsp.hh:123
gem5::MipsISA::FIXED_W_SMIN
const uint64_t FIXED_W_SMIN
Definition: dsp.hh:124
gem5::MipsISA::FIXED_W_UMAX
const uint64_t FIXED_W_UMAX
Definition: dsp.hh:114
gem5::MipsISA::FIXED_L_SMAX
const uint64_t FIXED_L_SMAX
Definition: dsp.hh:109
gem5::MipsISA::FIXED_L_UMAX
const uint64_t FIXED_L_UMAX
Definition: dsp.hh:113
gem5::MipsISA::FIXED_L_UMIN
const uint64_t FIXED_L_UMIN
Definition: dsp.hh:127
gem5::MipsISA::FIXED_H_UMAX
const uint64_t FIXED_H_UMAX
Definition: dsp.hh:115
gem5::MipsISA::FIXED_B_UMIN
const uint64_t FIXED_B_UMIN
Definition: dsp.hh:130
gem5::MipsISA::FIXED_B_SMIN
const uint64_t FIXED_B_SMIN
Definition: dsp.hh:126
gem5::MipsISA::FIXED_H_UMIN
const uint64_t FIXED_H_UMIN
Definition: dsp.hh:129
gem5::MipsISA::FIXED_B_SMAX
const uint64_t FIXED_B_SMAX
Definition: dsp.hh:112
gem5::MipsISA::FIXED_B_UMAX
const uint64_t FIXED_B_UMAX
Definition: dsp.hh:116
gem5::MipsISA::FIXED_H_SMIN
const uint64_t FIXED_H_SMIN
Definition: dsp.hh:125

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