gem5  v22.1.0.0
handlers.hh
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28 
29 #ifndef __ARCH_SPARC_HANDLERS_HH__
30 #define __ARCH_SPARC_HANDLERS_HH__
31 
32 #include "arch/sparc/types.hh"
33 #include "sim/byteswap.hh"
34 
35 namespace gem5
36 {
37 
38 namespace SparcISA {
39 
40 // We only use 19 instructions for the trap handlers, but there would be
41 // space for 32 in a real SPARC trap table.
42 const int numFillInsts = 32;
43 const int numSpillInsts = 32;
44 
45 const MachInst fillHandler64[numFillInsts] =
46 {
47  htobe<MachInst>(0x87802016), // wr %g0, ASI_AIUP, %asi
48  htobe<MachInst>(0xe0dba7ff), // ldxa [%sp + BIAS + (0*8)] %asi, %l0
49  htobe<MachInst>(0xe2dba807), // ldxa [%sp + BIAS + (1*8)] %asi, %l1
50  htobe<MachInst>(0xe4dba80f), // ldxa [%sp + BIAS + (2*8)] %asi, %l2
51  htobe<MachInst>(0xe6dba817), // ldxa [%sp + BIAS + (3*8)] %asi, %l3
52  htobe<MachInst>(0xe8dba81f), // ldxa [%sp + BIAS + (4*8)] %asi, %l4
53  htobe<MachInst>(0xeadba827), // ldxa [%sp + BIAS + (5*8)] %asi, %l5
54  htobe<MachInst>(0xecdba82f), // ldxa [%sp + BIAS + (6*8)] %asi, %l6
55  htobe<MachInst>(0xeedba837), // ldxa [%sp + BIAS + (7*8)] %asi, %l7
56  htobe<MachInst>(0xf0dba83f), // ldxa [%sp + BIAS + (8*8)] %asi, %i0
57  htobe<MachInst>(0xf2dba847), // ldxa [%sp + BIAS + (9*8)] %asi, %i1
58  htobe<MachInst>(0xf4dba84f), // ldxa [%sp + BIAS + (10*8)] %asi, %i2
59  htobe<MachInst>(0xf6dba857), // ldxa [%sp + BIAS + (11*8)] %asi, %i3
60  htobe<MachInst>(0xf8dba85f), // ldxa [%sp + BIAS + (12*8)] %asi, %i4
61  htobe<MachInst>(0xfadba867), // ldxa [%sp + BIAS + (13*8)] %asi, %i5
62  htobe<MachInst>(0xfcdba86f), // ldxa [%sp + BIAS + (14*8)] %asi, %i6
63  htobe<MachInst>(0xfedba877), // ldxa [%sp + BIAS + (15*8)] %asi, %i7
64  htobe<MachInst>(0x83880000), // restored
65  htobe<MachInst>(0x83F00000), // retry
66  htobe<MachInst>(0x00000000), // illtrap
67  htobe<MachInst>(0x00000000), // illtrap
68  htobe<MachInst>(0x00000000), // illtrap
69  htobe<MachInst>(0x00000000), // illtrap
70  htobe<MachInst>(0x00000000), // illtrap
71  htobe<MachInst>(0x00000000), // illtrap
72  htobe<MachInst>(0x00000000), // illtrap
73  htobe<MachInst>(0x00000000), // illtrap
74  htobe<MachInst>(0x00000000), // illtrap
75  htobe<MachInst>(0x00000000), // illtrap
76  htobe<MachInst>(0x00000000), // illtrap
77  htobe<MachInst>(0x00000000), // illtrap
78  htobe<MachInst>(0x00000000) // illtrap
79 };
80 
81 const MachInst fillHandler32[numFillInsts] =
82 {
83  htobe<MachInst>(0x87802016), // wr %g0, ASI_AIUP, %asi
84  htobe<MachInst>(0xe083a000), // lduwa [%sp + (0*4)] %asi, %l0
85  htobe<MachInst>(0xe283a004), // lduwa [%sp + (1*4)] %asi, %l1
86  htobe<MachInst>(0xe483a008), // lduwa [%sp + (2*4)] %asi, %l2
87  htobe<MachInst>(0xe683a00c), // lduwa [%sp + (3*4)] %asi, %l3
88  htobe<MachInst>(0xe883a010), // lduwa [%sp + (4*4)] %asi, %l4
89  htobe<MachInst>(0xea83a014), // lduwa [%sp + (5*4)] %asi, %l5
90  htobe<MachInst>(0xec83a018), // lduwa [%sp + (6*4)] %asi, %l6
91  htobe<MachInst>(0xee83a01c), // lduwa [%sp + (7*4)] %asi, %l7
92  htobe<MachInst>(0xf083a020), // lduwa [%sp + (8*4)] %asi, %i0
93  htobe<MachInst>(0xf283a024), // lduwa [%sp + (9*4)] %asi, %i1
94  htobe<MachInst>(0xf483a028), // lduwa [%sp + (10*4)] %asi, %i2
95  htobe<MachInst>(0xf683a02c), // lduwa [%sp + (11*4)] %asi, %i3
96  htobe<MachInst>(0xf883a030), // lduwa [%sp + (12*4)] %asi, %i4
97  htobe<MachInst>(0xfa83a034), // lduwa [%sp + (13*4)] %asi, %i5
98  htobe<MachInst>(0xfc83a038), // lduwa [%sp + (14*4)] %asi, %i6
99  htobe<MachInst>(0xfe83a03c), // lduwa [%sp + (15*4)] %asi, %i7
100  htobe<MachInst>(0x83880000), // restored
101  htobe<MachInst>(0x83F00000), // retry
102  htobe<MachInst>(0x00000000), // illtrap
103  htobe<MachInst>(0x00000000), // illtrap
104  htobe<MachInst>(0x00000000), // illtrap
105  htobe<MachInst>(0x00000000), // illtrap
106  htobe<MachInst>(0x00000000), // illtrap
107  htobe<MachInst>(0x00000000), // illtrap
108  htobe<MachInst>(0x00000000), // illtrap
109  htobe<MachInst>(0x00000000), // illtrap
110  htobe<MachInst>(0x00000000), // illtrap
111  htobe<MachInst>(0x00000000), // illtrap
112  htobe<MachInst>(0x00000000), // illtrap
113  htobe<MachInst>(0x00000000), // illtrap
114  htobe<MachInst>(0x00000000) // illtrap
115 };
116 
117 const MachInst spillHandler64[numSpillInsts] =
118 {
119  htobe<MachInst>(0x87802016), // wr %g0, ASI_AIUP, %asi
120  htobe<MachInst>(0xe0f3a7ff), // stxa %l0, [%sp + BIAS + (0*8)] %asi
121  htobe<MachInst>(0xe2f3a807), // stxa %l1, [%sp + BIAS + (1*8)] %asi
122  htobe<MachInst>(0xe4f3a80f), // stxa %l2, [%sp + BIAS + (2*8)] %asi
123  htobe<MachInst>(0xe6f3a817), // stxa %l3, [%sp + BIAS + (3*8)] %asi
124  htobe<MachInst>(0xe8f3a81f), // stxa %l4, [%sp + BIAS + (4*8)] %asi
125  htobe<MachInst>(0xeaf3a827), // stxa %l5, [%sp + BIAS + (5*8)] %asi
126  htobe<MachInst>(0xecf3a82f), // stxa %l6, [%sp + BIAS + (6*8)] %asi
127  htobe<MachInst>(0xeef3a837), // stxa %l7, [%sp + BIAS + (7*8)] %asi
128  htobe<MachInst>(0xf0f3a83f), // stxa %i0, [%sp + BIAS + (8*8)] %asi
129  htobe<MachInst>(0xf2f3a847), // stxa %i1, [%sp + BIAS + (9*8)] %asi
130  htobe<MachInst>(0xf4f3a84f), // stxa %i2, [%sp + BIAS + (10*8)] %asi
131  htobe<MachInst>(0xf6f3a857), // stxa %i3, [%sp + BIAS + (11*8)] %asi
132  htobe<MachInst>(0xf8f3a85f), // stxa %i4, [%sp + BIAS + (12*8)] %asi
133  htobe<MachInst>(0xfaf3a867), // stxa %i5, [%sp + BIAS + (13*8)] %asi
134  htobe<MachInst>(0xfcf3a86f), // stxa %i6, [%sp + BIAS + (14*8)] %asi
135  htobe<MachInst>(0xfef3a877), // stxa %i7, [%sp + BIAS + (15*8)] %asi
136  htobe<MachInst>(0x81880000), // saved
137  htobe<MachInst>(0x83F00000), // retry
138  htobe<MachInst>(0x00000000), // illtrap
139  htobe<MachInst>(0x00000000), // illtrap
140  htobe<MachInst>(0x00000000), // illtrap
141  htobe<MachInst>(0x00000000), // illtrap
142  htobe<MachInst>(0x00000000), // illtrap
143  htobe<MachInst>(0x00000000), // illtrap
144  htobe<MachInst>(0x00000000), // illtrap
145  htobe<MachInst>(0x00000000), // illtrap
146  htobe<MachInst>(0x00000000), // illtrap
147  htobe<MachInst>(0x00000000), // illtrap
148  htobe<MachInst>(0x00000000), // illtrap
149  htobe<MachInst>(0x00000000), // illtrap
150  htobe<MachInst>(0x00000000) // illtrap
151 };
152 
153 const MachInst spillHandler32[numSpillInsts] =
154 {
155  htobe<MachInst>(0x87802016), // wr %g0, ASI_AIUP, %asi
156  htobe<MachInst>(0xe0a3a000), // stwa %l0, [%sp + (0*4)] %asi
157  htobe<MachInst>(0xe2a3a004), // stwa %l1, [%sp + (1*4)] %asi
158  htobe<MachInst>(0xe4a3a008), // stwa %l2, [%sp + (2*4)] %asi
159  htobe<MachInst>(0xe6a3a00c), // stwa %l3, [%sp + (3*4)] %asi
160  htobe<MachInst>(0xe8a3a010), // stwa %l4, [%sp + (4*4)] %asi
161  htobe<MachInst>(0xeaa3a014), // stwa %l5, [%sp + (5*4)] %asi
162  htobe<MachInst>(0xeca3a018), // stwa %l6, [%sp + (6*4)] %asi
163  htobe<MachInst>(0xeea3a01c), // stwa %l7, [%sp + (7*4)] %asi
164  htobe<MachInst>(0xf0a3a020), // stwa %i0, [%sp + (8*4)] %asi
165  htobe<MachInst>(0xf2a3a024), // stwa %i1, [%sp + (9*4)] %asi
166  htobe<MachInst>(0xf4a3a028), // stwa %i2, [%sp + (10*4)] %asi
167  htobe<MachInst>(0xf6a3a02c), // stwa %i3, [%sp + (11*4)] %asi
168  htobe<MachInst>(0xf8a3a030), // stwa %i4, [%sp + (12*4)] %asi
169  htobe<MachInst>(0xfaa3a034), // stwa %i5, [%sp + (13*4)] %asi
170  htobe<MachInst>(0xfca3a038), // stwa %i6, [%sp + (14*4)] %asi
171  htobe<MachInst>(0xfea3a03c), // stwa %i7, [%sp + (15*4)] %asi
172  htobe<MachInst>(0x81880000), // saved
173  htobe<MachInst>(0x83F00000), // retry
174  htobe<MachInst>(0x00000000), // illtrap
175  htobe<MachInst>(0x00000000), // illtrap
176  htobe<MachInst>(0x00000000), // illtrap
177  htobe<MachInst>(0x00000000), // illtrap
178  htobe<MachInst>(0x00000000), // illtrap
179  htobe<MachInst>(0x00000000), // illtrap
180  htobe<MachInst>(0x00000000), // illtrap
181  htobe<MachInst>(0x00000000), // illtrap
182  htobe<MachInst>(0x00000000), // illtrap
183  htobe<MachInst>(0x00000000), // illtrap
184  htobe<MachInst>(0x00000000), // illtrap
185  htobe<MachInst>(0x00000000), // illtrap
186  htobe<MachInst>(0x00000000) // illtrap
187 };
188 
189 } // namespace SparcISA
190 } // namespace gem5
191 
192 #endif // __ARCH_SPARC_HANDLERS_HH__
gem5::SparcISA::spillHandler64
const MachInst spillHandler64[numSpillInsts]
Definition: handlers.hh:117
gem5::SparcISA::fillHandler64
const MachInst fillHandler64[numFillInsts]
Definition: handlers.hh:45
gem5::SparcISA::numFillInsts
const int numFillInsts
Definition: handlers.hh:42
gem5::SparcISA::fillHandler32
const MachInst fillHandler32[numFillInsts]
Definition: handlers.hh:81
gem5::SparcISA::numSpillInsts
const int numSpillInsts
Definition: handlers.hh:43
gem5::SparcISA::MachInst
uint32_t MachInst
Definition: types.hh:41
gem5::SparcISA::spillHandler32
const MachInst spillHandler32[numSpillInsts]
Definition: handlers.hh:153
gem5
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Definition: gpu_translation_state.hh:38
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