gem5  v21.1.0.2
Classes | Typedefs | Enumerations | Functions | Variables
gem5::SparcISA Namespace Reference

Classes

class  BlockMem
 
class  BlockMemImm
 
class  BlockMemImmMicro
 
class  BlockMemMicro
 
class  Branch
 Base class for branch operations. More...
 
class  BranchDisp
 Base class for branch operations with an immediate displacement. More...
 
class  BranchImm13
 Base class for branches that use an immediate and a register to compute their displacements. More...
 
class  BranchNBits
 Base class for branches with n bit displacements. More...
 
class  BranchSplit
 Base class for 16bit split displacements. More...
 
class  CleanWindow
 
class  CpuMondo
 
class  DataAccessError
 
class  DataAccessException
 
class  DataAccessProtection
 
class  DataInvalidTSBEntry
 
class  DataRealTranslationMiss
 
class  Decoder
 
class  DevMondo
 
class  DivisionByZero
 
class  EmuLinux
 
class  EnumeratedFault
 
class  ExternallyInitiatedReset
 
class  FailUnimplemented
 Static instruction class for unimplemented instructions that cause simulator termination. More...
 
class  FastDataAccessMMUMiss
 
class  FastDataAccessProtection
 
class  FastInstructionAccessMMUMiss
 
class  FillNNormal
 
class  FillNOther
 
class  FpDisabled
 
class  FpExceptionIEEE754
 
class  FpExceptionOther
 
class  FpUnimpl
 
class  FsWorkload
 
class  HstickMatch
 
class  IllegalInstruction
 
class  InstructionAccessError
 
class  InstructionAccessException
 
class  InstructionBreakpoint
 
class  InstructionInvalidTSBEntry
 
class  InstructionRealTranslationMiss
 
class  InternalProcessorError
 
class  InterruptLevelN
 
class  Interrupts
 
class  InterruptVector
 
class  IntOp
 Base class for integer operations. More...
 
class  IntOpImm
 Base class for immediate integer operations. More...
 
class  IntOpImm10
 Base class for 10 bit immediate integer operations. More...
 
class  IntOpImm11
 Base class for 11 bit immediate integer operations. More...
 
class  IntOpImm13
 Base class for 13 bit immediate integer operations. More...
 
class  ISA
 
class  LDDFMemAddressNotAligned
 
class  LDQFMemAddressNotAligned
 
class  Mem
 Base class for memory operations. More...
 
class  MemAddressNotAligned
 
class  MemImm
 Class for memory operations which use an immediate offset. More...
 
class  MMU
 
class  Nop
 Nop class. More...
 
class  PageTableEntry
 
class  PAWatchpoint
 
class  PowerOnReset
 
class  Priv
 Base class for privelege mode operations. More...
 
class  PrivilegedAction
 
class  PrivilegedOpcode
 
class  PrivImm
 Base class for privelege mode operations with immediates. More...
 
class  PrivReg
 
class  RdPriv
 
class  REDStateException
 
class  RemoteGDB
 
class  ResumableError
 
class  SetHi
 Base class for sethi. More...
 
class  SEWorkload
 
class  SoftwareInitiatedReset
 
class  SparcDelayedMicroInst
 
class  SparcFault
 
class  SparcFaultBase
 
class  SparcMacroInst
 
class  SparcMicroInst
 
class  SparcStaticInst
 Base class for all SPARC static instructions. More...
 
class  SpillNNormal
 
class  SpillNOther
 
class  StackTrace
 
class  STDFMemAddressNotAligned
 
class  StoreError
 
class  STQFMemAddressNotAligned
 
class  TagOverflow
 
class  TLB
 
struct  TlbEntry
 
class  TlbMap
 
struct  TlbRange
 
class  Trap
 Base class for trap instructions, or instructions that always fault. More...
 
class  TrapInstruction
 
class  TrapLevelZero
 
class  TteTag
 
class  Unknown
 Class for Unknown/Illegal instructions. More...
 
class  VAWatchpoint
 
class  VecDisabled
 
class  WarnUnimplemented
 Base class for unimplemented instructions that cause a warning to be printed (but do not terminate simulation). More...
 
class  WatchDogReset
 
class  WrPriv
 
class  WrPrivImm
 

Typedefs

typedef uint32_t TrapType
 
typedef uint32_t FaultPriority
 
typedef GenericISA::DelaySlotUPCState< 4 > PCState
 
typedef uint32_t MachInst
 
typedef uint64_t ExtMachInst
 
using VecElem = ::gem5::DummyVecElem
 
using VecRegContainer = ::gem5::DummyVecRegContainer
 
using VecPredRegContainer = ::gem5::DummyVecPredRegContainer
 

Enumerations

enum  ASI {
  ASI_IMPLICIT = 0x00, ASI_NUCLEUS = 0x4, ASI_N = 0x4, ASI_NL = 0xC,
  ASI_NUCLEUS_LITTLE = ASI_NL, ASI_AIUP = 0x10, ASI_AS_IF_USER_PRIMARY = ASI_AIUP, ASI_AIUS = 0x11,
  ASI_AS_IF_USER_SECONDARY = ASI_AIUS, ASI_REAL = 0x14, ASI_REAL_IO = 0x15, ASI_BLK_AIUP = 0x16,
  ASI_BLOCK_AS_IF_USER_PRIMARY = ASI_BLK_AIUP, ASI_BLK_AIUS = 0x17, ASI_BLOCK_AS_IF_USER_SECONDARY = ASI_BLK_AIUS, ASI_AIUP_L = 0x18,
  ASI_AS_IF_USER_PRIMARY_LITTLE = ASI_AIUP_L, ASI_AIUS_L = 0x19, ASI_AS_IF_USER_SECONDARY_LITTLE = ASI_AIUS_L, ASI_REAL_L = 0x1C,
  ASI_REAL_LITTLE = ASI_REAL_L, ASI_REAL_IO_L = 0x1D, ASI_REAL_IO_LITTLE = ASI_REAL_IO_L, ASI_BLK_AIUP_L = 0x1E,
  ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE = ASI_BLK_AIUP_L, ASI_BLK_AIUS_L = 0x1F, ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE = ASI_BLK_AIUS_L, ASI_SCRATCHPAD = 0x20,
  ASI_MMU = 0x21, ASI_LDTX_AIUP = 0x22, ASI_LD_TWINX_AS_IF_USER_PRIMARY = ASI_LDTX_AIUP, ASI_LDTX_AIUS = 0x23,
  ASI_LD_TWINX_AS_IF_USER_SECONDARY = ASI_LDTX_AIUS, ASI_QUAD_LDD = 0x24, ASI_QUEUE = 0x25, ASI_QUAD_LDD_REAL = 0x26,
  ASI_LDTX_REAL = ASI_QUAD_LDD_REAL, ASI_LDTX_N = 0x27, ASI_LD_TWINX_NUCLEUS = ASI_LDTX_N, ASI_ST_BLKINIT_NUCLEUS = ASI_LDTX_N,
  ASI_STBI_N = ASI_LDTX_N, ASI_LDTX_AIUP_L = 0x2A, ASI_TWINX_AS_IF_USER_PRIMARY_LITTLE = ASI_LDTX_AIUP_L, ASI_ST_BLKINIT_AS_IF_USER_PRIMARY_LITTLE = ASI_LDTX_AIUP_L,
  ASI_STBI_AIUP_L = ASI_LDTX_AIUP_L, ASI_LDTX_AIUS_L = 0x2B, ASI_LD_TWINX_AS_IF_USER_SECONDARY_LITTLE = ASI_LDTX_AIUS_L, ASI_ST_BLKINIT_AS_IF_USER_SECONDARY_LITTLE = ASI_LDTX_AIUS_L,
  ASI_STBI_AIUS_L = ASI_LDTX_AIUS_L, ASI_LTX_L = 0x2C, ASI_TWINX_LITTLE = ASI_LTX_L, ASI_LDTX_REAL_L = 0x2E,
  ASI_LD_TWINX_REAL_LITTLE = ASI_LDTX_REAL_L, ASI_LDTX_NL = 0x2F, ASI_LD_TWINX_NUCLEUS_LITTLE = ASI_LDTX_NL, ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0 = 0x31,
  ASI_DMMU_CTXT_ZERO_TSB_BASE_PS1 = 0x32, ASI_DMMU_CTXT_ZERO_CONFIG = 0x33, ASI_IMMU_CTXT_ZERO_TSB_BASE_PS0 = 0x35, ASI_IMMU_CTXT_ZERO_TSB_BASE_PS1 = 0x36,
  ASI_IMMU_CTXT_ZERO_CONFIG = 0x37, ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS0 = 0x39, ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS1 = 0x3A, ASI_DMMU_CTXT_NONZERO_CONFIG = 0x3B,
  ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS0 = 0x3D, ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS1 = 0x3E, ASI_IMMU_CTXT_NONZERO_CONFIG = 0x3F, ASI_STREAM_MA = 0x40,
  ASI_CMT_SHARED = 0x41, ASI_SPARC_BIST_CONTROL = 0x42, ASI_INST_MASK_REG = 0x42, ASI_LSU_DIAG_REG = 0x42,
  ASI_STM_CTL_REG = 0x44, ASI_LSU_CONTROL_REG = 0x45, ASI_DCACHE_DATA = 0x46, ASI_DCACHE_TAG = 0x47,
  ASI_INTR_DISPATCH_STATUS = 0x48, ASI_INTR_RECEIVE = 0x49, ASI_UPA_CONFIG_REGISTER = 0x4A, ASI_SPARC_ERROR_EN_REG = 0x4B,
  ASI_SPARC_ERROR_STATUS_REG = 0x4C, ASI_SPARC_ERROR_ADDRESS_REG = 0x4D, ASI_ECACHE_TAG_DATA = 0x4E, ASI_HYP_SCRATCHPAD = 0x4F,
  ASI_IMMU = 0x50, ASI_IMMU_TSB_PS0_PTR_REG = 0x51, ASI_IMMU_TSB_PS1_PTR_REG = 0x52, ASI_ITLB_DATA_IN_REG = 0x54,
  ASI_ITLB_DATA_ACCESS_REG = 0x55, ASI_ITLB_TAG_READ_REG = 0x56, ASI_IMMU_DEMAP = 0x57, ASI_DMMU = 0x58,
  ASI_DMMU_TSB_PS0_PTR_REG = 0x59, ASI_DMMU_TSB_PS1_PTR_REG = 0x5A, ASI_DMMU_TSB_DIRECT_PTR_REG = 0x5B, ASI_DTLB_DATA_IN_REG = 0x5C,
  ASI_DTLB_DATA_ACCESS_REG = 0x5D, ASI_DTLB_TAG_READ_REG = 0x5E, ASI_DMMU_DEMAP = 0x5F, ASI_TLB_INVALIDATE_ALL = 0x60,
  ASI_CMT_PER_STRAND = 0x63, ASI_ICACHE_INSTR = 0x66, ASI_ICACHE_TAG = 0x67, ASI_SWVR_INTR_RECEIVE = 0x72,
  ASI_SWVR_UDB_INTR_W = 0x73, ASI_SWVR_UDB_INTR_R = 0x74, ASI_P = 0x80, ASI_PRIMARY = ASI_P,
  ASI_S = 0x81, ASI_SECONDARY = ASI_S, ASI_PNF = 0x82, ASI_PRIMARY_NO_FAULT = ASI_PNF,
  ASI_SNF = 0x83, ASI_SECONDARY_NO_FAULT = ASI_SNF, ASI_PL = 0x88, ASI_PRIMARY_LITTLE = ASI_PL,
  ASI_SL = 0x89, ASI_SECONDARY_LITTLE = ASI_SL, ASI_PNFL = 0x8A, ASI_PRIMARY_NO_FAULT_LITTLE = ASI_PNFL,
  ASI_SNFL = 0x8B, ASI_SECONDARY_NO_FAULT_LITTLE = ASI_SNFL, ASI_PST8_P = 0xC0, ASI_PST8_PRIMARY = ASI_PST8_P,
  ASI_PST8_S = 0xC1, ASI_PST8_SECONDARY = ASI_PST8_S, ASI_PST16_P = 0xC2, ASI_PST16_PRIMARY = ASI_PST16_P,
  ASI_PST16_S = 0xC3, ASI_PST16_SECONDARY = ASI_PST16_S, ASI_PST32_P = 0xC4, ASI_PST32_PRIMARY = ASI_PST32_P,
  ASI_PST32_S = 0xC5, ASI_PST32_SECONDARY = ASI_PST32_S, ASI_PST8_PL = 0xC8, ASI_PST8_PRIMARY_LITTLE = ASI_PST8_PL,
  ASI_PST8_SL = 0xC9, ASI_PST8_SECONDARY_LITTLE = ASI_PST8_SL, ASI_PST16_PL = 0xCA, ASI_PST16_PRIMARY_LITTLE = ASI_PST16_PL,
  ASI_PST16_SL = 0xCB, ASI_PST16_SECONDARY_LITTLE = ASI_PST16_SL, ASI_PST32_PL = 0xCC, ASI_PST32_PRIMARY_LITTLE = ASI_PST32_PL,
  ASI_PST32_SL = 0xCD, ASI_PST32_SECONDARY_LITTLE = ASI_PST32_SL, ASI_FL8_P = 0xD0, ASI_FL8_PRIMARY = ASI_FL8_P,
  ASI_FL8_S = 0xD1, ASI_FL8_SECONDARY = ASI_FL8_S, ASI_FL16_P = 0xD2, ASI_FL16_PRIMARY = ASI_FL16_P,
  ASI_FL16_S = 0xD3, ASI_FL16_SECONDARY = ASI_FL16_S, ASI_FL8_PL = 0xD8, ASI_FL8_PRIMARY_LITTLE = ASI_FL8_PL,
  ASI_FL8_SL = 0xD9, ASI_FL8_SECONDARY_LITTLE = ASI_FL8_SL, ASI_FL16_PL = 0xDA, ASI_FL16_PRIMARY_LITTLE = ASI_FL16_PL,
  ASI_FL16_SL = 0xDB, ASI_FL16_SECONDARY_LITTLE = ASI_FL16_SL, ASI_LDTX_P = 0xE2, ASI_LD_TWINX_PRIMARY = ASI_LDTX_P,
  ASI_LDTX_S = 0xE3, ASI_LD_TWINX_SECONDARY = ASI_LDTX_S, ASI_LDTX_PL = 0xEA, ASI_LD_TWINX_PRIMARY_LITTLE = ASI_LDTX_PL,
  ASI_LDTX_SL = 0xEB, ASI_LD_TWINX_SECONDARY_LITTLE = ASI_LDTX_SL, ASI_BLK_P = 0xF0, ASI_BLOCK_PRIMARY = ASI_BLK_P,
  ASI_BLK_S = 0xF1, ASI_BLOCK_SECONDARY = ASI_BLK_S, ASI_BLK_PL = 0xF8, ASI_BLOCK_PRIMARY_LITTLE = ASI_BLK_PL,
  ASI_BLK_SL = 0xF9, ASI_BLOCK_SECONDARY_LITTLE = ASI_BLK_SL, MAX_ASI = 0xFF
}
 
enum  CondTest {
  Always =0x8, Never =0x0, NotEqual =0x9, Equal =0x1,
  Greater =0xA, LessOrEqual =0x2, GreaterOrEqual =0xB, Less =0x3,
  GreaterUnsigned =0xC, LessOrEqualUnsigned =0x4, CarryClear =0xD, CarrySet =0x5,
  Positive =0xE, Negative =0x6, OverflowClear =0xF, OverflowSet =0x7
}
 
enum  FpCondTest {
  FAlways =0x8, FNever =0x0, FUnordered =0x7, FGreater =0x6,
  FUnorderedOrGreater =0x5, FLess =0x4, FUnorderedOrLess =0x3, FLessOrGreater =0x2,
  FNotEqual =0x1, FEqual =0x9, FUnorderedOrEqual =0xA, FGreaterOrEqual =0xB,
  FUnorderedOrGreaterOrEqual =0xC, FLessOrEqual =0xD, FUnorderedOrLessOrEqual =0xE, FOrdered =0xF
}
 
enum  InterruptTypes {
  IT_TRAP_LEVEL_ZERO, IT_HINTP, IT_INT_VEC, IT_CPU_MONDO,
  IT_DEV_MONDO, IT_RES_ERROR, IT_SOFT_INT, NumInterruptTypes
}
 
enum  {
  INTREG_G0, INTREG_G1, INTREG_G2, INTREG_G3,
  INTREG_G4, INTREG_G5, INTREG_G6, INTREG_G7,
  INTREG_O0, INTREG_O1, INTREG_O2, INTREG_O3,
  INTREG_O4, INTREG_O5, INTREG_O6, INTREG_O7,
  INTREG_L0, INTREG_L1, INTREG_L2, INTREG_L3,
  INTREG_L4, INTREG_L5, INTREG_L6, INTREG_L7,
  INTREG_I0, INTREG_I1, INTREG_I2, INTREG_I3,
  INTREG_I4, INTREG_I5, INTREG_I6, INTREG_I7,
  NumIntArchRegs, INTREG_UREG0 = NumIntArchRegs, INTREG_Y, INTREG_CCR,
  INTREG_CANSAVE, INTREG_CANRESTORE, INTREG_CLEANWIN, INTREG_OTHERWIN,
  INTREG_WSTATE, INTREG_GSR, NumMicroIntRegs = INTREG_GSR - INTREG_UREG0 + 1
}
 
enum  MiscRegIndex {
  MISCREG_ASI, MISCREG_TICK, MISCREG_FPRS, MISCREG_PCR,
  MISCREG_PIC, MISCREG_GSR, MISCREG_SOFTINT_SET, MISCREG_SOFTINT_CLR,
  MISCREG_SOFTINT, MISCREG_TICK_CMPR, MISCREG_STICK, MISCREG_STICK_CMPR,
  MISCREG_TPC, MISCREG_TNPC, MISCREG_TSTATE, MISCREG_TT,
  MISCREG_PRIVTICK, MISCREG_TBA, MISCREG_PSTATE, MISCREG_TL,
  MISCREG_PIL, MISCREG_CWP, MISCREG_GL, MISCREG_HPSTATE,
  MISCREG_HTSTATE, MISCREG_HINTP, MISCREG_HTBA, MISCREG_HVER,
  MISCREG_STRAND_STS_REG, MISCREG_HSTICK_CMPR, MISCREG_FSR, MISCREG_MMU_P_CONTEXT,
  MISCREG_MMU_S_CONTEXT, MISCREG_MMU_PART_ID, MISCREG_MMU_LSU_CTRL, MISCREG_SCRATCHPAD_R0,
  MISCREG_SCRATCHPAD_R1, MISCREG_SCRATCHPAD_R2, MISCREG_SCRATCHPAD_R3, MISCREG_SCRATCHPAD_R4,
  MISCREG_SCRATCHPAD_R5, MISCREG_SCRATCHPAD_R6, MISCREG_SCRATCHPAD_R7, MISCREG_QUEUE_CPU_MONDO_HEAD,
  MISCREG_QUEUE_CPU_MONDO_TAIL, MISCREG_QUEUE_DEV_MONDO_HEAD, MISCREG_QUEUE_DEV_MONDO_TAIL, MISCREG_QUEUE_RES_ERROR_HEAD,
  MISCREG_QUEUE_RES_ERROR_TAIL, MISCREG_QUEUE_NRES_ERROR_HEAD, MISCREG_QUEUE_NRES_ERROR_TAIL, MISCREG_TLB_DATA,
  MISCREG_NUMMISCREGS
}
 

Functions

bool asiIsBlock (ASI asi)
 
bool asiIsPrimary (ASI asi)
 
bool asiIsSecondary (ASI asi)
 
bool asiIsNucleus (ASI asi)
 
bool asiIsAsIfUser (ASI asi)
 
bool asiIsIO (ASI asi)
 
bool asiIsReal (ASI asi)
 
bool asiIsLittle (ASI asi)
 
bool asiIsTwin (ASI asi)
 
bool asiIsPartialStore (ASI asi)
 
bool asiIsFloatingLoad (ASI asi)
 
bool asiIsNoFault (ASI asi)
 
bool asiIsScratchPad (ASI asi)
 
bool asiIsCmt (ASI asi)
 
bool asiIsQueue (ASI asi)
 
bool asiIsInterrupt (ASI asi)
 
bool asiIsMmu (ASI asi)
 
bool asiIsUnPriv (ASI asi)
 
bool asiIsPriv (ASI asi)
 
bool asiIsHPriv (ASI asi)
 
bool asiIsReg (ASI asi)
 
bool asiIsSparcError (ASI asi)
 
bool asiIsDtlb (ASI)
 
void enterREDState (ThreadContext *tc)
 This causes the thread context to enter RED state. More...
 
void doREDFault (ThreadContext *tc, TrapType tt)
 This sets everything up for a RED state trap except for actually jumping to the handler. More...
 
void doNormalFault (ThreadContext *tc, TrapType tt, bool gotoHpriv)
 This sets everything up for a normal trap except for actually jumping to the handler. More...
 
void getREDVector (RegVal TT, Addr &PC, Addr &NPC)
 
void getHyperVector (ThreadContext *tc, Addr &PC, Addr &NPC, RegVal TT)
 
void getPrivVector (ThreadContext *tc, Addr &PC, Addr &NPC, RegVal TT, RegVal TL)
 
static PSTATE buildPstateMask ()
 
static void copyMiscRegs (ThreadContext *src, ThreadContext *dest)
 
static SyscallReturn unameFunc (SyscallDesc *desc, ThreadContext *tc, VPtr< Linux::utsname > name)
 Target uname() handler. More...
 
static SyscallReturn getresuidFunc (SyscallDesc *desc, ThreadContext *tc, VPtr<> ruid, VPtr<> euid, VPtr<> suid)
 
 BitUnion64 (HPSTATE) Bitfield< 0 > tlz
 
 EndBitUnion (HPSTATE) BitUnion16(PSTATE) Bitfield< 1 > ie
 
 EndBitUnion (PSTATE) BitUnion8(CCR) SubBitUnion(xcc
 
 EndSubBitUnion (xcc) SubBitUnion(icc
 
 EndSubBitUnion (icc) EndBitUnion(CCR) struct STS
 

Variables

const int numFillInsts = 32
 
const int numSpillInsts = 32
 
const MachInst fillHandler64 [numFillInsts]
 
const MachInst fillHandler32 [numFillInsts]
 
const MachInst spillHandler64 [numSpillInsts]
 
const MachInst spillHandler32 [numSpillInsts]
 
const char * CondTestAbbrev []
 
static const PSTATE PstateMask = buildPstateMask()
 
const Addr PageShift = 13
 
const Addr PageBytes = 1ULL << PageShift
 
const int NumFloatRegs = 64
 
const int NumFloatArchRegs = NumFloatRegs
 
const int ReturnAddressReg = INTREG_I7
 
const int ReturnValueReg = INTREG_O0
 
const int StackPointerReg = INTREG_O6
 
const int FramePointerReg = INTREG_I6
 
const int SyscallPseudoReturnReg = INTREG_O1
 
const int NumIntRegs = (MaxGL + 1) * 8 + NWindows * 16 + NumMicroIntRegs
 
Bitfield< 2 > hpriv
 
Bitfield< 5 > red
 
Bitfield< 10 > ibe
 
Bitfield< 11 > id
 
Bitfield< 2 > priv
 
Bitfield< 3 > am
 
Bitfield< 4 > pef
 
Bitfield< 7, 6 > mm
 
Bitfield< 8 > tle
 
Bitfield< 9 > cle
 
Bitfield< 10 > pid0
 
Bitfield< 11 > pid1
 
Bitfield< 7 > n
 
Bitfield< 6 > z
 
Bitfield< 5 > v
 
Bitfield< 4 > c
 
const int NumMiscRegs = MISCREG_NUMMISCREGS
 
const int MaxPTL = 2
 
const int MaxTL = 6
 
const int MaxGL = 3
 
const int MaxPGL = 2
 
const int NWindows = 8
 
const Addr StartVAddrHole = 0x0000800000000000ULL
 
const Addr EndVAddrHole = 0xFFFF7FFFFFFFFFFFULL
 
const Addr VAddrAMask = 0xFFFFFFFFULL
 
const Addr PAddrImplMask = 0x000000FFFFFFFFFFULL
 
constexpr unsigned NumVecElemPerVecReg = ::gem5::DummyNumVecElemPerVecReg
 

Typedef Documentation

◆ ExtMachInst

typedef uint64_t gem5::SparcISA::ExtMachInst

Definition at line 42 of file types.hh.

◆ FaultPriority

Definition at line 45 of file faults.hh.

◆ MachInst

typedef uint32_t gem5::SparcISA::MachInst

Definition at line 41 of file types.hh.

◆ PCState

Definition at line 40 of file pcstate.hh.

◆ TrapType

typedef uint32_t gem5::SparcISA::TrapType

Definition at line 44 of file faults.hh.

◆ VecElem

Definition at line 42 of file vecregs.hh.

◆ VecPredRegContainer

Definition at line 47 of file vecregs.hh.

◆ VecRegContainer

Definition at line 43 of file vecregs.hh.

Enumeration Type Documentation

◆ anonymous enum

anonymous enum
Enumerator
INTREG_G0 
INTREG_G1 
INTREG_G2 
INTREG_G3 
INTREG_G4 
INTREG_G5 
INTREG_G6 
INTREG_G7 
INTREG_O0 
INTREG_O1 
INTREG_O2 
INTREG_O3 
INTREG_O4 
INTREG_O5 
INTREG_O6 
INTREG_O7 
INTREG_L0 
INTREG_L1 
INTREG_L2 
INTREG_L3 
INTREG_L4 
INTREG_L5 
INTREG_L6 
INTREG_L7 
INTREG_I0 
INTREG_I1 
INTREG_I2 
INTREG_I3 
INTREG_I4 
INTREG_I5 
INTREG_I6 
INTREG_I7 
NumIntArchRegs 
INTREG_UREG0 
INTREG_Y 
INTREG_CCR 
INTREG_CANSAVE 
INTREG_CANRESTORE 
INTREG_CLEANWIN 
INTREG_OTHERWIN 
INTREG_WSTATE 
INTREG_GSR 
NumMicroIntRegs 

Definition at line 41 of file int.hh.

◆ ASI

Enumerator
ASI_IMPLICIT 
ASI_NUCLEUS 
ASI_N 
ASI_NL 
ASI_NUCLEUS_LITTLE 
ASI_AIUP 
ASI_AS_IF_USER_PRIMARY 
ASI_AIUS 
ASI_AS_IF_USER_SECONDARY 
ASI_REAL 
ASI_REAL_IO 
ASI_BLK_AIUP 
ASI_BLOCK_AS_IF_USER_PRIMARY 
ASI_BLK_AIUS 
ASI_BLOCK_AS_IF_USER_SECONDARY 
ASI_AIUP_L 
ASI_AS_IF_USER_PRIMARY_LITTLE 
ASI_AIUS_L 
ASI_AS_IF_USER_SECONDARY_LITTLE 
ASI_REAL_L 
ASI_REAL_LITTLE 
ASI_REAL_IO_L 
ASI_REAL_IO_LITTLE 
ASI_BLK_AIUP_L 
ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE 
ASI_BLK_AIUS_L 
ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE 
ASI_SCRATCHPAD 
ASI_MMU 
ASI_LDTX_AIUP 
ASI_LD_TWINX_AS_IF_USER_PRIMARY 
ASI_LDTX_AIUS 
ASI_LD_TWINX_AS_IF_USER_SECONDARY 
ASI_QUAD_LDD 
ASI_QUEUE 
ASI_QUAD_LDD_REAL 
ASI_LDTX_REAL 
ASI_LDTX_N 
ASI_LD_TWINX_NUCLEUS 
ASI_ST_BLKINIT_NUCLEUS 
ASI_STBI_N 
ASI_LDTX_AIUP_L 
ASI_TWINX_AS_IF_USER_PRIMARY_LITTLE 
ASI_ST_BLKINIT_AS_IF_USER_PRIMARY_LITTLE 
ASI_STBI_AIUP_L 
ASI_LDTX_AIUS_L 
ASI_LD_TWINX_AS_IF_USER_SECONDARY_LITTLE 
ASI_ST_BLKINIT_AS_IF_USER_SECONDARY_LITTLE 
ASI_STBI_AIUS_L 
ASI_LTX_L 
ASI_TWINX_LITTLE 
ASI_LDTX_REAL_L 
ASI_LD_TWINX_REAL_LITTLE 
ASI_LDTX_NL 
ASI_LD_TWINX_NUCLEUS_LITTLE 
ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0 
ASI_DMMU_CTXT_ZERO_TSB_BASE_PS1 
ASI_DMMU_CTXT_ZERO_CONFIG 
ASI_IMMU_CTXT_ZERO_TSB_BASE_PS0 
ASI_IMMU_CTXT_ZERO_TSB_BASE_PS1 
ASI_IMMU_CTXT_ZERO_CONFIG 
ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS0 
ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS1 
ASI_DMMU_CTXT_NONZERO_CONFIG 
ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS0 
ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS1 
ASI_IMMU_CTXT_NONZERO_CONFIG 
ASI_STREAM_MA 
ASI_CMT_SHARED 
ASI_SPARC_BIST_CONTROL 
ASI_INST_MASK_REG 
ASI_LSU_DIAG_REG 
ASI_STM_CTL_REG 
ASI_LSU_CONTROL_REG 
ASI_DCACHE_DATA 
ASI_DCACHE_TAG 
ASI_INTR_DISPATCH_STATUS 
ASI_INTR_RECEIVE 
ASI_UPA_CONFIG_REGISTER 
ASI_SPARC_ERROR_EN_REG 
ASI_SPARC_ERROR_STATUS_REG 
ASI_SPARC_ERROR_ADDRESS_REG 
ASI_ECACHE_TAG_DATA 
ASI_HYP_SCRATCHPAD 
ASI_IMMU 
ASI_IMMU_TSB_PS0_PTR_REG 
ASI_IMMU_TSB_PS1_PTR_REG 
ASI_ITLB_DATA_IN_REG 
ASI_ITLB_DATA_ACCESS_REG 
ASI_ITLB_TAG_READ_REG 
ASI_IMMU_DEMAP 
ASI_DMMU 
ASI_DMMU_TSB_PS0_PTR_REG 
ASI_DMMU_TSB_PS1_PTR_REG 
ASI_DMMU_TSB_DIRECT_PTR_REG 
ASI_DTLB_DATA_IN_REG 
ASI_DTLB_DATA_ACCESS_REG 
ASI_DTLB_TAG_READ_REG 
ASI_DMMU_DEMAP 
ASI_TLB_INVALIDATE_ALL 
ASI_CMT_PER_STRAND 
ASI_ICACHE_INSTR 
ASI_ICACHE_TAG 
ASI_SWVR_INTR_RECEIVE 
ASI_SWVR_UDB_INTR_W 
ASI_SWVR_UDB_INTR_R 
ASI_P 
ASI_PRIMARY 
ASI_S 
ASI_SECONDARY 
ASI_PNF 
ASI_PRIMARY_NO_FAULT 
ASI_SNF 
ASI_SECONDARY_NO_FAULT 
ASI_PL 
ASI_PRIMARY_LITTLE 
ASI_SL 
ASI_SECONDARY_LITTLE 
ASI_PNFL 
ASI_PRIMARY_NO_FAULT_LITTLE 
ASI_SNFL 
ASI_SECONDARY_NO_FAULT_LITTLE 
ASI_PST8_P 
ASI_PST8_PRIMARY 
ASI_PST8_S 
ASI_PST8_SECONDARY 
ASI_PST16_P 
ASI_PST16_PRIMARY 
ASI_PST16_S 
ASI_PST16_SECONDARY 
ASI_PST32_P 
ASI_PST32_PRIMARY 
ASI_PST32_S 
ASI_PST32_SECONDARY 
ASI_PST8_PL 
ASI_PST8_PRIMARY_LITTLE 
ASI_PST8_SL 
ASI_PST8_SECONDARY_LITTLE 
ASI_PST16_PL 
ASI_PST16_PRIMARY_LITTLE 
ASI_PST16_SL 
ASI_PST16_SECONDARY_LITTLE 
ASI_PST32_PL 
ASI_PST32_PRIMARY_LITTLE 
ASI_PST32_SL 
ASI_PST32_SECONDARY_LITTLE 
ASI_FL8_P 
ASI_FL8_PRIMARY 
ASI_FL8_S 
ASI_FL8_SECONDARY 
ASI_FL16_P 
ASI_FL16_PRIMARY 
ASI_FL16_S 
ASI_FL16_SECONDARY 
ASI_FL8_PL 
ASI_FL8_PRIMARY_LITTLE 
ASI_FL8_SL 
ASI_FL8_SECONDARY_LITTLE 
ASI_FL16_PL 
ASI_FL16_PRIMARY_LITTLE 
ASI_FL16_SL 
ASI_FL16_SECONDARY_LITTLE 
ASI_LDTX_P 
ASI_LD_TWINX_PRIMARY 
ASI_LDTX_S 
ASI_LD_TWINX_SECONDARY 
ASI_LDTX_PL 
ASI_LD_TWINX_PRIMARY_LITTLE 
ASI_LDTX_SL 
ASI_LD_TWINX_SECONDARY_LITTLE 
ASI_BLK_P 
ASI_BLOCK_PRIMARY 
ASI_BLK_S 
ASI_BLOCK_SECONDARY 
ASI_BLK_PL 
ASI_BLOCK_PRIMARY_LITTLE 
ASI_BLK_SL 
ASI_BLOCK_SECONDARY_LITTLE 
MAX_ASI 

Definition at line 38 of file asi.hh.

◆ CondTest

Enumerator
Always 
Never 
NotEqual 
Equal 
Greater 
LessOrEqual 
GreaterOrEqual 
Less 
GreaterUnsigned 
LessOrEqualUnsigned 
CarryClear 
CarrySet 
Positive 
Negative 
OverflowClear 
OverflowSet 

Definition at line 46 of file static_inst.hh.

◆ FpCondTest

Enumerator
FAlways 
FNever 
FUnordered 
FGreater 
FUnorderedOrGreater 
FLess 
FUnorderedOrLess 
FLessOrGreater 
FNotEqual 
FEqual 
FUnorderedOrEqual 
FGreaterOrEqual 
FUnorderedOrGreaterOrEqual 
FLessOrEqual 
FUnorderedOrLessOrEqual 
FOrdered 

Definition at line 68 of file static_inst.hh.

◆ InterruptTypes

Enumerator
IT_TRAP_LEVEL_ZERO 
IT_HINTP 
IT_INT_VEC 
IT_CPU_MONDO 
IT_DEV_MONDO 
IT_RES_ERROR 
IT_SOFT_INT 
NumInterruptTypes 

Definition at line 46 of file interrupts.hh.

◆ MiscRegIndex

Enumerator
MISCREG_ASI 

Ancillary State Registers.

MISCREG_TICK 
MISCREG_FPRS 
MISCREG_PCR 
MISCREG_PIC 
MISCREG_GSR 
MISCREG_SOFTINT_SET 
MISCREG_SOFTINT_CLR 
MISCREG_SOFTINT 
MISCREG_TICK_CMPR 
MISCREG_STICK 
MISCREG_STICK_CMPR 
MISCREG_TPC 

Privilged Registers.

MISCREG_TNPC 
MISCREG_TSTATE 
MISCREG_TT 
MISCREG_PRIVTICK 
MISCREG_TBA 
MISCREG_PSTATE 
MISCREG_TL 
MISCREG_PIL 
MISCREG_CWP 
MISCREG_GL 
MISCREG_HPSTATE 

Hyper privileged registers.

MISCREG_HTSTATE 
MISCREG_HINTP 
MISCREG_HTBA 
MISCREG_HVER 
MISCREG_STRAND_STS_REG 
MISCREG_HSTICK_CMPR 
MISCREG_FSR 

Floating Point Status Register.

MISCREG_MMU_P_CONTEXT 

MMU Internal Registers.

MISCREG_MMU_S_CONTEXT 
MISCREG_MMU_PART_ID 
MISCREG_MMU_LSU_CTRL 
MISCREG_SCRATCHPAD_R0 

Scratchpad regiscers.

MISCREG_SCRATCHPAD_R1 
MISCREG_SCRATCHPAD_R2 
MISCREG_SCRATCHPAD_R3 
MISCREG_SCRATCHPAD_R4 
MISCREG_SCRATCHPAD_R5 
MISCREG_SCRATCHPAD_R6 
MISCREG_SCRATCHPAD_R7 
MISCREG_QUEUE_CPU_MONDO_HEAD 
MISCREG_QUEUE_CPU_MONDO_TAIL 
MISCREG_QUEUE_DEV_MONDO_HEAD 
MISCREG_QUEUE_DEV_MONDO_TAIL 
MISCREG_QUEUE_RES_ERROR_HEAD 
MISCREG_QUEUE_RES_ERROR_TAIL 
MISCREG_QUEUE_NRES_ERROR_HEAD 
MISCREG_QUEUE_NRES_ERROR_TAIL 
MISCREG_TLB_DATA 
MISCREG_NUMMISCREGS 

Definition at line 40 of file misc.hh.

Function Documentation

◆ asiIsAsIfUser()

bool gem5::SparcISA::asiIsAsIfUser ( ASI  asi)

◆ asiIsBlock()

bool gem5::SparcISA::asiIsBlock ( ASI  asi)

◆ asiIsCmt()

bool gem5::SparcISA::asiIsCmt ( ASI  asi)

Definition at line 249 of file asi.cc.

References ASI_CMT_PER_STRAND, and ASI_CMT_SHARED.

Referenced by asiIsReg().

◆ asiIsDtlb()

bool gem5::SparcISA::asiIsDtlb ( ASI  )

◆ asiIsFloatingLoad()

bool gem5::SparcISA::asiIsFloatingLoad ( ASI  asi)

Definition at line 220 of file asi.cc.

References ASI_FL16_P, ASI_FL16_PL, ASI_FL16_S, ASI_FL16_SL, ASI_FL8_P, ASI_FL8_PL, ASI_FL8_S, and ASI_FL8_SL.

◆ asiIsHPriv()

bool gem5::SparcISA::asiIsHPriv ( ASI  asi)

Definition at line 298 of file asi.cc.

◆ asiIsInterrupt()

bool gem5::SparcISA::asiIsInterrupt ( ASI  asi)

Definition at line 262 of file asi.cc.

References ASI_SWVR_INTR_RECEIVE, ASI_SWVR_UDB_INTR_R, and ASI_SWVR_UDB_INTR_W.

Referenced by asiIsReg().

◆ asiIsIO()

bool gem5::SparcISA::asiIsIO ( ASI  asi)

Definition at line 135 of file asi.cc.

References ASI_REAL_IO, and ASI_REAL_IO_L.

◆ asiIsLittle()

bool gem5::SparcISA::asiIsLittle ( ASI  asi)

◆ asiIsMmu()

bool gem5::SparcISA::asiIsMmu ( ASI  asi)

◆ asiIsNoFault()

bool gem5::SparcISA::asiIsNoFault ( ASI  asi)

Definition at line 233 of file asi.cc.

References ASI_PNF, ASI_PNFL, ASI_SNF, and ASI_SNFL.

◆ asiIsNucleus()

bool gem5::SparcISA::asiIsNucleus ( ASI  asi)

Definition at line 109 of file asi.cc.

References ASI_LDTX_N, ASI_LDTX_NL, ASI_N, and ASI_NL.

◆ asiIsPartialStore()

bool gem5::SparcISA::asiIsPartialStore ( ASI  asi)

◆ asiIsPrimary()

bool gem5::SparcISA::asiIsPrimary ( ASI  asi)

◆ asiIsPriv()

bool gem5::SparcISA::asiIsPriv ( ASI  asi)

Definition at line 291 of file asi.cc.

◆ asiIsQueue()

bool gem5::SparcISA::asiIsQueue ( ASI  asi)

Definition at line 256 of file asi.cc.

References ASI_QUEUE.

◆ asiIsReal()

bool gem5::SparcISA::asiIsReal ( ASI  asi)

◆ asiIsReg()

bool gem5::SparcISA::asiIsReg ( ASI  asi)

Definition at line 304 of file asi.cc.

References asiIsCmt(), asiIsInterrupt(), asiIsMmu(), asiIsScratchPad(), and asiIsSparcError().

◆ asiIsScratchPad()

bool gem5::SparcISA::asiIsScratchPad ( ASI  asi)

Definition at line 242 of file asi.cc.

References ASI_HYP_SCRATCHPAD, and ASI_SCRATCHPAD.

Referenced by asiIsReg().

◆ asiIsSecondary()

bool gem5::SparcISA::asiIsSecondary ( ASI  asi)

◆ asiIsSparcError()

bool gem5::SparcISA::asiIsSparcError ( ASI  asi)

Definition at line 312 of file asi.cc.

References ASI_SPARC_ERROR_EN_REG, and ASI_SPARC_ERROR_STATUS_REG.

Referenced by asiIsReg().

◆ asiIsTwin()

bool gem5::SparcISA::asiIsTwin ( ASI  asi)

◆ asiIsUnPriv()

bool gem5::SparcISA::asiIsUnPriv ( ASI  asi)

Definition at line 285 of file asi.cc.

◆ BitUnion64()

gem5::SparcISA::BitUnion64 ( HPSTATE  )

◆ buildPstateMask()

static PSTATE gem5::SparcISA::buildPstateMask ( )
static

Definition at line 53 of file isa.cc.

References gem5::mask().

◆ copyMiscRegs()

static void gem5::SparcISA::copyMiscRegs ( ThreadContext src,
ThreadContext dest 
)
static

◆ doNormalFault()

void gem5::SparcISA::doNormalFault ( ThreadContext tc,
TrapType  tt,
bool  gotoHpriv 
)

◆ doREDFault()

void gem5::SparcISA::doREDFault ( ThreadContext tc,
TrapType  tt 
)

◆ EndBitUnion() [1/2]

gem5::SparcISA::EndBitUnion ( HPSTATE  )

◆ EndBitUnion() [2/2]

gem5::SparcISA::EndBitUnion ( PSTATE  )

◆ EndSubBitUnion() [1/2]

gem5::SparcISA::EndSubBitUnion ( icc  )

Definition at line 151 of file misc.hh.

◆ EndSubBitUnion() [2/2]

gem5::SparcISA::EndSubBitUnion ( xcc  )

◆ enterREDState()

void gem5::SparcISA::enterREDState ( ThreadContext tc)

This causes the thread context to enter RED state.

This causes the side effects which go with entering RED state because of a trap.

Definition at line 282 of file faults.cc.

References MISCREG_HPSTATE, MISCREG_PSTATE, gem5::ThreadContext::readMiscRegNoEffect(), and gem5::ThreadContext::setMiscReg().

Referenced by gem5::SparcISA::SparcFaultBase::invoke(), and gem5::SparcISA::PowerOnReset::invoke().

◆ getHyperVector()

void gem5::SparcISA::getHyperVector ( ThreadContext tc,
Addr PC,
Addr NPC,
RegVal  TT 
)

◆ getPrivVector()

void gem5::SparcISA::getPrivVector ( ThreadContext tc,
Addr PC,
Addr NPC,
RegVal  TT,
RegVal  TL 
)

◆ getREDVector()

void gem5::SparcISA::getREDVector ( RegVal  TT,
Addr PC,
Addr NPC 
)

◆ getresuidFunc()

static SyscallReturn gem5::SparcISA::getresuidFunc ( SyscallDesc desc,
ThreadContext tc,
VPtr<>  ruid,
VPtr<>  euid,
VPtr<>  suid 
)
static

◆ unameFunc()

static SyscallReturn gem5::SparcISA::unameFunc ( SyscallDesc desc,
ThreadContext tc,
VPtr< Linux::utsname name 
)
static

Target uname() handler.

Definition at line 44 of file syscalls.cc.

References gem5::ThreadContext::getProcessPtr(), and name().

Variable Documentation

◆ am

Bitfield<3> gem5::SparcISA::am

◆ c

Bitfield< 0 > gem5::SparcISA::c

Definition at line 144 of file misc.hh.

Referenced by gem5::SparcISA::SparcStaticInst::passesCondition().

◆ cle

Bitfield<9> gem5::SparcISA::cle

Definition at line 134 of file misc.hh.

◆ CondTestAbbrev

const char * gem5::SparcISA::CondTestAbbrev
Initial value:
=
{
[Never] = "nev",
[Equal] = "e",
[LessOrEqual] = "le",
[Less] = "l",
[CarrySet] = "c",
[Negative] = "n",
[OverflowSet] = "o",
[Always] = "a",
[NotEqual] = "ne",
[Greater] = "g",
[GreaterOrEqual] = "ge",
[GreaterUnsigned] = "gu",
[CarryClear] = "cc",
[Positive] = "p",
[OverflowClear] = "oc"
}

Definition at line 42 of file static_inst.cc.

◆ EndVAddrHole

const Addr gem5::SparcISA::EndVAddrHole = 0xFFFF7FFFFFFFFFFFULL

Definition at line 49 of file tlb.hh.

Referenced by gem5::SparcISA::TLB::validVirtualAddress().

◆ fillHandler32

const MachInst gem5::SparcISA::fillHandler32[numFillInsts]

Definition at line 81 of file handlers.hh.

Referenced by gem5::Sparc32Process::argsInit().

◆ fillHandler64

const MachInst gem5::SparcISA::fillHandler64[numFillInsts]

Definition at line 45 of file handlers.hh.

Referenced by gem5::Sparc64Process::argsInit().

◆ FramePointerReg

const int gem5::SparcISA::FramePointerReg = INTREG_I6

Definition at line 74 of file int.hh.

Referenced by gem5::SparcISA::SparcStaticInst::printReg().

◆ hpriv

Bitfield<2> gem5::SparcISA::hpriv

◆ ibe

Bitfield<10> gem5::SparcISA::ibe

Definition at line 123 of file misc.hh.

◆ id

Bitfield<11> gem5::SparcISA::id

Definition at line 124 of file misc.hh.

◆ MaxGL

const int gem5::SparcISA::MaxGL = 3

◆ MaxPGL

const int gem5::SparcISA::MaxPGL = 2

Definition at line 41 of file sparc_traits.hh.

Referenced by doNormalFault().

◆ MaxPTL

const int gem5::SparcISA::MaxPTL = 2

Definition at line 38 of file sparc_traits.hh.

Referenced by gem5::SparcISA::SparcFaultBase::invoke().

◆ MaxTL

const int gem5::SparcISA::MaxTL = 6

◆ mm

Bitfield<7, 6> gem5::SparcISA::mm

Definition at line 132 of file misc.hh.

Referenced by QTIsaac< ALPHA >::isaac().

◆ n

Bitfield< 3 > gem5::SparcISA::n

Definition at line 140 of file misc.hh.

Referenced by gem5::SparcISA::SparcStaticInst::passesCondition().

◆ numFillInsts

const int gem5::SparcISA::numFillInsts = 32

◆ NumFloatArchRegs

const int gem5::SparcISA::NumFloatArchRegs = NumFloatRegs

Definition at line 39 of file float.hh.

Referenced by gem5::SparcISA::ISA::copyRegsFrom().

◆ NumFloatRegs

const int gem5::SparcISA::NumFloatRegs = 64

Definition at line 38 of file float.hh.

Referenced by gem5::SparcISA::ISA::ISA().

◆ NumIntRegs

const int gem5::SparcISA::NumIntRegs = (MaxGL + 1) * 8 + NWindows * 16 + NumMicroIntRegs

◆ NumMiscRegs

const int gem5::SparcISA::NumMiscRegs = MISCREG_NUMMISCREGS

Definition at line 173 of file misc.hh.

Referenced by gem5::getMiscRegName(), and gem5::SparcISA::ISA::ISA().

◆ numSpillInsts

const int gem5::SparcISA::numSpillInsts = 32

Definition at line 43 of file handlers.hh.

Referenced by gem5::Sparc32Process::argsInit(), and gem5::Sparc64Process::argsInit().

◆ NumVecElemPerVecReg

constexpr unsigned gem5::SparcISA::NumVecElemPerVecReg = ::gem5::DummyNumVecElemPerVecReg
constexpr

Definition at line 44 of file vecregs.hh.

◆ NWindows

const int gem5::SparcISA::NWindows = 8

◆ PAddrImplMask

const Addr gem5::SparcISA::PAddrImplMask = 0x000000FFFFFFFFFFULL

Definition at line 51 of file tlb.hh.

◆ PageBytes

const Addr gem5::SparcISA::PageBytes = 1ULL << PageShift

◆ PageShift

const Addr gem5::SparcISA::PageShift = 13

Definition at line 40 of file page_size.hh.

◆ pef

Bitfield<4> gem5::SparcISA::pef

Definition at line 131 of file misc.hh.

◆ pid0

Bitfield<10> gem5::SparcISA::pid0

Definition at line 135 of file misc.hh.

◆ pid1

Bitfield<11> gem5::SparcISA::pid1

Definition at line 136 of file misc.hh.

◆ priv

Bitfield<2> gem5::SparcISA::priv

Definition at line 129 of file misc.hh.

Referenced by doREDFault().

◆ PstateMask

const PSTATE gem5::SparcISA::PstateMask = buildPstateMask()
static

◆ red

Bitfield<5> gem5::SparcISA::red

◆ ReturnAddressReg

const int gem5::SparcISA::ReturnAddressReg = INTREG_I7

Definition at line 71 of file int.hh.

◆ ReturnValueReg

const int gem5::SparcISA::ReturnValueReg = INTREG_O0

◆ spillHandler32

const MachInst gem5::SparcISA::spillHandler32[numSpillInsts]

Definition at line 153 of file handlers.hh.

Referenced by gem5::Sparc32Process::argsInit().

◆ spillHandler64

const MachInst gem5::SparcISA::spillHandler64[numSpillInsts]

Definition at line 117 of file handlers.hh.

Referenced by gem5::Sparc64Process::argsInit().

◆ StackPointerReg

const int gem5::SparcISA::StackPointerReg = INTREG_O6

◆ StartVAddrHole

const Addr gem5::SparcISA::StartVAddrHole = 0x0000800000000000ULL

Definition at line 48 of file tlb.hh.

Referenced by gem5::SparcISA::TLB::validVirtualAddress().

◆ SyscallPseudoReturnReg

const int gem5::SparcISA::SyscallPseudoReturnReg = INTREG_O1

◆ tle

Bitfield<8> gem5::SparcISA::tle

Definition at line 133 of file misc.hh.

◆ v

Bitfield< 1 > gem5::SparcISA::v

Definition at line 143 of file misc.hh.

Referenced by gem5::SparcISA::SparcStaticInst::passesCondition().

◆ VAddrAMask

const Addr gem5::SparcISA::VAddrAMask = 0xFFFFFFFFULL

Definition at line 50 of file tlb.hh.

Referenced by gem5::SparcISA::TLB::translateFunctional().

◆ z

Bitfield< 2 > gem5::SparcISA::z

Definition at line 142 of file misc.hh.

Referenced by gem5::SparcISA::SparcStaticInst::passesCondition().

gem5::SparcISA::OverflowSet
@ OverflowSet
Definition: static_inst.hh:63
gem5::SparcISA::Less
@ Less
Definition: static_inst.hh:55
gem5::SparcISA::Never
@ Never
Definition: static_inst.hh:49
gem5::SparcISA::CarryClear
@ CarryClear
Definition: static_inst.hh:58
gem5::SparcISA::CarrySet
@ CarrySet
Definition: static_inst.hh:59
gem5::SparcISA::NotEqual
@ NotEqual
Definition: static_inst.hh:50
gem5::SparcISA::Equal
@ Equal
Definition: static_inst.hh:51
gem5::SparcISA::OverflowClear
@ OverflowClear
Definition: static_inst.hh:62
gem5::SparcISA::LessOrEqual
@ LessOrEqual
Definition: static_inst.hh:53
gem5::SparcISA::LessOrEqualUnsigned
@ LessOrEqualUnsigned
Definition: static_inst.hh:57
gem5::SparcISA::GreaterUnsigned
@ GreaterUnsigned
Definition: static_inst.hh:56
gem5::SparcISA::GreaterOrEqual
@ GreaterOrEqual
Definition: static_inst.hh:54
gem5::SparcISA::Greater
@ Greater
Definition: static_inst.hh:52
gem5::SparcISA::Positive
@ Positive
Definition: static_inst.hh:60
gem5::SparcISA::Negative
@ Negative
Definition: static_inst.hh:61
gem5::SparcISA::Always
@ Always
Definition: static_inst.hh:48

Generated on Tue Sep 21 2021 12:32:20 for gem5 by doxygen 1.8.17