gem5  v21.1.0.2
Classes | Namespaces | Enumerations | Functions
ns_gige_reg.h File Reference

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Classes

struct  gem5::ns_desc32
 
struct  gem5::ns_desc64
 

Namespaces

 gem5
 Reference material can be found at the JEDEC website: UFS standard http://www.jedec.org/standards-documents/results/jesd220 UFS HCI specification http://www.jedec.org/standards-documents/results/jesd223.
 

Enumerations

enum  gem5::DeviceRegisterAddress {
  gem5::CR = 0x00, gem5::CFGR = 0x04, gem5::MEAR = 0x08, gem5::PTSCR = 0x0c,
  gem5::ISR = 0x10, gem5::IMR = 0x14, gem5::IER = 0x18, gem5::IHR = 0x1c,
  gem5::TXDP = 0x20, gem5::TXDP_HI = 0x24, gem5::TX_CFG = 0x28, gem5::GPIOR = 0x2c,
  gem5::RXDP = 0x30, gem5::RXDP_HI = 0x34, gem5::RX_CFG = 0x38, gem5::PQCR = 0x3c,
  gem5::WCSR = 0x40, gem5::PCR = 0x44, gem5::RFCR = 0x48, gem5::RFDR = 0x4c,
  gem5::BRAR = 0x50, gem5::BRDR = 0x54, gem5::SRR = 0x58, gem5::MIBC = 0x5c,
  gem5::MIB_START = 0x60, gem5::MIB_END = 0x88, gem5::VRCR = 0xbc, gem5::VTCR = 0xc0,
  gem5::VDR = 0xc4, gem5::CCSR = 0xcc, gem5::TBICR = 0xe0, gem5::TBISR = 0xe4,
  gem5::TANAR = 0xe8, gem5::TANLPAR = 0xec, gem5::TANER = 0xf0, gem5::TESR = 0xf4,
  gem5::M5REG = 0xf8, gem5::LAST = 0xf8, gem5::RESERVED = 0xfc
}
 
enum  gem5::ChipCommandRegister {
  gem5::CR_TXE = 0x00000001, gem5::CR_TXD = 0x00000002, gem5::CR_RXE = 0x00000004, gem5::CR_RXD = 0x00000008,
  gem5::CR_TXR = 0x00000010, gem5::CR_RXR = 0x00000020, gem5::CR_SWI = 0x00000080, gem5::CR_RST = 0x00000100
}
 
enum  gem5::ConfigurationRegisters {
  gem5::CFGR_ZERO = 0x00000000, gem5::CFGR_LNKSTS = 0x80000000, gem5::CFGR_SPDSTS = 0x60000000, gem5::CFGR_SPDSTS1 = 0x40000000,
  gem5::CFGR_SPDSTS0 = 0x20000000, gem5::CFGR_DUPSTS = 0x10000000, gem5::CFGR_TBI_EN = 0x01000000, gem5::CFGR_RESERVED = 0x0e000000,
  gem5::CFGR_MODE_1000 = 0x00400000, gem5::CFGR_AUTO_1000 = 0x00200000, gem5::CFGR_PINT_CTL = 0x001c0000, gem5::CFGR_PINT_DUPSTS = 0x00100000,
  gem5::CFGR_PINT_LNKSTS = 0x00080000, gem5::CFGR_PINT_SPDSTS = 0x00040000, gem5::CFGR_TMRTEST = 0x00020000, gem5::CFGR_MRM_DIS = 0x00010000,
  gem5::CFGR_MWI_DIS = 0x00008000, gem5::CFGR_T64ADDR = 0x00004000, gem5::CFGR_PCI64_DET = 0x00002000, gem5::CFGR_DATA64_EN = 0x00001000,
  gem5::CFGR_M64ADDR = 0x00000800, gem5::CFGR_PHY_RST = 0x00000400, gem5::CFGR_PHY_DIS = 0x00000200, gem5::CFGR_EXTSTS_EN = 0x00000100,
  gem5::CFGR_REQALG = 0x00000080, gem5::CFGR_SB = 0x00000040, gem5::CFGR_POW = 0x00000020, gem5::CFGR_EXD = 0x00000010,
  gem5::CFGR_PESEL = 0x00000008, gem5::CFGR_BROM_DIS = 0x00000004, gem5::CFGR_EXT_125 = 0x00000002, gem5::CFGR_BEM = 0x00000001
}
 
enum  gem5::EEPROMAccessRegister {
  gem5::MEAR_EEDI = 0x00000001, gem5::MEAR_EEDO = 0x00000002, gem5::MEAR_EECLK = 0x00000004, gem5::MEAR_EESEL = 0x00000008,
  gem5::MEAR_MDIO = 0x00000010, gem5::MEAR_MDDIR = 0x00000020, gem5::MEAR_MDC = 0x00000040
}
 
enum  gem5::PCITestControlRegister {
  gem5::PTSCR_EEBIST_FAIL = 0x00000001, gem5::PTSCR_EEBIST_EN = 0x00000002, gem5::PTSCR_EELOAD_EN = 0x00000004, gem5::PTSCR_RBIST_FAIL = 0x000001b8,
  gem5::PTSCR_RBIST_DONE = 0x00000200, gem5::PTSCR_RBIST_EN = 0x00000400, gem5::PTSCR_RBIST_RST = 0x00002000, gem5::PTSCR_RBIST_RDONLY = 0x000003f9
}
 
enum  gem5::InterruptStatusRegister {
  gem5::ISR_RESERVE = 0x80000000, gem5::ISR_TXDESC3 = 0x40000000, gem5::ISR_TXDESC2 = 0x20000000, gem5::ISR_TXDESC1 = 0x10000000,
  gem5::ISR_TXDESC0 = 0x08000000, gem5::ISR_RXDESC3 = 0x04000000, gem5::ISR_RXDESC2 = 0x02000000, gem5::ISR_RXDESC1 = 0x01000000,
  gem5::ISR_RXDESC0 = 0x00800000, gem5::ISR_TXRCMP = 0x00400000, gem5::ISR_RXRCMP = 0x00200000, gem5::ISR_DPERR = 0x00100000,
  gem5::ISR_SSERR = 0x00080000, gem5::ISR_RMABT = 0x00040000, gem5::ISR_RTAB = 0x00020000, gem5::ISR_RXSOVR = 0x00010000,
  gem5::ISR_HIBINT = 0x00008000, gem5::ISR_PHY = 0x00004000, gem5::ISR_PME = 0x00002000, gem5::ISR_SWI = 0x00001000,
  gem5::ISR_MIB = 0x00000800, gem5::ISR_TXURN = 0x00000400, gem5::ISR_TXIDLE = 0x00000200, gem5::ISR_TXERR = 0x00000100,
  gem5::ISR_TXDESC = 0x00000080, gem5::ISR_TXOK = 0x00000040, gem5::ISR_RXORN = 0x00000020, gem5::ISR_RXIDLE = 0x00000010,
  gem5::ISR_RXEARLY = 0x00000008, gem5::ISR_RXERR = 0x00000004, gem5::ISR_RXDESC = 0x00000002, gem5::ISR_RXOK = 0x00000001,
  gem5::ISR_ALL = 0x7FFFFFFF, gem5::ISR_DELAY, gem5::ISR_NODELAY = (ISR_ALL & ~ISR_DELAY), gem5::ISR_IMPL,
  gem5::ISR_NOIMPL = (ISR_ALL & ~ISR_IMPL)
}
 
enum  gem5::TransmitConfigurationRegister {
  gem5::TX_CFG_CSI = 0x80000000, gem5::TX_CFG_HBI = 0x40000000, gem5::TX_CFG_MLB = 0x20000000, gem5::TX_CFG_ATP = 0x10000000,
  gem5::TX_CFG_ECRETRY = 0x00800000, gem5::TX_CFG_BRST_DIS = 0x00080000, gem5::TX_CFG_MXDMA1024 = 0x00000000, gem5::TX_CFG_MXDMA512 = 0x00700000,
  gem5::TX_CFG_MXDMA256 = 0x00600000, gem5::TX_CFG_MXDMA128 = 0x00500000, gem5::TX_CFG_MXDMA64 = 0x00400000, gem5::TX_CFG_MXDMA32 = 0x00300000,
  gem5::TX_CFG_MXDMA16 = 0x00200000, gem5::TX_CFG_MXDMA8 = 0x00100000, gem5::TX_CFG_MXDMA = 0x00700000, gem5::TX_CFG_FLTH_MASK = 0x0000ff00,
  gem5::TX_CFG_DRTH_MASK = 0x000000ff
}
 
enum  gem5::GeneralPurposeIOControlRegister {
  gem5::GPIOR_UNUSED = 0xffff8000, gem5::GPIOR_GP5_IN = 0x00004000, gem5::GPIOR_GP4_IN = 0x00002000, gem5::GPIOR_GP3_IN = 0x00001000,
  gem5::GPIOR_GP2_IN = 0x00000800, gem5::GPIOR_GP1_IN = 0x00000400, gem5::GPIOR_GP5_OE = 0x00000200, gem5::GPIOR_GP4_OE = 0x00000100,
  gem5::GPIOR_GP3_OE = 0x00000080, gem5::GPIOR_GP2_OE = 0x00000040, gem5::GPIOR_GP1_OE = 0x00000020, gem5::GPIOR_GP5_OUT = 0x00000010,
  gem5::GPIOR_GP4_OUT = 0x00000008, gem5::GPIOR_GP3_OUT = 0x00000004, gem5::GPIOR_GP2_OUT = 0x00000002, gem5::GPIOR_GP1_OUT = 0x00000001
}
 
enum  gem5::ReceiveConfigurationRegister {
  gem5::RX_CFG_AEP = 0x80000000, gem5::RX_CFG_ARP = 0x40000000, gem5::RX_CFG_STRIPCRC = 0x20000000, gem5::RX_CFG_RX_FD = 0x10000000,
  gem5::RX_CFG_ALP = 0x08000000, gem5::RX_CFG_AIRL = 0x04000000, gem5::RX_CFG_MXDMA512 = 0x00700000, gem5::RX_CFG_MXDMA = 0x00700000,
  gem5::RX_CFG_DRTH = 0x0000003e, gem5::RX_CFG_DRTH0 = 0x00000002
}
 
enum  gem5::PauseControlStatusRegister {
  gem5::PCR_PSEN = (1 << 31), gem5::PCR_PS_MCAST = (1 << 30), gem5::PCR_PS_DA = (1 << 29), gem5::PCR_STHI_8 = (3 << 23),
  gem5::PCR_STLO_4 = (1 << 23), gem5::PCR_FFHI_8K = (3 << 21), gem5::PCR_FFLO_4K = (1 << 21), gem5::PCR_PAUSE_CNT = 0xFFFE
}
 
enum  gem5::ReceiveFilterMatchControlRegister {
  gem5::RFCR_RFEN = 0x80000000, gem5::RFCR_AAB = 0x40000000, gem5::RFCR_AAM = 0x20000000, gem5::RFCR_AAU = 0x10000000,
  gem5::RFCR_APM = 0x08000000, gem5::RFCR_APAT = 0x07800000, gem5::RFCR_APAT3 = 0x04000000, gem5::RFCR_APAT2 = 0x02000000,
  gem5::RFCR_APAT1 = 0x01000000, gem5::RFCR_APAT0 = 0x00800000, gem5::RFCR_AARP = 0x00400000, gem5::RFCR_MHEN = 0x00200000,
  gem5::RFCR_UHEN = 0x00100000, gem5::RFCR_ULM = 0x00080000, gem5::RFCR_RFADDR = 0x000003ff
}
 
enum  gem5::ReceiveFilterMatchDataRegister { gem5::RFDR_BMASK = 0x00030000, gem5::RFDR_RFDATA0 = 0x000000ff, gem5::RFDR_RFDATA1 = 0x0000ff00 }
 
enum  gem5::ManagementInformationBaseControlRegister { gem5::MIBC_MIBS = 0x00000008, gem5::MIBC_ACLR = 0x00000004, gem5::MIBC_FRZ = 0x00000002, gem5::MIBC_WRN = 0x00000001 }
 
enum  gem5::VLANIPReceiveControlRegister {
  gem5::VRCR_RUDPE = 0x00000080, gem5::VRCR_RTCPE = 0x00000040, gem5::VRCR_RIPE = 0x00000020, gem5::VRCR_IPEN = 0x00000010,
  gem5::VRCR_DUTF = 0x00000008, gem5::VRCR_DVTF = 0x00000004, gem5::VRCR_VTREN = 0x00000002, gem5::VRCR_VTDEN = 0x00000001
}
 
enum  gem5::VLANIPTransmitControlRegister { gem5::VTCR_PPCHK = 0x00000008, gem5::VTCR_GCHK = 0x00000004, gem5::VTCR_VPPTI = 0x00000002, gem5::VTCR_VGTI = 0x00000001 }
 
enum  gem5::ClockrunControlStatusRegister { gem5::CCSR_CLKRUN_EN = 0x00000001 }
 
enum  gem5::TBIControlRegister { gem5::TBICR_MR_LOOPBACK = 0x00004000, gem5::TBICR_MR_AN_ENABLE = 0x00001000, gem5::TBICR_MR_RESTART_AN = 0x00000200 }
 
enum  gem5::TBIStatusRegister { gem5::TBISR_MR_LINK_STATUS = 0x00000020, gem5::TBISR_MR_AN_COMPLETE = 0x00000004 }
 
enum  gem5::TBIAutoNegotiationAdvertisementRegister {
  gem5::TANAR_NP = 0x00008000, gem5::TANAR_RF2 = 0x00002000, gem5::TANAR_RF1 = 0x00001000, gem5::TANAR_PS2 = 0x00000100,
  gem5::TANAR_PS1 = 0x00000080, gem5::TANAR_HALF_DUP = 0x00000040, gem5::TANAR_FULL_DUP = 0x00000020, gem5::TANAR_UNUSED = 0x00000E1F
}
 
enum  gem5::M5ControlRegister { gem5::M5REG_RESERVED = 0xfffffffc, gem5::M5REG_RSS = 0x00000004, gem5::M5REG_RX_THREAD = 0x00000002, gem5::M5REG_TX_THREAD = 0x00000001 }
 
enum  gem5::CMDSTSFlatsForDescriptors {
  gem5::CMDSTS_OWN = 0x80000000, gem5::CMDSTS_MORE = 0x40000000, gem5::CMDSTS_INTR = 0x20000000, gem5::CMDSTS_ERR = 0x10000000,
  gem5::CMDSTS_OK = 0x08000000, gem5::CMDSTS_LEN_MASK = 0x0000ffff, gem5::CMDSTS_DEST_MASK = 0x01800000, gem5::CMDSTS_DEST_SELF = 0x00800000,
  gem5::CMDSTS_DEST_MULTI = 0x01000000
}
 
enum  gem5::ExtendedFlagsForDescriptors {
  gem5::EXTSTS_UDPERR = 0x00400000, gem5::EXTSTS_UDPPKT = 0x00200000, gem5::EXTSTS_TCPERR = 0x00100000, gem5::EXTSTS_TCPPKT = 0x00080000,
  gem5::EXTSTS_IPERR = 0x00040000, gem5::EXTSTS_IPPKT = 0x00020000
}
 

Functions

static int gem5::SPDSTS_POLARITY (int lnksts)
 

Detailed Description

Ethernet device register definitions for the National Semiconductor DP83820 Ethernet controller

Definition in file ns_gige_reg.h.


Generated on Tue Sep 21 2021 12:26:35 for gem5 by doxygen 1.8.17