gem5 v24.0.0.0
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ns_gige_reg.h
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1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
34#ifndef __DEV_NS_GIGE_REG_H__
35#define __DEV_NS_GIGE_REG_H__
36
37namespace gem5
38{
39
40/* Device Register Address Map */
42{
43 CR = 0x00,
44 CFGR = 0x04,
45 MEAR = 0x08,
46 PTSCR = 0x0c,
47 ISR = 0x10,
48 IMR = 0x14,
49 IER = 0x18,
50 IHR = 0x1c,
51 TXDP = 0x20,
52 TXDP_HI = 0x24,
53 TX_CFG = 0x28,
54 GPIOR = 0x2c,
55 RXDP = 0x30,
56 RXDP_HI = 0x34,
57 RX_CFG = 0x38,
58 PQCR = 0x3c,
59 WCSR = 0x40,
60 PCR = 0x44,
61 RFCR = 0x48,
62 RFDR = 0x4c,
63 BRAR = 0x50,
64 BRDR = 0x54,
65 SRR = 0x58,
66 MIBC = 0x5c,
67 MIB_START = 0x60,
68 MIB_END = 0x88,
69 VRCR = 0xbc,
70 VTCR = 0xc0,
71 VDR = 0xc4,
72 CCSR = 0xcc,
73 TBICR = 0xe0,
74 TBISR = 0xe4,
75 TANAR = 0xe8,
76 TANLPAR = 0xec,
77 TANER = 0xf0,
78 TESR = 0xf4,
79 M5REG = 0xf8,
80 LAST = 0xf8,
81 RESERVED = 0xfc
82};
83
84/* Chip Command Register */
86{
87 CR_TXE = 0x00000001,
88 CR_TXD = 0x00000002,
89 CR_RXE = 0x00000004,
90 CR_RXD = 0x00000008,
91 CR_TXR = 0x00000010,
92 CR_RXR = 0x00000020,
93 CR_SWI = 0x00000080,
94 CR_RST = 0x00000100
95};
96
97/* configuration register */
99{
100 CFGR_ZERO = 0x00000000,
101 CFGR_LNKSTS = 0x80000000,
102 CFGR_SPDSTS = 0x60000000,
103 CFGR_SPDSTS1 = 0x40000000,
104 CFGR_SPDSTS0 = 0x20000000,
105 CFGR_DUPSTS = 0x10000000,
106 CFGR_TBI_EN = 0x01000000,
107 CFGR_RESERVED = 0x0e000000,
108 CFGR_MODE_1000 = 0x00400000,
109 CFGR_AUTO_1000 = 0x00200000,
110 CFGR_PINT_CTL = 0x001c0000,
111 CFGR_PINT_DUPSTS = 0x00100000,
112 CFGR_PINT_LNKSTS = 0x00080000,
113 CFGR_PINT_SPDSTS = 0x00040000,
114 CFGR_TMRTEST = 0x00020000,
115 CFGR_MRM_DIS = 0x00010000,
116 CFGR_MWI_DIS = 0x00008000,
117 CFGR_T64ADDR = 0x00004000,
118 CFGR_PCI64_DET = 0x00002000,
119 CFGR_DATA64_EN = 0x00001000,
120 CFGR_M64ADDR = 0x00000800,
121 CFGR_PHY_RST = 0x00000400,
122 CFGR_PHY_DIS = 0x00000200,
123 CFGR_EXTSTS_EN = 0x00000100,
124 CFGR_REQALG = 0x00000080,
125 CFGR_SB = 0x00000040,
126 CFGR_POW = 0x00000020,
127 CFGR_EXD = 0x00000010,
128 CFGR_PESEL = 0x00000008,
129 CFGR_BROM_DIS = 0x00000004,
130 CFGR_EXT_125 = 0x00000002,
131 CFGR_BEM = 0x00000001
133
134/* EEPROM access register */
136{
137 MEAR_EEDI = 0x00000001,
138 MEAR_EEDO = 0x00000002,
139 MEAR_EECLK = 0x00000004,
140 MEAR_EESEL = 0x00000008,
141 MEAR_MDIO = 0x00000010,
142 MEAR_MDDIR = 0x00000020,
143 MEAR_MDC = 0x00000040,
144};
145
146/* PCI test control register */
148{
149 PTSCR_EEBIST_FAIL = 0x00000001,
150 PTSCR_EEBIST_EN = 0x00000002,
151 PTSCR_EELOAD_EN = 0x00000004,
152 PTSCR_RBIST_FAIL = 0x000001b8,
153 PTSCR_RBIST_DONE = 0x00000200,
154 PTSCR_RBIST_EN = 0x00000400,
155 PTSCR_RBIST_RST = 0x00002000,
156 PTSCR_RBIST_RDONLY = 0x000003f9
158
159/* interrupt status register */
161{
162 ISR_RESERVE = 0x80000000,
163 ISR_TXDESC3 = 0x40000000,
164 ISR_TXDESC2 = 0x20000000,
165 ISR_TXDESC1 = 0x10000000,
166 ISR_TXDESC0 = 0x08000000,
167 ISR_RXDESC3 = 0x04000000,
168 ISR_RXDESC2 = 0x02000000,
169 ISR_RXDESC1 = 0x01000000,
170 ISR_RXDESC0 = 0x00800000,
171 ISR_TXRCMP = 0x00400000,
172 ISR_RXRCMP = 0x00200000,
173 ISR_DPERR = 0x00100000,
174 ISR_SSERR = 0x00080000,
175 ISR_RMABT = 0x00040000,
176 ISR_RTAB = 0x00020000,
177 ISR_RXSOVR = 0x00010000,
178 ISR_HIBINT = 0x00008000,
179 ISR_PHY = 0x00004000,
180 ISR_PME = 0x00002000,
181 ISR_SWI = 0x00001000,
182 ISR_MIB = 0x00000800,
183 ISR_TXURN = 0x00000400,
184 ISR_TXIDLE = 0x00000200,
185 ISR_TXERR = 0x00000100,
186 ISR_TXDESC = 0x00000080,
187 ISR_TXOK = 0x00000040,
188 ISR_RXORN = 0x00000020,
189 ISR_RXIDLE = 0x00000010,
190 ISR_RXEARLY = 0x00000008,
191 ISR_RXERR = 0x00000004,
192 ISR_RXDESC = 0x00000002,
193 ISR_RXOK = 0x00000001,
194 ISR_ALL = 0x7FFFFFFF,
202
203/* transmit configuration register */
205{
206 TX_CFG_CSI = 0x80000000,
207 TX_CFG_HBI = 0x40000000,
208 TX_CFG_MLB = 0x20000000,
209 TX_CFG_ATP = 0x10000000,
210 TX_CFG_ECRETRY = 0x00800000,
211 TX_CFG_BRST_DIS = 0x00080000,
212 TX_CFG_MXDMA1024 = 0x00000000,
213 TX_CFG_MXDMA512 = 0x00700000,
214 TX_CFG_MXDMA256 = 0x00600000,
215 TX_CFG_MXDMA128 = 0x00500000,
216 TX_CFG_MXDMA64 = 0x00400000,
217 TX_CFG_MXDMA32 = 0x00300000,
218 TX_CFG_MXDMA16 = 0x00200000,
219 TX_CFG_MXDMA8 = 0x00100000,
220 TX_CFG_MXDMA = 0x00700000,
221
222 TX_CFG_FLTH_MASK = 0x0000ff00,
223 TX_CFG_DRTH_MASK = 0x000000ff
225
226/*general purpose I/O control register */
228{
229 GPIOR_UNUSED = 0xffff8000,
230 GPIOR_GP5_IN = 0x00004000,
231 GPIOR_GP4_IN = 0x00002000,
232 GPIOR_GP3_IN = 0x00001000,
233 GPIOR_GP2_IN = 0x00000800,
234 GPIOR_GP1_IN = 0x00000400,
235 GPIOR_GP5_OE = 0x00000200,
236 GPIOR_GP4_OE = 0x00000100,
237 GPIOR_GP3_OE = 0x00000080,
238 GPIOR_GP2_OE = 0x00000040,
239 GPIOR_GP1_OE = 0x00000020,
240 GPIOR_GP5_OUT = 0x00000010,
241 GPIOR_GP4_OUT = 0x00000008,
242 GPIOR_GP3_OUT = 0x00000004,
243 GPIOR_GP2_OUT = 0x00000002,
244 GPIOR_GP1_OUT = 0x00000001
246
247/* receive configuration register */
249{
250 RX_CFG_AEP = 0x80000000,
251 RX_CFG_ARP = 0x40000000,
252 RX_CFG_STRIPCRC = 0x20000000,
253 RX_CFG_RX_FD = 0x10000000,
254 RX_CFG_ALP = 0x08000000,
255 RX_CFG_AIRL = 0x04000000,
256 RX_CFG_MXDMA512 = 0x00700000,
257 RX_CFG_MXDMA = 0x00700000,
258 RX_CFG_DRTH = 0x0000003e,
259 RX_CFG_DRTH0 = 0x00000002
261
262/* pause control status register */
264{
265 PCR_PSEN = (1 << 31),
266 PCR_PS_MCAST = (1 << 30),
267 PCR_PS_DA = (1 << 29),
268 PCR_STHI_8 = (3 << 23),
269 PCR_STLO_4 = (1 << 23),
270 PCR_FFHI_8K = (3 << 21),
271 PCR_FFLO_4K = (1 << 21),
272 PCR_PAUSE_CNT = 0xFFFE
274
275/*receive filter/match control register */
277{
278 RFCR_RFEN = 0x80000000,
279 RFCR_AAB = 0x40000000,
280 RFCR_AAM = 0x20000000,
281 RFCR_AAU = 0x10000000,
282 RFCR_APM = 0x08000000,
283 RFCR_APAT = 0x07800000,
284 RFCR_APAT3 = 0x04000000,
285 RFCR_APAT2 = 0x02000000,
286 RFCR_APAT1 = 0x01000000,
287 RFCR_APAT0 = 0x00800000,
288 RFCR_AARP = 0x00400000,
289 RFCR_MHEN = 0x00200000,
290 RFCR_UHEN = 0x00100000,
291 RFCR_ULM = 0x00080000,
292 RFCR_RFADDR = 0x000003ff
294
295/* receive filter/match data register */
297{
298 RFDR_BMASK = 0x00030000,
299 RFDR_RFDATA0 = 0x000000ff,
300 RFDR_RFDATA1 = 0x0000ff00
302
303/* management information base control register */
305{
306 MIBC_MIBS = 0x00000008,
307 MIBC_ACLR = 0x00000004,
308 MIBC_FRZ = 0x00000002,
309 MIBC_WRN = 0x00000001
311
312/* VLAN/IP receive control register */
314{
315 VRCR_RUDPE = 0x00000080,
316 VRCR_RTCPE = 0x00000040,
317 VRCR_RIPE = 0x00000020,
318 VRCR_IPEN = 0x00000010,
319 VRCR_DUTF = 0x00000008,
320 VRCR_DVTF = 0x00000004,
321 VRCR_VTREN = 0x00000002,
322 VRCR_VTDEN = 0x00000001
324
325/* VLAN/IP transmit control register */
327{
328 VTCR_PPCHK = 0x00000008,
329 VTCR_GCHK = 0x00000004,
330 VTCR_VPPTI = 0x00000002,
331 VTCR_VGTI = 0x00000001
333
334/* Clockrun Control/Status Register */
339
340/* TBI control register */
342{
343 TBICR_MR_LOOPBACK = 0x00004000,
344 TBICR_MR_AN_ENABLE = 0x00001000,
345 TBICR_MR_RESTART_AN = 0x00000200
347
348/* TBI status register */
350{
352 TBISR_MR_AN_COMPLETE = 0x00000004
354
355/* TBI auto-negotiation advertisement register */
357{
358 TANAR_NP = 0x00008000,
359 TANAR_RF2 = 0x00002000,
360 TANAR_RF1 = 0x00001000,
361 TANAR_PS2 = 0x00000100,
362 TANAR_PS1 = 0x00000080,
363 TANAR_HALF_DUP = 0x00000040,
364 TANAR_FULL_DUP = 0x00000020,
365 TANAR_UNUSED = 0x00000E1F
367
368/* M5 control register */
370{
371 M5REG_RESERVED = 0xfffffffc,
372 M5REG_RSS = 0x00000004,
373 M5REG_RX_THREAD = 0x00000002,
374 M5REG_TX_THREAD = 0x00000001
376
378{
379 uint32_t link; /* link field to next descriptor in linked list */
380 uint32_t bufptr; /* pointer to the first fragment or buffer */
381 uint32_t cmdsts; /* command/status field */
382 uint32_t extsts; /* extended status field for VLAN and IP info */
383};
384
386{
387 uint64_t link; /* link field to next descriptor in linked list */
388 uint64_t bufptr; /* pointer to the first fragment or buffer */
389 uint32_t cmdsts; /* command/status field */
390 uint32_t extsts; /* extended status field for VLAN and IP info */
391};
392
393/* cmdsts flags for descriptors */
395{
396 CMDSTS_OWN = 0x80000000,
397 CMDSTS_MORE = 0x40000000,
398 CMDSTS_INTR = 0x20000000,
399 CMDSTS_ERR = 0x10000000,
400 CMDSTS_OK = 0x08000000,
401 CMDSTS_LEN_MASK = 0x0000ffff,
402
403 CMDSTS_DEST_MASK = 0x01800000,
404 CMDSTS_DEST_SELF = 0x00800000,
405 CMDSTS_DEST_MULTI = 0x01000000
407
408/* extended flags for descriptors */
410{
411 EXTSTS_UDPERR = 0x00400000,
412 EXTSTS_UDPPKT = 0x00200000,
413 EXTSTS_TCPERR = 0x00100000,
414 EXTSTS_TCPPKT = 0x00080000,
415 EXTSTS_IPERR = 0x00040000,
416 EXTSTS_IPPKT = 0x00020000
418
419/* speed status */
420static inline int
422{
424 (lnksts ? CFGR_LNKSTS : CFGR_ZERO));
425}
426
427} // namespace gem5
428
429#endif /* __DEV_NS_GIGE_REG_H__ */
Copyright (c) 2024 - Pranith Kumar Copyright (c) 2020 Inria All rights reserved.
Definition binary32.hh:36
ClockrunControlStatusRegister
@ CCSR_CLKRUN_EN
ExtendedFlagsForDescriptors
@ EXTSTS_TCPERR
@ EXTSTS_IPERR
@ EXTSTS_TCPPKT
@ EXTSTS_UDPPKT
@ EXTSTS_UDPERR
@ EXTSTS_IPPKT
ReceiveConfigurationRegister
@ RX_CFG_AIRL
@ RX_CFG_ARP
@ RX_CFG_STRIPCRC
@ RX_CFG_ALP
@ RX_CFG_DRTH
@ RX_CFG_MXDMA512
@ RX_CFG_RX_FD
@ RX_CFG_MXDMA
@ RX_CFG_DRTH0
@ RX_CFG_AEP
TBIStatusRegister
@ TBISR_MR_AN_COMPLETE
@ TBISR_MR_LINK_STATUS
EEPROMAccessRegister
@ MEAR_MDDIR
@ MEAR_EEDO
@ MEAR_EESEL
@ MEAR_MDIO
@ MEAR_MDC
@ MEAR_EEDI
@ MEAR_EECLK
ChipCommandRegister
Definition ns_gige_reg.h:86
@ CR_RST
Definition ns_gige_reg.h:94
@ CR_TXD
Definition ns_gige_reg.h:88
@ CR_TXE
Definition ns_gige_reg.h:87
@ CR_TXR
Definition ns_gige_reg.h:91
@ CR_RXE
Definition ns_gige_reg.h:89
@ CR_SWI
Definition ns_gige_reg.h:93
@ CR_RXR
Definition ns_gige_reg.h:92
@ CR_RXD
Definition ns_gige_reg.h:90
ReceiveFilterMatchDataRegister
@ RFDR_RFDATA0
@ RFDR_BMASK
@ RFDR_RFDATA1
TBIAutoNegotiationAdvertisementRegister
@ TANAR_NP
@ TANAR_PS1
@ TANAR_RF2
@ TANAR_RF1
@ TANAR_HALF_DUP
@ TANAR_UNUSED
@ TANAR_FULL_DUP
@ TANAR_PS2
DeviceRegisterAddress
Definition ns_gige_reg.h:42
@ TBICR
Definition ns_gige_reg.h:73
@ GPIOR
Definition ns_gige_reg.h:54
@ TANLPAR
Definition ns_gige_reg.h:76
@ TXDP_HI
Definition ns_gige_reg.h:52
@ RXDP_HI
Definition ns_gige_reg.h:56
@ TANER
Definition ns_gige_reg.h:77
@ RESERVED
Definition ns_gige_reg.h:81
@ M5REG
Definition ns_gige_reg.h:79
@ RX_CFG
Definition ns_gige_reg.h:57
@ MIB_END
Definition ns_gige_reg.h:68
@ MIB_START
Definition ns_gige_reg.h:67
@ TANAR
Definition ns_gige_reg.h:75
@ TBISR
Definition ns_gige_reg.h:74
@ PTSCR
Definition ns_gige_reg.h:46
@ TX_CFG
Definition ns_gige_reg.h:53
PCITestControlRegister
@ PTSCR_RBIST_RDONLY
@ PTSCR_EEBIST_FAIL
@ PTSCR_EELOAD_EN
@ PTSCR_RBIST_EN
@ PTSCR_RBIST_FAIL
@ PTSCR_EEBIST_EN
@ PTSCR_RBIST_DONE
@ PTSCR_RBIST_RST
ManagementInformationBaseControlRegister
@ MIBC_FRZ
@ MIBC_MIBS
@ MIBC_ACLR
@ MIBC_WRN
ConfigurationRegisters
Definition ns_gige_reg.h:99
@ CFGR_PESEL
@ CFGR_TBI_EN
@ CFGR_SPDSTS1
@ CFGR_PINT_LNKSTS
@ CFGR_LNKSTS
@ CFGR_PCI64_DET
@ CFGR_BROM_DIS
@ CFGR_DUPSTS
@ CFGR_DATA64_EN
@ CFGR_PHY_RST
@ CFGR_M64ADDR
@ CFGR_SPDSTS0
@ CFGR_SPDSTS
@ CFGR_PINT_CTL
@ CFGR_EXT_125
@ CFGR_TMRTEST
@ CFGR_T64ADDR
@ CFGR_PINT_DUPSTS
@ CFGR_MWI_DIS
@ CFGR_MODE_1000
@ CFGR_PINT_SPDSTS
@ CFGR_AUTO_1000
@ CFGR_POW
@ CFGR_EXTSTS_EN
@ CFGR_BEM
@ CFGR_ZERO
@ CFGR_EXD
@ CFGR_REQALG
@ CFGR_SB
@ CFGR_PHY_DIS
@ CFGR_RESERVED
@ CFGR_MRM_DIS
M5ControlRegister
@ M5REG_RX_THREAD
@ M5REG_TX_THREAD
@ M5REG_RESERVED
@ M5REG_RSS
GeneralPurposeIOControlRegister
@ GPIOR_GP3_OE
@ GPIOR_GP5_IN
@ GPIOR_GP5_OE
@ GPIOR_GP1_OUT
@ GPIOR_GP4_OUT
@ GPIOR_GP2_OE
@ GPIOR_GP2_IN
@ GPIOR_GP1_OE
@ GPIOR_GP3_IN
@ GPIOR_GP5_OUT
@ GPIOR_GP4_OE
@ GPIOR_UNUSED
@ GPIOR_GP2_OUT
@ GPIOR_GP3_OUT
@ GPIOR_GP4_IN
@ GPIOR_GP1_IN
VLANIPReceiveControlRegister
@ VRCR_RUDPE
@ VRCR_RTCPE
@ VRCR_VTDEN
@ VRCR_DVTF
@ VRCR_DUTF
@ VRCR_VTREN
@ VRCR_RIPE
@ VRCR_IPEN
InterruptStatusRegister
@ ISR_RXDESC
@ ISR_RXRCMP
@ ISR_DPERR
@ ISR_TXDESC2
@ ISR_IMPL
@ ISR_RMABT
@ ISR_RXEARLY
@ ISR_NODELAY
@ ISR_TXDESC1
@ ISR_RXDESC2
@ ISR_TXDESC3
@ ISR_RXOK
@ ISR_PHY
@ ISR_DELAY
@ ISR_TXIDLE
@ ISR_TXDESC
@ ISR_RXDESC1
@ ISR_TXOK
@ ISR_MIB
@ ISR_RXDESC3
@ ISR_SWI
@ ISR_RESERVE
@ ISR_RXSOVR
@ ISR_TXDESC0
@ ISR_RXERR
@ ISR_TXERR
@ ISR_RXORN
@ ISR_TXRCMP
@ ISR_PME
@ ISR_NOIMPL
@ ISR_HIBINT
@ ISR_TXURN
@ ISR_ALL
@ ISR_SSERR
@ ISR_RXIDLE
@ ISR_RXDESC0
@ ISR_RTAB
ReceiveFilterMatchControlRegister
@ RFCR_APAT0
@ RFCR_APAT1
@ RFCR_APAT3
@ RFCR_UHEN
@ RFCR_APM
@ RFCR_ULM
@ RFCR_MHEN
@ RFCR_APAT
@ RFCR_AARP
@ RFCR_APAT2
@ RFCR_AAM
@ RFCR_AAU
@ RFCR_RFADDR
@ RFCR_AAB
@ RFCR_RFEN
TransmitConfigurationRegister
@ TX_CFG_ECRETRY
@ TX_CFG_MXDMA8
@ TX_CFG_MXDMA1024
@ TX_CFG_BRST_DIS
@ TX_CFG_FLTH_MASK
@ TX_CFG_MXDMA512
@ TX_CFG_HBI
@ TX_CFG_MXDMA
@ TX_CFG_MXDMA16
@ TX_CFG_CSI
@ TX_CFG_MXDMA128
@ TX_CFG_MXDMA32
@ TX_CFG_ATP
@ TX_CFG_DRTH_MASK
@ TX_CFG_MLB
@ TX_CFG_MXDMA256
@ TX_CFG_MXDMA64
CMDSTSFlatsForDescriptors
@ CMDSTS_OWN
@ CMDSTS_LEN_MASK
@ CMDSTS_OK
@ CMDSTS_INTR
@ CMDSTS_DEST_MASK
@ CMDSTS_DEST_SELF
@ CMDSTS_ERR
@ CMDSTS_DEST_MULTI
@ CMDSTS_MORE
static int SPDSTS_POLARITY(int lnksts)
PauseControlStatusRegister
@ PCR_STHI_8
@ PCR_PAUSE_CNT
@ PCR_PS_DA
@ PCR_PSEN
@ PCR_STLO_4
@ PCR_FFLO_4K
@ PCR_FFHI_8K
@ PCR_PS_MCAST
TBIControlRegister
@ TBICR_MR_LOOPBACK
@ TBICR_MR_AN_ENABLE
@ TBICR_MR_RESTART_AN
VLANIPTransmitControlRegister
@ VTCR_GCHK
@ VTCR_PPCHK
@ VTCR_VPPTI
@ VTCR_VGTI

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