gem5  v21.1.0.2
ns_gige_reg.h
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1 /*
2  * Copyright (c) 2004-2005 The Regents of The University of Michigan
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions are
7  * met: redistributions of source code must retain the above copyright
8  * notice, this list of conditions and the following disclaimer;
9  * redistributions in binary form must reproduce the above copyright
10  * notice, this list of conditions and the following disclaimer in the
11  * documentation and/or other materials provided with the distribution;
12  * neither the name of the copyright holders nor the names of its
13  * contributors may be used to endorse or promote products derived from
14  * this software without specific prior written permission.
15  *
16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27  */
28 
34 #ifndef __DEV_NS_GIGE_REG_H__
35 #define __DEV_NS_GIGE_REG_H__
36 
37 namespace gem5
38 {
39 
40 /* Device Register Address Map */
42 {
43  CR = 0x00,
44  CFGR = 0x04,
45  MEAR = 0x08,
46  PTSCR = 0x0c,
47  ISR = 0x10,
48  IMR = 0x14,
49  IER = 0x18,
50  IHR = 0x1c,
51  TXDP = 0x20,
52  TXDP_HI = 0x24,
53  TX_CFG = 0x28,
54  GPIOR = 0x2c,
55  RXDP = 0x30,
56  RXDP_HI = 0x34,
57  RX_CFG = 0x38,
58  PQCR = 0x3c,
59  WCSR = 0x40,
60  PCR = 0x44,
61  RFCR = 0x48,
62  RFDR = 0x4c,
63  BRAR = 0x50,
64  BRDR = 0x54,
65  SRR = 0x58,
66  MIBC = 0x5c,
67  MIB_START = 0x60,
68  MIB_END = 0x88,
69  VRCR = 0xbc,
70  VTCR = 0xc0,
71  VDR = 0xc4,
72  CCSR = 0xcc,
73  TBICR = 0xe0,
74  TBISR = 0xe4,
75  TANAR = 0xe8,
76  TANLPAR = 0xec,
77  TANER = 0xf0,
78  TESR = 0xf4,
79  M5REG = 0xf8,
80  LAST = 0xf8,
81  RESERVED = 0xfc
82 };
83 
84 /* Chip Command Register */
86 {
87  CR_TXE = 0x00000001,
88  CR_TXD = 0x00000002,
89  CR_RXE = 0x00000004,
90  CR_RXD = 0x00000008,
91  CR_TXR = 0x00000010,
92  CR_RXR = 0x00000020,
93  CR_SWI = 0x00000080,
94  CR_RST = 0x00000100
95 };
96 
97 /* configuration register */
99 {
100  CFGR_ZERO = 0x00000000,
101  CFGR_LNKSTS = 0x80000000,
102  CFGR_SPDSTS = 0x60000000,
103  CFGR_SPDSTS1 = 0x40000000,
104  CFGR_SPDSTS0 = 0x20000000,
105  CFGR_DUPSTS = 0x10000000,
106  CFGR_TBI_EN = 0x01000000,
107  CFGR_RESERVED = 0x0e000000,
108  CFGR_MODE_1000 = 0x00400000,
109  CFGR_AUTO_1000 = 0x00200000,
110  CFGR_PINT_CTL = 0x001c0000,
111  CFGR_PINT_DUPSTS = 0x00100000,
112  CFGR_PINT_LNKSTS = 0x00080000,
113  CFGR_PINT_SPDSTS = 0x00040000,
114  CFGR_TMRTEST = 0x00020000,
115  CFGR_MRM_DIS = 0x00010000,
116  CFGR_MWI_DIS = 0x00008000,
117  CFGR_T64ADDR = 0x00004000,
118  CFGR_PCI64_DET = 0x00002000,
119  CFGR_DATA64_EN = 0x00001000,
120  CFGR_M64ADDR = 0x00000800,
121  CFGR_PHY_RST = 0x00000400,
122  CFGR_PHY_DIS = 0x00000200,
123  CFGR_EXTSTS_EN = 0x00000100,
124  CFGR_REQALG = 0x00000080,
125  CFGR_SB = 0x00000040,
126  CFGR_POW = 0x00000020,
127  CFGR_EXD = 0x00000010,
128  CFGR_PESEL = 0x00000008,
129  CFGR_BROM_DIS = 0x00000004,
130  CFGR_EXT_125 = 0x00000002,
131  CFGR_BEM = 0x00000001
132 };
133 
134 /* EEPROM access register */
136 {
137  MEAR_EEDI = 0x00000001,
138  MEAR_EEDO = 0x00000002,
139  MEAR_EECLK = 0x00000004,
140  MEAR_EESEL = 0x00000008,
141  MEAR_MDIO = 0x00000010,
142  MEAR_MDDIR = 0x00000020,
143  MEAR_MDC = 0x00000040,
144 };
145 
146 /* PCI test control register */
148 {
149  PTSCR_EEBIST_FAIL = 0x00000001,
150  PTSCR_EEBIST_EN = 0x00000002,
151  PTSCR_EELOAD_EN = 0x00000004,
152  PTSCR_RBIST_FAIL = 0x000001b8,
153  PTSCR_RBIST_DONE = 0x00000200,
154  PTSCR_RBIST_EN = 0x00000400,
155  PTSCR_RBIST_RST = 0x00002000,
156  PTSCR_RBIST_RDONLY = 0x000003f9
157 };
158 
159 /* interrupt status register */
161 {
162  ISR_RESERVE = 0x80000000,
163  ISR_TXDESC3 = 0x40000000,
164  ISR_TXDESC2 = 0x20000000,
165  ISR_TXDESC1 = 0x10000000,
166  ISR_TXDESC0 = 0x08000000,
167  ISR_RXDESC3 = 0x04000000,
168  ISR_RXDESC2 = 0x02000000,
169  ISR_RXDESC1 = 0x01000000,
170  ISR_RXDESC0 = 0x00800000,
171  ISR_TXRCMP = 0x00400000,
172  ISR_RXRCMP = 0x00200000,
173  ISR_DPERR = 0x00100000,
174  ISR_SSERR = 0x00080000,
175  ISR_RMABT = 0x00040000,
176  ISR_RTAB = 0x00020000,
177  ISR_RXSOVR = 0x00010000,
178  ISR_HIBINT = 0x00008000,
179  ISR_PHY = 0x00004000,
180  ISR_PME = 0x00002000,
181  ISR_SWI = 0x00001000,
182  ISR_MIB = 0x00000800,
183  ISR_TXURN = 0x00000400,
184  ISR_TXIDLE = 0x00000200,
185  ISR_TXERR = 0x00000100,
186  ISR_TXDESC = 0x00000080,
187  ISR_TXOK = 0x00000040,
188  ISR_RXORN = 0x00000020,
189  ISR_RXIDLE = 0x00000010,
190  ISR_RXEARLY = 0x00000008,
191  ISR_RXERR = 0x00000004,
192  ISR_RXDESC = 0x00000002,
193  ISR_RXOK = 0x00000001,
194  ISR_ALL = 0x7FFFFFFF,
201 };
202 
203 /* transmit configuration register */
205 {
206  TX_CFG_CSI = 0x80000000,
207  TX_CFG_HBI = 0x40000000,
208  TX_CFG_MLB = 0x20000000,
209  TX_CFG_ATP = 0x10000000,
210  TX_CFG_ECRETRY = 0x00800000,
211  TX_CFG_BRST_DIS = 0x00080000,
212  TX_CFG_MXDMA1024 = 0x00000000,
213  TX_CFG_MXDMA512 = 0x00700000,
214  TX_CFG_MXDMA256 = 0x00600000,
215  TX_CFG_MXDMA128 = 0x00500000,
216  TX_CFG_MXDMA64 = 0x00400000,
217  TX_CFG_MXDMA32 = 0x00300000,
218  TX_CFG_MXDMA16 = 0x00200000,
219  TX_CFG_MXDMA8 = 0x00100000,
220  TX_CFG_MXDMA = 0x00700000,
221 
222  TX_CFG_FLTH_MASK = 0x0000ff00,
223  TX_CFG_DRTH_MASK = 0x000000ff
224 };
225 
226 /*general purpose I/O control register */
228 {
229  GPIOR_UNUSED = 0xffff8000,
230  GPIOR_GP5_IN = 0x00004000,
231  GPIOR_GP4_IN = 0x00002000,
232  GPIOR_GP3_IN = 0x00001000,
233  GPIOR_GP2_IN = 0x00000800,
234  GPIOR_GP1_IN = 0x00000400,
235  GPIOR_GP5_OE = 0x00000200,
236  GPIOR_GP4_OE = 0x00000100,
237  GPIOR_GP3_OE = 0x00000080,
238  GPIOR_GP2_OE = 0x00000040,
239  GPIOR_GP1_OE = 0x00000020,
240  GPIOR_GP5_OUT = 0x00000010,
241  GPIOR_GP4_OUT = 0x00000008,
242  GPIOR_GP3_OUT = 0x00000004,
243  GPIOR_GP2_OUT = 0x00000002,
244  GPIOR_GP1_OUT = 0x00000001
245 };
246 
247 /* receive configuration register */
249 {
250  RX_CFG_AEP = 0x80000000,
251  RX_CFG_ARP = 0x40000000,
252  RX_CFG_STRIPCRC = 0x20000000,
253  RX_CFG_RX_FD = 0x10000000,
254  RX_CFG_ALP = 0x08000000,
255  RX_CFG_AIRL = 0x04000000,
256  RX_CFG_MXDMA512 = 0x00700000,
257  RX_CFG_MXDMA = 0x00700000,
258  RX_CFG_DRTH = 0x0000003e,
259  RX_CFG_DRTH0 = 0x00000002
260 };
261 
262 /* pause control status register */
264 {
265  PCR_PSEN = (1 << 31),
266  PCR_PS_MCAST = (1 << 30),
267  PCR_PS_DA = (1 << 29),
268  PCR_STHI_8 = (3 << 23),
269  PCR_STLO_4 = (1 << 23),
270  PCR_FFHI_8K = (3 << 21),
271  PCR_FFLO_4K = (1 << 21),
272  PCR_PAUSE_CNT = 0xFFFE
273 };
274 
275 /*receive filter/match control register */
277 {
278  RFCR_RFEN = 0x80000000,
279  RFCR_AAB = 0x40000000,
280  RFCR_AAM = 0x20000000,
281  RFCR_AAU = 0x10000000,
282  RFCR_APM = 0x08000000,
283  RFCR_APAT = 0x07800000,
284  RFCR_APAT3 = 0x04000000,
285  RFCR_APAT2 = 0x02000000,
286  RFCR_APAT1 = 0x01000000,
287  RFCR_APAT0 = 0x00800000,
288  RFCR_AARP = 0x00400000,
289  RFCR_MHEN = 0x00200000,
290  RFCR_UHEN = 0x00100000,
291  RFCR_ULM = 0x00080000,
292  RFCR_RFADDR = 0x000003ff
293 };
294 
295 /* receive filter/match data register */
297 {
298  RFDR_BMASK = 0x00030000,
299  RFDR_RFDATA0 = 0x000000ff,
300  RFDR_RFDATA1 = 0x0000ff00
301 };
302 
303 /* management information base control register */
305 {
306  MIBC_MIBS = 0x00000008,
307  MIBC_ACLR = 0x00000004,
308  MIBC_FRZ = 0x00000002,
309  MIBC_WRN = 0x00000001
310 };
311 
312 /* VLAN/IP receive control register */
314 {
315  VRCR_RUDPE = 0x00000080,
316  VRCR_RTCPE = 0x00000040,
317  VRCR_RIPE = 0x00000020,
318  VRCR_IPEN = 0x00000010,
319  VRCR_DUTF = 0x00000008,
320  VRCR_DVTF = 0x00000004,
321  VRCR_VTREN = 0x00000002,
322  VRCR_VTDEN = 0x00000001
323 };
324 
325 /* VLAN/IP transmit control register */
327 {
328  VTCR_PPCHK = 0x00000008,
329  VTCR_GCHK = 0x00000004,
330  VTCR_VPPTI = 0x00000002,
331  VTCR_VGTI = 0x00000001
332 };
333 
334 /* Clockrun Control/Status Register */
336 {
337  CCSR_CLKRUN_EN = 0x00000001
338 };
339 
340 /* TBI control register */
342 {
343  TBICR_MR_LOOPBACK = 0x00004000,
344  TBICR_MR_AN_ENABLE = 0x00001000,
345  TBICR_MR_RESTART_AN = 0x00000200
346 };
347 
348 /* TBI status register */
350 {
351  TBISR_MR_LINK_STATUS = 0x00000020,
352  TBISR_MR_AN_COMPLETE = 0x00000004
353 };
354 
355 /* TBI auto-negotiation advertisement register */
357 {
358  TANAR_NP = 0x00008000,
359  TANAR_RF2 = 0x00002000,
360  TANAR_RF1 = 0x00001000,
361  TANAR_PS2 = 0x00000100,
362  TANAR_PS1 = 0x00000080,
363  TANAR_HALF_DUP = 0x00000040,
364  TANAR_FULL_DUP = 0x00000020,
365  TANAR_UNUSED = 0x00000E1F
366 };
367 
368 /* M5 control register */
370 {
371  M5REG_RESERVED = 0xfffffffc,
372  M5REG_RSS = 0x00000004,
373  M5REG_RX_THREAD = 0x00000002,
374  M5REG_TX_THREAD = 0x00000001
375 };
376 
377 struct ns_desc32
378 {
379  uint32_t link; /* link field to next descriptor in linked list */
380  uint32_t bufptr; /* pointer to the first fragment or buffer */
381  uint32_t cmdsts; /* command/status field */
382  uint32_t extsts; /* extended status field for VLAN and IP info */
383 };
384 
385 struct ns_desc64
386 {
387  uint64_t link; /* link field to next descriptor in linked list */
388  uint64_t bufptr; /* pointer to the first fragment or buffer */
389  uint32_t cmdsts; /* command/status field */
390  uint32_t extsts; /* extended status field for VLAN and IP info */
391 };
392 
393 /* cmdsts flags for descriptors */
395 {
396  CMDSTS_OWN = 0x80000000,
397  CMDSTS_MORE = 0x40000000,
398  CMDSTS_INTR = 0x20000000,
399  CMDSTS_ERR = 0x10000000,
400  CMDSTS_OK = 0x08000000,
401  CMDSTS_LEN_MASK = 0x0000ffff,
402 
403  CMDSTS_DEST_MASK = 0x01800000,
404  CMDSTS_DEST_SELF = 0x00800000,
405  CMDSTS_DEST_MULTI = 0x01000000
406 };
407 
408 /* extended flags for descriptors */
410 {
411  EXTSTS_UDPERR = 0x00400000,
412  EXTSTS_UDPPKT = 0x00200000,
413  EXTSTS_TCPERR = 0x00100000,
414  EXTSTS_TCPPKT = 0x00080000,
415  EXTSTS_IPERR = 0x00040000,
416  EXTSTS_IPPKT = 0x00020000
417 };
418 
419 /* speed status */
420 static inline int
421 SPDSTS_POLARITY(int lnksts)
422 {
424  (lnksts ? CFGR_LNKSTS : CFGR_ZERO));
425 }
426 
427 } // namespace gem5
428 
429 #endif /* __DEV_NS_GIGE_REG_H__ */
gem5::GPIOR_UNUSED
@ GPIOR_UNUSED
Definition: ns_gige_reg.h:229
gem5::MEAR
@ MEAR
Definition: ns_gige_reg.h:45
gem5::CMDSTS_LEN_MASK
@ CMDSTS_LEN_MASK
Definition: ns_gige_reg.h:401
gem5::VRCR_DUTF
@ VRCR_DUTF
Definition: ns_gige_reg.h:319
gem5::ns_desc64::bufptr
uint64_t bufptr
Definition: ns_gige_reg.h:388
gem5::RESERVED
@ RESERVED
Definition: ns_gige_reg.h:81
gem5::PTSCR_RBIST_RDONLY
@ PTSCR_RBIST_RDONLY
Definition: ns_gige_reg.h:156
gem5::TBIAutoNegotiationAdvertisementRegister
TBIAutoNegotiationAdvertisementRegister
Definition: ns_gige_reg.h:356
gem5::TX_CFG_MXDMA16
@ TX_CFG_MXDMA16
Definition: ns_gige_reg.h:218
gem5::CFGR_PHY_RST
@ CFGR_PHY_RST
Definition: ns_gige_reg.h:121
gem5::RX_CFG_ARP
@ RX_CFG_ARP
Definition: ns_gige_reg.h:251
gem5::PCITestControlRegister
PCITestControlRegister
Definition: ns_gige_reg.h:147
gem5::TANAR_PS2
@ TANAR_PS2
Definition: ns_gige_reg.h:361
gem5::EXTSTS_IPPKT
@ EXTSTS_IPPKT
Definition: ns_gige_reg.h:416
gem5::ISR_SWI
@ ISR_SWI
Definition: ns_gige_reg.h:181
gem5::BRAR
@ BRAR
Definition: ns_gige_reg.h:63
gem5::RFCR_APM
@ RFCR_APM
Definition: ns_gige_reg.h:282
gem5::ISR_DELAY
@ ISR_DELAY
Definition: ns_gige_reg.h:195
gem5::M5REG_RESERVED
@ M5REG_RESERVED
Definition: ns_gige_reg.h:371
gem5::ISR_RESERVE
@ ISR_RESERVE
Definition: ns_gige_reg.h:162
gem5::ns_desc32::extsts
uint32_t extsts
Definition: ns_gige_reg.h:382
gem5::ReceiveFilterMatchControlRegister
ReceiveFilterMatchControlRegister
Definition: ns_gige_reg.h:276
gem5::M5REG
@ M5REG
Definition: ns_gige_reg.h:79
gem5::RFCR_UHEN
@ RFCR_UHEN
Definition: ns_gige_reg.h:290
gem5::ISR_RXORN
@ ISR_RXORN
Definition: ns_gige_reg.h:188
gem5::ISR_DPERR
@ ISR_DPERR
Definition: ns_gige_reg.h:173
gem5::IER
@ IER
Definition: ns_gige_reg.h:49
gem5::PCR_STLO_4
@ PCR_STLO_4
Definition: ns_gige_reg.h:269
gem5::CFGR_EXD
@ CFGR_EXD
Definition: ns_gige_reg.h:127
gem5::IMR
@ IMR
Definition: ns_gige_reg.h:48
gem5::CFGR_M64ADDR
@ CFGR_M64ADDR
Definition: ns_gige_reg.h:120
gem5::ClockrunControlStatusRegister
ClockrunControlStatusRegister
Definition: ns_gige_reg.h:335
gem5::TANAR_RF2
@ TANAR_RF2
Definition: ns_gige_reg.h:359
gem5::ISR_TXERR
@ ISR_TXERR
Definition: ns_gige_reg.h:185
gem5::VLANIPTransmitControlRegister
VLANIPTransmitControlRegister
Definition: ns_gige_reg.h:326
gem5::RX_CFG_MXDMA
@ RX_CFG_MXDMA
Definition: ns_gige_reg.h:257
gem5::ISR_RTAB
@ ISR_RTAB
Definition: ns_gige_reg.h:176
gem5::VRCR_DVTF
@ VRCR_DVTF
Definition: ns_gige_reg.h:320
gem5::CMDSTS_DEST_SELF
@ CMDSTS_DEST_SELF
Definition: ns_gige_reg.h:404
gem5::VRCR_VTDEN
@ VRCR_VTDEN
Definition: ns_gige_reg.h:322
gem5::VTCR_PPCHK
@ VTCR_PPCHK
Definition: ns_gige_reg.h:328
gem5::RFCR_APAT2
@ RFCR_APAT2
Definition: ns_gige_reg.h:285
gem5::GPIOR_GP1_IN
@ GPIOR_GP1_IN
Definition: ns_gige_reg.h:234
gem5::RFCR_AAU
@ RFCR_AAU
Definition: ns_gige_reg.h:281
gem5::TransmitConfigurationRegister
TransmitConfigurationRegister
Definition: ns_gige_reg.h:204
gem5::PQCR
@ PQCR
Definition: ns_gige_reg.h:58
gem5::TANAR_HALF_DUP
@ TANAR_HALF_DUP
Definition: ns_gige_reg.h:363
gem5::CFGR_ZERO
@ CFGR_ZERO
Definition: ns_gige_reg.h:100
gem5::VRCR_RIPE
@ VRCR_RIPE
Definition: ns_gige_reg.h:317
gem5::RFCR_APAT
@ RFCR_APAT
Definition: ns_gige_reg.h:283
gem5::TX_CFG_MXDMA512
@ TX_CFG_MXDMA512
Definition: ns_gige_reg.h:213
gem5::GeneralPurposeIOControlRegister
GeneralPurposeIOControlRegister
Definition: ns_gige_reg.h:227
gem5::CFGR_EXTSTS_EN
@ CFGR_EXTSTS_EN
Definition: ns_gige_reg.h:123
gem5::CFGR_PINT_DUPSTS
@ CFGR_PINT_DUPSTS
Definition: ns_gige_reg.h:111
gem5::RFCR_APAT1
@ RFCR_APAT1
Definition: ns_gige_reg.h:286
gem5::IHR
@ IHR
Definition: ns_gige_reg.h:50
gem5::RFCR_APAT0
@ RFCR_APAT0
Definition: ns_gige_reg.h:287
gem5::CMDSTSFlatsForDescriptors
CMDSTSFlatsForDescriptors
Definition: ns_gige_reg.h:394
gem5::BRDR
@ BRDR
Definition: ns_gige_reg.h:64
gem5::PTSCR_RBIST_DONE
@ PTSCR_RBIST_DONE
Definition: ns_gige_reg.h:153
gem5::TX_CFG_MXDMA1024
@ TX_CFG_MXDMA1024
Definition: ns_gige_reg.h:212
gem5::CFGR_BEM
@ CFGR_BEM
Definition: ns_gige_reg.h:131
gem5::RX_CFG_DRTH0
@ RX_CFG_DRTH0
Definition: ns_gige_reg.h:259
gem5::TX_CFG_FLTH_MASK
@ TX_CFG_FLTH_MASK
Definition: ns_gige_reg.h:222
gem5::DeviceRegisterAddress
DeviceRegisterAddress
Definition: ns_gige_reg.h:41
gem5::VRCR_RTCPE
@ VRCR_RTCPE
Definition: ns_gige_reg.h:316
gem5::RFCR_ULM
@ RFCR_ULM
Definition: ns_gige_reg.h:291
gem5::CFGR_DATA64_EN
@ CFGR_DATA64_EN
Definition: ns_gige_reg.h:119
gem5::TX_CFG_ATP
@ TX_CFG_ATP
Definition: ns_gige_reg.h:209
gem5::GPIOR_GP5_OE
@ GPIOR_GP5_OE
Definition: ns_gige_reg.h:235
gem5::RXDP_HI
@ RXDP_HI
Definition: ns_gige_reg.h:56
gem5::ISR_TXDESC3
@ ISR_TXDESC3
Definition: ns_gige_reg.h:163
gem5::CR_RST
@ CR_RST
Definition: ns_gige_reg.h:94
gem5::ISR_MIB
@ ISR_MIB
Definition: ns_gige_reg.h:182
gem5::EXTSTS_TCPPKT
@ EXTSTS_TCPPKT
Definition: ns_gige_reg.h:414
gem5::CR_RXR
@ CR_RXR
Definition: ns_gige_reg.h:92
gem5::VLANIPReceiveControlRegister
VLANIPReceiveControlRegister
Definition: ns_gige_reg.h:313
gem5::RX_CFG_MXDMA512
@ RX_CFG_MXDMA512
Definition: ns_gige_reg.h:256
gem5::RFCR
@ RFCR
Definition: ns_gige_reg.h:61
gem5::GPIOR_GP2_OUT
@ GPIOR_GP2_OUT
Definition: ns_gige_reg.h:243
gem5::GPIOR_GP4_OE
@ GPIOR_GP4_OE
Definition: ns_gige_reg.h:236
gem5::TXDP_HI
@ TXDP_HI
Definition: ns_gige_reg.h:52
gem5::CFGR_PCI64_DET
@ CFGR_PCI64_DET
Definition: ns_gige_reg.h:118
gem5::TANAR_RF1
@ TANAR_RF1
Definition: ns_gige_reg.h:360
gem5::RFDR_RFDATA0
@ RFDR_RFDATA0
Definition: ns_gige_reg.h:299
gem5::ManagementInformationBaseControlRegister
ManagementInformationBaseControlRegister
Definition: ns_gige_reg.h:304
gem5::CR_TXE
@ CR_TXE
Definition: ns_gige_reg.h:87
gem5::ISR_RXDESC3
@ ISR_RXDESC3
Definition: ns_gige_reg.h:167
gem5::RFDR_BMASK
@ RFDR_BMASK
Definition: ns_gige_reg.h:298
gem5::PTSCR_EEBIST_FAIL
@ PTSCR_EEBIST_FAIL
Definition: ns_gige_reg.h:149
gem5::GPIOR_GP1_OUT
@ GPIOR_GP1_OUT
Definition: ns_gige_reg.h:244
gem5::ISR_PME
@ ISR_PME
Definition: ns_gige_reg.h:180
gem5::ns_desc64::cmdsts
uint32_t cmdsts
Definition: ns_gige_reg.h:389
gem5::TXDP
@ TXDP
Definition: ns_gige_reg.h:51
gem5::CMDSTS_OK
@ CMDSTS_OK
Definition: ns_gige_reg.h:400
gem5::EXTSTS_UDPERR
@ EXTSTS_UDPERR
Definition: ns_gige_reg.h:411
gem5::TX_CFG_MXDMA256
@ TX_CFG_MXDMA256
Definition: ns_gige_reg.h:214
gem5::TBISR_MR_AN_COMPLETE
@ TBISR_MR_AN_COMPLETE
Definition: ns_gige_reg.h:352
gem5::M5REG_RSS
@ M5REG_RSS
Definition: ns_gige_reg.h:372
gem5::RFCR_APAT3
@ RFCR_APAT3
Definition: ns_gige_reg.h:284
gem5::TANAR_UNUSED
@ TANAR_UNUSED
Definition: ns_gige_reg.h:365
gem5::TBIStatusRegister
TBIStatusRegister
Definition: ns_gige_reg.h:349
gem5::CFGR_SPDSTS1
@ CFGR_SPDSTS1
Definition: ns_gige_reg.h:103
gem5::TX_CFG_MLB
@ TX_CFG_MLB
Definition: ns_gige_reg.h:208
gem5::ISR_RXDESC
@ ISR_RXDESC
Definition: ns_gige_reg.h:192
gem5::MIBC_ACLR
@ MIBC_ACLR
Definition: ns_gige_reg.h:307
gem5::TANAR_FULL_DUP
@ TANAR_FULL_DUP
Definition: ns_gige_reg.h:364
gem5::TANAR_PS1
@ TANAR_PS1
Definition: ns_gige_reg.h:362
gem5::CCSR
@ CCSR
Definition: ns_gige_reg.h:72
gem5::RFCR_AAM
@ RFCR_AAM
Definition: ns_gige_reg.h:280
gem5::CFGR_BROM_DIS
@ CFGR_BROM_DIS
Definition: ns_gige_reg.h:129
gem5::RX_CFG_DRTH
@ RX_CFG_DRTH
Definition: ns_gige_reg.h:258
gem5::GPIOR_GP3_IN
@ GPIOR_GP3_IN
Definition: ns_gige_reg.h:232
gem5::TX_CFG_ECRETRY
@ TX_CFG_ECRETRY
Definition: ns_gige_reg.h:210
gem5::ISR_TXRCMP
@ ISR_TXRCMP
Definition: ns_gige_reg.h:171
gem5::SRR
@ SRR
Definition: ns_gige_reg.h:65
gem5::GPIOR_GP3_OE
@ GPIOR_GP3_OE
Definition: ns_gige_reg.h:237
gem5::VRCR_RUDPE
@ VRCR_RUDPE
Definition: ns_gige_reg.h:315
gem5::ISR_TXDESC2
@ ISR_TXDESC2
Definition: ns_gige_reg.h:164
gem5::PTSCR
@ PTSCR
Definition: ns_gige_reg.h:46
gem5::MEAR_MDC
@ MEAR_MDC
Definition: ns_gige_reg.h:143
gem5::EXTSTS_TCPERR
@ EXTSTS_TCPERR
Definition: ns_gige_reg.h:413
gem5::ISR_TXDESC1
@ ISR_TXDESC1
Definition: ns_gige_reg.h:165
gem5::CFGR_POW
@ CFGR_POW
Definition: ns_gige_reg.h:126
gem5::RFCR_RFADDR
@ RFCR_RFADDR
Definition: ns_gige_reg.h:292
gem5::ISR_TXOK
@ ISR_TXOK
Definition: ns_gige_reg.h:187
gem5::GPIOR_GP4_OUT
@ GPIOR_GP4_OUT
Definition: ns_gige_reg.h:241
gem5::CFGR_PINT_SPDSTS
@ CFGR_PINT_SPDSTS
Definition: ns_gige_reg.h:113
gem5::GPIOR_GP2_IN
@ GPIOR_GP2_IN
Definition: ns_gige_reg.h:233
gem5::M5ControlRegister
M5ControlRegister
Definition: ns_gige_reg.h:369
gem5::ISR_RXRCMP
@ ISR_RXRCMP
Definition: ns_gige_reg.h:172
gem5::VRCR
@ VRCR
Definition: ns_gige_reg.h:69
gem5::PTSCR_RBIST_RST
@ PTSCR_RBIST_RST
Definition: ns_gige_reg.h:155
gem5::RX_CFG_AEP
@ RX_CFG_AEP
Definition: ns_gige_reg.h:250
gem5::VRCR_VTREN
@ VRCR_VTREN
Definition: ns_gige_reg.h:321
gem5::PCR_FFHI_8K
@ PCR_FFHI_8K
Definition: ns_gige_reg.h:270
gem5::ns_desc64
Definition: ns_gige_reg.h:385
gem5::TBISR
@ TBISR
Definition: ns_gige_reg.h:74
gem5::TX_CFG_MXDMA64
@ TX_CFG_MXDMA64
Definition: ns_gige_reg.h:216
gem5::TX_CFG_HBI
@ TX_CFG_HBI
Definition: ns_gige_reg.h:207
gem5::PTSCR_RBIST_FAIL
@ PTSCR_RBIST_FAIL
Definition: ns_gige_reg.h:152
gem5::VTCR_VGTI
@ VTCR_VGTI
Definition: ns_gige_reg.h:331
gem5::TBICR_MR_RESTART_AN
@ TBICR_MR_RESTART_AN
Definition: ns_gige_reg.h:345
gem5::CFGR_T64ADDR
@ CFGR_T64ADDR
Definition: ns_gige_reg.h:117
gem5::ISR_IMPL
@ ISR_IMPL
Definition: ns_gige_reg.h:198
gem5::TX_CFG_MXDMA128
@ TX_CFG_MXDMA128
Definition: ns_gige_reg.h:215
gem5::TX_CFG
@ TX_CFG
Definition: ns_gige_reg.h:53
gem5::CMDSTS_ERR
@ CMDSTS_ERR
Definition: ns_gige_reg.h:399
gem5::ISR_TXDESC0
@ ISR_TXDESC0
Definition: ns_gige_reg.h:166
gem5::CFGR_AUTO_1000
@ CFGR_AUTO_1000
Definition: ns_gige_reg.h:109
gem5::CCSR_CLKRUN_EN
@ CCSR_CLKRUN_EN
Definition: ns_gige_reg.h:337
gem5::GPIOR_GP2_OE
@ GPIOR_GP2_OE
Definition: ns_gige_reg.h:238
gem5::CMDSTS_DEST_MULTI
@ CMDSTS_DEST_MULTI
Definition: ns_gige_reg.h:405
gem5::ns_desc32::cmdsts
uint32_t cmdsts
Definition: ns_gige_reg.h:381
gem5::InterruptStatusRegister
InterruptStatusRegister
Definition: ns_gige_reg.h:160
gem5::TX_CFG_MXDMA8
@ TX_CFG_MXDMA8
Definition: ns_gige_reg.h:219
gem5::CFGR_LNKSTS
@ CFGR_LNKSTS
Definition: ns_gige_reg.h:101
gem5::VDR
@ VDR
Definition: ns_gige_reg.h:71
gem5::PCR_PSEN
@ PCR_PSEN
Definition: ns_gige_reg.h:265
gem5::MIBC_WRN
@ MIBC_WRN
Definition: ns_gige_reg.h:309
gem5::ISR_TXURN
@ ISR_TXURN
Definition: ns_gige_reg.h:183
gem5::M5REG_RX_THREAD
@ M5REG_RX_THREAD
Definition: ns_gige_reg.h:373
gem5::MIB_START
@ MIB_START
Definition: ns_gige_reg.h:67
gem5::ReceiveFilterMatchDataRegister
ReceiveFilterMatchDataRegister
Definition: ns_gige_reg.h:296
gem5::GPIOR_GP5_OUT
@ GPIOR_GP5_OUT
Definition: ns_gige_reg.h:240
gem5::GPIOR_GP5_IN
@ GPIOR_GP5_IN
Definition: ns_gige_reg.h:230
gem5::PauseControlStatusRegister
PauseControlStatusRegister
Definition: ns_gige_reg.h:263
gem5::GPIOR_GP1_OE
@ GPIOR_GP1_OE
Definition: ns_gige_reg.h:239
gem5::ISR
@ ISR
Definition: ns_gige_reg.h:47
gem5::VTCR_VPPTI
@ VTCR_VPPTI
Definition: ns_gige_reg.h:330
gem5::MEAR_MDDIR
@ MEAR_MDDIR
Definition: ns_gige_reg.h:142
gem5::CFGR_SPDSTS
@ CFGR_SPDSTS
Definition: ns_gige_reg.h:102
gem5::CR
@ CR
Definition: ns_gige_reg.h:43
gem5::CFGR_MWI_DIS
@ CFGR_MWI_DIS
Definition: ns_gige_reg.h:116
gem5::CFGR_MODE_1000
@ CFGR_MODE_1000
Definition: ns_gige_reg.h:108
gem5::TBIControlRegister
TBIControlRegister
Definition: ns_gige_reg.h:341
gem5::CMDSTS_OWN
@ CMDSTS_OWN
Definition: ns_gige_reg.h:396
gem5::TANAR
@ TANAR
Definition: ns_gige_reg.h:75
gem5::ISR_PHY
@ ISR_PHY
Definition: ns_gige_reg.h:179
gem5::CFGR_MRM_DIS
@ CFGR_MRM_DIS
Definition: ns_gige_reg.h:115
gem5::TANLPAR
@ TANLPAR
Definition: ns_gige_reg.h:76
gem5::ISR_TXDESC
@ ISR_TXDESC
Definition: ns_gige_reg.h:186
gem5::CMDSTS_MORE
@ CMDSTS_MORE
Definition: ns_gige_reg.h:397
gem5::MEAR_MDIO
@ MEAR_MDIO
Definition: ns_gige_reg.h:141
gem5::ISR_NOIMPL
@ ISR_NOIMPL
Definition: ns_gige_reg.h:200
gem5::CFGR_DUPSTS
@ CFGR_DUPSTS
Definition: ns_gige_reg.h:105
gem5::CR_TXD
@ CR_TXD
Definition: ns_gige_reg.h:88
gem5::PCR_STHI_8
@ PCR_STHI_8
Definition: ns_gige_reg.h:268
gem5::TBICR_MR_AN_ENABLE
@ TBICR_MR_AN_ENABLE
Definition: ns_gige_reg.h:344
gem5::ExtendedFlagsForDescriptors
ExtendedFlagsForDescriptors
Definition: ns_gige_reg.h:409
gem5::ISR_RXDESC0
@ ISR_RXDESC0
Definition: ns_gige_reg.h:170
gem5::CFGR_SB
@ CFGR_SB
Definition: ns_gige_reg.h:125
gem5::CFGR
@ CFGR
Definition: ns_gige_reg.h:44
gem5::LAST
@ LAST
Definition: ns_gige_reg.h:80
gem5::WCSR
@ WCSR
Definition: ns_gige_reg.h:59
gem5::TBISR_MR_LINK_STATUS
@ TBISR_MR_LINK_STATUS
Definition: ns_gige_reg.h:351
gem5::ns_desc32::bufptr
uint32_t bufptr
Definition: ns_gige_reg.h:380
gem5::ISR_RXDESC1
@ ISR_RXDESC1
Definition: ns_gige_reg.h:169
gem5::MEAR_EECLK
@ MEAR_EECLK
Definition: ns_gige_reg.h:139
gem5::MIBC_FRZ
@ MIBC_FRZ
Definition: ns_gige_reg.h:308
gem5::MEAR_EEDO
@ MEAR_EEDO
Definition: ns_gige_reg.h:138
gem5::PCR_PS_MCAST
@ PCR_PS_MCAST
Definition: ns_gige_reg.h:266
gem5::RX_CFG_RX_FD
@ RX_CFG_RX_FD
Definition: ns_gige_reg.h:253
gem5::RFCR_AARP
@ RFCR_AARP
Definition: ns_gige_reg.h:288
gem5::M5REG_TX_THREAD
@ M5REG_TX_THREAD
Definition: ns_gige_reg.h:374
gem5::RX_CFG_STRIPCRC
@ RX_CFG_STRIPCRC
Definition: ns_gige_reg.h:252
gem5::RXDP
@ RXDP
Definition: ns_gige_reg.h:55
gem5::PCR_PS_DA
@ PCR_PS_DA
Definition: ns_gige_reg.h:267
gem5::ISR_RXERR
@ ISR_RXERR
Definition: ns_gige_reg.h:191
gem5::RFCR_MHEN
@ RFCR_MHEN
Definition: ns_gige_reg.h:289
gem5::CR_SWI
@ CR_SWI
Definition: ns_gige_reg.h:93
gem5::CFGR_PESEL
@ CFGR_PESEL
Definition: ns_gige_reg.h:128
gem5::PTSCR_EELOAD_EN
@ PTSCR_EELOAD_EN
Definition: ns_gige_reg.h:151
gem5::ns_desc64::extsts
uint32_t extsts
Definition: ns_gige_reg.h:390
gem5::TESR
@ TESR
Definition: ns_gige_reg.h:78
gem5::TX_CFG_CSI
@ TX_CFG_CSI
Definition: ns_gige_reg.h:206
gem5::CFGR_SPDSTS0
@ CFGR_SPDSTS0
Definition: ns_gige_reg.h:104
gem5::RX_CFG_AIRL
@ RX_CFG_AIRL
Definition: ns_gige_reg.h:255
gem5::ISR_RMABT
@ ISR_RMABT
Definition: ns_gige_reg.h:175
gem5::CFGR_EXT_125
@ CFGR_EXT_125
Definition: ns_gige_reg.h:130
gem5::TX_CFG_MXDMA
@ TX_CFG_MXDMA
Definition: ns_gige_reg.h:220
gem5::MEAR_EEDI
@ MEAR_EEDI
Definition: ns_gige_reg.h:137
gem5::EEPROMAccessRegister
EEPROMAccessRegister
Definition: ns_gige_reg.h:135
gem5::ISR_HIBINT
@ ISR_HIBINT
Definition: ns_gige_reg.h:178
gem5::PCR_FFLO_4K
@ PCR_FFLO_4K
Definition: ns_gige_reg.h:271
gem5::CMDSTS_INTR
@ CMDSTS_INTR
Definition: ns_gige_reg.h:398
gem5::EXTSTS_IPERR
@ EXTSTS_IPERR
Definition: ns_gige_reg.h:415
gem5::RX_CFG
@ RX_CFG
Definition: ns_gige_reg.h:57
gem5::CFGR_TBI_EN
@ CFGR_TBI_EN
Definition: ns_gige_reg.h:106
gem5::CFGR_PINT_CTL
@ CFGR_PINT_CTL
Definition: ns_gige_reg.h:110
gem5::MIB_END
@ MIB_END
Definition: ns_gige_reg.h:68
gem5::CFGR_TMRTEST
@ CFGR_TMRTEST
Definition: ns_gige_reg.h:114
gem5::CR_RXE
@ CR_RXE
Definition: ns_gige_reg.h:89
gem5::CFGR_RESERVED
@ CFGR_RESERVED
Definition: ns_gige_reg.h:107
gem5::ReceiveConfigurationRegister
ReceiveConfigurationRegister
Definition: ns_gige_reg.h:248
gem5::ISR_RXSOVR
@ ISR_RXSOVR
Definition: ns_gige_reg.h:177
gem5::RFDR_RFDATA1
@ RFDR_RFDATA1
Definition: ns_gige_reg.h:300
gem5::GPIOR_GP4_IN
@ GPIOR_GP4_IN
Definition: ns_gige_reg.h:231
gem5::ISR_TXIDLE
@ ISR_TXIDLE
Definition: ns_gige_reg.h:184
gem5::CFGR_PINT_LNKSTS
@ CFGR_PINT_LNKSTS
Definition: ns_gige_reg.h:112
gem5::MIBC
@ MIBC
Definition: ns_gige_reg.h:66
gem5::CR_RXD
@ CR_RXD
Definition: ns_gige_reg.h:90
gem5::ISR_SSERR
@ ISR_SSERR
Definition: ns_gige_reg.h:174
gem5::CMDSTS_DEST_MASK
@ CMDSTS_DEST_MASK
Definition: ns_gige_reg.h:403
gem5::RFDR
@ RFDR
Definition: ns_gige_reg.h:62
gem5::TBICR_MR_LOOPBACK
@ TBICR_MR_LOOPBACK
Definition: ns_gige_reg.h:343
gem5::TX_CFG_BRST_DIS
@ TX_CFG_BRST_DIS
Definition: ns_gige_reg.h:211
gem5::MEAR_EESEL
@ MEAR_EESEL
Definition: ns_gige_reg.h:140
gem5::TANER
@ TANER
Definition: ns_gige_reg.h:77
gem5::VTCR_GCHK
@ VTCR_GCHK
Definition: ns_gige_reg.h:329
gem5::TBICR
@ TBICR
Definition: ns_gige_reg.h:73
gem5::PTSCR_EEBIST_EN
@ PTSCR_EEBIST_EN
Definition: ns_gige_reg.h:150
gem5::TANAR_NP
@ TANAR_NP
Definition: ns_gige_reg.h:358
gem5::ns_desc64::link
uint64_t link
Definition: ns_gige_reg.h:387
gem5::PCR_PAUSE_CNT
@ PCR_PAUSE_CNT
Definition: ns_gige_reg.h:272
gem5::TX_CFG_DRTH_MASK
@ TX_CFG_DRTH_MASK
Definition: ns_gige_reg.h:223
gem5::CFGR_REQALG
@ CFGR_REQALG
Definition: ns_gige_reg.h:124
gem5::PCR
@ PCR
Definition: ns_gige_reg.h:60
gem5::TX_CFG_MXDMA32
@ TX_CFG_MXDMA32
Definition: ns_gige_reg.h:217
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::ConfigurationRegisters
ConfigurationRegisters
Definition: ns_gige_reg.h:98
gem5::ISR_RXOK
@ ISR_RXOK
Definition: ns_gige_reg.h:193
gem5::PTSCR_RBIST_EN
@ PTSCR_RBIST_EN
Definition: ns_gige_reg.h:154
gem5::ns_desc32::link
uint32_t link
Definition: ns_gige_reg.h:379
gem5::CR_TXR
@ CR_TXR
Definition: ns_gige_reg.h:91
gem5::ISR_ALL
@ ISR_ALL
Definition: ns_gige_reg.h:194
gem5::RFCR_RFEN
@ RFCR_RFEN
Definition: ns_gige_reg.h:278
gem5::GPIOR_GP3_OUT
@ GPIOR_GP3_OUT
Definition: ns_gige_reg.h:242
gem5::ISR_NODELAY
@ ISR_NODELAY
Definition: ns_gige_reg.h:197
gem5::GPIOR
@ GPIOR
Definition: ns_gige_reg.h:54
gem5::RFCR_AAB
@ RFCR_AAB
Definition: ns_gige_reg.h:279
gem5::ChipCommandRegister
ChipCommandRegister
Definition: ns_gige_reg.h:85
gem5::SPDSTS_POLARITY
static int SPDSTS_POLARITY(int lnksts)
Definition: ns_gige_reg.h:421
gem5::ns_desc32
Definition: ns_gige_reg.h:377
gem5::VTCR
@ VTCR
Definition: ns_gige_reg.h:70
gem5::MIBC_MIBS
@ MIBC_MIBS
Definition: ns_gige_reg.h:306
gem5::ISR_RXIDLE
@ ISR_RXIDLE
Definition: ns_gige_reg.h:189
gem5::ISR_RXDESC2
@ ISR_RXDESC2
Definition: ns_gige_reg.h:168
gem5::EXTSTS_UDPPKT
@ EXTSTS_UDPPKT
Definition: ns_gige_reg.h:412
gem5::VRCR_IPEN
@ VRCR_IPEN
Definition: ns_gige_reg.h:318
gem5::ISR_RXEARLY
@ ISR_RXEARLY
Definition: ns_gige_reg.h:190
gem5::CFGR_PHY_DIS
@ CFGR_PHY_DIS
Definition: ns_gige_reg.h:122
gem5::RX_CFG_ALP
@ RX_CFG_ALP
Definition: ns_gige_reg.h:254

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