gem5  v22.0.0.1
plic_device.cc
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37 
38 #include "dev/riscv/plic_device.hh"
39 
40 namespace gem5
41 {
42 
43 using namespace RiscvISA;
44 
46  BasicPioDevice(params, params.pio_size),
47  system(params.system),
48  platform(params.platform),
49  _interruptID(params.interrupt_id)
50 {
51 }
52 
53 } // namespace gem5
gem5::PlicIntDevice::PlicIntDevice
PlicIntDevice(const Params &params)
Definition: plic_device.cc:45
gem5::X86ISA::system
Bitfield< 15 > system
Definition: misc.hh:997
gem5::PioDevice::Params
PioDeviceParams Params
Definition: io_device.hh:134
plic_device.hh
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::BasicPioDevice
Definition: io_device.hh:147

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