Namespaces
namespace	gem5
	Copyright (c) 2024 Arm Limited All rights reserved.

Macros
#define	mmCP_RB0_BASE 0x040

#define	mmCP_RB0_CNTL 0x041

#define	mmCP_RB_WPTR_POLL_ADDR_LO 0x046

#define	mmCP_RB_WPTR_POLL_ADDR_HI 0x047

#define	mmCP_RB_VMID 0x051

#define	mmCP_RB0_RPTR_ADDR 0x043

#define	mmCP_RB0_RPTR_ADDR_HI 0x044

#define	mmCP_RB0_WPTR 0x054

#define	mmCP_RB0_WPTR_HI 0x055

#define	mmCP_RB_DOORBELL_CONTROL 0x059

#define	mmCP_RB_DOORBELL_RANGE_LOWER 0x05a

#define	mmCP_RB_DOORBELL_RANGE_UPPER 0x05b

#define	mmCP_RB0_BASE_HI 0x0b1

#define	mmCP_HQD_ACTIVE 0x247

#define	mmCP_HQD_VMID 0x248

#define	mmCP_HQD_PQ_BASE 0x24d

#define	mmCP_HQD_PQ_BASE_HI 0x24e

#define	mmCP_HQD_PQ_DOORBELL_CONTROL 0x254

#define	mmCP_HQD_PQ_RPTR 0x24f

#define	mmCP_HQD_PQ_RPTR_REPORT_ADDR 0x250

#define	mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI 0x251

#define	mmCP_HQD_PQ_WPTR_POLL_ADDR 0x252

#define	mmCP_HQD_PQ_WPTR_POLL_ADDR_HI 0x253

#define	mmCP_HQD_PQ_CONTROL 0x256

#define	mmCP_HQD_IB_CONTROL 0x25a

#define	mmCP_HQD_PQ_WPTR_LO 0x27b

#define	mmCP_HQD_PQ_WPTR_HI 0x27c

Macro Definition Documentation

◆ mmCP_HQD_ACTIVE

#define mmCP_HQD_ACTIVE 0x247

Definition at line 53 of file pm4_mmio.hh.

◆ mmCP_HQD_IB_CONTROL

#define mmCP_HQD_IB_CONTROL 0x25a

Definition at line 64 of file pm4_mmio.hh.

◆ mmCP_HQD_PQ_BASE

#define mmCP_HQD_PQ_BASE 0x24d

Definition at line 55 of file pm4_mmio.hh.

◆ mmCP_HQD_PQ_BASE_HI

#define mmCP_HQD_PQ_BASE_HI 0x24e

Definition at line 56 of file pm4_mmio.hh.

◆ mmCP_HQD_PQ_CONTROL

#define mmCP_HQD_PQ_CONTROL 0x256

Definition at line 63 of file pm4_mmio.hh.

◆ mmCP_HQD_PQ_DOORBELL_CONTROL

#define mmCP_HQD_PQ_DOORBELL_CONTROL 0x254

Definition at line 57 of file pm4_mmio.hh.

◆ mmCP_HQD_PQ_RPTR

#define mmCP_HQD_PQ_RPTR 0x24f

Definition at line 58 of file pm4_mmio.hh.

◆ mmCP_HQD_PQ_RPTR_REPORT_ADDR

#define mmCP_HQD_PQ_RPTR_REPORT_ADDR 0x250

Definition at line 59 of file pm4_mmio.hh.

◆ mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI

#define mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI 0x251

Definition at line 60 of file pm4_mmio.hh.

◆ mmCP_HQD_PQ_WPTR_HI

#define mmCP_HQD_PQ_WPTR_HI 0x27c

Definition at line 66 of file pm4_mmio.hh.

◆ mmCP_HQD_PQ_WPTR_LO

#define mmCP_HQD_PQ_WPTR_LO 0x27b

Definition at line 65 of file pm4_mmio.hh.

◆ mmCP_HQD_PQ_WPTR_POLL_ADDR

#define mmCP_HQD_PQ_WPTR_POLL_ADDR 0x252

Definition at line 61 of file pm4_mmio.hh.

◆ mmCP_HQD_PQ_WPTR_POLL_ADDR_HI

#define mmCP_HQD_PQ_WPTR_POLL_ADDR_HI 0x253

Definition at line 62 of file pm4_mmio.hh.

◆ mmCP_HQD_VMID

#define mmCP_HQD_VMID 0x248

Definition at line 54 of file pm4_mmio.hh.

◆ mmCP_RB0_BASE

#define mmCP_RB0_BASE 0x040

Definition at line 39 of file pm4_mmio.hh.

◆ mmCP_RB0_BASE_HI

#define mmCP_RB0_BASE_HI 0x0b1

Definition at line 51 of file pm4_mmio.hh.

◆ mmCP_RB0_CNTL

#define mmCP_RB0_CNTL 0x041

Definition at line 40 of file pm4_mmio.hh.

◆ mmCP_RB0_RPTR_ADDR

#define mmCP_RB0_RPTR_ADDR 0x043

Definition at line 44 of file pm4_mmio.hh.

◆ mmCP_RB0_RPTR_ADDR_HI

#define mmCP_RB0_RPTR_ADDR_HI 0x044

Definition at line 45 of file pm4_mmio.hh.

◆ mmCP_RB0_WPTR

#define mmCP_RB0_WPTR 0x054

Definition at line 46 of file pm4_mmio.hh.

◆ mmCP_RB0_WPTR_HI

#define mmCP_RB0_WPTR_HI 0x055

Definition at line 47 of file pm4_mmio.hh.

◆ mmCP_RB_DOORBELL_CONTROL

#define mmCP_RB_DOORBELL_CONTROL 0x059

Definition at line 48 of file pm4_mmio.hh.

◆ mmCP_RB_DOORBELL_RANGE_LOWER

#define mmCP_RB_DOORBELL_RANGE_LOWER 0x05a

Definition at line 49 of file pm4_mmio.hh.

◆ mmCP_RB_DOORBELL_RANGE_UPPER

#define mmCP_RB_DOORBELL_RANGE_UPPER 0x05b

Definition at line 50 of file pm4_mmio.hh.

◆ mmCP_RB_VMID

#define mmCP_RB_VMID 0x051

Definition at line 43 of file pm4_mmio.hh.

◆ mmCP_RB_WPTR_POLL_ADDR_HI

#define mmCP_RB_WPTR_POLL_ADDR_HI 0x047

Definition at line 42 of file pm4_mmio.hh.

◆ mmCP_RB_WPTR_POLL_ADDR_LO

#define mmCP_RB_WPTR_POLL_ADDR_LO 0x046

Definition at line 41 of file pm4_mmio.hh.

Namespaces

Macros