33 #ifndef __DEV_AMDGPU_PM4_MMIO_HH__
34 #define __DEV_AMDGPU_PM4_MMIO_HH__
39 #define mmCP_RB0_BASE 0x1040
40 #define mmCP_RB0_CNTL 0x1041
41 #define mmCP_RB_WPTR_POLL_ADDR_LO 0x1046
42 #define mmCP_RB_WPTR_POLL_ADDR_HI 0x1047
43 #define mmCP_RB_VMID 0x1051
44 #define mmCP_RB0_RPTR_ADDR 0x1043
45 #define mmCP_RB0_RPTR_ADDR_HI 0x1044
46 #define mmCP_RB0_WPTR 0x1054
47 #define mmCP_RB0_WPTR_HI 0x1055
48 #define mmCP_RB_DOORBELL_CONTROL 0x1059
49 #define mmCP_RB_DOORBELL_RANGE_LOWER 0x105a
50 #define mmCP_RB_DOORBELL_RANGE_UPPER 0x105b
51 #define mmCP_RB0_BASE_HI 0x10b1
53 #define mmCP_HQD_ACTIVE 0x1247
54 #define mmCP_HQD_VMID 0x1248
55 #define mmCP_HQD_PQ_BASE 0x124d
56 #define mmCP_HQD_PQ_BASE_HI 0x124e
57 #define mmCP_HQD_PQ_DOORBELL_CONTROL 0x1254
58 #define mmCP_HQD_PQ_RPTR 0x124f
59 #define mmCP_HQD_PQ_RPTR_REPORT_ADDR 0x1250
60 #define mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI 0x1251
61 #define mmCP_HQD_PQ_WPTR_POLL_ADDR 0x1252
62 #define mmCP_HQD_PQ_WPTR_POLL_ADDR_HI 0x1253
63 #define mmCP_HQD_PQ_CONTROL 0x1256
64 #define mmCP_HQD_IB_CONTROL 0x125a
65 #define mmCP_HQD_PQ_WPTR_LO 0x127b
66 #define mmCP_HQD_PQ_WPTR_HI 0x127c
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....