- e -

• E820Entry() : X86ISA::E820Entry
• E820Table() : X86ISA::E820Table
• earliestReturnTime() : LdsState
• eaSrcsReady() : BaseDynInst< Impl >
• ec() : ArmISA::ArmFault , ArmISA::ArmFaultVals< T > , ArmISA::DataAbort , ArmISA::HypervisorCall , ArmISA::HypervisorTrap , ArmISA::PrefetchAbort , ArmISA::SecureMonitorCall , ArmISA::SecureMonitorTrap , ArmISA::SoftwareBreakpoint , ArmISA::SupervisorCall , ArmISA::SupervisorTrap , ArmISA::UndefinedInstruction
• echo() : Net::TcpOpt
• EcoffObject() : EcoffObject
• eepromKick() : NSGigE
• effAddrValid() : BaseDynInst< Impl >
• egid() : Process
• elaboration_check() : tlm_utils::simple_socket_base
• elaboration_done() : sc_core::sc_simcontext
• elaborationDone() : sc_gem5::Scheduler
• ElasticDataGen() : TraceCPU::ElasticDataGen
• ElasticTrace() : ElasticTrace
• element() : tlm_utils::time_ordered_list< PAYLOAD >::element
• elementAt() : NetDest , Set
• elemId() : PhysRegId
• elemIndex() : RegId
• ElfObject() : ElfObject
• EmbeddedPyBind() : EmbeddedPyBind
• EmbeddedPython() : EmbeddedPython
• emitUpdate() : ThermalDomain
• empty() : AddrRangeMap< V, max_cache_size > , CallbackQueue , CircularQueue< T > , DependencyGraph< DynInstPtr > , EtherSwitch::Interface::PortFifo , EventQueue , Fifo< T > , GPUCoalescer , Iris::ThreadContext::BpInfo , Minor::InputBuffer< ElemType, ReportTraits, BubbleTraits > , Minor::Latch< Data > , Minor::MinorBuffer< ElemType, ReportTraits, BubbleTraits > , Minor::Queue< ElemType, ReportTraits, BubbleTraits > , PacketFifo , ReturnAddrStack , sc_gem5::NodeList< T > , Sequencer , SparcISA::TlbMap
• EmptyPGE() : LinuxAlphaSystem , LinuxMipsSystem
• EmptyPGT() : LinuxAlphaSystem , LinuxMipsSystem
• emptyRenameInsts() : DefaultIEW< Impl >
• EmulatedDriver() : EmulatedDriver
• EmulationPageTable() : EmulationPageTable
• EmulEnv() : X86ISA::EmulEnv
• enable() : ArmISA::PMU::PMUEvent , ArmISA::PMU::RegularEvent , ArmISA::PMU::SWIncrementEvent , Debug::AllFlags , Debug::CompoundFlag , Debug::Flag , Debug::SimpleFlag , PollEvent , sc_core::sc_process_handle , sc_gem5::Process , Stats::Info , Stats::Vector2dInfo , Stats::VectorDistInfo , Stats::VectorInfo
• enableAll() : Debug::SimpleFlag
• enabled() : CPA , HDLcd
• enableFunctionTrace() : BaseCPU
• enableKernelIRQChip() : KvmVM
• enableSignals() : PerfKvmCounter
• enableSm() : IGbE::DescCache< T > , IGbE::RxDescCache , IGbE::TxDescCache
• enc() : sc_dt::scfx_params
• encodeBinaryData() : BaseRemoteGDB
• encodedValue() : SyscallReturn
• encodeXferResponse() : BaseRemoteGDB
• encoding() : ArmISA::ArmStaticInst
• end() : AddrRange , AddrRangeMap< V, max_cache_size > , AssociativeSet< Entry > , ChannelAddrRange , CircularQueue< T > , PacketFifo , sc_core::sc_attr_cltn , sc_core::sc_vector< T > , sc_core::sc_vector_assembly< T, MT > , sc_dt::sc_context< T > , SimpleRenameMap , SparcISA::TlbMap , Stats::Hdf5 , Stats::Output , Stats::Text
• end_args() : cp::Print
• end_module() : sc_core::sc_module
• end_of_elaboration() : FastModel::SCGIC , FastModel::ScxEvsCortexA76< Types > , sc_core::sc_export< IF > , sc_core::sc_export_base , sc_core::sc_in< T > , sc_core::sc_in< bool > , sc_core::sc_in< sc_dt::sc_bigint< W > > , sc_core::sc_in< sc_dt::sc_biguint< W > > , sc_core::sc_in< sc_dt::sc_int< W > > , sc_core::sc_in< sc_dt::sc_logic > , sc_core::sc_in< sc_dt::sc_uint< W > > , sc_core::sc_in_resolved , sc_core::sc_in_rv< W > , sc_core::sc_inout< T > , sc_core::sc_inout< bool > , sc_core::sc_inout< sc_dt::sc_bigint< W > > , sc_core::sc_inout< sc_dt::sc_biguint< W > > , sc_core::sc_inout< sc_dt::sc_int< W > > , sc_core::sc_inout< sc_dt::sc_logic > , sc_core::sc_inout< sc_dt::sc_uint< W > > , sc_core::sc_inout_resolved , sc_core::sc_inout_rv< W > , sc_core::sc_module , sc_core::sc_port_b< IF > , sc_core::sc_port_base , sc_core::sc_prim_channel , tlm_utils::multi_passthrough_target_socket< MODULE, BUSWIDTH, TYPES, N, POL >
• end_of_simulation() : sc_core::sc_export< IF > , sc_core::sc_export_base , sc_core::sc_module , sc_core::sc_port_b< IF > , sc_core::sc_port_base , sc_core::sc_prim_channel , SimpleLTInitiator1_dmi , SimpleLTInitiator2_dmi , SimpleLTInitiator_ext
• EndBitUnion() : ArmISA::PMU , ContextDescriptor , CpuLocalTimer::Timer , GicV2 , Gicv3CPUInterface , Gicv3Distributor , Gicv3Its , Gicv3Redistributor , HDLcd , IdeController , Intel8254Timer , MC146818 , Pl050 , Pl111 , PS2Mouse , RealViewCtrl , SMMUCommand , StreamTableEntry , VGic , VirtIODeviceBase , X86ISA::I8042 , X86ISA::Interrupts , X86ISA::PageFault , X86ISA::Speaker
• endGroup() : Stats::Hdf5 , Stats::Output , Stats::Text
• endModule() : sc_gem5::Module
• endOfElaboration() : sc_gem5::Module
• endOfSimulation() : sc_gem5::Module
• endOfSimulationComplete() : sc_gem5::Kernel
• EndQuiesceEvent() : EndQuiesceEvent
• endRequest() : SimpleATTarget1
• endResponse() : SimpleATInitiator1 , SimpleATTarget1 , SimpleATTarget2
• endWalk() : X86ISA::Walker::WalkerState
• EnergyCtrl() : EnergyCtrl
• enqueue() : DRAMSim2Wrapper , EtherSwitch::Interface , MessageBuffer , WireBuffer
• enqueueNextFetchRequest() : CacheRecorder
• enqueueNextFlushRequest() : CacheRecorder
• enqueuePacket() : QoS::LrgQueuePolicy , QoS::QueuePolicy
• enqueuePrefetch() : AbstractController
• enqueueRubyEvent() : RubySystem
• enter() : BaseGen , ExitGen , IdleGen , LinearGen , RandomGen , TraceGen
• enterPwrGating() : BaseCPU
• Entry() : EmulationPageTable::Entry
• entry() : ExtensionPool< T >::entry
• Entry() : IniFile::Entry
• entry() : memory
• entry1() : fun
• entry2() : fun
• entryAmount() : InstructionQueue< Impl > , LSQ< Impl > , ROB< Impl >
• entryExists() : CheckpointIn , IniFile
• entryPoint() : ObjectFile
• entryTrampoline() : Fiber
• EnumeratedFault() : SparcISA::EnumeratedFault< T >
• eoiMaintenanceInterruptStatus() : Gicv3CPUInterface
• equal() : DataBlock
• equal_range() : PCEventQueue
• equalsInit() : RenameMode< ISA > , RenameMode< ArmISA::ISA >
• erase() : AddrRangeMap< V, max_cache_size > , SparcISA::TlbMap
• eraseIfNullEntry() : SnoopFilter
• errnoValue() : SyscallReturn
• escalate() : QoS::MemCtrl
• escalateQueues() : QoS::MemCtrl
• establish_bebuf() : tlm::tlm_endian_context
• establish_dbuf() : tlm::tlm_endian_context
• establishConnection() : TCPIface
• etcPasswd() : Linux
• EthAddr() : Net::EthAddr
• EtherBus() : EtherBus
• EtherDevBase() : EtherDevBase
• EtherDevice() : EtherDevice
• EtherDump() : EtherDump
• EtherInt() : EtherInt
• EtherLink() : EtherLink
• EtherSwitch() : EtherSwitch
• EtherTapBase() : EtherTapBase
• EtherTapInt() : EtherTapInt
• EtherTapStub() : EtherTapStub
• EthPacketData() : EthPacketData
• EthPtr() : Net::EthPtr
• ethRxPkt() : IGbE
• ethTxDone() : IGbE
• euid() : Process
• eval() : MathExpr , MathExprPowerModel , TimingExpr , TimingExprBin , TimingExprIf , TimingExprLet , TimingExprLiteral , TimingExprReadIntReg , TimingExprRef , TimingExprSrcReg , TimingExprUn
• evaluate() : Minor::Decode , Minor::Execute , Minor::Fetch1 , Minor::Fetch2 , Minor::Latch< Data > , Minor::MinorActivityRecorder , Minor::Pipeline , Ticked
• Event() : Event
• event() : sc_core::sc_in< T > , sc_core::sc_in< bool > , sc_core::sc_in< sc_dt::sc_bigint< W > > , sc_core::sc_in< sc_dt::sc_biguint< W > > , sc_core::sc_in< sc_dt::sc_int< W > > , sc_core::sc_in< sc_dt::sc_logic > , sc_core::sc_in< sc_dt::sc_uint< W > > , sc_core::sc_inout< T > , sc_core::sc_inout< bool > , sc_core::sc_inout< sc_dt::sc_bigint< W > > , sc_core::sc_inout< sc_dt::sc_biguint< W > > , sc_core::sc_inout< sc_dt::sc_int< W > > , sc_core::sc_inout< sc_dt::sc_logic > , sc_core::sc_inout< sc_dt::sc_uint< W > > , sc_core::sc_signal< sc_dt::sc_bigint< W > > , sc_core::sc_signal< sc_dt::sc_biguint< W > > , sc_core::sc_signal< sc_dt::sc_int< W > > , sc_core::sc_signal< sc_dt::sc_uint< W > > , sc_core::sc_signal_in_if< T > , sc_core::sc_signal_in_if< bool > , sc_core::sc_signal_in_if< sc_dt::sc_bigint< W > > , sc_core::sc_signal_in_if< sc_dt::sc_biguint< W > > , sc_core::sc_signal_in_if< sc_dt::sc_int< W > > , sc_core::sc_signal_in_if< sc_dt::sc_logic > , sc_core::sc_signal_in_if< sc_dt::sc_uint< W > >
• Event() : sc_gem5::Event
• event() : sc_gem5::ScSignalBase , sc_gem5::ScSignalBaseT< T, WRITER_POLICY >
• Event() : TapListener::Event
• EventFunctionWrapper() : EventFunctionWrapper
• EventManager() : EventManager
• eventQueue() : EventManager
• EventQueue() : EventQueue
• eventQueueEmpty() : RubySystem
• EventWrapper() : EventWrapper< T, F >
• evictBlock() : BaseCache , Cache , NoncoherentCache
• evictionCallback() : GPUCoalescer , RubyPort::MemSlavePort , Sequencer
• evictLRU() : X86ISA::TLB
• Exception() : CxxConfigManager::Exception
• exception() : RiscvISA::RiscvFault
• ExceptionWrapper() : sc_gem5::ExceptionWrapper< T >
• exceptUserMode() : ArmISA::ISA::MiscRegLUTEntryInitializer
• exclude_host() : PerfKvmCounterConfig
• exclude_hv() : PerfKvmCounterConfig
• exec() : ComputeUnit , ConditionRegisterState , ExecStage , FetchStage , FetchUnit , GlobalMemPipeline , GpuDispatcher , LocalMemPipeline , ScheduleStage , ScoreboardCheckStage , Shader , VectorRegisterFile , Wavefront
• execAtomic() : GPUStaticInst , HsailISA::AtomicInst< MemDataType, AddrOperandType, NumSrcOperands, HasDst >
• execAtomicAcq() : GPUStaticInst , HsailISA::AtomicInst< MemDataType, AddrOperandType, NumSrcOperands, HasDst >
• ExecContext() : Minor::ExecContext
• execLdAcq() : GPUStaticInst , HsailISA::LdInst< MemDataType, DestDataType, AddrOperandType >
• execMask() : Wavefront
• execPseudoInst() : HsailISA::Call
• execSeqNumToWaitFor() : Minor::Scoreboard
• execSt() : GPUStaticInst , HsailISA::StInst< MemDataType, SrcDataType, AddrOperandType >
• ExecStage() : ExecStage
• execute() : ArmISA::PredMacroOp , ArmISA::SveIndexedMemSV< RegElemType, MemElemType, MicroopType, FirstFaultWritebackMicroopType > , ArmISA::SveIndexedMemVI< RegElemType, MemElemType, MicroopType, FirstFaultWritebackMicroopType > , ArmISA::SveLdStructSI< Element, MicroopLdMemType, MicroopDeIntrlvType > , ArmISA::SveLdStructSS< Element, MicroopLdMemType, MicroopDeIntrlvType > , ArmISA::SveStStructSI< Element, MicroopStMemType, MicroopIntrlvType > , ArmISA::SveStStructSS< Element, MicroopStMemType, MicroopIntrlvType > , AtomicGeneric2Op< T > , AtomicGeneric3Op< T > , AtomicGenericPair3Op< T > , AtomicOpAdd< T > , AtomicOpAnd< T > , AtomicOpCAS< T > , AtomicOpDec< T > , AtomicOpExch< T > , AtomicOpInc< T > , AtomicOpMax< T > , AtomicOpMin< T > , AtomicOpOr< T > , AtomicOpSub< T > , AtomicOpXor< T > , BaseO3DynInst< Impl > , DecoderFaultInst , FailUnimplemented , GPUDynInst , GPUStaticInst , HsailISA::AtomicInst< MemDataType, AddrOperandType, NumSrcOperands, HasDst > , HsailISA::Barrier , HsailISA::BrInstBase< TargetType > , HsailISA::BrnInstBase< TargetType > , HsailISA::Call , HsailISA::CbrInstBase< TargetType > , HsailISA::LdaInst< DestDataType, AddrOperandType > , HsailISA::LdInst< MemDataType, DestDataType, AddrOperandType > , HsailISA::MemFence , HsailISA::Ret , HsailISA::StInst< MemDataType, SrcDataType, AddrOperandType > , IllegalExecInst , KernelLaunchStaticInst , McrMrcImplDefined , McrMrcMiscInst
• Execute() : Minor::Execute
• execute() : MiscRegImplDefined64 , RiscvISA::AtomicGenericOp< T > , RiscvISA::MemFenceMicro , RiscvISA::RiscvMacroInst , RiscvISA::Unknown , SparcISA::FailUnimplemented , SparcISA::Nop , SparcISA::SparcMacroInst , SparcISA::Unknown , SparcISA::WarnUnimplemented , StaticInst , TraceCPU::ElasticDataGen , TypedAtomicOpFunctor< T > , WarnUnimplemented
• executedAs() : GPUDynInst
• executeInsts() : DefaultIEW< Impl >
• executeLoad() : LSQ< Impl > , LSQUnit< Impl >
• executeMemRefInst() : Minor::Execute
• executeMemReq() : TraceCPU::ElasticDataGen
• executeStore() : LSQ< Impl > , LSQUnit< Impl >
• ExecuteThreadInfo() : Minor::Execute::ExecuteThreadInfo
• ExeTracer() : Trace::ExeTracer
• ExeTracerRecord() : Trace::ExeTracerRecord
• exit() : BaseGen , Logger , ThreadContext , TraceCPU::ElasticDataGen , TraceCPU::FixedRetryGen , TraceGen
• exit_helper() : Logger
• exitCallback() : X86ISA::GpuTLB
• ExitGen() : ExitGen
• exitThreads() : FullO3CPU< Impl >
• expand() : tlm::tlm_array< T >
• ExplicitATTarget() : ExplicitATTarget
• ExplicitLTTarget() : ExplicitLTTarget
• exponent() : sc_dt::scfx_ieee_double , sc_dt::scfx_ieee_float
• ExtConfigEntry() : X86ISA::IntelMP::ExtConfigEntry
• extend_shortest_path() : Topology
• extend_sign() : sc_dt::sc_int_base , sc_dt::sc_uint_base
• extendMask() : Trie< Key, Value >
• extendReg64() : ArmISA::ArmStaticInst
• extensionLength() : Net::Ip6Hdr
• ExtensionPool() : ExtensionPool< T >
• ExternalInterrupt() : X86ISA::ExternalInterrupt
• ExternalMaster() : ExternalMaster
• ExternalPort() : ExternalMaster::ExternalPort , ExternalSlave::ExternalPort
• ExternalSlave() : ExternalSlave
• extlen() : Net::Ip6Opt
• extraAltCalc() : TAGE_SC_L_TAGE , TAGEBase
• extractBlkOffset() : BaseTags
• extractConfig() : DRAMSim2Wrapper
• ExtractInsertInst() : HsailISA::ExtractInsertInst< DataType >
• extractResourceId() : Iris::ThreadContext
• extractResourceMap() : Iris::ThreadContext
• extractSectorOffset() : SectorTags
• extractServiceableTargets() : MSHR
• extractSet() : SetAssociative , SkewedAssociative
• extractTag() : BaseIndexingPolicy , BaseTags , FALRU
• extraDataValid() : Request