- n -

• n_bits() : sc_dt::sc_fxnum , sc_dt::sc_fxnum_fast , sc_dt::sc_fxtype_params , sc_dt::scfx_params
• name() : A9GlobalTimer::Timer , ActivityRecorder , AlphaISA::AlignmentFault , AlphaISA::ArithmeticFault , AlphaISA::DtbAcvFault , AlphaISA::DtbAlignmentFault , AlphaISA::DtbFault , AlphaISA::DtbPageFault , AlphaISA::FloatEnableFault , AlphaISA::IntegerOverflowFault , AlphaISA::InterruptFault , AlphaISA::ItbAcvFault , AlphaISA::ItbFault , AlphaISA::ItbPageFault , AlphaISA::MachineCheckFault , AlphaISA::NDtbMissFault , AlphaISA::PalFault , AlphaISA::PDtbMissFault , AlphaISA::ProcessInfo , AlphaISA::RemoteGDB::AlphaGdbRegCache , AlphaISA::ResetFault , AlphaISA::UnimplementedOpcodeFault , AlphaISA::VectorEnableFault , ArchTimer , ArmISA::ArmFaultVals< T > , ArmISA::ProcessInfo , ArmISA::RemoteGDB::AArch32GdbRegCache , ArmISA::RemoteGDB::AArch64GdbRegCache , ArmISA::TableWalker::WalkerState , BaseGdbRegCache , BaseGen , BasePixelPump::PixelEvent , BaseRemoteGDB , BaseXBar::Layer< SrcType, DstType > , CallbackQueue , ConditionRegisterState , CopyEngine::CopyEngineChannel , CpuLocalTimer::Timer , Debug::Flag , DefaultCommit< Impl > , DefaultDecode< Impl > , DefaultFetch< Impl > , DefaultIEW< Impl > , DefaultRename< Impl > , DistEtherLink::Link , DmaCallback , DRAMCtrl::Rank , ElasticTrace , EmulationPageTable , EtherInt , EtherLink::Link , EtherSwitch::Interface::PortFifo , Event , EventFunctionWrapper , EventQueue , EventWrapper< T, F > , ExecStage , FaultBase , FetchStage , GenericAlignmentFault , GenericISA::M5FatalFault , GenericISA::M5HackFaultBase< Base > , GenericISA::M5InformFaultBase< Base > , GenericISA::M5PanicFault , GenericISA::M5WarnFaultBase< Base > , GenericPageTableFault , GlobalMemPipeline , HardBreakpoint , HsaCode , HsaObject , IGbE::DescCache< T > , InstructionQueue< Impl > , Intel8254Timer::Counter , Intel8254Timer , ItsProcess , Kernel::Statistics , LocalMemPipeline , LSQ< Impl > , LSQUnit< Impl > , MC146818 , MemDepUnit< MemDepPred, Impl >::MemDepEntry , MemDepUnit< MemDepPred, Impl > , MipsISA::MipsFault< T > , MipsISA::ProcessInfo , MipsISA::RemoteGDB::MipsGdbRegCache , Named , OutputStream , PacketQueue , PAL , PCEvent , PciHost::DeviceInterface , PerfectSwitch , PhysicalMemory , Port , PowerISA::PowerFault , PowerISA::ProcessInfo , PowerISA::RemoteGDB::PowerGdbRegCache , ReExec , ReqPacketQueue , RespPacketQueue , RiscvISA::ProcessInfo , RiscvISA::RemoteGDB::RiscvGdbRegCache , RiscvISA::Reset , RiscvISA::RiscvFault , ROB< Impl > , sc_core::sc_attr_base , sc_core::sc_event , sc_core::sc_object , sc_core::sc_process_handle , sc_gem5::Event , sc_gem5::Module , sc_gem5::Object , sc_gem5::Scheduler , ScheduleStage , Scoreboard , ScoreboardCheckStage , SimObject , SimpleThread , SimpleTrace , SMMUDeviceRetryEvent , SMMUProcess , SnoopRespPacketQueue , Sp804::Timer , SparcISA::RemoteGDB::SPARC64GdbRegCache , SparcISA::RemoteGDB::SPARCGdbRegCache , SparcISA::SparcFault< T > , Stats::DataWrap< Derived, InfoProxyType > , StridePrefetcher::PCTable , SyscallDesc , SyscallRetryFault , Throttle , TraceCPU::ElasticDataGen , TraceCPU::FixedRetryGen , UnifiedFreeList , UnimpFault , VecRegisterState , VirtIO9PBase::FSQueue , VirtIOBlock::RequestQueue , VirtIOConsole::TermRecvQueue , VirtIOConsole::TermTransQueue , X86ISA::ProcessInfo , X86ISA::RemoteGDB::AMD64GdbRegCache , X86ISA::RemoteGDB::X86GdbRegCache , X86ISA::UnimpInstFault , X86ISA::Walker::WalkerState , X86ISA::X86FaultBase
• Named() : Named
• nameOut() : Serializable::ScopedCheckpointSection
• nan() : sc_dt::scfx_ieee_double
• nand_reduce() : sc_core::sc_in< sc_dt::sc_bigint< W > > , sc_core::sc_in< sc_dt::sc_biguint< W > > , sc_core::sc_in< sc_dt::sc_int< W > > , sc_core::sc_in< sc_dt::sc_uint< W > > , sc_core::sc_inout< sc_dt::sc_bigint< W > > , sc_core::sc_inout< sc_dt::sc_biguint< W > > , sc_core::sc_inout< sc_dt::sc_int< W > > , sc_core::sc_inout< sc_dt::sc_uint< W > > , sc_dt::sc_concatref , sc_dt::sc_fxnum_fast_subref , sc_dt::sc_fxnum_subref , sc_dt::sc_int_base , sc_dt::sc_int_subref_r , sc_dt::sc_proxy< X > , sc_dt::sc_signed , sc_dt::sc_signed_subref_r , sc_dt::sc_uint_base , sc_dt::sc_uint_subref_r , sc_dt::sc_unsigned , sc_dt::sc_unsigned_subref_r
• NativeTrace() : Trace::NativeTrace
• NativeTraceRecord() : Trace::NativeTraceRecord
• nb2b_thread() : tlm_utils::simple_target_socket_b< MODULE, BUSWIDTH, TYPES, POL >::fw_process , tlm_utils::simple_target_socket_tagged_b< MODULE, BUSWIDTH, TYPES, POL >::fw_process
• nb_bound() : tlm::tlm_fifo< T > , tlm::tlm_fifo_config_size_if
• nb_can_get() : tlm::tlm_fifo< T > , tlm::tlm_nonblocking_get_if< T > , tlm::tlm_put_get_imp< PUT_DATA, GET_DATA >
• nb_can_peek() : tlm::tlm_fifo< T > , tlm::tlm_nonblocking_peek_if< T > , tlm::tlm_put_get_imp< PUT_DATA, GET_DATA >
• nb_can_put() : tlm::tlm_fifo< T > , tlm::tlm_nonblocking_put_if< T > , tlm::tlm_put_get_imp< PUT_DATA, GET_DATA >
• nb_expand() : tlm::tlm_fifo< T > , tlm::tlm_fifo_config_size_if
• nb_get() : tlm::tlm_fifo< T > , tlm::tlm_nonblocking_get_if< T > , tlm::tlm_put_get_imp< PUT_DATA, GET_DATA >
• nb_peek() : tlm::tlm_fifo< T > , tlm::tlm_fifo_debug_if< T > , tlm::tlm_nonblocking_peek_if< T > , tlm::tlm_put_get_imp< PUT_DATA, GET_DATA >
• nb_poke() : tlm::tlm_fifo< T > , tlm::tlm_fifo_debug_if< T >
• nb_put() : tlm::tlm_fifo< T > , tlm::tlm_nonblocking_put_if< T > , tlm::tlm_put_get_imp< PUT_DATA, GET_DATA >
• nb_read() : sc_core::sc_fifo< T > , sc_core::sc_fifo_in< T > , sc_core::sc_fifo_nonblocking_in_if< T >
• nb_reduce() : tlm::tlm_fifo< T > , tlm::tlm_fifo_config_size_if
• nb_transport_bw() : sc_gem5::Gem5ToTlmBridge< BITWIDTH > , SimpleLTInitiator1 , SimpleLTInitiator1_dmi , tlm::tlm_bw_nonblocking_transport_if< TRANS, PHASE > , tlm_utils::callback_binder_bw< TYPES > , tlm_utils::simple_initiator_socket_b< MODULE, BUSWIDTH, TYPES, POL >::process , tlm_utils::simple_initiator_socket_tagged_b< MODULE, BUSWIDTH, TYPES, POL >::process , tlm_utils::simple_target_socket_b< MODULE, BUSWIDTH, TYPES, POL >::bw_process , tlm_utils::simple_target_socket_tagged_b< MODULE, BUSWIDTH, TYPES, POL >::bw_process
• nb_transport_fw() : sc_gem5::TlmToGem5Bridge< BITWIDTH > , SimpleLTTarget1 , tlm::tlm_fw_nonblocking_transport_if< TRANS, PHASE > , tlm_utils::callback_binder_fw< TYPES > , tlm_utils::passthrough_target_socket_b< MODULE, BUSWIDTH, TYPES, POL >::process , tlm_utils::passthrough_target_socket_tagged_b< MODULE, BUSWIDTH, TYPES, POL >::process , tlm_utils::simple_target_socket_b< MODULE, BUSWIDTH, TYPES, POL >::fw_process , tlm_utils::simple_target_socket_tagged_b< MODULE, BUSWIDTH, TYPES, POL >::fw_process
• nb_unbound() : tlm::tlm_fifo< T > , tlm::tlm_fifo_config_size_if
• nb_write() : sc_core::sc_fifo< T > , sc_core::sc_fifo_nonblocking_out_if< T > , sc_core::sc_fifo_out< T >
• nbrOutstanding() : DRAMSim2
• NDtbMissFault() : AlphaISA::NDtbMissFault
• need_stage() : InputUnit , VirtualChannel
• need_sync() : tlm_utils::tlm_quantumkeeper
• needClose() : ArmSemihosting::File
• needMoreBytes() : AlphaISA::Decoder , ArmISA::Decoder , MipsISA::Decoder , PowerISA::Decoder , RiscvISA::Decoder , SparcISA::Decoder , X86ISA::Decoder
• needsResponse() : MemCmd , Packet
• needsRetry() : SyscallReturn
• needsStart() : sc_gem5::Process
• needsToBeSentToStoreBuffer() : Minor::LSQ::LSQRequest
• needsToTick() : Minor::LSQ
• needsWritable() : MemCmd , MSHR , Packet
• neg() : sc_core::sc_in< bool > , sc_core::sc_in< sc_dt::sc_logic > , sc_core::sc_inout< bool > , sc_core::sc_inout< sc_dt::sc_logic > , sc_dt::scfx_pow10
• negative() : sc_dt::scfx_ieee_double , sc_dt::scfx_ieee_float
• negedge() : sc_core::sc_in< bool > , sc_core::sc_in< sc_dt::sc_logic > , sc_core::sc_inout< bool > , sc_core::sc_inout< sc_dt::sc_logic > , sc_core::sc_signal_in_if< bool > , sc_core::sc_signal_in_if< sc_dt::sc_logic > , sc_gem5::ScSignalBaseBinary , sc_gem5::ScSignalBinary< T, WRITER_POLICY >
• negedge_event() : sc_core::sc_in< bool > , sc_core::sc_in< sc_dt::sc_logic > , sc_core::sc_inout< bool > , sc_core::sc_inout< sc_dt::sc_logic > , sc_core::sc_signal_in_if< bool > , sc_core::sc_signal_in_if< sc_dt::sc_logic > , sc_gem5::ScSignalBinary< T, WRITER_POLICY >
• negedgeEvent() : sc_gem5::ScSignalBaseBinary
• NetDest() : NetDest
• netmask() : Net::IpNetmask
• Network() : Network
• NetworkInterface() : NetworkInterface
• NetworkLink() : NetworkLink
• neverSeen() : MultiperspectivePerceptron::FilterEntry
• newest() : sc_gem5::Process
• next() : ChunkGenerator , tlm_utils::peq_with_cb_and_phase< OWNER, TYPES >::delta_list , VirtDescriptor
• next_object() : sc_core::sc_simcontext
• next_time() : tlm_utils::time_ordered_list< PAYLOAD >
• next_trigger() : sc_core::sc_module , sc_core::sc_prim_channel
• nextAddress() : TimerTable
• nextCycle() : Clocked
• nextDescAddr() : ArmISA::TableWalker::LongDescriptor
• nextExecute() : TraceCPU::FixedRetryGen
• nextGenerator() : BaseTrafficGen , PyTrafficGen , TrafficGen
• nextGlbRdBus() : ComputeUnit
• nextIdxs() : ArmISA::VfpMacroOp
• nextInstAddr() : BaseDynInst< Impl > , CheckerCPU , CheckerThreadContext< TC > , DefaultCommit< Impl > , FullO3CPU< Impl > , GenericISA::PCStateBase , GPUStaticInst , Iris::ThreadContext , O3ThreadContext< Impl > , SimpleThread , ThreadContext
• nextIOState() : BaseKvmCPU::KVMCpuPort
• nextLevelPointer() : PageTableOps , V7LPageTableOps , V8PageTableOps16k , V8PageTableOps4k , V8PageTableOps64k
• nextLocRdBus() : ComputeUnit
• nextMode() : ArmISA::ArmFault , ArmISA::ArmFaultVals< T >
• nextnlu() : AlphaISA::TLB , MipsISA::TLB , PowerISA::TLB , RiscvISA::TLB
• nextPacketTick() : BaseGen , ExitGen , IdleGen , LinearGen , RandomGen , TraceGen
• nextPixel() : BasePixelPump , HDLcd::PixelPump
• nextPrefetchReadyTime() : BasePrefetcher , MultiPrefetcher , QueuedPrefetcher
• nextQueueReadyTime() : BaseCache
• nextReadyTime() : Queue< Entry >
• nextSeq() : X86ISA::TLB
• nextSignalName() : sc_gem5::VcdTraceFile
• nextState() : TrafficGen
• nextTableAddr() : ArmISA::TableWalker::LongDescriptor
• nextTick() : EventQueue
• nextWalk() : ArmISA::TableWalker
• nnpc() : GenericISA::DelaySlotPCState< MachInst >
• Node() : MathExpr::Node , StackDistCalc::Node , Trie< Key, Value >::Node
• NodeList() : sc_gem5::NodeList< T >
• nofault() : SparcISA::PageTableEntry
• NoMaliGpu() : NoMaliGpu
• NonCachingSimpleCPU() : NonCachingSimpleCPU
• NoncoherentCache() : NoncoherentCache
• NoncoherentXBar() : NoncoherentXBar
• NoncoherentXBarMasterPort() : NoncoherentXBar::NoncoherentXBarMasterPort
• NoncoherentXBarSlavePort() : NoncoherentXBar::NoncoherentXBarSlavePort
• noneActive() : VecPredRegT< VecElem, NumElems, Packed, Const >
• noneSet() : Flags< T >
• NonMaskableInterrupt() : X86ISA::NonMaskableInterrupt
• nonSecure() : ArmISA::ISA::MiscRegLUTEntryInitializer
• nonSpecInstReady() : MemDepUnit< MemDepPred, Impl >
• noOutput() : Stats::Text
• Nop() : SparcISA::Nop
• noProgress() : BaseTrafficGen
• nor_reduce() : sc_core::sc_in< sc_dt::sc_bigint< W > > , sc_core::sc_in< sc_dt::sc_biguint< W > > , sc_core::sc_in< sc_dt::sc_int< W > > , sc_core::sc_in< sc_dt::sc_uint< W > > , sc_core::sc_inout< sc_dt::sc_bigint< W > > , sc_core::sc_inout< sc_dt::sc_biguint< W > > , sc_core::sc_inout< sc_dt::sc_int< W > > , sc_core::sc_inout< sc_dt::sc_uint< W > > , sc_dt::sc_concatref , sc_dt::sc_fxnum_fast_subref , sc_dt::sc_fxnum_subref , sc_dt::sc_int_base , sc_dt::sc_int_subref_r , sc_dt::sc_proxy< X > , sc_dt::sc_signed , sc_dt::sc_signed_subref_r , sc_dt::sc_uint_base , sc_dt::sc_uint_subref_r , sc_dt::sc_unsigned , sc_dt::sc_unsigned_subref_r
• noRequest() : MemTest
• noResponse() : MemTest
• normalize() : sc_dt::scfx_rep
• notAnInst() : BaseDynInst< Impl >
• noThrow() : Iris::ThreadContext
• notify() : ArmISA::PMU::RegularEvent::RegularProbe , BaseMemProbe::PacketListener , BasePrefetcher , BasePrefetcher::PrefetchListener , MultiPrefetcher , PIFPrefetcher::PrefetchListenerPC , PowerModel::ThermalProbeListener , ProbeListenerArg< T, Arg > , ProbeListenerArgBase< Arg > , ProbePointArg< Arg > , QueuedPrefetcher , sc_core::sc_event , sc_core::sc_event_queue , sc_core::sc_event_queue_if , sc_gem5::Event , sc_gem5::Sensitivity , tlm_utils::peq_with_cb_and_phase< OWNER, TYPES > , tlm_utils::peq_with_get< PAYLOAD >
• notify_delayed() : sc_core::sc_event
• notifyDelayed() : sc_gem5::Event
• notifyFill() : BasePrefetcher , BOPPrefetcher , MultiPrefetcher , SBOOEPrefetcher
• notifyFork() : BaseKvmCPU , CowDiskImage , Drainable , KvmVM , RawDiskImage
• notifyInterface() : SerialDevice
• notifyRetiredInst() : PIFPrefetcher
• notifyWgCompl() : GpuDispatcher
• notifyWork() : sc_gem5::DynamicSensitivityEventAndList , sc_gem5::DynamicSensitivityEventOrList , sc_gem5::Sensitivity
• npc() : GenericISA::SimplePCState< MachInst >
• nsAccessToSecInt() : Gicv3Distributor
• nsec() : Time
• NSGigE() : NSGigE
• NSGigEInt() : NSGigEInt
• null() : AtagHeader , AtagNone
• nullCallback() : IGbE::TxDescCache
• num() : ArmInterruptPin
• num_attributes() : sc_core::sc_object , sc_gem5::Object
• num_available() : sc_core::sc_fifo< T > , sc_core::sc_fifo_in< T > , sc_core::sc_fifo_in_if< T >
• num_bits() : sc_dt::sc_signed , sc_dt::sc_unsigned
• num_free() : sc_core::sc_fifo< T > , sc_core::sc_fifo_out< T > , sc_core::sc_fifo_out_if< T >
• numActiveThreads() : FullO3CPU< Impl >
• number() : IntSinkPinBase
• numCCDestRegs() : BaseDynInst< Impl > , StaticInst
• numCCPhysRegs() : PhysRegFile
• numContexts() : BaseCPU , System
• numCycles() : sc_gem5::Scheduler
• numDestRegs() : BaseDynInst< Impl > , StaticInst
• numDomains() : DVFSHandler
• numDstRegOperands() : GPUDynInst , GPUStaticInst , HsailISA::AtomicInstBase< OperandType, AddrOperandType, NumSrcOperands, HasDst > , HsailISA::BrDirectInst , HsailISA::BrIndirectInst , HsailISA::BrnDirectInst , HsailISA::BrnIndirectInst , HsailISA::Call , HsailISA::CbrDirectInst , HsailISA::CbrIndirectInst , HsailISA::CommonInstBase< DestOperandType, SrcOperandType, NumSrcOperands > , HsailISA::LdaInstBase< DestOperandType, AddrOperandType > , HsailISA::LdInstBase< MemOperandType, DestOperandType, AddrOperandType > , HsailISA::SpecialInst1SrcBase< DestOperandType > , HsailISA::SpecialInstNoSrcBase< DestOperandType > , HsailISA::SpecialInstNoSrcNoDest , HsailISA::StInstBase< MemDataType, SrcOperandType, AddrOperandType > , HsailISA::Stub , HsailISA::ThreeNonUniformSourceInstBase< DestOperandType, Src0OperandType, Src1OperandType, Src2OperandType > , HsailISA::TwoNonUniformSourceInstBase< DestOperandType, Src0OperandType, Src1OperandType > , KernelLaunchStaticInst
• numFloatPhysRegs() : PhysRegFile
• numFPDestRegs() : BaseDynInst< Impl > , StaticInst
• numFreeCCEntries() : UnifiedRenameMap
• numFreeCCRegs() : UnifiedFreeList
• numFreeEntries() : InstructionQueue< Impl > , LSQ< Impl > , ROB< Impl > , SimpleRenameMap , UnifiedRenameMap
• numFreeFloatEntries() : UnifiedRenameMap
• numFreeFloatRegs() : UnifiedFreeList
• numFreeIntEntries() : UnifiedRenameMap
• numFreeIntRegs() : UnifiedFreeList
• numFreeLoadEntries() : LSQ< Impl > , LSQUnit< Impl >
• numFreePredEntries() : UnifiedRenameMap
• numFreeRegs() : SimpleFreeList
• numFreeStoreEntries() : LSQ< Impl > , LSQUnit< Impl >
• numFreeVecElems() : UnifiedFreeList
• numFreeVecEntries() : UnifiedRenameMap
• numFreeVecPredRegs() : UnifiedFreeList
• numFreeVecRegs() : UnifiedFreeList
• numInflight() : X86ISA::Walker::WalkerState
• numInFlightFetches() : Minor::Fetch1
• numInService() : Queue< Entry >
• numInsts() : HsaCode
• numIntDestRegs() : BaseDynInst< Impl > , StaticInst
• numIntPhysRegs() : PhysRegFile
• numItems() : X86ISA::MediaOpBase
• numKernels() : BrigObject , HsaObject
• numLoads() : LSQ< Impl > , LSQUnit< Impl >
• numPerfLevels() : DVFSHandler , SrcClockDomain
• numPredPhysRegs() : PhysRegFile
• numPriorities() : QoS::MemCtrl
• numRegs() : ConditionRegisterState , VectorRegisterFile
• numROBFreeEntries() : DefaultCommit< Impl >
• numRunningContexts() : System
• numSimulatedCPUs() : BaseCPU
• numSimulatedInsts() : BaseCPU
• numSimulatedOps() : BaseCPU
• numSrcRegOperands() : GPUDynInst , GPUStaticInst , HsailISA::AtomicInstBase< OperandType, AddrOperandType, NumSrcOperands, HasDst > , HsailISA::BrDirectInst , HsailISA::BrIndirectInst , HsailISA::BrnDirectInst , HsailISA::BrnIndirectInst , HsailISA::Call , HsailISA::CbrDirectInst , HsailISA::CbrIndirectInst , HsailISA::CommonInstBase< DestOperandType, SrcOperandType, NumSrcOperands > , HsailISA::LdaInstBase< DestOperandType, AddrOperandType > , HsailISA::LdInstBase< MemOperandType, DestOperandType, AddrOperandType > , HsailISA::SpecialInst1SrcBase< DestOperandType > , HsailISA::SpecialInstNoSrcBase< DestOperandType > , HsailISA::SpecialInstNoSrcNoDest , HsailISA::StInstBase< MemDataType, SrcOperandType, AddrOperandType > , HsailISA::Stub , HsailISA::ThreeNonUniformSourceInstBase< DestOperandType, Src0OperandType, Src1OperandType, Src2OperandType > , HsailISA::TwoNonUniformSourceInstBase< DestOperandType, Src0OperandType, Src1OperandType > , KernelLaunchStaticInst
• numSrcRegs() : BaseDynInst< Impl > , StaticInst
• numStores() : LSQ< Impl > , LSQUnit< Impl >
• numStoresToWB() : LSQ< Impl > , LSQUnit< Impl >
• numSwitches() : Topology
• numUnissuedStores() : Minor::LSQ::StoreBuffer
• numVecDestRegs() : BaseDynInst< Impl > , StaticInst
• numVecElemDestRegs() : BaseDynInst< Impl > , StaticInst
• numVecElemPhysRegs() : PhysRegFile
• numVecPhysRegs() : PhysRegFile
• numVecPredDestRegs() : BaseDynInst< Impl > , StaticInst
• numVoltages() : VoltageDomain
• nupc() : GenericISA::DelaySlotUPCState< MachInst > , GenericISA::UPCState< MachInst >
• nxt() : Net::Ip6Hdr , Net::Ip6Opt