Abstract superclass for simulation objects. More...

#include <sim_object.hh>

Inheritance diagram for SimObject:

Public Types
typedef SimObjectParams	Params

Public Member Functions
const Params *	params () const

	SimObject (const Params *_params)

virtual	~SimObject ()

virtual const std::string	name () const

virtual void	init ()
	init() is called after all C++ SimObjects have been created and all ports are connected. More...

virtual void	loadState (CheckpointIn &cp)
	loadState() is called on each SimObject when restoring from a checkpoint. More...

virtual void	initState ()
	initState() is called on each SimObject when not restoring from a checkpoint. More...

virtual void	regProbePoints ()
	Register probe points for this object. More...

virtual void	regProbeListeners ()
	Register probe listeners for this object. More...

ProbeManager *	getProbeManager ()
	Get the probe manager for this object. More...

virtual Port &	getPort (const std::string &if_name, PortID idx=InvalidPortID)
	Get a port with a given name and index. More...

virtual void	startup ()
	startup() is the final initialization call before simulation. More...

DrainState	drain () override
	Provide a default implementation of the drain interface for objects that don't need draining. More...

virtual void	memWriteback ()
	Write back dirty buffers to memory using functional writes. More...

virtual void	memInvalidate ()
	Invalidate the contents of memory buffers. More...

void	serialize (CheckpointOut &cp) const override
	Serialize an object. More...

void	unserialize (CheckpointIn &cp) override
	Unserialize an object. More...

Public Member Functions inherited from EventManager
	EventManager (EventManager &em)

	EventManager (EventManager *em)

	EventManager (EventQueue *eq)

EventQueue *	eventQueue () const

void	schedule (Event &event, Tick when)

void	deschedule (Event &event)

void	reschedule (Event &event, Tick when, bool always=false)

void	schedule (Event *event, Tick when)

void	deschedule (Event *event)

void	reschedule (Event *event, Tick when, bool always=false)

void	wakeupEventQueue (Tick when=(Tick) -1)

void	setCurTick (Tick newVal)

Public Member Functions inherited from Serializable
	Serializable ()

virtual	~Serializable ()

void	serializeSection (CheckpointOut &cp, const char *name) const
	Serialize an object into a new section. More...

void	serializeSection (CheckpointOut &cp, const std::string &name) const

void	unserializeSection (CheckpointIn &cp, const char *name)
	Unserialize an a child object. More...

void	unserializeSection (CheckpointIn &cp, const std::string &name)

Public Member Functions inherited from Drainable
DrainState	drainState () const
	Return the current drain state of an object. More...

virtual void	notifyFork ()
	Notify a child process of a fork. More...

Public Member Functions inherited from Stats::Group
	Group ()=delete

	Group (const Group &)=delete

Group &	operator= (const Group &)=delete

	Group (Group parent, const char name=nullptr)
	Construct a new statistics group. More...

virtual	~Group ()

virtual void	regStats ()
	Callback to set stat parameters. More...

virtual void	resetStats ()
	Callback to reset stats. More...

virtual void	preDumpStats ()
	Callback before stats are dumped. More...

void	addStat (Stats::Info *info)
	Register a stat with this group. More...

const std::map< std::string, Group * > &	getStatGroups () const
	Get all child groups associated with this object. More...

const std::vector< Info * > &	getStats () const
	Get all stats associated with this object. More...

void	addStatGroup (const char name, Group block)
	Add a stat block as a child of this block. More...

Static Public Member Functions
static void	serializeAll (CheckpointOut &cp)
	Serialize all SimObjects in the system. More...

static SimObject *	find (const char *name)
	Find the SimObject with the given name and return a pointer to it. More...

Static Public Member Functions inherited from Serializable
static const std::string &	currentSection ()
	Get the fully-qualified name of the active section. More...

static void	serializeAll (const std::string &cpt_dir)

static void	unserializeGlobals (CheckpointIn &cp)

Protected Attributes
const SimObjectParams *	_params
	Cached copy of the object parameters. More...

Protected Attributes inherited from EventManager
EventQueue *	eventq
	A pointer to this object's event queue. More...

Private Types
typedef std::vector< SimObject * >	SimObjectList

Private Attributes
ProbeManager *	probeManager
	Manager coordinates hooking up probe points with listeners. More...

Static Private Attributes
static SimObjectList	simObjectList
	List of all instantiated simulation objects. More...

Additional Inherited Members
Static Public Attributes inherited from Serializable
static int	ckptCount = 0

static int	ckptMaxCount = 0

static int	ckptPrevCount = -1

Protected Member Functions inherited from Drainable
	Drainable ()

virtual	~Drainable ()

virtual void	drainResume ()
	Resume execution after a successful drain. More...

void	signalDrainDone () const
	Signal that an object is drained. More...

Detailed Description

Abstract superclass for simulation objects.

Represents things that correspond to physical components and can be specified via the config file (CPUs, caches, etc.).

SimObject initialization is controlled by the instantiate method in src/python/m5/simulate.py. There are slightly different initialization paths when starting the simulation afresh and when loading from a checkpoint. After instantiation and connecting ports, simulate.py initializes the object using the following call sequence:

SimObject::init()
SimObject::regStats()
- SimObject::initState() if starting afresh.
- SimObject::loadState() if restoring from a checkpoint.
SimObject::resetStats()
SimObject::startup()
Drainable::drainResume() if resuming from a checkpoint.

Note: Whenever a method is called on all objects in the simulator's object tree (e.g., init(), startup(), or loadState()), a pre-order depth-first traversal is performed (see descendants() in SimObject.py). This has the effect of calling the method on the parent node before its children.

Definition at line 96 of file sim_object.hh.

Member Typedef Documentation

◆ Params

typedef SimObjectParams SimObject::Params

Definition at line 113 of file sim_object.hh.

◆ SimObjectList

typedef std::vector<SimObject *> SimObject::SimObjectList

private

Definition at line 100 of file sim_object.hh.

Constructor & Destructor Documentation

◆ SimObject()

SimObject::SimObject ( const Params * _params )

Definition at line 58 of file sim_object.cc.

References probeManager, and simObjectList.

Referenced by params().

◆ ~SimObject()

SimObject::~SimObject ( )

virtual

Definition at line 70 of file sim_object.cc.

References probeManager.

Referenced by params().

Member Function Documentation

◆ drain()

DrainState SimObject::drain ( )

inlineoverridevirtual

Provide a default implementation of the drain interface for objects that don't need draining.

Implements Drainable.

Reimplemented in FullO3CPU< O3CPUImpl >.

Definition at line 189 of file sim_object.hh.

References Drained.

Referenced by FullO3CPU< O3CPUImpl >::isDraining().

◆ find()

SimObject * SimObject::find ( const char * name )

static

Find the SimObject with the given name and return a pointer to it.

Primarily used for interactive debugging. Argument is char* rather than std::string to make it callable from gdb.

Definition at line 174 of file sim_object.cc.

References ArmISA::i, name(), and simObjectList.

Referenced by DVFSHandler::findDomain(), X86KvmCPU::getMsrIntersection(), and unserialize().

◆ getPort()

Port & SimObject::getPort	(	const std::string &	if_name,
		PortID	idx = `InvalidPortID`
	)

virtual

Get a port with a given name and index.

This is used at binding time and returns a reference to a protocol-agnostic port.

Parameters

if_name	Port name
idx	Index in the case of a VectorPort

Returns: A reference to the given port

Reimplemented in DRAMCtrl, BaseCache, ArmISA::TableWalker, ComputeUnit, IGbE, LdsState, BaseXBar, NSGigE, Bridge, SerialLink, SimpleCache, X86ISA::GpuTLB, BaseTrafficGen, SimpleMemobj, Sinic::Device, X86ISA::Interrupts, DistEtherLink, TLBCoalescer, DmaDevice, BaseCPU, CopyEngine, DRAMSim2, SMMUv3, SimpleMemory, X86ISA::Walker, EtherLink, RubyPort, PioDevice, GpuDispatcher, QoS::MemSinkCtrl, Network, AbstractController, X86ISA::I8042, ExternalSlave, FastModel::GIC, MessageBuffer, System, ExternalMaster, SMMUv3SlaveInterface, FastModel::CortexA76Cluster, X86ISA::I82094AA, EtherTapBase, Gicv3Its, RubyTester, X86ISA::I8259, FastModel::CortexA76, CommMonitor, X86ISA::Cmos, MemTest, EtherBus, X86ISA::I8254, MemCheckerMonitor, MemDelay, RubyDirectedTester, GarnetSyntheticTraffic, AddrMapper, and EtherSwitch.

Definition at line 126 of file sim_object.cc.

References fatal, and name().

Referenced by CxxConfigManager::bindPort(), EtherSwitch::getPort(), AddrMapper::getPort(), GarnetSyntheticTraffic::getPort(), RubyDirectedTester::getPort(), MemCheckerMonitor::getPort(), MemDelay::getPort(), MemTest::getPort(), CommMonitor::getPort(), RubyTester::getPort(), EtherTapBase::getPort(), FastModel::CortexA76Cluster::getPort(), SMMUv3SlaveInterface::getPort(), ExternalMaster::getPort(), ExternalSlave::getPort(), QoS::MemSinkCtrl::getPort(), PioDevice::getPort(), RubyPort::getPort(), EtherLink::getPort(), X86ISA::Walker::getPort(), SimpleMemory::getPort(), SMMUv3::getPort(), DRAMSim2::getPort(), BaseCPU::getPort(), DistEtherLink::getPort(), X86ISA::Interrupts::getPort(), SimpleMemobj::getPort(), BaseTrafficGen::getPort(), SimpleCache::getPort(), SerialLink::getPort(), Bridge::getPort(), BaseXBar::getPort(), ArmISA::TableWalker::getPort(), BaseCache::getPort(), DRAMCtrl::getPort(), and name().

◆ getProbeManager()

ProbeManager * SimObject::getProbeManager ( )

Get the probe manager for this object.

Definition at line 120 of file sim_object.cc.

References probeManager.

Referenced by BasePrefetcher::addEventProbe(), PIFPrefetcher::addEventProbeRetiredInsts(), name(), BPredUnit::pmuProbePoint(), BaseCPU::pmuProbePoint(), BasePrefetcher::regProbeListeners(), CommMonitor::regProbePoints(), PowerModel::regProbePoints(), FullO3CPU< O3CPUImpl >::regProbePoints(), AtomicSimpleCPU::regProbePoints(), BaseCPU::regProbePoints(), ArmISA::TLB::regProbePoints(), BaseCache::regProbePoints(), and ThermalDomain::setSubSystem().

◆ init()

void SimObject::init ( )

virtual

init() is called after all C++ SimObjects have been created and all ports are connected.

Initializations that are independent of unserialization but rely on a fully instantiated and connected SimObject graph should be done here.

Reimplemented in DRAMCtrl, BaseCache, MultiperspectivePerceptron, ArmISA::TableWalker, IGbE, CoherentXBar, Wavefront, Bridge, SerialLink, BaseCPU, ComputeUnit, QoS::MemCtrl, StatisticalCorrector, LoopPredictor, BaseTrafficGen, DistEtherLink, MultiperspectivePerceptronTAGE, ArmISA::TLB, FullO3CPU< Impl >, FullO3CPU< O3CPUImpl >, AbstractMemory, X86ISA::Interrupts, DmaDevice, DRAMSim2, SimpleMemory, CpuLocalTimer, SMMUv3, Shader, TraceCPU, RubyPort, QoS::MemSinkCtrl, PioDevice, EnergyCtrl, ExternalSlave, ExternalMaster, TrafficGen, MinorCPU, Iris::BaseCPU, Gicv3, System, RubyTester, X86ISA::I82094AA, BaseSimpleCPU, CheckerCPU, BaseKvmCPU, Network, Tsunami, CommMonitor, SimPoint, GarnetExtLink, AbstractController, RubyDirectedTester, MemCheckerMonitor, Process, RubyPortProxy, LTAGE, BaseGic, MemDelay, AddrMapper, QoS::Policy, Router, TAGEBase, Switch, GarnetSyntheticTraffic, QoS::FixedPriorityPolicy, DirectoryMemory, WireBuffer, DMASequencer, Pc, AtomicSimpleCPU, GarnetNetwork, NetworkInterface, CacheMemory, TimingSimpleCPU, NoMaliGpu, EtherDump, GarnetIntLink, sc_gem5::Kernel, BasicLink, SimpleNetwork, X86ISA::I8259, and BasicRouter.

Definition at line 76 of file sim_object.cc.

Referenced by RenameMode< ArmISA::ISA >::equalsInit(), LTAGE::init(), BaseTrafficGen::init(), CoherentXBar::init(), CxxConfigManager::instantiate(), and name().

◆ initState()

void SimObject::initState ( )

virtual

initState() is called on each SimObject when not restoring from a checkpoint.

This provides a hook for state initializations that are only required for a "cold start".

Reimplemented in System, GenericArmSystem, X86ISA::I386Process, ArmSystem, Sparc64Process, LinuxAlphaSystem, X86ISA::X86_64Process, TrafficGen, Sparc32Process, ArmProcess64, ArmLinuxProcess64, LinuxArmSystem, X86System, FastModel::CortexA76, ArmFreebsdProcess64, ArmProcess32, Process, FreebsdArmSystem, ArmLinuxProcess32, RiscvProcess32, RiscvProcess64, ArmFreebsdProcess32, LinuxX86System, AlphaSystem, SparcProcess, SparcSystem, PowerProcess, MipsProcess, PowerLinuxProcess, BareMetalRiscvSystem, and AlphaProcess.

Definition at line 94 of file sim_object.cc.

Referenced by TrafficGen::initState(), CxxConfigManager::initState(), name(), and X86ISA::Walker::WalkerState::WalkerState().

◆ loadState()

void SimObject::loadState ( CheckpointIn & cp )

virtual

loadState() is called on each SimObject when restoring from a checkpoint.

The default implementation simply calls unserialize() if there is a corresponding section in the checkpoint. However, objects can override loadState() to get other behaviors, e.g., doing other programmed initializations after unserialize(), or complaining if no checkpoint section is found.

Parameters

cp	Checkpoint to restore the state from.

Definition at line 81 of file sim_object.cc.

References DPRINTF, name(), CheckpointIn::sectionExists(), and Serializable::unserializeSection().

Referenced by name().

◆ memInvalidate()

virtual void SimObject::memInvalidate ( )

inlinevirtual

Invalidate the contents of memory buffers.

When the switching to hardware virtualized CPU models, we need to make sure that we don't have any cached state in the system that might become stale when we return. This method is used to flush all such state back to main memory.

This does not cause any dirty state to be written back to memory.

Reimplemented in BaseCache, and BaseTLB.

Definition at line 212 of file sim_object.hh.

◆ memWriteback()

virtual void SimObject::memWriteback ( )

inlinevirtual

Write back dirty buffers to memory using functional writes.

After returning, an object implementing this method should have written all its dirty data back to memory. This method is typically used to prepare a system with caches for checkpointing.

Reimplemented in BaseCache, MinorCPU, and RubySystem.

Definition at line 199 of file sim_object.hh.

◆ name()

virtual const std::string SimObject::name ( ) const

inlinevirtual

Reimplemented in ElasticTrace, and SimpleTrace.

Definition at line 120 of file sim_object.hh.

References getPort(), getProbeManager(), init(), initState(), InvalidPortID, loadState(), params(), regProbeListeners(), regProbePoints(), and startup().

Referenced by System::_getMasterId(), Terminal::accept(), VncServer::accept(), Cache::access(), BaseCache::access(), AccessMapPatternMatching::AccessMapPatternMatching(), ArmISA::PMU::addEventProbe(), StridePrefetcher::allocateNewContext(), AtomicSimpleCPU::AtomicSimpleCPU(), SMMUv3SlaveInterface::atsSlaveRecvAtomic(), SMMUv3SlaveInterface::atsSlaveRecvTimingReq(), BaseCache::BaseCache(), BaseCPU::BaseCPU(), BaseTrafficGen::BaseTrafficGen(), CxxConfigManager::bindMasterPort(), CxxConfigManager::bindPort(), BOPPrefetcher::BOPPrefetcher(), NetworkInterface::calculateVC(), TraceCPU::checkAndSchedExitEvent(), DVFSHandler::clkPeriodAtPerfLevel(), SrcClockDomain::clockPeriod(), RealViewOsc::clockPeriod(), CoherentXBar::CoherentXBar(), CommMonitor::CommMonitor(), MemTest::completeRequest(), Sinic::Base::cpuIntrPost(), NSGigE::cpuIntrPost(), X86ISA::StackTrace::decodePrologue(), AlphaISA::StackTrace::decodePrologue(), Sinic::Device::Device(), DistEtherLink::DistEtherLink(), Pl111::dmaDone(), DRAMCtrl::DRAMCtrl(), DRAMSim2::DRAMSim2(), FUPool::dump(), SimpleThread::dumpFuncProfile(), ArmKvmCPU::dumpKvmStateCoProc(), DVFSHandler::DVFSHandler(), IdeController::EndBitUnion(), EnergyCtrl::EnergyCtrl(), MessageBuffer::enqueue(), EtherLink::EtherLink(), EtherSwitch::EtherSwitch(), find(), FlashDevice::FlashDevice(), FullO3CPU< O3CPUImpl >::FullO3CPU(), BaseCache::functionalAccess(), GarnetSyntheticTraffic::GarnetSyntheticTraffic(), GenericTimerMem::GenericTimerMem(), GicV2::getCpuTarget(), FastModel::GIC::getPort(), getPort(), ComputeUnit::getPort(), Gicv3Its::Gicv3Its(), GoodbyeObject::GoodbyeObject(), GpuDispatcher::GpuDispatcher(), X86ISA::GpuTLB::GpuTLB(), BaseCache::handleFill(), SimpleCache::handleRequest(), Cache::handleSnoop(), HDLcd::HDLcd(), HelloObject::HelloObject(), CPA::hwWe(), X86ISA::I8042::I8042(), X86ISA::I82094AA::I82094AA(), X86ISA::I8259::I8259(), IdeDisk::IdeDisk(), IGbE::IGbE(), FetchStage::init(), LocalMemPipeline::init(), ScheduleStage::init(), GlobalMemPipeline::init(), ScoreboardCheckStage::init(), ExecStage::init(), System::init(), ExternalMaster::init(), ExternalSlave::init(), PioDevice::init(), TraceCPU::init(), CpuLocalTimer::init(), DRAMSim2::init(), DmaDevice::init(), BaseTrafficGen::init(), CoherentXBar::init(), BaseCache::init(), DRAMCtrl::init(), Process::initState(), X86ISA::Interrupts::Interrupts(), System::leafMasterName(), LinuxArmSystem::LinuxArmSystem(), Terminal::listen(), VncServer::listen(), loadState(), System::lookupMasterId(), MathExprPowerModel::MathExprPowerModel(), MemTest::MemTest(), MemTraceProbe::MemTraceProbe(), SMMUDeviceRetryEvent::name(), SimpleTrace::name(), CopyEngine::CopyEngineChannel::name(), PciHost::DeviceInterface::name(), ElasticTrace::name(), BaseRemoteGDB::name(), X86ISA::Walker::WalkerState::name(), ItsProcess::name(), DRAMCtrl::Rank::name(), ArmISA::TableWalker::WalkerState::name(), NoncoherentXBar::NoncoherentXBar(), BaseTrafficGen::noProgress(), MemTest::noRequest(), MemTest::noResponse(), NSGigE::NSGigE(), Linux::openSpecialFile(), TrafficGen::parseConfig(), VoltageDomain::perfLevel(), SrcClockDomain::perfLevel(), Minor::Pipeline::Pipeline(), Pl011::Pl011(), PL031::PL031(), Pl111::Pl111(), BasicRouter::print(), SimpleExtLink::print(), BasicLink::print(), GarnetIntLink::print(), SimpleIntLink::print(), GarnetExtLink::print(), Prefetcher::print(), MessageBuffer::print(), CacheMemory::print(), System::printSystems(), EndQuiesceEvent::process(), Linux::DebugPrintkEvent::process(), Linux::DmesgDumpEvent::process(), AnnotateDumpCallback::process(), Linux::KernelPanicEvent::process(), CPUProgressEvent::process(), TLBCoalescer::processProbeTLBEvent(), ClockedObject::pwrState(), HDLcd::pxlFrameDone(), ThreadContext::quiesceTick(), AmbaFake::read(), IsaFake::read(), UFSHostDevice::readCallback(), PciDevice::readConfig(), UFSHostDevice::readDevice(), IdeDisk::readDisk(), CacheMemory::recordCacheContents(), SMMUv3SlaveInterface::recvAtomic(), NoncoherentXBar::recvAtomicBackdoor(), CoherentXBar::recvAtomicBackdoor(), CoherentXBar::recvAtomicSnoop(), NoncoherentXBar::recvFunctional(), SimpleMemory::recvFunctional(), SerialLink::SerialLinkSlavePort::recvFunctional(), DRAMSim2::recvFunctional(), Bridge::BridgeSlavePort::recvFunctional(), QoS::MemSinkCtrl::recvFunctional(), CoherentXBar::recvFunctional(), CoherentXBar::recvFunctionalSnoop(), SMMUv3SlaveInterface::recvTimingReq(), CoherentXBar::recvTimingReq(), MemCheckerMonitor::recvTimingResp(), AddrMapper::recvTimingResp(), BaseCache::recvTimingResp(), CoherentXBar::recvTimingSnoopReq(), System::registerThreadContext(), StackDistProbe::regStats(), SimpleNetwork::regStats(), EtherDevice::regStats(), MemFootprintProbe::regStats(), TAGEBase::regStats(), Switch::regStats(), RubySystem::regStats(), BPredUnit::regStats(), MemTest::regStats(), MultiCompressor::regStats(), BaseKvmCPU::regStats(), PowerModelState::regStats(), AlphaISA::TLB::regStats(), ThermalDomain::regStats(), HDLcd::regStats(), AbstractController::regStats(), BaseDictionaryCompressor::regStats(), Router::regStats(), GarnetNetwork::regStats(), GPUCoalescer::regStats(), RiscvISA::TLB::regStats(), Prefetcher::regStats(), MipsISA::TLB::regStats(), Process::regStats(), CacheMemory::regStats(), MessageBuffer::regStats(), PowerModel::regStats(), MinorCPU::regStats(), BaseSimpleCPU::regStats(), TLBCoalescer::regStats(), FlashDevice::regStats(), X86ISA::TLB::regStats(), FALRU::regStats(), SMMUv3::regStats(), PowerISA::TLB::regStats(), FullO3CPU< O3CPUImpl >::regStats(), QueuedPrefetcher::regStats(), SnoopFilter::regStats(), X86ISA::GpuTLB::regStats(), QoS::MemSinkCtrl::regStats(), LoopPredictor::regStats(), StatisticalCorrector::regStats(), IdeDisk::regStats(), Sinic::Device::regStats(), BaseCPU::regStats(), SimpleCache::regStats(), Wavefront::regStats(), BasePrefetcher::regStats(), ComputeUnit::regStats(), ArmISA::TLB::regStats(), System::regStats(), TraceCPU::ElasticDataGen::regStats(), UFSHostDevice::regStats(), TraceCPU::regStats(), UFSHostDevice::requestHandler(), TrafficGen::resolveFile(), Root::Root(), RubyDirectedTester::RubyDirectedTester(), RubyPort::RubyPort(), RubyTester::RubyTester(), VoltageDomain::sanitiseVoltages(), SBOOEPrefetcher::SBOOEPrefetcher(), RubySystem::serialize(), CowDiskImage::serialize(), BaseTrafficGen::serialize(), serializeAll(), Cache::serviceMSHRTargets(), WireBuffer::setDescription(), ConditionRegisterState::setParent(), VecRegisterState::setParent(), LdsState::setParent(), ArmISA::TLB::setTestInterface(), SimpleCache::SimpleCache(), SimpleMemory::SimpleMemory(), SMMUv3::SMMUv3(), Sp805::Sp805(), SrcClockDomain::SrcClockDomain(), MemTraceProbe::startup(), BaseKvmCPU::startup(), LinuxArmSystem::startup(), VoltageDomain::startup(), System::stripSystemName(), FastModel::GIC::supportsVersion(), ArmISA::TableWalker::TableWalker(), ThermalModel::ThermalModel(), GarnetSyntheticTraffic::tick(), MemTest::tick(), TimingSimpleCPU::TimingCPUPort::TimingCPUPort(), TimingSimpleCPU::TimingSimpleCPU(), TLBCoalescer::TLBCoalescer(), TraceCPU::TraceCPU(), QueuedPrefetcher::translationComplete(), DrainManager::tryDrain(), RubyPort::trySendRetries(), UFSHostDevice::UFSHostDevice(), Sinic::Base::unserialize(), unserialize(), BaseTrafficGen::unserialize(), NSGigE::unserialize(), BaseTrafficGen::update(), DerivedClockDomain::updateClockPeriod(), TraceCPU::updateNumOps(), VncInput::VncInput(), VoltageDomain::voltage(), DVFSHandler::voltageAtPerfLevel(), VoltageDomain::VoltageDomain(), AmbaFake::write(), IsaFake::write(), PciDevice::writeConfig(), UFSHostDevice::writeDevice(), IdeDisk::writeDisk(), PIFPrefetcher::~PIFPrefetcher(), SimObjectResolver::~SimObjectResolver(), and SMMUv3::~SMMUv3().

◆ params()

const Params* SimObject::params ( ) const

inline

◆ regProbeListeners()

void SimObject::regProbeListeners ( )

virtual

Register probe listeners for this object.

No probe listeners by default, so do nothing in base.

Reimplemented in BasePrefetcher, ArmISA::PMU, ElasticTrace, SimPoint, BaseMemProbe, and SimpleTrace.

Definition at line 115 of file sim_object.cc.

Referenced by CxxConfigManager::instantiate(), and name().

◆ regProbePoints()

void SimObject::regProbePoints ( )

virtual

Register probe points for this object.

No probe points by default, so do nothing in base.

Reimplemented in BaseCache, ArmISA::TLB, BaseCPU, AtomicSimpleCPU, FullO3CPU< Impl >, FullO3CPU< O3CPUImpl >, PowerModel, CommMonitor, and BPredUnit.

Definition at line 107 of file sim_object.cc.

Referenced by CxxConfigManager::instantiate(), name(), and PowerModel::regStats().

◆ serialize()

void SimObject::serialize ( CheckpointOut & cp ) const

inlineoverridevirtual

Serialize an object.

Output an object's state into the current checkpoint section.

Parameters

cp	Checkpoint state

Implements Serializable.

Reimplemented in System, TickedObject, and VoltageDomain.

Definition at line 214 of file sim_object.hh.

Referenced by SrcClockDomain::clkPeriodAtPerfLevel(), and SrcClockDomain::serialize().

◆ serializeAll()

void SimObject::serializeAll ( CheckpointOut & cp )

static

Serialize all SimObjects in the system.

Definition at line 135 of file sim_object.cc.

References ArmISA::i, ObjectMatch::match(), name(), Serializable::serializeSection(), and simObjectList.

Referenced by Serializable::serializeAll(), and unserialize().

◆ startup()

void SimObject::startup ( )

virtual

startup() is the final initialization call before simulation.

All state is initialized (including unserialized state, if any, such as the curTick() value), so this is the appropriate place to schedule initial event(s) for objects that need them.

Reimplemented in DRAMCtrl, VirtIO9PSocket, BaseCPU, VirtIO9PDiod, SrcClockDomain, DistEtherLink, FullO3CPU< Impl >, FullO3CPU< O3CPUImpl >, RealViewOsc, DRAMSim2, AccessMapPatternMatching, MuxingKvmGic, ThermalModel, TsunamiIO, BaseSimpleCPU, MaltaIO, EnergyCtrl, MinorCPU, X86ISA::I8254, VoltageDomain, AlphaBackdoor, Root, X86ISA::Cmos, LinuxArmSystem, RubySystem, ArmV8KvmCPU, MathExprPowerModel, BaseKvmCPU, CommMonitor, FreebsdArmSystem, HelloObject, AlphaSystem, ArmKvmCPU, MemTraceProbe, BaseArmKvmCPU, sc_gem5::Kernel, and X86KvmCPU.

Definition at line 99 of file sim_object.cc.

Referenced by ThermalModel::addNode(), SrcClockDomain::clkPeriodAtPerfLevel(), X86ISA::ISA::flattenMiscIndex(), name(), RiscvISA::ISA::startup(), MipsISA::ISA::startup(), PowerISA::ISA::startup(), AlphaISA::ISA::startup(), SparcISA::ISA::startup(), MuxingKvmGic::startup(), CxxConfigManager::startup(), ArmISA::ISA::unserialize(), ArmISA::ISA::vecRegRenameMode(), and RealViewOsc::~RealViewOsc().

◆ unserialize()

void SimObject::unserialize ( CheckpointIn & cp )

inlineoverridevirtual

Unserialize an object.

Read an object's state from the current checkpoint section.

Parameters

cp	Checkpoint state

Implements Serializable.

Reimplemented in System, TickedObject, and VoltageDomain.

Definition at line 215 of file sim_object.hh.

References find(), name(), and serializeAll().

Referenced by SrcClockDomain::clkPeriodAtPerfLevel(), and SrcClockDomain::unserialize().

Member Data Documentation

◆ _params

const SimObjectParams* SimObject::_params

protected

Cached copy of the object parameters.

Definition at line 110 of file sim_object.hh.

Referenced by GenericTimer::createTimers(), ArmPPIGen::get(), BasicRouter::params(), SimpleExtLink::params(), BasicLink::params(), X86ISA::I8237::params(), PowerISA::Interrupts::params(), BaseInterrupts::params(), MipsISA::Interrupts::params(), EtherDevice::params(), MmDisk::params(), BadDevice::params(), DumbTOD::params(), EtherSwitch::params(), MemCheckerMonitor::params(), FaultModel::params(), Uart::params(), X86ISA::Speaker::params(), QoS::PropFairPolicy::params(), AmbaFake::params(), IsaFake::params(), EtherBus::params(), AlphaISA::Interrupts::params(), SimpleIntLink::params(), RiscvISA::Interrupts::params(), EtherTapBase::params(), X86ISA::ISA::params(), RealView::params(), TsunamiPChip::params(), CommMonitor::params(), BasicExtLink::params(), BaseGic::params(), ArmISA::Interrupts::params(), SparcISA::Interrupts::params(), Network::params(), Sinic::Base::params(), X86ISA::I8254::params(), BasicIntLink::params(), MaltaCChip::params(), Uart8250::params(), X86ISA::I8259::params(), TsunamiCChip::params(), X86ISA::I82094AA::params(), RiscvISA::ISA::params(), Root::params(), PL031::params(), Trace::ArmNativeTrace::params(), AlphaBackdoor::params(), MaltaIO::params(), params(), Gicv3::params(), TsunamiIO::params(), X86ISA::I8042::params(), Iob::params(), SMMUv3SlaveInterface::params(), EtherDevBase::params(), Sp804::params(), MipsISA::ISA::params(), PowerISA::ISA::params(), AlphaISA::ISA::params(), IdeController::params(), EtherTapStub::params(), EtherLink::params(), A9GlobalTimer::params(), RealViewCtrl::params(), CpuLocalTimer::params(), CopyEngine::params(), VGic::params(), X86ISA::Walker::params(), X86ISA::Interrupts::params(), DistEtherLink::params(), GenericTimer::params(), SparcISA::ISA::params(), Pl111::params(), GicV2::params(), IGbE::params(), ArmISA::ISA::params(), ArmISA::TableWalker::params(), and CheckerCPU::setSystem().

◆ probeManager

ProbeManager* SimObject::probeManager

private

Manager coordinates hooking up probe points with listeners.

Definition at line 106 of file sim_object.hh.

Referenced by getProbeManager(), SimObject(), and ~SimObject().

◆ simObjectList

SimObject::SimObjectList SimObject::simObjectList

staticprivate

List of all instantiated simulation objects.

Definition at line 103 of file sim_object.hh.

Referenced by find(), serializeAll(), and SimObject().

The documentation for this class was generated from the following files:

sim/sim_object.hh
sim/sim_object.cc

Public Types

Public Member Functions

Static Public Member Functions

Protected Attributes

Private Types

Private Attributes

Static Private Attributes

Additional Inherited Members

Detailed Description

Member Typedef Documentation

◆ Params

◆ SimObjectList

Constructor & Destructor Documentation

◆ SimObject()

◆ ~SimObject()

Member Function Documentation

◆ drain()

◆ find()

◆ getPort()

◆ getProbeManager()

◆ init()

◆ initState()

◆ loadState()

◆ memInvalidate()

◆ memWriteback()

◆ name()

◆ params()

◆ regProbeListeners()

◆ regProbePoints()

◆ serialize()

◆ serializeAll()

◆ startup()

◆ unserialize()

Member Data Documentation

◆ _params

◆ probeManager

◆ simObjectList