Namespaces
	Kernel

Classes
class	AddressFault

class	AtomicGenericOp
	A generic atomic op class. More...

class	AtomicMemOp

class	AtomicMemOpMicro

class	BreakpointFault

class	CompRegOp
	Base class for compressed operations that work only on registers. More...

struct	CSRMetadata

class	CSROp
	Base class for CSR operations. More...

class	Decoder

class	IllegalFrmFault

class	IllegalInstFault

class	ImmOp
	Base class for operations with immediates (I is the type of immediate) More...

class	InstFault

class	InterruptFault

class	Interrupts

class	ISA

class	Load

class	LoadReserved

class	LoadReservedMicro

class	MemFenceMicro

class	MemInst

class	PCState

class	ProcessInfo

struct	PTE

class	RegOp
	Base class for operations that work only on registers. More...

class	RemoteGDB

class	Reset

class	RiscvFault

class	RiscvMacroInst
	Base class for all RISC-V Macroops. More...

class	RiscvMicroInst
	Base class for all RISC-V Microops. More...

class	RiscvStaticInst
	Base class for all RISC-V static instructions. More...

class	StackTrace

class	Store

class	StoreCond

class	StoreCondMicro

class	SyscallFault

class	SystemOp
	Base class for system operations. More...

class	TLB

struct	TlbEntry

class	UnimplementedFault

class	Unknown
	Static instruction class for unknown (illegal) instructions. More...

class	UnknownInstFault

struct	VAddr

Typedefs
using	VecElem = ::DummyVecElem

using	VecReg = ::DummyVecReg

using	ConstVecReg = ::DummyConstVecReg

using	VecRegContainer = ::DummyVecRegContainer

using	VecPredReg = ::DummyVecPredReg

using	ConstVecPredReg = ::DummyConstVecPredReg

using	VecPredRegContainer = ::DummyVecPredRegContainer

typedef uint32_t	MachInst

typedef uint64_t	ExtMachInst

Enumerations
enum	FloatException : uint64_t { FloatInexact = 0x1, FloatUnderflow = 0x2, FloatOverflow = 0x4, FloatDivZero = 0x8, FloatInvalid = 0x10 }

enum	ExceptionCode : uint64_t { INST_ADDR_MISALIGNED = 0, INST_ACCESS = 1, INST_ILLEGAL = 2, BREAKPOINT = 3, LOAD_ADDR_MISALIGNED = 4, LOAD_ACCESS = 5, STORE_ADDR_MISALIGNED = 6, AMO_ADDR_MISALIGNED = 6, STORE_ACCESS = 7, AMO_ACCESS = 7, ECALL_USER = 8, ECALL_SUPER = 9, ECALL_MACHINE = 11, INST_PAGE = 12, LOAD_PAGE = 13, STORE_PAGE = 15, AMO_PAGE = 15, INT_SOFTWARE_USER = 0, INT_SOFTWARE_SUPER = 1, INT_SOFTWARE_MACHINE = 3, INT_TIMER_USER = 4, INT_TIMER_SUPER = 5, INT_TIMER_MACHINE = 7, INT_EXT_USER = 8, INT_EXT_SUPER = 9, INT_EXT_MACHINE = 11, NumInterruptTypes }

enum	PrivilegeMode { PRV_U = 0, PRV_S = 1, PRV_M = 3 }

enum	MiscRegIndex { MISCREG_PRV = 0, MISCREG_ISA, MISCREG_VENDORID, MISCREG_ARCHID, MISCREG_IMPID, MISCREG_HARTID, MISCREG_STATUS, MISCREG_IP, MISCREG_IE, MISCREG_CYCLE, MISCREG_TIME, MISCREG_INSTRET, MISCREG_HPMCOUNTER03, MISCREG_HPMCOUNTER04, MISCREG_HPMCOUNTER05, MISCREG_HPMCOUNTER06, MISCREG_HPMCOUNTER07, MISCREG_HPMCOUNTER08, MISCREG_HPMCOUNTER09, MISCREG_HPMCOUNTER10, MISCREG_HPMCOUNTER11, MISCREG_HPMCOUNTER12, MISCREG_HPMCOUNTER13, MISCREG_HPMCOUNTER14, MISCREG_HPMCOUNTER15, MISCREG_HPMCOUNTER16, MISCREG_HPMCOUNTER17, MISCREG_HPMCOUNTER18, MISCREG_HPMCOUNTER19, MISCREG_HPMCOUNTER20, MISCREG_HPMCOUNTER21, MISCREG_HPMCOUNTER22, MISCREG_HPMCOUNTER23, MISCREG_HPMCOUNTER24, MISCREG_HPMCOUNTER25, MISCREG_HPMCOUNTER26, MISCREG_HPMCOUNTER27, MISCREG_HPMCOUNTER28, MISCREG_HPMCOUNTER29, MISCREG_HPMCOUNTER30, MISCREG_HPMCOUNTER31, MISCREG_HPMEVENT03, MISCREG_HPMEVENT04, MISCREG_HPMEVENT05, MISCREG_HPMEVENT06, MISCREG_HPMEVENT07, MISCREG_HPMEVENT08, MISCREG_HPMEVENT09, MISCREG_HPMEVENT10, MISCREG_HPMEVENT11, MISCREG_HPMEVENT12, MISCREG_HPMEVENT13, MISCREG_HPMEVENT14, MISCREG_HPMEVENT15, MISCREG_HPMEVENT16, MISCREG_HPMEVENT17, MISCREG_HPMEVENT18, MISCREG_HPMEVENT19, MISCREG_HPMEVENT20, MISCREG_HPMEVENT21, MISCREG_HPMEVENT22, MISCREG_HPMEVENT23, MISCREG_HPMEVENT24, MISCREG_HPMEVENT25, MISCREG_HPMEVENT26, MISCREG_HPMEVENT27, MISCREG_HPMEVENT28, MISCREG_HPMEVENT29, MISCREG_HPMEVENT30, MISCREG_HPMEVENT31, MISCREG_TSELECT, MISCREG_TDATA1, MISCREG_TDATA2, MISCREG_TDATA3, MISCREG_DCSR, MISCREG_DPC, MISCREG_DSCRATCH, MISCREG_MEDELEG, MISCREG_MIDELEG, MISCREG_MTVEC, MISCREG_MCOUNTEREN, MISCREG_MSCRATCH, MISCREG_MEPC, MISCREG_MCAUSE, MISCREG_MTVAL, MISCREG_PMPCFG0, MISCREG_PMPCFG2, MISCREG_PMPADDR00, MISCREG_PMPADDR01, MISCREG_PMPADDR02, MISCREG_PMPADDR03, MISCREG_PMPADDR04, MISCREG_PMPADDR05, MISCREG_PMPADDR06, MISCREG_PMPADDR07, MISCREG_PMPADDR08, MISCREG_PMPADDR09, MISCREG_PMPADDR10, MISCREG_PMPADDR11, MISCREG_PMPADDR12, MISCREG_PMPADDR13, MISCREG_PMPADDR14, MISCREG_PMPADDR15, MISCREG_SEDELEG, MISCREG_SIDELEG, MISCREG_STVEC, MISCREG_SCOUNTEREN, MISCREG_SSCRATCH, MISCREG_SEPC, MISCREG_SCAUSE, MISCREG_STVAL, MISCREG_SATP, MISCREG_UTVEC, MISCREG_USCRATCH, MISCREG_UEPC, MISCREG_UCAUSE, MISCREG_UTVAL, MISCREG_FFLAGS, MISCREG_FRM, NUM_MISCREGS }

enum	CSRIndex { CSR_USTATUS = 0x000, CSR_UIE = 0x004, CSR_UTVEC = 0x005, CSR_USCRATCH = 0x040, CSR_UEPC = 0x041, CSR_UCAUSE = 0x042, CSR_UTVAL = 0x043, CSR_UIP = 0x044, CSR_FFLAGS = 0x001, CSR_FRM = 0x002, CSR_FCSR = 0x003, CSR_CYCLE = 0xC00, CSR_TIME = 0xC01, CSR_INSTRET = 0xC02, CSR_HPMCOUNTER03 = 0xC03, CSR_HPMCOUNTER04 = 0xC04, CSR_HPMCOUNTER05 = 0xC05, CSR_HPMCOUNTER06 = 0xC06, CSR_HPMCOUNTER07 = 0xC07, CSR_HPMCOUNTER08 = 0xC08, CSR_HPMCOUNTER09 = 0xC09, CSR_HPMCOUNTER10 = 0xC0A, CSR_HPMCOUNTER11 = 0xC0B, CSR_HPMCOUNTER12 = 0xC0C, CSR_HPMCOUNTER13 = 0xC0D, CSR_HPMCOUNTER14 = 0xC0E, CSR_HPMCOUNTER15 = 0xC0F, CSR_HPMCOUNTER16 = 0xC10, CSR_HPMCOUNTER17 = 0xC11, CSR_HPMCOUNTER18 = 0xC12, CSR_HPMCOUNTER19 = 0xC13, CSR_HPMCOUNTER20 = 0xC14, CSR_HPMCOUNTER21 = 0xC15, CSR_HPMCOUNTER22 = 0xC16, CSR_HPMCOUNTER23 = 0xC17, CSR_HPMCOUNTER24 = 0xC18, CSR_HPMCOUNTER25 = 0xC19, CSR_HPMCOUNTER26 = 0xC1A, CSR_HPMCOUNTER27 = 0xC1B, CSR_HPMCOUNTER28 = 0xC1C, CSR_HPMCOUNTER29 = 0xC1D, CSR_HPMCOUNTER30 = 0xC1E, CSR_HPMCOUNTER31 = 0xC1F, CSR_SSTATUS = 0x100, CSR_SEDELEG = 0x102, CSR_SIDELEG = 0x103, CSR_SIE = 0x104, CSR_STVEC = 0x105, CSR_SCOUNTEREN = 0x106, CSR_SSCRATCH = 0x140, CSR_SEPC = 0x141, CSR_SCAUSE = 0x142, CSR_STVAL = 0x143, CSR_SIP = 0x144, CSR_SATP = 0x180, CSR_MVENDORID = 0xF11, CSR_MARCHID = 0xF12, CSR_MIMPID = 0xF13, CSR_MHARTID = 0xF14, CSR_MSTATUS = 0x300, CSR_MISA = 0x301, CSR_MEDELEG = 0x302, CSR_MIDELEG = 0x303, CSR_MIE = 0x304, CSR_MTVEC = 0x305, CSR_MCOUNTEREN = 0x306, CSR_MSCRATCH = 0x340, CSR_MEPC = 0x341, CSR_MCAUSE = 0x342, CSR_MTVAL = 0x343, CSR_MIP = 0x344, CSR_PMPCFG0 = 0x3A0, CSR_PMPCFG2 = 0x3A2, CSR_PMPADDR00 = 0x3B0, CSR_PMPADDR01 = 0x3B1, CSR_PMPADDR02 = 0x3B2, CSR_PMPADDR03 = 0x3B3, CSR_PMPADDR04 = 0x3B4, CSR_PMPADDR05 = 0x3B5, CSR_PMPADDR06 = 0x3B6, CSR_PMPADDR07 = 0x3B7, CSR_PMPADDR08 = 0x3B8, CSR_PMPADDR09 = 0x3B9, CSR_PMPADDR10 = 0x3BA, CSR_PMPADDR11 = 0x3BB, CSR_PMPADDR12 = 0x3BC, CSR_PMPADDR13 = 0x3BD, CSR_PMPADDR14 = 0x3BE, CSR_PMPADDR15 = 0x3BF, CSR_MCYCLE = 0xB00, CSR_MINSTRET = 0xB02, CSR_MHPMCOUNTER03 = 0xC03, CSR_MHPMCOUNTER04 = 0xC04, CSR_MHPMCOUNTER05 = 0xC05, CSR_MHPMCOUNTER06 = 0xC06, CSR_MHPMCOUNTER07 = 0xC07, CSR_MHPMCOUNTER08 = 0xC08, CSR_MHPMCOUNTER09 = 0xC09, CSR_MHPMCOUNTER10 = 0xC0A, CSR_MHPMCOUNTER11 = 0xC0B, CSR_MHPMCOUNTER12 = 0xC0C, CSR_MHPMCOUNTER13 = 0xC0D, CSR_MHPMCOUNTER14 = 0xC0E, CSR_MHPMCOUNTER15 = 0xC0F, CSR_MHPMCOUNTER16 = 0xC10, CSR_MHPMCOUNTER17 = 0xC11, CSR_MHPMCOUNTER18 = 0xC12, CSR_MHPMCOUNTER19 = 0xC13, CSR_MHPMCOUNTER20 = 0xC14, CSR_MHPMCOUNTER21 = 0xC15, CSR_MHPMCOUNTER22 = 0xC16, CSR_MHPMCOUNTER23 = 0xC17, CSR_MHPMCOUNTER24 = 0xC18, CSR_MHPMCOUNTER25 = 0xC19, CSR_MHPMCOUNTER26 = 0xC1A, CSR_MHPMCOUNTER27 = 0xC1B, CSR_MHPMCOUNTER28 = 0xC1C, CSR_MHPMCOUNTER29 = 0xC1D, CSR_MHPMCOUNTER30 = 0xC1E, CSR_MHPMCOUNTER31 = 0xC1F, CSR_MHPMEVENT03 = 0x323, CSR_MHPMEVENT04 = 0x324, CSR_MHPMEVENT05 = 0x325, CSR_MHPMEVENT06 = 0x326, CSR_MHPMEVENT07 = 0x327, CSR_MHPMEVENT08 = 0x328, CSR_MHPMEVENT09 = 0x329, CSR_MHPMEVENT10 = 0x32A, CSR_MHPMEVENT11 = 0x32B, CSR_MHPMEVENT12 = 0x32C, CSR_MHPMEVENT13 = 0x32D, CSR_MHPMEVENT14 = 0x32E, CSR_MHPMEVENT15 = 0x32F, CSR_MHPMEVENT16 = 0x330, CSR_MHPMEVENT17 = 0x331, CSR_MHPMEVENT18 = 0x332, CSR_MHPMEVENT19 = 0x333, CSR_MHPMEVENT20 = 0x334, CSR_MHPMEVENT21 = 0x335, CSR_MHPMEVENT22 = 0x336, CSR_MHPMEVENT23 = 0x337, CSR_MHPMEVENT24 = 0x338, CSR_MHPMEVENT25 = 0x339, CSR_MHPMEVENT26 = 0x33A, CSR_MHPMEVENT27 = 0x33B, CSR_MHPMEVENT28 = 0x33C, CSR_MHPMEVENT29 = 0x33D, CSR_MHPMEVENT30 = 0x33E, CSR_MHPMEVENT31 = 0x33F, CSR_TSELECT = 0x7A0, CSR_TDATA1 = 0x7A1, CSR_TDATA2 = 0x7A2, CSR_TDATA3 = 0x7A3, CSR_DCSR = 0x7B0, CSR_DPC = 0x7B1, CSR_DSCRATCH = 0x7B2 }

Functions
template<class XC >
void	handleLockedSnoop (XC *xc, PacketPtr pkt, Addr cacheBlockMask)

template<class XC >
void	handleLockedRead (XC *xc, const RequestPtr &req)

template<class XC >
void	handleLockedSnoopHit (XC *xc)

template<class XC >
bool	handleLockedWrite (XC *xc, const RequestPtr &req, Addr cacheBlockMask)

template<class XC >
void	globalClearExclusive (XC *xc)

Cycles	handleIprRead (ThreadContext , Packet )

Cycles	handleIprWrite (ThreadContext , Packet )

	BitUnion32 (IndexReg) Bitfield< 31 > p

	EndBitUnion (IndexReg) BitUnion32(RandomReg) Bitfield< 30

	EndBitUnion (RandomReg) BitUnion64(EntryLoReg) Bitfield< 63

	EndBitUnion (EntryLoReg) BitUnion64(ContextReg) Bitfield< 63

	EndBitUnion (ContextReg) BitUnion32(PageMaskReg) Bitfield< 28

	EndBitUnion (PageMaskReg) BitUnion32(PageGrainReg) Bitfield< 31

	EndBitUnion (PageGrainReg) BitUnion32(WiredReg) Bitfield< 30

	EndBitUnion (WiredReg) BitUnion32(HWREnaReg) Bitfield< 31

	EndBitUnion (HWREnaReg) BitUnion64(EntryHiReg) Bitfield< 63

	EndBitUnion (EntryHiReg) BitUnion32(StatusReg) SubBitUnion(cu

	EndSubBitUnion (cu) Bitfield< 27 > rp

	SubBitUnion (im, 15, 8) Bitfield< 15 > im7

	EndSubBitUnion (im) Bitfield< 7 > kx

	EndBitUnion (StatusReg) BitUnion32(IntCtlReg) Bitfield< 31

	EndBitUnion (IntCtlReg) BitUnion32(SRSCtlReg) Bitfield< 29

	EndBitUnion (SRSCtlReg) BitUnion32(SRSMapReg) Bitfield< 31

	EndBitUnion (SRSMapReg) BitUnion32(CauseReg) Bitfield< 31 > bd

	SubBitUnion (ip, 15, 8) Bitfield< 15 > ip7

	EndSubBitUnion (ip)

	EndBitUnion (CauseReg) BitUnion32(PRIdReg) Bitfield< 31

	EndBitUnion (PRIdReg) BitUnion32(EBaseReg) Bitfield< 29

	EndBitUnion (EBaseReg) BitUnion32(ConfigReg) Bitfield< 31 > m

	EndBitUnion (ConfigReg) BitUnion32(Config1Reg) Bitfield< 31 > m

	EndBitUnion (Config1Reg) BitUnion32(Config2Reg) Bitfield< 31 > m

	EndBitUnion (Config2Reg) BitUnion32(Config3Reg) Bitfield< 31 > m

	EndBitUnion (Config3Reg) BitUnion64(WatchLoReg) Bitfield< 63

	EndBitUnion (WatchLoReg) BitUnion32(WatchHiReg) Bitfield< 31 > m

	EndBitUnion (WatchHiReg) BitUnion32(PerfCntCtlReg) Bitfield< 31 > m

	EndBitUnion (PerfCntCtlReg) BitUnion32(CacheErrReg) Bitfield< 31 > er

	EndBitUnion (CacheErrReg) BitUnion32(TagLoReg) Bitfield< 31

	BitUnion64 (STATUS) Bitfield< 63 > sd
	These fields are specified in the RISC-V Instruction Set Manual, Volume II, v1.10, accessible at www.riscv.org. More...

	EndBitUnion (STATUS) BitUnion64(INTERRUPT) Bitfield< 11 > mei
	These fields are specified in the RISC-V Instruction Set Manual, Volume II, v1.10 in Figures 3.11 and 3.12, accessible at www.riscv.org. More...

	EndBitUnion (INTERRUPT) const off_t MXL_OFFSET

template<typename T >
bool	isquietnan (T val)

template<>
bool	isquietnan< float > (float val)

template<>
bool	isquietnan< double > (double val)

template<typename T >
bool	issignalingnan (T val)

template<>
bool	issignalingnan< float > (float val)

template<>
bool	issignalingnan< double > (double val)

PCState	buildRetPC (const PCState &curPC, const PCState &callPC)

uint64_t	getArgument (ThreadContext *tc, int &number, uint16_t size, bool fp)

void	copyRegs (ThreadContext src, ThreadContext dest)

std::string	registerName (RegId reg)

void	skipFunction (ThreadContext *tc)

void	advancePC (PCState &pc, const StaticInstPtr &inst)

static bool	inUserMode (ThreadContext *tc)

uint64_t	getExecutingAsid (ThreadContext *tc)

Addr	vtophys (Addr vaddr)

Addr	vtophys (ThreadContext *tc, Addr vaddr)

Variables
static const MachInst	LowerBitMask = (1 << sizeof(MachInst) * 4) - 1

static const MachInst	UpperBitMask = LowerBitMask << sizeof(MachInst) * 4

const ByteOrder	GuestByteOrder = LittleEndianByteOrder

const Addr	PageShift = 12

const Addr	PageBytes = ULL(1) << PageShift

const bool	HasUnalignedMemAcc = true

const bool	CurThreadInfoImplemented = false

const int	CurThreadInfoReg = -1

std::unordered_map< int, std::stack< Addr > >	locked_addrs

const int	WARN_FAILURE = 10000

Bitfield< 30, 0 >	index

	random

	fill

Bitfield< 29, 6 >	pfn

Bitfield< 5, 3 >	c

Bitfield< 2 >	d

Bitfield< 1 >	v

Bitfield< 0 >	g

	pteBase

Bitfield< 22, 4 >	badVPN2

	mask

Bitfield< 12, 11 >	maskx

	aseUp

Bitfield< 29 >	elpa

Bitfield< 28 >	esp

Bitfield< 12, 8 >	aseDn

	wired

	impl

	r

Bitfield< 39, 13 >	vpn2

Bitfield< 12, 11 >	vpn2x

Bitfield< 7, 0 >	asid

Bitfield< 31 >	cu3

Bitfield< 30 >	cu2

Bitfield< 29 >	cu1

Bitfield< 28 >	cu0

Bitfield< 26 >	fr

Bitfield< 25 >	re

Bitfield< 24 >	mx

Bitfield< 23 >	px

Bitfield< 22 >	bev

Bitfield< 21 >	ts

Bitfield< 20 >	sr

Bitfield< 19 >	nmi

Bitfield< 15, 10 >	ipl

Bitfield< 14 >	im6

Bitfield< 13 >	im5

Bitfield< 12 >	im4

Bitfield< 11 >	im3

Bitfield< 10 >	im2

Bitfield< 9 >	im1

Bitfield< 8 >	im0

Bitfield< 6 >	sx

Bitfield< 5 >	ux

Bitfield< 4, 3 >	ksu

Bitfield< 4 >	um

Bitfield< 3 >	r0

Bitfield< 2 >	erl

Bitfield< 1 >	exl

Bitfield< 0 >	ie

	ipti

Bitfield< 28, 26 >	ippci

Bitfield< 9, 5 >	vs

	hss

Bitfield< 21, 18 >	eicss

Bitfield< 15, 12 >	ess

Bitfield< 9, 6 >	pss

Bitfield< 3, 0 >	css

	ssv7

Bitfield< 27, 24 >	ssv6

Bitfield< 23, 20 >	ssv5

Bitfield< 19, 16 >	ssv4

Bitfield< 15, 12 >	ssv3

Bitfield< 11, 8 >	ssv2

Bitfield< 7, 4 >	ssv1

Bitfield< 3, 0 >	ssv0

Bitfield< 30 >	ti

Bitfield< 29, 28 >	ce

Bitfield< 27 >	dc

Bitfield< 26 >	pci

Bitfield< 23 >	iv

Bitfield< 22 >	wp

Bitfield< 15, 10 >	ripl

Bitfield< 14 >	ip6

Bitfield< 13 >	ip5

Bitfield< 12 >	ip4

Bitfield< 11 >	ip3

Bitfield< 10 >	ip2

Bitfield< 9 >	ip1

Bitfield< 8 >	ip0

Bitfield< 6, 2 >	excCode

	coOp

Bitfield< 23, 16 >	coId

Bitfield< 15, 8 >	procId

Bitfield< 7, 0 >	rev

	exceptionBase

Bitfield< 9, 9 >	cpuNum

Bitfield< 30, 28 >	k23

Bitfield< 27, 25 >	ku

Bitfield< 15 >	be

Bitfield< 14, 13 >	at

Bitfield< 12, 10 >	ar

Bitfield< 9, 7 >	mt

Bitfield< 3 >	vi

Bitfield< 2, 0 >	k0

Bitfield< 30, 25 >	mmuSize

Bitfield< 24, 22 >	is

Bitfield< 21, 19 >	il

Bitfield< 18, 16 >	ia

Bitfield< 15, 13 >	ds

Bitfield< 12, 10 >	dl

Bitfield< 9, 7 >	da

Bitfield< 6 >	c2

Bitfield< 5 >	md

Bitfield< 4 >	pc

Bitfield< 3 >	wr

Bitfield< 2 >	ca

Bitfield< 1 >	ep

Bitfield< 0 >	fp

Bitfield< 30, 28 >	tu

Bitfield< 23, 20 >	tl

Bitfield< 19, 16 >	ta

Bitfield< 15, 12 >	su

Bitfield< 11, 8 >	ss

Bitfield< 7, 4 >	sl

Bitfield< 3, 0 >	sa

Bitfield< 10 >	dspp

Bitfield< 7 >	lpa

Bitfield< 6 >	veic

Bitfield< 5 >	vint

Bitfield< 4 >	sp

Bitfield< 1 >	sm

	vaddr

Bitfield< 2 >	i

Bitfield< 0 >	w

Bitfield< 10, 5 >	event

Bitfield< 3 >	u

Bitfield< 2 >	s

Bitfield< 1 >	k

Bitfield< 30 >	ec

Bitfield< 29 >	ed

Bitfield< 28 >	et

Bitfield< 27 >	es

Bitfield< 26 >	ee

Bitfield< 25 >	eb

	pTagLo

Bitfield< 7, 6 >	pState

Bitfield< 5 >	l

Bitfield< 0 >	p

const int	MaxMiscDestRegs = 2

constexpr unsigned	NumVecElemPerVecReg = ::DummyNumVecElemPerVecReg

constexpr size_t	VecRegSizeBytes = ::DummyVecRegSizeBytes

constexpr size_t	VecPredRegSizeBits = ::DummyVecPredRegSizeBits

constexpr bool	VecPredRegHasPackedRepr = ::DummyVecPredRegHasPackedRepr

const int	NumIntArchRegs = 32

const int	NumMicroIntRegs = 1

const int	NumIntRegs = NumIntArchRegs + NumMicroIntRegs

const int	NumFloatRegs = 32

const unsigned	NumVecRegs = 1

const int	NumVecPredRegs = 1

const int	NumCCRegs = 0

const int	ZeroReg = 0

const int	ReturnAddrReg = 1

const int	StackPointerReg = 2

const int	GlobalPointerReg = 3

const int	ThreadPointerReg = 4

const int	FramePointerReg = 8

const int	ReturnValueReg = 10

const std::vector< int >	ReturnValueRegs = {10, 11}

const std::vector< int >	ArgumentRegs = {10, 11, 12, 13, 14, 15, 16, 17}

const int	AMOTempReg = 32

const int	SyscallPseudoReturnReg = 10

const std::vector< int >	SyscallArgumentRegs = {10, 11, 12, 13, 14, 15, 16}

const int	SyscallNumReg = 17

const std::vector< std::string >	IntRegNames

const std::vector< std::string >	FloatRegNames

const int	NumMiscRegs = NUM_MISCREGS

const std::map< int, CSRMetadata >	CSRData

Bitfield< 35, 34 >	sxl

Bitfield< 33, 32 >	uxl

Bitfield< 22 >	tsr

Bitfield< 21 >	tw

Bitfield< 20 >	tvm

Bitfield< 19 >	mxr

Bitfield< 18 >	sum

Bitfield< 17 >	mprv

Bitfield< 16, 15 >	xs

Bitfield< 14, 13 >	fs

Bitfield< 12, 11 >	mpp

Bitfield< 8 >	spp

Bitfield< 7 >	mpie

Bitfield< 5 >	spie

Bitfield< 4 >	upie

Bitfield< 3 >	mie

Bitfield< 1 >	sie

Bitfield< 0 >	uie

Bitfield< 9 >	sei

Bitfield< 8 >	uei

Bitfield< 7 >	mti

Bitfield< 5 >	sti

Bitfield< 4 >	uti

Bitfield< 3 >	msi

Bitfield< 1 >	ssi

Bitfield< 0 >	usi

const off_t	SXL_OFFSET = 34

const off_t	UXL_OFFSET = 32

const off_t	FS_OFFSET = 13

const off_t	FRM_OFFSET = 5

const RegVal	ISA_MXL_MASK = 3ULL << MXL_OFFSET

const RegVal	ISA_EXT_MASK = mask(26)

const RegVal	MISA_MASK = ISA_MXL_MASK \| ISA_EXT_MASK

const RegVal	STATUS_SD_MASK = 1ULL << ((sizeof(uint64_t) * 8) - 1)

const RegVal	STATUS_SXL_MASK = 3ULL << SXL_OFFSET

const RegVal	STATUS_UXL_MASK = 3ULL << UXL_OFFSET

const RegVal	STATUS_TSR_MASK = 1ULL << 22

const RegVal	STATUS_TW_MASK = 1ULL << 21

const RegVal	STATUS_TVM_MASK = 1ULL << 20

const RegVal	STATUS_MXR_MASK = 1ULL << 19

const RegVal	STATUS_SUM_MASK = 1ULL << 18

const RegVal	STATUS_MPRV_MASK = 1ULL << 17

const RegVal	STATUS_XS_MASK = 3ULL << 15

const RegVal	STATUS_FS_MASK = 3ULL << FS_OFFSET

const RegVal	STATUS_MPP_MASK = 3ULL << 11

const RegVal	STATUS_SPP_MASK = 1ULL << 8

const RegVal	STATUS_MPIE_MASK = 1ULL << 7

const RegVal	STATUS_SPIE_MASK = 1ULL << 5

const RegVal	STATUS_UPIE_MASK = 1ULL << 4

const RegVal	STATUS_MIE_MASK = 1ULL << 3

const RegVal	STATUS_SIE_MASK = 1ULL << 1

const RegVal	STATUS_UIE_MASK = 1ULL << 0

const RegVal	MSTATUS_MASK

const RegVal	SSTATUS_MASK

const RegVal	USTATUS_MASK

const RegVal	MEI_MASK = 1ULL << 11

const RegVal	SEI_MASK = 1ULL << 9

const RegVal	UEI_MASK = 1ULL << 8

const RegVal	MTI_MASK = 1ULL << 7

const RegVal	STI_MASK = 1ULL << 5

const RegVal	UTI_MASK = 1ULL << 4

const RegVal	MSI_MASK = 1ULL << 3

const RegVal	SSI_MASK = 1ULL << 1

const RegVal	USI_MASK = 1ULL << 0

const RegVal	MI_MASK

const RegVal	SI_MASK

const RegVal	UI_MASK = UEI_MASK \| UTI_MASK \| USI_MASK

const RegVal	FFLAGS_MASK = (1 << FRM_OFFSET) - 1

const RegVal	FRM_MASK = 0x7

const std::map< int, RegVal >	CSRMasks

Typedef Documentation

◆ ConstVecPredReg

using RiscvISA::ConstVecPredReg = typedef ::DummyConstVecPredReg

Definition at line 82 of file registers.hh.

◆ ConstVecReg

using RiscvISA::ConstVecReg = typedef ::DummyConstVecReg

Definition at line 75 of file registers.hh.

◆ ExtMachInst

typedef uint64_t RiscvISA::ExtMachInst

Definition at line 55 of file types.hh.

◆ MachInst

typedef uint32_t RiscvISA::MachInst

Definition at line 54 of file types.hh.

◆ VecElem

using RiscvISA::VecElem = typedef ::DummyVecElem

Definition at line 73 of file registers.hh.

◆ VecPredReg

using RiscvISA::VecPredReg = typedef ::DummyVecPredReg

Definition at line 81 of file registers.hh.

◆ VecPredRegContainer

using RiscvISA::VecPredRegContainer = typedef ::DummyVecPredRegContainer

Definition at line 83 of file registers.hh.

◆ VecReg

using RiscvISA::VecReg = typedef ::DummyVecReg

Definition at line 74 of file registers.hh.

◆ VecRegContainer

using RiscvISA::VecRegContainer = typedef ::DummyVecRegContainer

Definition at line 76 of file registers.hh.

Enumeration Type Documentation

◆ CSRIndex

enum RiscvISA::CSRIndex

Enumerator
CSR_USTATUS
CSR_UIE
CSR_UTVEC
CSR_USCRATCH
CSR_UEPC
CSR_UCAUSE
CSR_UTVAL
CSR_UIP
CSR_FFLAGS
CSR_FRM
CSR_FCSR
CSR_CYCLE
CSR_TIME
CSR_INSTRET
CSR_HPMCOUNTER03
CSR_HPMCOUNTER04
CSR_HPMCOUNTER05
CSR_HPMCOUNTER06
CSR_HPMCOUNTER07
CSR_HPMCOUNTER08
CSR_HPMCOUNTER09
CSR_HPMCOUNTER10
CSR_HPMCOUNTER11
CSR_HPMCOUNTER12
CSR_HPMCOUNTER13
CSR_HPMCOUNTER14
CSR_HPMCOUNTER15
CSR_HPMCOUNTER16
CSR_HPMCOUNTER17
CSR_HPMCOUNTER18
CSR_HPMCOUNTER19
CSR_HPMCOUNTER20
CSR_HPMCOUNTER21
CSR_HPMCOUNTER22
CSR_HPMCOUNTER23
CSR_HPMCOUNTER24
CSR_HPMCOUNTER25
CSR_HPMCOUNTER26
CSR_HPMCOUNTER27
CSR_HPMCOUNTER28
CSR_HPMCOUNTER29
CSR_HPMCOUNTER30
CSR_HPMCOUNTER31
CSR_SSTATUS
CSR_SEDELEG
CSR_SIDELEG
CSR_SIE
CSR_STVEC
CSR_SCOUNTEREN
CSR_SSCRATCH
CSR_SEPC
CSR_SCAUSE
CSR_STVAL
CSR_SIP
CSR_SATP
CSR_MVENDORID
CSR_MARCHID
CSR_MIMPID
CSR_MHARTID
CSR_MSTATUS
CSR_MISA
CSR_MEDELEG
CSR_MIDELEG
CSR_MIE
CSR_MTVEC
CSR_MCOUNTEREN
CSR_MSCRATCH
CSR_MEPC
CSR_MCAUSE
CSR_MTVAL
CSR_MIP
CSR_PMPCFG0
CSR_PMPCFG2
CSR_PMPADDR00
CSR_PMPADDR01
CSR_PMPADDR02
CSR_PMPADDR03
CSR_PMPADDR04
CSR_PMPADDR05
CSR_PMPADDR06
CSR_PMPADDR07
CSR_PMPADDR08
CSR_PMPADDR09
CSR_PMPADDR10
CSR_PMPADDR11
CSR_PMPADDR12
CSR_PMPADDR13
CSR_PMPADDR14
CSR_PMPADDR15
CSR_MCYCLE
CSR_MINSTRET
CSR_MHPMCOUNTER03
CSR_MHPMCOUNTER04
CSR_MHPMCOUNTER05
CSR_MHPMCOUNTER06
CSR_MHPMCOUNTER07
CSR_MHPMCOUNTER08
CSR_MHPMCOUNTER09
CSR_MHPMCOUNTER10
CSR_MHPMCOUNTER11
CSR_MHPMCOUNTER12
CSR_MHPMCOUNTER13
CSR_MHPMCOUNTER14
CSR_MHPMCOUNTER15
CSR_MHPMCOUNTER16
CSR_MHPMCOUNTER17
CSR_MHPMCOUNTER18
CSR_MHPMCOUNTER19
CSR_MHPMCOUNTER20
CSR_MHPMCOUNTER21
CSR_MHPMCOUNTER22
CSR_MHPMCOUNTER23
CSR_MHPMCOUNTER24
CSR_MHPMCOUNTER25
CSR_MHPMCOUNTER26
CSR_MHPMCOUNTER27
CSR_MHPMCOUNTER28
CSR_MHPMCOUNTER29
CSR_MHPMCOUNTER30
CSR_MHPMCOUNTER31
CSR_MHPMEVENT03
CSR_MHPMEVENT04
CSR_MHPMEVENT05
CSR_MHPMEVENT06
CSR_MHPMEVENT07
CSR_MHPMEVENT08
CSR_MHPMEVENT09
CSR_MHPMEVENT10
CSR_MHPMEVENT11
CSR_MHPMEVENT12
CSR_MHPMEVENT13
CSR_MHPMEVENT14
CSR_MHPMEVENT15
CSR_MHPMEVENT16
CSR_MHPMEVENT17
CSR_MHPMEVENT18
CSR_MHPMEVENT19
CSR_MHPMEVENT20
CSR_MHPMEVENT21
CSR_MHPMEVENT22
CSR_MHPMEVENT23
CSR_MHPMEVENT24
CSR_MHPMEVENT25
CSR_MHPMEVENT26
CSR_MHPMEVENT27
CSR_MHPMEVENT28
CSR_MHPMEVENT29
CSR_MHPMEVENT30
CSR_MHPMEVENT31
CSR_TSELECT
CSR_TDATA1
CSR_TDATA2
CSR_TDATA3
CSR_DCSR
CSR_DPC
CSR_DSCRATCH

Definition at line 266 of file registers.hh.

◆ ExceptionCode

enum RiscvISA::ExceptionCode : uint64_t

Enumerator
INST_ADDR_MISALIGNED
INST_ACCESS
INST_ILLEGAL
BREAKPOINT
LOAD_ADDR_MISALIGNED
LOAD_ACCESS
STORE_ADDR_MISALIGNED
AMO_ADDR_MISALIGNED
STORE_ACCESS
AMO_ACCESS
ECALL_USER
ECALL_SUPER
ECALL_MACHINE
INST_PAGE
LOAD_PAGE
STORE_PAGE
AMO_PAGE
INT_SOFTWARE_USER
INT_SOFTWARE_SUPER
INT_SOFTWARE_MACHINE
INT_TIMER_USER
INT_TIMER_SUPER
INT_TIMER_MACHINE
INT_EXT_USER
INT_EXT_SUPER
INT_EXT_MACHINE
NumInterruptTypes

Definition at line 64 of file faults.hh.

◆ FloatException

enum RiscvISA::FloatException : uint64_t

Enumerator
FloatInexact
FloatUnderflow
FloatOverflow
FloatDivZero
FloatInvalid

Definition at line 47 of file faults.hh.

◆ MiscRegIndex

enum RiscvISA::MiscRegIndex

Enumerator
MISCREG_PRV
MISCREG_ISA
MISCREG_VENDORID
MISCREG_ARCHID
MISCREG_IMPID
MISCREG_HARTID
MISCREG_STATUS
MISCREG_IP
MISCREG_IE
MISCREG_CYCLE
MISCREG_TIME
MISCREG_INSTRET
MISCREG_HPMCOUNTER03
MISCREG_HPMCOUNTER04
MISCREG_HPMCOUNTER05
MISCREG_HPMCOUNTER06
MISCREG_HPMCOUNTER07
MISCREG_HPMCOUNTER08
MISCREG_HPMCOUNTER09
MISCREG_HPMCOUNTER10
MISCREG_HPMCOUNTER11
MISCREG_HPMCOUNTER12
MISCREG_HPMCOUNTER13
MISCREG_HPMCOUNTER14
MISCREG_HPMCOUNTER15
MISCREG_HPMCOUNTER16
MISCREG_HPMCOUNTER17
MISCREG_HPMCOUNTER18
MISCREG_HPMCOUNTER19
MISCREG_HPMCOUNTER20
MISCREG_HPMCOUNTER21
MISCREG_HPMCOUNTER22
MISCREG_HPMCOUNTER23
MISCREG_HPMCOUNTER24
MISCREG_HPMCOUNTER25
MISCREG_HPMCOUNTER26
MISCREG_HPMCOUNTER27
MISCREG_HPMCOUNTER28
MISCREG_HPMCOUNTER29
MISCREG_HPMCOUNTER30
MISCREG_HPMCOUNTER31
MISCREG_HPMEVENT03
MISCREG_HPMEVENT04
MISCREG_HPMEVENT05
MISCREG_HPMEVENT06
MISCREG_HPMEVENT07
MISCREG_HPMEVENT08
MISCREG_HPMEVENT09
MISCREG_HPMEVENT10
MISCREG_HPMEVENT11
MISCREG_HPMEVENT12
MISCREG_HPMEVENT13
MISCREG_HPMEVENT14
MISCREG_HPMEVENT15
MISCREG_HPMEVENT16
MISCREG_HPMEVENT17
MISCREG_HPMEVENT18
MISCREG_HPMEVENT19
MISCREG_HPMEVENT20
MISCREG_HPMEVENT21
MISCREG_HPMEVENT22
MISCREG_HPMEVENT23
MISCREG_HPMEVENT24
MISCREG_HPMEVENT25
MISCREG_HPMEVENT26
MISCREG_HPMEVENT27
MISCREG_HPMEVENT28
MISCREG_HPMEVENT29
MISCREG_HPMEVENT30
MISCREG_HPMEVENT31
MISCREG_TSELECT
MISCREG_TDATA1
MISCREG_TDATA2
MISCREG_TDATA3
MISCREG_DCSR
MISCREG_DPC
MISCREG_DSCRATCH
MISCREG_MEDELEG
MISCREG_MIDELEG
MISCREG_MTVEC
MISCREG_MCOUNTEREN
MISCREG_MSCRATCH
MISCREG_MEPC
MISCREG_MCAUSE
MISCREG_MTVAL
MISCREG_PMPCFG0
MISCREG_PMPCFG2
MISCREG_PMPADDR00
MISCREG_PMPADDR01
MISCREG_PMPADDR02
MISCREG_PMPADDR03
MISCREG_PMPADDR04
MISCREG_PMPADDR05
MISCREG_PMPADDR06
MISCREG_PMPADDR07
MISCREG_PMPADDR08
MISCREG_PMPADDR09
MISCREG_PMPADDR10
MISCREG_PMPADDR11
MISCREG_PMPADDR12
MISCREG_PMPADDR13
MISCREG_PMPADDR14
MISCREG_PMPADDR15
MISCREG_SEDELEG
MISCREG_SIDELEG
MISCREG_STVEC
MISCREG_SCOUNTEREN
MISCREG_SSCRATCH
MISCREG_SEPC
MISCREG_SCAUSE
MISCREG_STVAL
MISCREG_SATP
MISCREG_UTVEC
MISCREG_USCRATCH
MISCREG_UEPC
MISCREG_UCAUSE
MISCREG_UTVAL
MISCREG_FFLAGS
MISCREG_FRM
NUM_MISCREGS

Definition at line 136 of file registers.hh.

◆ PrivilegeMode

enum RiscvISA::PrivilegeMode

Enumerator
PRV_U
PRV_S
PRV_M

Definition at line 60 of file isa.hh.

Function Documentation

◆ advancePC()

void RiscvISA::advancePC	(	PCState &	pc,
		const StaticInstPtr &	inst
	)

inline

Definition at line 167 of file utility.hh.

References StaticInst::advancePC().

Referenced by RiscvISA::RiscvFault::invoke().

◆ BitUnion32()

RiscvISA::BitUnion32 ( IndexReg )

◆ BitUnion64()

RiscvISA::BitUnion64 ( STATUS )

These fields are specified in the RISC-V Instruction Set Manual, Volume II, v1.10, accessible at www.riscv.org.

in Figure 3.7. The main register that uses these fields is the MSTATUS register, which is shadowed by two others accessible at lower privilege levels (SSTATUS and USTATUS) that can't see the fields for higher privileges.

◆ buildRetPC()

PCState RiscvISA::buildRetPC	(	const PCState &	curPC,
		const PCState &	callPC
	)

inline

Definition at line 106 of file utility.hh.

References GenericISA::SimplePCState< MachInst >::advance(), GenericISA::SimplePCState< MachInst >::npc(), and GenericISA::SimplePCState< MachInst >::pc().

◆ copyRegs()

void RiscvISA::copyRegs	(	ThreadContext *	src,
		ThreadContext *	dest
	)

inline

Definition at line 121 of file utility.hh.

References i, NumIntRegs, ThreadContext::pcState(), ThreadContext::readIntReg(), and ThreadContext::setIntReg().

Referenced by RiscvLinux64::archClone(), and RiscvLinux32::archClone().

◆ EndBitUnion() [1/26]

RiscvISA::EndBitUnion ( IndexReg )

◆ EndBitUnion() [2/26]

RiscvISA::EndBitUnion ( RandomReg )

◆ EndBitUnion() [3/26]

RiscvISA::EndBitUnion ( EntryLoReg )

◆ EndBitUnion() [4/26]

RiscvISA::EndBitUnion ( ContextReg )

◆ EndBitUnion() [5/26]

RiscvISA::EndBitUnion ( PageMaskReg )

◆ EndBitUnion() [6/26]

RiscvISA::EndBitUnion ( PageGrainReg )

◆ EndBitUnion() [7/26]

RiscvISA::EndBitUnion ( WiredReg )

◆ EndBitUnion() [8/26]

RiscvISA::EndBitUnion ( HWREnaReg )

◆ EndBitUnion() [9/26]

RiscvISA::EndBitUnion ( EntryHiReg )

◆ EndBitUnion() [10/26]

RiscvISA::EndBitUnion ( StatusReg )

◆ EndBitUnion() [11/26]

RiscvISA::EndBitUnion ( IntCtlReg )

◆ EndBitUnion() [12/26]

RiscvISA::EndBitUnion ( SRSCtlReg )

◆ EndBitUnion() [13/26]

RiscvISA::EndBitUnion ( SRSMapReg )

◆ EndBitUnion() [14/26]

RiscvISA::EndBitUnion ( CauseReg )

◆ EndBitUnion() [15/26]

RiscvISA::EndBitUnion ( PRIdReg )

◆ EndBitUnion() [16/26]

RiscvISA::EndBitUnion ( EBaseReg )

◆ EndBitUnion() [17/26]

RiscvISA::EndBitUnion ( ConfigReg )

◆ EndBitUnion() [18/26]

RiscvISA::EndBitUnion ( Config1Reg )

◆ EndBitUnion() [19/26]

RiscvISA::EndBitUnion ( Config2Reg )

◆ EndBitUnion() [20/26]

RiscvISA::EndBitUnion ( Config3Reg )

◆ EndBitUnion() [21/26]

RiscvISA::EndBitUnion ( WatchLoReg )

◆ EndBitUnion() [22/26]

RiscvISA::EndBitUnion ( WatchHiReg )

◆ EndBitUnion() [23/26]

RiscvISA::EndBitUnion ( PerfCntCtlReg )

◆ EndBitUnion() [24/26]

RiscvISA::EndBitUnion ( CacheErrReg )

◆ EndBitUnion() [25/26]

RiscvISA::EndBitUnion ( STATUS )

These fields are specified in the RISC-V Instruction Set Manual, Volume II, v1.10 in Figures 3.11 and 3.12, accessible at www.riscv.org.

Both the MIP and MIE registers have the same fields, so accesses to either should use this bit union.

◆ EndBitUnion() [26/26]

RiscvISA::EndBitUnion ( INTERRUPT ) const

◆ EndSubBitUnion() [1/3]

RiscvISA::EndSubBitUnion ( cu )

◆ EndSubBitUnion() [2/3]

RiscvISA::EndSubBitUnion ( im )

◆ EndSubBitUnion() [3/3]

RiscvISA::EndSubBitUnion ( ip )

◆ getArgument()

uint64_t RiscvISA::getArgument	(	ThreadContext *	tc,
		int &	number,
		uint16_t	size,
		bool	fp
	)

inline

Definition at line 115 of file utility.hh.

◆ getExecutingAsid()

uint64_t RiscvISA::getExecutingAsid ( ThreadContext * tc )

inline

Definition at line 179 of file utility.hh.

◆ globalClearExclusive()

template<class XC >

void RiscvISA::globalClearExclusive ( XC * xc )

inline

Definition at line 138 of file locked_mem.hh.

◆ handleIprRead()

Cycles RiscvISA::handleIprRead	(	ThreadContext *	,
		Packet *
	)

inline

Definition at line 48 of file mmapped_ipr.hh.

◆ handleIprWrite()

Cycles RiscvISA::handleIprWrite	(	ThreadContext *	,
		Packet *
	)

inline

Definition at line 49 of file mmapped_ipr.hh.

◆ handleLockedRead()

template<class XC >

void RiscvISA::handleLockedRead	(	XC *	xc,
		const RequestPtr &	req
	)

inline

Definition at line 88 of file locked_mem.hh.

References DPRINTF.

◆ handleLockedSnoop()

template<class XC >

void RiscvISA::handleLockedSnoop	(	XC *	xc,
		PacketPtr	pkt,
		Addr	cacheBlockMask
	)

inline

Definition at line 74 of file locked_mem.hh.

References DPRINTF, and Packet::getAddr().

◆ handleLockedSnoopHit()

template<class XC >

void RiscvISA::handleLockedSnoopHit ( XC * xc )

inline

Definition at line 98 of file locked_mem.hh.

◆ handleLockedWrite()

template<class XC >

bool RiscvISA::handleLockedWrite	(	XC *	xc,
		const RequestPtr &	req,
		Addr	cacheBlockMask
	)

inline

Definition at line 102 of file locked_mem.hh.

References curTick(), DPRINTF, and warn.

◆ inUserMode()

static bool RiscvISA::inUserMode ( ThreadContext * tc )

inlinestatic

Definition at line 173 of file utility.hh.

◆ isquietnan()

template<typename T >

bool RiscvISA::isquietnan ( T val )

inline

Definition at line 66 of file utility.hh.

◆ isquietnan< double >()

template<>

bool RiscvISA::isquietnan< double > ( double val )

inline

Definition at line 79 of file utility.hh.

References X86ISA::val.

◆ isquietnan< float >()

template<>

bool RiscvISA::isquietnan< float > ( float val )

inline

Definition at line 72 of file utility.hh.

References X86ISA::val.

◆ issignalingnan()

template<typename T >

bool RiscvISA::issignalingnan ( T val )

inline

Definition at line 86 of file utility.hh.

◆ issignalingnan< double >()

template<>

bool RiscvISA::issignalingnan< double > ( double val )

inline

Definition at line 99 of file utility.hh.

References X86ISA::val.

◆ issignalingnan< float >()

template<>

bool RiscvISA::issignalingnan< float > ( float val )

inline

Definition at line 92 of file utility.hh.

References X86ISA::val.

◆ registerName()

std::string RiscvISA::registerName ( RegId reg )

inline

Definition at line 132 of file utility.hh.

References FloatRegNames, RegId::index(), IntRegNames, RegId::isIntReg(), NumFloatRegs, and NumIntArchRegs.

◆ skipFunction()

void RiscvISA::skipFunction ( ThreadContext * tc )

inline

Definition at line 161 of file utility.hh.

References panic.

◆ SubBitUnion() [1/2]

RiscvISA::SubBitUnion	(	im	,
		15	,
		8
	)

◆ SubBitUnion() [2/2]

RiscvISA::SubBitUnion	(	ip	,
		15	,
		8
	)

◆ vtophys() [1/2]

Addr RiscvISA::vtophys ( Addr vaddr )

inline

Definition at line 49 of file vtophys.hh.

References fatal, and vaddr.

Referenced by vtophys().

◆ vtophys() [2/2]

Addr RiscvISA::vtophys	(	ThreadContext *	tc,
		Addr	vaddr
	)

inline

Definition at line 56 of file vtophys.hh.

References fatal, and vtophys().

Variable Documentation

◆ AMOTempReg

const int RiscvISA::AMOTempReg = 32

Definition at line 109 of file registers.hh.

◆ ar

Bitfield<12, 10> RiscvISA::ar

Definition at line 224 of file pra_constants.hh.

◆ ArgumentRegs

const std::vector<int> RiscvISA::ArgumentRegs = {10, 11, 12, 13, 14, 15, 16, 17}

Definition at line 108 of file registers.hh.

◆ aseDn

Bitfield<12, 8> RiscvISA::aseDn

Definition at line 82 of file pra_constants.hh.

◆ aseUp

RiscvISA::aseUp

Definition at line 78 of file pra_constants.hh.

◆ asid

Bitfield< 23, 16 > RiscvISA::asid

Definition at line 101 of file pra_constants.hh.

◆ at

Bitfield<14, 13> RiscvISA::at

Definition at line 223 of file pra_constants.hh.

◆ badVPN2

Bitfield<22, 4> RiscvISA::badVPN2

Definition at line 66 of file pra_constants.hh.

◆ be

Bitfield<15> RiscvISA::be

Definition at line 222 of file pra_constants.hh.

◆ bev

Bitfield<22> RiscvISA::bev

Definition at line 116 of file pra_constants.hh.

◆ c

Bitfield<5, 3> RiscvISA::c

Definition at line 58 of file pra_constants.hh.

Referenced by RiscvISA::PCState::compressed(), and RiscvISA::Interrupts::getInterrupt().

◆ c2

Bitfield<6> RiscvISA::c2

Definition at line 240 of file pra_constants.hh.

◆ ca

Bitfield<2> RiscvISA::ca

Definition at line 244 of file pra_constants.hh.

◆ ce

Bitfield<29, 28> RiscvISA::ce

Definition at line 179 of file pra_constants.hh.

◆ coId

Bitfield<23, 16> RiscvISA::coId

Definition at line 204 of file pra_constants.hh.

◆ coOp

RiscvISA::coOp

Definition at line 203 of file pra_constants.hh.

◆ cpuNum

Bitfield<9, 9> RiscvISA::cpuNum

Definition at line 214 of file pra_constants.hh.

◆ CSRData

const std::map<int, CSRMetadata> RiscvISA::CSRData

Definition at line 438 of file registers.hh.

Referenced by RiscvISA::CSROp::generateDisassembly(), and RiscvISA::ISA::setMiscReg().

◆ CSRMasks

const std::map<int, RegVal> RiscvISA::CSRMasks

Initial value:

= {
    {CSR_USTATUS, USTATUS_MASK},
    {CSR_UIE, UI_MASK},
    {CSR_UIP, UI_MASK},
    {CSR_FFLAGS, FFLAGS_MASK},
    {CSR_FRM, FRM_MASK},
    {CSR_FCSR, FFLAGS_MASK | (FRM_MASK << FRM_OFFSET)},
    {CSR_SSTATUS, SSTATUS_MASK},
    {CSR_SIE, SI_MASK},
    {CSR_SIP, SI_MASK},
    {CSR_MSTATUS, MSTATUS_MASK},
    {CSR_MISA, MISA_MASK},
    {CSR_MIE, MI_MASK},
    {CSR_MIP, MI_MASK}
}

Definition at line 718 of file registers.hh.

◆ css

Bitfield<3, 0> RiscvISA::css

Definition at line 162 of file pra_constants.hh.

◆ cu0

Bitfield<28> RiscvISA::cu0

Definition at line 109 of file pra_constants.hh.

◆ cu1

Bitfield<29> RiscvISA::cu1

Definition at line 108 of file pra_constants.hh.

◆ cu2

Bitfield<30> RiscvISA::cu2

Definition at line 107 of file pra_constants.hh.

◆ cu3

Bitfield<31> RiscvISA::cu3

Definition at line 105 of file pra_constants.hh.

◆ CurThreadInfoImplemented

const bool RiscvISA::CurThreadInfoImplemented = false

Definition at line 64 of file isa_traits.hh.

◆ CurThreadInfoReg

const int RiscvISA::CurThreadInfoReg = -1

Definition at line 65 of file isa_traits.hh.

◆ d

Bitfield<2> RiscvISA::d

Definition at line 59 of file pra_constants.hh.

◆ da

Bitfield<9, 7> RiscvISA::da

Definition at line 239 of file pra_constants.hh.

◆ dc

Bitfield<27> RiscvISA::dc

Definition at line 180 of file pra_constants.hh.

◆ dl

Bitfield<12, 10> RiscvISA::dl

Definition at line 238 of file pra_constants.hh.

◆ ds

Bitfield<15, 13> RiscvISA::ds

Definition at line 237 of file pra_constants.hh.

◆ dspp

Bitfield<10> RiscvISA::dspp

Definition at line 264 of file pra_constants.hh.

◆ eb

Bitfield<25> RiscvISA::eb

Definition at line 314 of file pra_constants.hh.

◆ ec

Bitfield<30> RiscvISA::ec

Definition at line 309 of file pra_constants.hh.

◆ ed

Bitfield<29> RiscvISA::ed

Definition at line 310 of file pra_constants.hh.

◆ ee

Bitfield<26> RiscvISA::ee

Definition at line 313 of file pra_constants.hh.

◆ eicss

Bitfield<21, 18> RiscvISA::eicss

Definition at line 156 of file pra_constants.hh.

◆ elpa

Bitfield<29> RiscvISA::elpa

Definition at line 79 of file pra_constants.hh.

◆ ep

Bitfield<1> RiscvISA::ep

Definition at line 245 of file pra_constants.hh.

◆ erl

Bitfield<2> RiscvISA::erl

Definition at line 139 of file pra_constants.hh.

◆ es

Bitfield<27> RiscvISA::es

Definition at line 312 of file pra_constants.hh.

◆ esp

Bitfield<28> RiscvISA::esp

Definition at line 80 of file pra_constants.hh.

◆ ess

Bitfield<15, 12> RiscvISA::ess

Definition at line 158 of file pra_constants.hh.

◆ et

Bitfield<28> RiscvISA::et

Definition at line 311 of file pra_constants.hh.

◆ event

Bitfield<10, 5> RiscvISA::event

Definition at line 299 of file pra_constants.hh.

◆ excCode

Bitfield<6, 2> RiscvISA::excCode

Definition at line 198 of file pra_constants.hh.

◆ exceptionBase

RiscvISA::exceptionBase

Definition at line 212 of file pra_constants.hh.

◆ exl

Bitfield< 0 > RiscvISA::exl

Definition at line 140 of file pra_constants.hh.

◆ FFLAGS_MASK

const RegVal RiscvISA::FFLAGS_MASK = (1 << FRM_OFFSET) - 1

Definition at line 715 of file registers.hh.

◆ fill

Bitfield< 61, 40 > RiscvISA::fill

Definition at line 56 of file pra_constants.hh.

◆ FloatRegNames

const std::vector<std::string> RiscvISA::FloatRegNames

Initial value:

= {
    "ft0", "ft1", "ft2", "ft3",
    "ft4", "ft5", "ft6", "ft7",
    "fs0", "fs1", "fa0", "fa1",
    "fa2", "fa3", "fa4", "fa5",
    "fa6", "fa7", "fs2", "fs3",
    "fs4", "fs5", "fs6", "fs7",
    "fs8", "fs9", "fs10", "fs11",
    "ft8", "ft9", "ft10", "ft11"
}

Definition at line 125 of file registers.hh.

Referenced by registerName().

◆ fp

Bitfield<0> RiscvISA::fp

Definition at line 246 of file pra_constants.hh.

◆ fr

Bitfield<26> RiscvISA::fr

Definition at line 112 of file pra_constants.hh.

◆ FramePointerReg

const int RiscvISA::FramePointerReg = 8

Definition at line 105 of file registers.hh.

◆ FRM_MASK

const RegVal RiscvISA::FRM_MASK = 0x7

Definition at line 716 of file registers.hh.

◆ FRM_OFFSET

const off_t RiscvISA::FRM_OFFSET = 5

Definition at line 653 of file registers.hh.

◆ fs

Bitfield<14, 13> RiscvISA::fs

Definition at line 620 of file registers.hh.

◆ FS_OFFSET

const off_t RiscvISA::FS_OFFSET = 13

Definition at line 652 of file registers.hh.

Referenced by RiscvISA::ISA::clear().

◆ g

Bitfield< 30 > RiscvISA::g

Definition at line 61 of file pra_constants.hh.

◆ GlobalPointerReg

const int RiscvISA::GlobalPointerReg = 3

Definition at line 103 of file registers.hh.

◆ GuestByteOrder

const ByteOrder RiscvISA::GuestByteOrder = LittleEndianByteOrder

Definition at line 56 of file isa_traits.hh.

◆ HasUnalignedMemAcc

const bool RiscvISA::HasUnalignedMemAcc = true

Definition at line 62 of file isa_traits.hh.

◆ hss

RiscvISA::hss

Definition at line 154 of file pra_constants.hh.

◆ i

Bitfield< 2 > RiscvISA::i

Definition at line 278 of file pra_constants.hh.

Referenced by copyRegs(), RiscvISA::RemoteGDB::RiscvGdbRegCache::getRegs(), RiscvISA::TLB::insertAt(), RiscvISA::TLB::lookup(), RiscvISA::TLB::probeEntry(), RiscvISA::TLB::serialize(), RiscvISA::RemoteGDB::RiscvGdbRegCache::setRegs(), and RiscvISA::TLB::unserialize().

◆ ia

Bitfield<18, 16> RiscvISA::ia

Definition at line 236 of file pra_constants.hh.

◆ ie

Bitfield< 4 > RiscvISA::ie

Definition at line 141 of file pra_constants.hh.

◆ il

Bitfield<21, 19> RiscvISA::il

Definition at line 235 of file pra_constants.hh.

◆ im0

Bitfield<8> RiscvISA::im0

Definition at line 131 of file pra_constants.hh.

◆ im1

Bitfield<9> RiscvISA::im1

Definition at line 130 of file pra_constants.hh.

◆ im2

Bitfield<10> RiscvISA::im2

Definition at line 129 of file pra_constants.hh.

◆ im3

Bitfield<11> RiscvISA::im3

Definition at line 128 of file pra_constants.hh.

◆ im4

Bitfield<12> RiscvISA::im4

Definition at line 127 of file pra_constants.hh.

◆ im5

Bitfield<13> RiscvISA::im5

Definition at line 126 of file pra_constants.hh.

◆ im6

Bitfield<14> RiscvISA::im6

Definition at line 125 of file pra_constants.hh.

◆ impl

Bitfield< 4, 3 > RiscvISA::impl

Definition at line 92 of file pra_constants.hh.

◆ index

Bitfield< 22, 0 > RiscvISA::index

Definition at line 46 of file pra_constants.hh.

◆ IntRegNames

const std::vector<std::string> RiscvISA::IntRegNames

Initial value:

= {
    "zero", "ra", "sp", "gp",
    "tp", "t0", "t1", "t2",
    "s0", "s1", "a0", "a1",
    "a2", "a3", "a4", "a5",
    "a6", "a7", "s2", "s3",
    "s4", "s5", "s6", "s7",
    "s8", "s9", "s10", "s11",
    "t3", "t4", "t5", "t6"
}

Definition at line 115 of file registers.hh.

Referenced by registerName().

◆ ip0

Bitfield<8> RiscvISA::ip0

Definition at line 195 of file pra_constants.hh.

◆ ip1

Bitfield<9> RiscvISA::ip1

Definition at line 194 of file pra_constants.hh.

◆ ip2

Bitfield<10> RiscvISA::ip2

Definition at line 193 of file pra_constants.hh.

◆ ip3

Bitfield<11> RiscvISA::ip3

Definition at line 192 of file pra_constants.hh.

◆ ip4

Bitfield<12> RiscvISA::ip4

Definition at line 191 of file pra_constants.hh.

◆ ip5

Bitfield<13> RiscvISA::ip5

Definition at line 190 of file pra_constants.hh.

◆ ip6

Bitfield<14> RiscvISA::ip6

Definition at line 189 of file pra_constants.hh.

◆ ipl

Bitfield<15, 10> RiscvISA::ipl

Definition at line 122 of file pra_constants.hh.

◆ ippci

Bitfield<28, 26> RiscvISA::ippci

Definition at line 146 of file pra_constants.hh.

◆ ipti

RiscvISA::ipti

Definition at line 145 of file pra_constants.hh.

◆ is

Bitfield<24, 22> RiscvISA::is

Definition at line 234 of file pra_constants.hh.

◆ ISA_EXT_MASK

const RegVal RiscvISA::ISA_EXT_MASK = mask(26)

Definition at line 656 of file registers.hh.

◆ ISA_MXL_MASK

const RegVal RiscvISA::ISA_MXL_MASK = 3ULL << MXL_OFFSET

Definition at line 655 of file registers.hh.

◆ iv

Bitfield<23> RiscvISA::iv

Definition at line 183 of file pra_constants.hh.

◆ k

Bitfield<1> RiscvISA::k

Definition at line 303 of file pra_constants.hh.

◆ k0

Bitfield<2, 0> RiscvISA::k0

Definition at line 228 of file pra_constants.hh.

◆ k23

Bitfield<30, 28> RiscvISA::k23

Definition at line 219 of file pra_constants.hh.

◆ ksu

Bitfield<4, 3> RiscvISA::ksu

Definition at line 136 of file pra_constants.hh.

◆ ku

Bitfield<27, 25> RiscvISA::ku

Definition at line 220 of file pra_constants.hh.

◆ l

Bitfield<5> RiscvISA::l

Definition at line 322 of file pra_constants.hh.

◆ locked_addrs

std::unordered_map< int, std::stack< Addr > > RiscvISA::locked_addrs

Definition at line 9 of file locked_mem.cc.

Referenced by PhysicalMemory::serialize().

◆ LowerBitMask

const MachInst RiscvISA::LowerBitMask = (1 << sizeof(MachInst) * 4) - 1

static

Definition at line 40 of file decoder.cc.

Referenced by RiscvISA::Decoder::moreBytes().

◆ lpa

Bitfield<7> RiscvISA::lpa

Definition at line 266 of file pra_constants.hh.

◆ mask

Bitfield< 11, 3 > RiscvISA::mask

Definition at line 72 of file pra_constants.hh.

Referenced by RiscvISA::Interrupts::getInterrupt(), and RiscvISA::Interrupts::globalMask().

◆ maskx

Bitfield<12, 11> RiscvISA::maskx

Definition at line 73 of file pra_constants.hh.

◆ MaxMiscDestRegs

const int RiscvISA::MaxMiscDestRegs = 2

Definition at line 70 of file registers.hh.

◆ md

Bitfield<5> RiscvISA::md

Definition at line 241 of file pra_constants.hh.

◆ MEI_MASK

const RegVal RiscvISA::MEI_MASK = 1ULL << 11

Definition at line 699 of file registers.hh.

◆ MI_MASK

const RegVal RiscvISA::MI_MASK

Initial value:

= MEI_MASK | SEI_MASK | UEI_MASK |
                       MTI_MASK | STI_MASK | UTI_MASK |
                       MSI_MASK | SSI_MASK | USI_MASK

Definition at line 708 of file registers.hh.

◆ mie

Bitfield<3> RiscvISA::mie

Definition at line 626 of file registers.hh.

◆ MISA_MASK

const RegVal RiscvISA::MISA_MASK = ISA_MXL_MASK | ISA_EXT_MASK

Definition at line 657 of file registers.hh.

◆ mmuSize

Bitfield<30, 25> RiscvISA::mmuSize

Definition at line 233 of file pra_constants.hh.

◆ mpie

Bitfield<7> RiscvISA::mpie

Definition at line 623 of file registers.hh.

◆ mpp

Bitfield<12, 11> RiscvISA::mpp

Definition at line 621 of file registers.hh.

◆ mprv

Bitfield<17> RiscvISA::mprv

Definition at line 618 of file registers.hh.

◆ msi

Bitfield<3> RiscvISA::msi

Definition at line 644 of file registers.hh.

◆ MSI_MASK

const RegVal RiscvISA::MSI_MASK = 1ULL << 3

Definition at line 705 of file registers.hh.

◆ MSTATUS_MASK

const RegVal RiscvISA::MSTATUS_MASK

Initial value:

= STATUS_SD_MASK | STATUS_SXL_MASK |
                            STATUS_UXL_MASK | STATUS_TSR_MASK |
                            STATUS_TW_MASK | STATUS_TVM_MASK |
                            STATUS_MXR_MASK | STATUS_SUM_MASK |
                            STATUS_MPRV_MASK | STATUS_XS_MASK |
                            STATUS_FS_MASK | STATUS_MPP_MASK |
                            STATUS_SPP_MASK | STATUS_MPIE_MASK |
                            STATUS_SPIE_MASK | STATUS_UPIE_MASK |
                            STATUS_MIE_MASK | STATUS_SIE_MASK |
                            STATUS_UIE_MASK

Definition at line 678 of file registers.hh.

◆ mt

Bitfield< 2 > RiscvISA::mt

Definition at line 225 of file pra_constants.hh.

◆ mti

Bitfield<7> RiscvISA::mti

Definition at line 641 of file registers.hh.

◆ MTI_MASK

const RegVal RiscvISA::MTI_MASK = 1ULL << 7

Definition at line 702 of file registers.hh.

◆ mx

Bitfield<24> RiscvISA::mx

Definition at line 114 of file pra_constants.hh.

◆ mxr

Bitfield<19> RiscvISA::mxr

Definition at line 616 of file registers.hh.

◆ nmi

Bitfield<19> RiscvISA::nmi

Definition at line 119 of file pra_constants.hh.

◆ NumCCRegs

const int RiscvISA::NumCCRegs = 0

Definition at line 97 of file registers.hh.

◆ NumFloatRegs

const int RiscvISA::NumFloatRegs = 32

Definition at line 90 of file registers.hh.

Referenced by registerName().

◆ NumIntArchRegs

const int RiscvISA::NumIntArchRegs = 32

Definition at line 87 of file registers.hh.

Referenced by RiscvISA::RemoteGDB::RiscvGdbRegCache::getRegs(), registerName(), and RiscvISA::RemoteGDB::RiscvGdbRegCache::setRegs().

◆ NumIntRegs

const int RiscvISA::NumIntRegs = NumIntArchRegs + NumMicroIntRegs

Definition at line 89 of file registers.hh.

Referenced by copyRegs().

◆ NumMicroIntRegs

const int RiscvISA::NumMicroIntRegs = 1

Definition at line 88 of file registers.hh.

◆ NumMiscRegs

const int RiscvISA::NumMiscRegs = NUM_MISCREGS

Definition at line 264 of file registers.hh.

Referenced by RiscvISA::ISA::ISA(), RiscvISA::ISA::readMiscRegNoEffect(), and RiscvISA::ISA::setMiscRegNoEffect().

◆ NumVecElemPerVecReg

constexpr unsigned RiscvISA::NumVecElemPerVecReg = ::DummyNumVecElemPerVecReg

Definition at line 77 of file registers.hh.

◆ NumVecPredRegs

const int RiscvISA::NumVecPredRegs = 1

Definition at line 94 of file registers.hh.

◆ NumVecRegs

const unsigned RiscvISA::NumVecRegs = 1

Definition at line 92 of file registers.hh.

◆ p

Bitfield<0> RiscvISA::p

Definition at line 325 of file pra_constants.hh.

Referenced by RiscvISA::ISA::startup(), RiscvISA::TLB::translateData(), and RiscvISA::TLB::translateInst().

◆ PageBytes

const Addr RiscvISA::PageBytes = ULL(1) << PageShift

Definition at line 59 of file isa_traits.hh.

◆ PageShift

const Addr RiscvISA::PageShift = 12

Definition at line 58 of file isa_traits.hh.

◆ pc

Bitfield<4> RiscvISA::pc

Definition at line 242 of file pra_constants.hh.

Referenced by RiscvISA::Decoder::compressed(), RiscvISA::CSROp::CSROp(), RiscvISA::Reset::invoke(), and RiscvISA::MemFenceMicro::MemFenceMicro().

◆ pci

Bitfield<26> RiscvISA::pci

Definition at line 181 of file pra_constants.hh.

◆ pfn

Bitfield<29, 6> RiscvISA::pfn

Definition at line 57 of file pra_constants.hh.

◆ procId

Bitfield<15, 8> RiscvISA::procId

Definition at line 205 of file pra_constants.hh.

◆ pss

Bitfield<9, 6> RiscvISA::pss

Definition at line 160 of file pra_constants.hh.

◆ pState

Bitfield<7, 6> RiscvISA::pState

Definition at line 321 of file pra_constants.hh.

◆ pTagLo

RiscvISA::pTagLo

Definition at line 320 of file pra_constants.hh.

◆ pteBase

RiscvISA::pteBase

Definition at line 65 of file pra_constants.hh.

◆ px

Bitfield<23> RiscvISA::px

Definition at line 115 of file pra_constants.hh.

◆ r

Bitfield< 1 > RiscvISA::r

Definition at line 97 of file pra_constants.hh.

Referenced by RiscvISA::RemoteGDB::RiscvGdbRegCache::getRegs(), and RiscvISA::RemoteGDB::RiscvGdbRegCache::setRegs().

◆ r0

Bitfield<3> RiscvISA::r0

Definition at line 138 of file pra_constants.hh.

◆ random

RiscvISA::random

Definition at line 52 of file pra_constants.hh.

◆ re

Bitfield<25> RiscvISA::re

Definition at line 113 of file pra_constants.hh.

◆ ReturnAddrReg

const int RiscvISA::ReturnAddrReg = 1

Definition at line 101 of file registers.hh.

◆ ReturnValueReg

const int RiscvISA::ReturnValueReg = 10

Definition at line 106 of file registers.hh.

◆ ReturnValueRegs

const std::vector<int> RiscvISA::ReturnValueRegs = {10, 11}

Definition at line 107 of file registers.hh.

◆ rev

Bitfield<7, 0> RiscvISA::rev

Definition at line 206 of file pra_constants.hh.

◆ ripl

Bitfield<15, 10> RiscvISA::ripl

Definition at line 186 of file pra_constants.hh.

◆ s

Bitfield<2> RiscvISA::s

Definition at line 302 of file pra_constants.hh.

◆ sa

Bitfield<3, 0> RiscvISA::sa

Definition at line 258 of file pra_constants.hh.

◆ sei

Bitfield<9> RiscvISA::sei

Definition at line 639 of file registers.hh.

◆ SEI_MASK

const RegVal RiscvISA::SEI_MASK = 1ULL << 9

Definition at line 700 of file registers.hh.

◆ SI_MASK

const RegVal RiscvISA::SI_MASK

Initial value:

= SEI_MASK | UEI_MASK |
                       STI_MASK | UTI_MASK |
                       SSI_MASK | USI_MASK

Definition at line 711 of file registers.hh.

◆ sie

Bitfield<1> RiscvISA::sie

Definition at line 627 of file registers.hh.

◆ sl

Bitfield<7, 4> RiscvISA::sl

Definition at line 257 of file pra_constants.hh.

◆ sm

Bitfield<1> RiscvISA::sm

Definition at line 272 of file pra_constants.hh.

◆ sp

Bitfield<4> RiscvISA::sp

Definition at line 269 of file pra_constants.hh.

◆ spie

Bitfield<5> RiscvISA::spie

Definition at line 624 of file registers.hh.

◆ spp

Bitfield<8> RiscvISA::spp

Definition at line 622 of file registers.hh.

◆ sr

Bitfield<20> RiscvISA::sr

Definition at line 118 of file pra_constants.hh.

◆ ss

Bitfield<11, 8> RiscvISA::ss

Definition at line 256 of file pra_constants.hh.

Referenced by RiscvISA::CompRegOp::generateDisassembly().

◆ ssi

Bitfield<1> RiscvISA::ssi

Definition at line 645 of file registers.hh.

◆ SSI_MASK

const RegVal RiscvISA::SSI_MASK = 1ULL << 1

Definition at line 706 of file registers.hh.

◆ SSTATUS_MASK

const RegVal RiscvISA::SSTATUS_MASK

Initial value:

= STATUS_SD_MASK | STATUS_UXL_MASK |
                            STATUS_MXR_MASK | STATUS_SUM_MASK |
                            STATUS_XS_MASK | STATUS_FS_MASK |
                            STATUS_SPP_MASK | STATUS_SPIE_MASK |
                            STATUS_UPIE_MASK | STATUS_SIE_MASK |
                            STATUS_UIE_MASK

Definition at line 688 of file registers.hh.

◆ ssv0

Bitfield<3, 0> RiscvISA::ssv0

Definition at line 173 of file pra_constants.hh.

◆ ssv1

Bitfield<7, 4> RiscvISA::ssv1

Definition at line 172 of file pra_constants.hh.

◆ ssv2

Bitfield<11, 8> RiscvISA::ssv2

Definition at line 171 of file pra_constants.hh.

◆ ssv3

Bitfield<15, 12> RiscvISA::ssv3

Definition at line 170 of file pra_constants.hh.

◆ ssv4

Bitfield<19, 16> RiscvISA::ssv4

Definition at line 169 of file pra_constants.hh.

◆ ssv5

Bitfield<23, 20> RiscvISA::ssv5

Definition at line 168 of file pra_constants.hh.

◆ ssv6

Bitfield<27, 24> RiscvISA::ssv6

Definition at line 167 of file pra_constants.hh.

◆ ssv7

RiscvISA::ssv7

Definition at line 166 of file pra_constants.hh.

◆ StackPointerReg

const int RiscvISA::StackPointerReg = 2

Definition at line 102 of file registers.hh.

Referenced by RiscvLinux64::archClone(), and RiscvLinux32::archClone().

◆ STATUS_FS_MASK

const RegVal RiscvISA::STATUS_FS_MASK = 3ULL << FS_OFFSET

Definition at line 669 of file registers.hh.

◆ STATUS_MIE_MASK

const RegVal RiscvISA::STATUS_MIE_MASK = 1ULL << 3

Definition at line 675 of file registers.hh.

◆ STATUS_MPIE_MASK

const RegVal RiscvISA::STATUS_MPIE_MASK = 1ULL << 7

Definition at line 672 of file registers.hh.

◆ STATUS_MPP_MASK

const RegVal RiscvISA::STATUS_MPP_MASK = 3ULL << 11

Definition at line 670 of file registers.hh.

◆ STATUS_MPRV_MASK

const RegVal RiscvISA::STATUS_MPRV_MASK = 1ULL << 17

Definition at line 667 of file registers.hh.

◆ STATUS_MXR_MASK

const RegVal RiscvISA::STATUS_MXR_MASK = 1ULL << 19

Definition at line 665 of file registers.hh.

◆ STATUS_SD_MASK

const RegVal RiscvISA::STATUS_SD_MASK = 1ULL << ((sizeof(uint64_t) * 8) - 1)

Definition at line 659 of file registers.hh.

◆ STATUS_SIE_MASK

const RegVal RiscvISA::STATUS_SIE_MASK = 1ULL << 1

Definition at line 676 of file registers.hh.

◆ STATUS_SPIE_MASK

const RegVal RiscvISA::STATUS_SPIE_MASK = 1ULL << 5

Definition at line 673 of file registers.hh.

◆ STATUS_SPP_MASK

const RegVal RiscvISA::STATUS_SPP_MASK = 1ULL << 8

Definition at line 671 of file registers.hh.

◆ STATUS_SUM_MASK

const RegVal RiscvISA::STATUS_SUM_MASK = 1ULL << 18

Definition at line 666 of file registers.hh.

◆ STATUS_SXL_MASK

const RegVal RiscvISA::STATUS_SXL_MASK = 3ULL << SXL_OFFSET

Definition at line 660 of file registers.hh.

◆ STATUS_TSR_MASK

const RegVal RiscvISA::STATUS_TSR_MASK = 1ULL << 22

Definition at line 662 of file registers.hh.

◆ STATUS_TVM_MASK

const RegVal RiscvISA::STATUS_TVM_MASK = 1ULL << 20

Definition at line 664 of file registers.hh.

◆ STATUS_TW_MASK

const RegVal RiscvISA::STATUS_TW_MASK = 1ULL << 21

Definition at line 663 of file registers.hh.

◆ STATUS_UIE_MASK

const RegVal RiscvISA::STATUS_UIE_MASK = 1ULL << 0

Definition at line 677 of file registers.hh.

◆ STATUS_UPIE_MASK

const RegVal RiscvISA::STATUS_UPIE_MASK = 1ULL << 4

Definition at line 674 of file registers.hh.

◆ STATUS_UXL_MASK

const RegVal RiscvISA::STATUS_UXL_MASK = 3ULL << UXL_OFFSET

Definition at line 661 of file registers.hh.

◆ STATUS_XS_MASK

const RegVal RiscvISA::STATUS_XS_MASK = 3ULL << 15

Definition at line 668 of file registers.hh.

◆ sti

Bitfield<5> RiscvISA::sti

Definition at line 642 of file registers.hh.

Referenced by CPA::hwWe(), and AnnotateDumpCallback::process().

◆ STI_MASK

const RegVal RiscvISA::STI_MASK = 1ULL << 5

Definition at line 703 of file registers.hh.

◆ su

Bitfield<15, 12> RiscvISA::su

Definition at line 255 of file pra_constants.hh.

◆ sum

Bitfield<18> RiscvISA::sum

Definition at line 617 of file registers.hh.

Referenced by Net::__tu_cksum(), Net::__tu_cksum6(), Net::cksum(), StatTest::init(), TrafficGen::parseConfig(), popCount(), SimpleNetwork::regStats(), GarnetNetwork::regStats(), FullO3CPU< O3CPUImpl >::regStats(), SC_MODULE(), and TEST().

◆ sx

Bitfield<6> RiscvISA::sx

Definition at line 134 of file pra_constants.hh.

◆ sxl

Bitfield<35, 34> RiscvISA::sxl

Definition at line 611 of file registers.hh.

◆ SXL_OFFSET

const off_t RiscvISA::SXL_OFFSET = 34

Definition at line 650 of file registers.hh.

Referenced by RiscvISA::ISA::clear().

◆ SyscallArgumentRegs

const std::vector<int> RiscvISA::SyscallArgumentRegs = {10, 11, 12, 13, 14, 15, 16}

Definition at line 112 of file registers.hh.

Referenced by RiscvProcess::getSyscallArg().

◆ SyscallNumReg

const int RiscvISA::SyscallNumReg = 17

Definition at line 113 of file registers.hh.

◆ SyscallPseudoReturnReg

const int RiscvISA::SyscallPseudoReturnReg = 10

Definition at line 111 of file registers.hh.

◆ ta

Bitfield<19, 16> RiscvISA::ta

Definition at line 254 of file pra_constants.hh.

◆ ThreadPointerReg

const int RiscvISA::ThreadPointerReg = 4

Definition at line 104 of file registers.hh.

Referenced by RiscvLinux64::archClone().

◆ ti

Bitfield<30> RiscvISA::ti

Definition at line 178 of file pra_constants.hh.

◆ tl

Bitfield< 0 > RiscvISA::tl

Definition at line 253 of file pra_constants.hh.

◆ ts

Bitfield< 27, 24 > RiscvISA::ts

Definition at line 117 of file pra_constants.hh.

◆ tsr

Bitfield<22> RiscvISA::tsr

Definition at line 613 of file registers.hh.

◆ tu

Bitfield<30, 28> RiscvISA::tu

Definition at line 251 of file pra_constants.hh.

◆ tvm

Bitfield<20> RiscvISA::tvm

Definition at line 615 of file registers.hh.

◆ tw

Bitfield<21> RiscvISA::tw

Definition at line 614 of file registers.hh.

◆ u

Bitfield<3> RiscvISA::u

Definition at line 301 of file pra_constants.hh.

◆ uei

Bitfield<8> RiscvISA::uei

Definition at line 640 of file registers.hh.

◆ UEI_MASK

const RegVal RiscvISA::UEI_MASK = 1ULL << 8

Definition at line 701 of file registers.hh.

◆ UI_MASK

const RegVal RiscvISA::UI_MASK = UEI_MASK | UTI_MASK | USI_MASK

Definition at line 714 of file registers.hh.

◆ uie

Bitfield<0> RiscvISA::uie

Definition at line 628 of file registers.hh.

◆ um

Bitfield<4> RiscvISA::um

Definition at line 137 of file pra_constants.hh.

◆ upie

Bitfield<4> RiscvISA::upie

Definition at line 625 of file registers.hh.

◆ UpperBitMask

const MachInst RiscvISA::UpperBitMask = LowerBitMask << sizeof(MachInst) * 4

static

Definition at line 41 of file decoder.cc.

Referenced by RiscvISA::Decoder::moreBytes().

◆ usi

Bitfield<0> RiscvISA::usi

Definition at line 646 of file registers.hh.

◆ USI_MASK

const RegVal RiscvISA::USI_MASK = 1ULL << 0

Definition at line 707 of file registers.hh.

◆ USTATUS_MASK

const RegVal RiscvISA::USTATUS_MASK

Initial value:

= STATUS_SD_MASK | STATUS_MXR_MASK |
                            STATUS_SUM_MASK | STATUS_XS_MASK |
                            STATUS_FS_MASK | STATUS_UPIE_MASK |
                            STATUS_UIE_MASK

Definition at line 694 of file registers.hh.

◆ uti

Bitfield<4> RiscvISA::uti

Definition at line 643 of file registers.hh.

◆ UTI_MASK

const RegVal RiscvISA::UTI_MASK = 1ULL << 4

Definition at line 704 of file registers.hh.

◆ ux

Bitfield<5> RiscvISA::ux

Definition at line 135 of file pra_constants.hh.

◆ uxl

Bitfield<33, 32> RiscvISA::uxl

Definition at line 612 of file registers.hh.

◆ UXL_OFFSET

const off_t RiscvISA::UXL_OFFSET = 32

Definition at line 651 of file registers.hh.

Referenced by RiscvISA::ISA::clear().

◆ v

Bitfield<1> RiscvISA::v

Definition at line 60 of file pra_constants.hh.

◆ vaddr

RiscvISA::vaddr

Definition at line 277 of file pra_constants.hh.

Referenced by RiscvISA::TLB::getsize(), and vtophys().

◆ VecPredRegHasPackedRepr

constexpr bool RiscvISA::VecPredRegHasPackedRepr = ::DummyVecPredRegHasPackedRepr

Definition at line 85 of file registers.hh.

◆ VecPredRegSizeBits

constexpr size_t RiscvISA::VecPredRegSizeBits = ::DummyVecPredRegSizeBits

Definition at line 84 of file registers.hh.

◆ VecRegSizeBytes

constexpr size_t RiscvISA::VecRegSizeBytes = ::DummyVecRegSizeBytes

Definition at line 78 of file registers.hh.

◆ veic

Bitfield<6> RiscvISA::veic

Definition at line 267 of file pra_constants.hh.

◆ vi

Bitfield<3> RiscvISA::vi

Definition at line 227 of file pra_constants.hh.

◆ vint

Bitfield<5> RiscvISA::vint

Definition at line 268 of file pra_constants.hh.

◆ vpn2

Bitfield<39, 13> RiscvISA::vpn2

Definition at line 99 of file pra_constants.hh.

◆ vpn2x

Bitfield<12, 11> RiscvISA::vpn2x

Definition at line 100 of file pra_constants.hh.

◆ vs

Bitfield<9, 5> RiscvISA::vs

Definition at line 148 of file pra_constants.hh.

◆ w

Bitfield< 30 > RiscvISA::w

Definition at line 280 of file pra_constants.hh.

◆ WARN_FAILURE

const int RiscvISA::WARN_FAILURE = 10000

Definition at line 67 of file locked_mem.hh.

◆ wired

RiscvISA::wired

Definition at line 88 of file pra_constants.hh.

◆ wp

Bitfield<22> RiscvISA::wp

Definition at line 184 of file pra_constants.hh.

◆ wr

Bitfield<3> RiscvISA::wr

Definition at line 243 of file pra_constants.hh.

◆ xs

Bitfield<16, 15> RiscvISA::xs

Definition at line 619 of file registers.hh.

◆ ZeroReg

const int RiscvISA::ZeroReg = 0

Definition at line 100 of file registers.hh.

Namespaces

Classes

Typedefs

Enumerations

Functions

Variables

Typedef Documentation

◆ ConstVecPredReg

◆ ConstVecReg

◆ ExtMachInst

◆ MachInst

◆ VecElem

◆ VecPredReg

◆ VecPredRegContainer

◆ VecReg

◆ VecRegContainer

Enumeration Type Documentation

◆ CSRIndex

◆ ExceptionCode

◆ FloatException

◆ MiscRegIndex

◆ PrivilegeMode

Function Documentation

◆ advancePC()

◆ BitUnion32()

◆ BitUnion64()

◆ buildRetPC()

◆ copyRegs()

◆ EndBitUnion() [1/26]

◆ EndBitUnion() [2/26]

◆ EndBitUnion() [3/26]

◆ EndBitUnion() [4/26]

◆ EndBitUnion() [5/26]

◆ EndBitUnion() [6/26]

◆ EndBitUnion() [7/26]

◆ EndBitUnion() [8/26]

◆ EndBitUnion() [9/26]

◆ EndBitUnion() [10/26]

◆ EndBitUnion() [11/26]

◆ EndBitUnion() [12/26]

◆ EndBitUnion() [13/26]

◆ EndBitUnion() [14/26]

◆ EndBitUnion() [15/26]

◆ EndBitUnion() [16/26]

◆ EndBitUnion() [17/26]

◆ EndBitUnion() [18/26]

◆ EndBitUnion() [19/26]

◆ EndBitUnion() [20/26]

◆ EndBitUnion() [21/26]

◆ EndBitUnion() [22/26]

◆ EndBitUnion() [23/26]

◆ EndBitUnion() [24/26]

◆ EndBitUnion() [25/26]

◆ EndBitUnion() [26/26]

◆ EndSubBitUnion() [1/3]

◆ EndSubBitUnion() [2/3]

◆ EndSubBitUnion() [3/3]

◆ getArgument()

◆ getExecutingAsid()

◆ globalClearExclusive()

◆ handleIprRead()

◆ handleIprWrite()

◆ handleLockedRead()

◆ handleLockedSnoop()

◆ handleLockedSnoopHit()

◆ handleLockedWrite()

◆ inUserMode()

◆ isquietnan()

◆ isquietnan< double >()

◆ isquietnan< float >()

◆ issignalingnan()

◆ issignalingnan< double >()

◆ issignalingnan< float >()

◆ registerName()

◆ skipFunction()

◆ SubBitUnion() [1/2]

◆ SubBitUnion() [2/2]

◆ vtophys() [1/2]

◆ vtophys() [2/2]

Variable Documentation