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mmapped_ipr.hh
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1 /*
2  * Copyright (c) 2006 The Regents of The University of Michigan
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28  * Authors: Ali Saidi
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30 
31 #ifndef __ARCH_RISCV_MMAPPED_IPR_HH__
32 #define __ARCH_RISCV_MMAPPED_IPR_HH__
33 
40 #include "base/types.hh"
41 
42 class Packet;
43 class ThreadContext;
44 
45 namespace RiscvISA
46 {
47 
48 inline Cycles handleIprRead(ThreadContext *, Packet *) { return Cycles(1); }
49 inline Cycles handleIprWrite(ThreadContext *, Packet *) { return Cycles(1); }
50 
51 } // namespace RiscvISA
52 
53 #endif
Cycles is a wrapper class for representing cycle counts, i.e.
Definition: types.hh:83
ThreadContext is the external interface to all thread state for anything outside of the CPU...
Defines global host-dependent types: Counter, Tick, and (indirectly) {int,uint}{8,16,32,64}_t.
A Packet is used to encapsulate a transfer between two objects in the memory system (e...
Definition: packet.hh:255
Cycles handleIprWrite(ThreadContext *, Packet *)
Definition: mmapped_ipr.hh:49
Cycles handleIprRead(ThreadContext *, Packet *)
Definition: mmapped_ipr.hh:48

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