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CrossbarSwitch.cc
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1 /*
2  * Copyright (c) 2020 Inria
3  * Copyright (c) 2016 Georgia Institute of Technology
4  * Copyright (c) 2008 Princeton University
5  * All rights reserved.
6  *
7  * Redistribution and use in source and binary forms, with or without
8  * modification, are permitted provided that the following conditions are
9  * met: redistributions of source code must retain the above copyright
10  * notice, this list of conditions and the following disclaimer;
11  * redistributions in binary form must reproduce the above copyright
12  * notice, this list of conditions and the following disclaimer in the
13  * documentation and/or other materials provided with the distribution;
14  * neither the name of the copyright holders nor the names of its
15  * contributors may be used to endorse or promote products derived from
16  * this software without specific prior written permission.
17  *
18  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
19  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
20  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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22  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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24  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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26  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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28  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29  */
30 
31 
33 
34 #include "debug/RubyNetwork.hh"
37 
39  : Consumer(router), m_router(router), m_num_vcs(m_router->get_num_vcs()),
40  m_crossbar_activity(0), switchBuffers(0)
41 {
42 }
43 
44 void
46 {
48 }
49 
50 /*
51  * The wakeup function of the CrossbarSwitch loops through all input ports,
52  * and sends the winning flit (from SA) out of its output port on to the
53  * output link. The output link is scheduled for wakeup in the next cycle.
54  */
55 
56 void
58 {
59  DPRINTF(RubyNetwork, "CrossbarSwitch at Router %d woke up "
60  "at time: %lld\n",
62 
63  for (auto& switch_buffer : switchBuffers) {
64  if (!switch_buffer.isReady(m_router->curCycle())) {
65  continue;
66  }
67 
68  flit *t_flit = switch_buffer.peekTopFlit();
69  if (t_flit->is_stage(ST_, m_router->curCycle())) {
70  int outport = t_flit->get_outport();
71 
72  // flit performs LT_ in the next cycle
73  t_flit->advance_stage(LT_, m_router->curCycle() + Cycles(1));
74  t_flit->set_time(m_router->curCycle() + Cycles(1));
75 
76  // This will take care of waking up the Network Link
77  // in the next cycle
78  m_router->getOutputUnit(outport)->insert_flit(t_flit);
79  switch_buffer.getTopFlit();
81  }
82  }
83 }
84 
85 uint32_t
87 {
88  uint32_t num_functional_writes = 0;
89 
90  for (auto& switch_buffer : switchBuffers) {
91  num_functional_writes += switch_buffer.functionalWrite(pkt);
92  }
93 
94  return num_functional_writes;
95 }
96 
97 void
99 {
101 }
#define DPRINTF(x,...)
Definition: trace.hh:222
void set_time(Cycles time)
Definition: flit.hh:63
Cycles is a wrapper class for representing cycle counts, i.e.
Definition: types.hh:81
int get_outport()
Definition: flit.hh:48
uint32_t functionalWrite(Packet *pkt)
int get_id()
Definition: Router.hh:80
OutputUnit * getOutputUnit(unsigned port)
Definition: Router.hh:97
double m_crossbar_activity
Definition: flit.hh:41
Cycles curCycle() const
Determine the current cycle, corresponding to a tick aligned to a clock edge.
A Packet is used to encapsulate a transfer between two objects in the memory system (e...
Definition: packet.hh:249
bool is_stage(flit_stage stage, Cycles time)
Definition: flit.hh:73
Definition: Router.hh:56
std::vector< flitBuffer > switchBuffers
int get_num_inports()
Definition: Router.hh:78
void advance_stage(flit_stage t_stage, Cycles newTime)
Definition: flit.hh:80
CrossbarSwitch(Router *router)
void insert_flit(flit *t_flit)
Definition: OutputUnit.cc:151

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