#include <lsq.hh>

Inheritance diagram for LSQ< Impl >::SplitDataRequest:

Public Member Functions
	SplitDataRequest (LSQUnit port, const DynInstPtr &inst, bool isLoad, const Addr &addr, const uint32_t &size, const Request::Flags &flags_, PacketDataPtr data=nullptr, uint64_t res=nullptr)

virtual	~SplitDataRequest ()

virtual void	finish (const Fault &fault, const RequestPtr &req, ThreadContext *tc, BaseTLB::Mode mode)

virtual bool	recvTimingResp (PacketPtr pkt)

virtual void	initiateTranslation ()

virtual void	sendPacketToCache ()

virtual void	buildPackets ()

virtual Cycles	handleLocalAccess (ThreadContext *thread, PacketPtr pkt)
	Memory mapped IPR accesses. More...

virtual bool	isCacheBlockHit (Addr blockAddr, Addr cacheBlockMask)
	Caches may probe into the load-store queue to enforce memory ordering guarantees. More...

virtual RequestPtr	mainRequest ()

virtual PacketPtr	mainPacket ()

Public Member Functions inherited from LSQ< Impl >::LSQRequest
void	packetSent ()
	Update the status to reflect that a packet was sent. More...

void	packetNotSent ()
	Update the status to reflect that a packet was not sent. More...

void	sendFragmentToTranslation (int i)

bool	isComplete ()

bool	isInTranslation ()

bool	isTranslationComplete ()

bool	isTranslationBlocked ()

bool	isSent ()

bool	isPartialFault ()

bool	isMemAccessRequired ()

void	setStateToFault ()

void	freeLSQEntry ()
	The LSQ entry is cleared. More...

void	discard ()
	The request is discarded (e.g. More...

void	packetReplied ()

void	writebackScheduled ()

void	writebackDone ()

void	squashTranslation ()

void	complete ()

void	setContext (const ContextID &context_id)
	Convenience getters/setters. More...

const DynInstPtr &	instruction ()

void	setVirt (Addr vaddr, unsigned size, Request::Flags flags_, MasterID mid, Addr pc)
	Set up virtual request. More...

void	taskId (const uint32_t &v)

uint32_t	taskId () const

RequestPtr	request (int idx=0)

const RequestPtr	request (int idx=0) const

Addr	getVaddr (int idx=0) const

PacketPtr	packet (int idx=0)

void	senderState (LSQSenderState *st)

const LSQSenderState *	senderState () const

void	discardSenderState ()
	Mark senderState as discarded. More...

bool	isAnyOutstandingRequest ()
	Test if there is any in-flight translation or mem access request. More...

bool	isSplit () const

Public Member Functions inherited from BaseTLB::Translation
virtual	~Translation ()

Protected Types
using	Flag = typename LSQRequest::Flag

using	State = typename LSQRequest::State

Protected Types inherited from LSQ< Impl >::LSQRequest
enum	Flag : FlagsStorage { IsLoad = 0x00000001, WbStore = 0x00000002, Delayed = 0x00000004, IsSplit = 0x00000008, TranslationStarted = 0x00000010, TranslationFinished = 0x00000020, Sent = 0x00000040, Retry = 0x00000080, Complete = 0x00000100, TranslationSquashed = 0x00000200, Discarded = 0x00000400, LSQEntryFreed = 0x00000800, WritebackScheduled = 0x00001000, WritebackDone = 0x00002000, IsAtomic = 0x00004000 }

enum	State { State::NotIssued, State::Translation, State::Request, State::Fault, State::PartialFault }

typedef uint32_t	FlagsStorage

typedef ::Flags< FlagsStorage >	FlagsType

Protected Attributes
uint32_t	numFragments

uint32_t	numReceivedPackets

RequestPtr	mainReq

PacketPtr	_mainPacket

Protected Attributes inherited from LSQ< Impl >::LSQRequest
FlagsType	flags

State	_state

LSQSenderState *	_senderState

uint32_t	numTranslatedFragments

uint32_t	numInTranslationFragments

uint32_t	_entryIdx
	LQ/SQ entry idx. More...

Additional Inherited Members
Public Attributes inherited from LSQ< Impl >::LSQRequest
LSQUnit &	_port

const DynInstPtr	_inst

uint32_t	_taskId

PacketDataPtr	_data

std::vector< PacketPtr >	_packets

std::vector< RequestPtr >	_requests

std::vector< Fault >	_fault

uint64_t *	_res

const Addr	_addr

const uint32_t	_size

const Request::Flags	_flags

std::vector< bool >	_byteEnable

uint32_t	_numOutstandingPackets

AtomicOpFunctorPtr	_amo_op

Protected Member Functions inherited from LSQ< Impl >::LSQRequest
void	setState (const State &newState)

void	markDelayed () override
	Signal that the translation has been delayed due to a hw page table walk. More...

bool	isDelayed ()

LSQUnit *	lsqUnit ()

	LSQRequest (LSQUnit *port, const DynInstPtr &inst, bool isLoad)

	LSQRequest (LSQUnit port, const DynInstPtr &inst, bool isLoad, const Addr &addr, const uint32_t &size, const Request::Flags &flags_, PacketDataPtr data=nullptr, uint64_t res=nullptr, AtomicOpFunctorPtr amo_op=nullptr)

bool	isLoad () const

bool	isAtomic () const

void	install ()
	Install the request in the LQ/SQ. More...

virtual bool	squashed () const override
	This function is used by the page table walker to determine if it should translate the a pending request or if the underlying request has been squashed. More...

bool	isReleased ()
	Test if the LSQRequest has been released, i.e. More...

void	release (Flag reason)
	Release the LSQRequest. More...

void	addRequest (Addr addr, unsigned size, const std::vector< bool > &byte_enable)
	Helper function used to add a (sub)request, given its address `addr`, size `size` and byte-enable mask `byteEnable`. More...

virtual	~LSQRequest ()
	Destructor. More...

Detailed Description

template<class Impl>
class LSQ< Impl >::SplitDataRequest

Definition at line 744 of file lsq.hh.

Member Typedef Documentation

◆ Flag

template<class Impl>

using LSQ< Impl >::SplitDataRequest::Flag = typename LSQRequest::Flag

protected

Definition at line 749 of file lsq.hh.

◆ State

template<class Impl>

using LSQ< Impl >::SplitDataRequest::State = typename LSQRequest::State

protected

Definition at line 750 of file lsq.hh.

Constructor & Destructor Documentation

◆ SplitDataRequest()

template<class Impl>

LSQ< Impl >::SplitDataRequest::SplitDataRequest	(	LSQUnit *	port,
		const DynInstPtr &	inst,
		bool	isLoad,
		const Addr &	addr,
		const uint32_t &	size,
		const Request::Flags &	flags_,
		PacketDataPtr	data = `nullptr`,
		uint64_t *	res = `nullptr`
	)

inline

Definition at line 782 of file lsq.hh.

References Packet::set().

◆ ~SplitDataRequest()

template<class Impl>

virtual LSQ< Impl >::SplitDataRequest::~SplitDataRequest ( )

inlinevirtual

Definition at line 796 of file lsq.hh.

References LSQ< Impl >::LSQ(), ArmISA::mode, LSQ< Impl >::recvTimingResp(), and LSQ< Impl >::thread.

Member Function Documentation

◆ buildPackets()

template<class Impl >

void LSQ< Impl >::SplitDataRequest::buildPackets ( )

virtual

Implements LSQ< Impl >::LSQRequest.

Definition at line 1042 of file lsq_impl.hh.

References Packet::createRead(), Packet::createWrite(), Packet::dataDynamic(), Packet::dataStatic(), ArmISA::i, NoFault, ArmISA::offset, MipsISA::r, and Packet::senderState.

◆ finish()

template<class Impl >

void LSQ< Impl >::SplitDataRequest::finish	(	const Fault &	fault,
		const RequestPtr &	req,
		ThreadContext *	tc,
		BaseTLB::Mode	mode
	)

virtual

Implements BaseTLB::Translation.

Definition at line 804 of file lsq_impl.hh.

References ArmISA::i, and NoFault.

◆ handleLocalAccess()

template<class Impl >

Cycles LSQ< Impl >::SplitDataRequest::handleLocalAccess	(	ThreadContext *	thread,
		PacketPtr	pkt
	)

virtual

Memory mapped IPR accesses.

Implements LSQ< Impl >::LSQRequest.

Definition at line 1105 of file lsq_impl.hh.

References ArmISA::d, Packet::dataStatic(), Packet::getPtr(), ArmISA::offset, MipsISA::r, MemCmd::ReadReq, and MemCmd::WriteReq.

◆ initiateTranslation()

template<class Impl >

void LSQ< Impl >::SplitDataRequest::initiateTranslation ( )

virtual

Implements LSQ< Impl >::LSQRequest.

Definition at line 889 of file lsq_impl.hh.

References addrBlockAlign(), ArmISA::i, and MipsISA::r.

◆ isCacheBlockHit()

template<class Impl >

bool LSQ< Impl >::SplitDataRequest::isCacheBlockHit	(	Addr	blockAddr,
		Addr	blockMask
	)

virtual

Caches may probe into the load-store queue to enforce memory ordering guarantees.

This method supports probes by providing a mechanism to compare snoop messages with requests tracked by the load-store queue.

Consistency models must enforce ordering constraints. TSO, for instance, must prevent memory reorderings except stores which are reordered after loads. The reordering restrictions negatively impact performance by cutting down on memory level parallelism. However, the core can regain performance by generating speculative loads. Speculative loads may issue without affecting correctness if precautions are taken to handle invalid memory orders. The load queue must squash under memory model violations. Memory model violations may occur when block ownership is granted to another core or the block cannot be accurately monitored by the load queue.

The load-store queue handles partial faults which complicates this method. Physical addresses must be compared between requests and snoops. Some requests will not have a valid physical address, since partial faults may have outstanding translations. Therefore, the existence of a valid request address must be checked before comparing block hits. We assume no pipeline squash is needed if a valid request address does not exist.

Implements LSQ< Impl >::LSQRequest.

Definition at line 1148 of file lsq_impl.hh.

References MipsISA::r.

◆ mainPacket()

template<class Impl >

PacketPtr LSQ< Impl >::SplitDataRequest::mainPacket ( )

virtual

Reimplemented from LSQ< Impl >::LSQRequest.

Definition at line 875 of file lsq_impl.hh.

◆ mainRequest()

template<class Impl >

RequestPtr LSQ< Impl >::SplitDataRequest::mainRequest ( )

virtual

Reimplemented from LSQ< Impl >::LSQRequest.

Definition at line 882 of file lsq_impl.hh.

◆ recvTimingResp()

template<class Impl >

bool LSQ< Impl >::SplitDataRequest::recvTimingResp ( PacketPtr pkt )

virtual

Implements LSQ< Impl >::LSQRequest.

Definition at line 997 of file lsq_impl.hh.

References Packet::createRead(), Packet::createWrite(), Packet::dataStatic(), LSQ< Impl >::LSQSenderState::outstanding, and Packet::senderState.

◆ sendPacketToCache()

template<class Impl >

void LSQ< Impl >::SplitDataRequest::sendPacketToCache ( )

virtual

Implements LSQ< Impl >::LSQRequest.

Definition at line 1085 of file lsq_impl.hh.

Member Data Documentation

◆ _mainPacket

template<class Impl>

PacketPtr LSQ< Impl >::SplitDataRequest::_mainPacket

protected

Definition at line 779 of file lsq.hh.

◆ mainReq

template<class Impl>

RequestPtr LSQ< Impl >::SplitDataRequest::mainReq

protected

Definition at line 778 of file lsq.hh.

◆ numFragments

template<class Impl>

uint32_t LSQ< Impl >::SplitDataRequest::numFragments

protected

Definition at line 776 of file lsq.hh.

◆ numReceivedPackets

template<class Impl>

uint32_t LSQ< Impl >::SplitDataRequest::numReceivedPackets

protected

Definition at line 777 of file lsq.hh.

The documentation for this class was generated from the following files:

cpu/o3/lsq.hh
cpu/o3/lsq_impl.hh

Public Member Functions

Protected Types

Protected Attributes

Additional Inherited Members

Detailed Description

template<class Impl> class LSQ< Impl >::SplitDataRequest

Member Typedef Documentation

◆ Flag

◆ State

Constructor & Destructor Documentation

◆ SplitDataRequest()

◆ ~SplitDataRequest()

Member Function Documentation

◆ buildPackets()

◆ finish()

◆ handleLocalAccess()

◆ initiateTranslation()

◆ isCacheBlockHit()

◆ mainPacket()

◆ mainRequest()

◆ recvTimingResp()

◆ sendPacketToCache()

Member Data Documentation

◆ _mainPacket

◆ mainReq

◆ numFragments

◆ numReceivedPackets

template<class Impl>
class LSQ< Impl >::SplitDataRequest