IcachePort class that interfaces with L1 Instruction Cache. More...

#include <trace_cpu.hh>

Inheritance diagram for TraceCPU::IcachePort:

Public Member Functions
	IcachePort (TraceCPU *_cpu)
	Default constructor. More...

bool	recvTimingResp (PacketPtr pkt)
	Receive the timing reponse and simply delete the packet since instruction fetch requests are issued as per the timing in the trace and responses are ignored. More...

void	recvTimingSnoopReq (PacketPtr pkt)
	Required functionally but do nothing. More...

void	recvReqRetry ()
	Handle a retry signalled by the cache if instruction read failed in the first attempt. More...

Public Member Functions inherited from MasterPort
	MasterPort (const std::string &name, SimObject *_owner, PortID id=InvalidPortID)
	Master port. More...

virtual	~MasterPort ()

void	bind (Port &peer) override
	Bind this master port to a slave port. More...

void	unbind () override
	Unbind this master port and the associated slave port. More...

virtual bool	isSnooping () const
	Determine if this master port is snooping or not. More...

AddrRangeList	getAddrRanges () const
	Get the address ranges of the connected slave port. More...

void	printAddr (Addr a)
	Inject a PrintReq for the given address to print the state of that address throughout the memory system. More...

Tick	sendAtomic (PacketPtr pkt)
	Send an atomic request packet, where the data is moved and the state is updated in zero time, without interleaving with other memory accesses. More...

Tick	sendAtomicBackdoor (PacketPtr pkt, MemBackdoorPtr &backdoor)
	Send an atomic request packet like above, but also request a backdoor to the data being accessed. More...

void	sendFunctional (PacketPtr pkt) const
	Send a functional request packet, where the data is instantly updated everywhere in the memory system, without affecting the current state of any block or moving the block. More...

bool	sendTimingReq (PacketPtr pkt)
	Attempt to send a timing request to the slave port by calling its corresponding receive function. More...

bool	tryTiming (PacketPtr pkt) const
	Check if the slave can handle a timing request. More...

bool	sendTimingSnoopResp (PacketPtr pkt)
	Attempt to send a timing snoop response packet to the slave port by calling its corresponding receive function. More...

virtual void	sendRetryResp ()
	Send a retry to the slave port that previously attempted a sendTimingResp to this master port and failed. More...

Public Member Functions inherited from Port
virtual	~Port ()
	Virtual destructor due to inheritance. More...

Port &	getPeer ()
	Return a reference to this port's peer. More...

const std::string	name () const
	Return port name (for DPRINTF). More...

PortID	getId () const
	Get the port id. More...

bool	isConnected () const
	Is this port currently connected to a peer? More...

void	takeOverFrom (Port *old)
	A utility function to make it easier to swap out ports. More...

Private Attributes
TraceCPU *	owner

Additional Inherited Members
Protected Member Functions inherited from MasterPort
virtual void	recvRangeChange ()
	Called to receive an address range change from the peer slave port. More...

Tick	recvAtomicSnoop (PacketPtr pkt) override
	Default implementations. More...

void	recvFunctionalSnoop (PacketPtr pkt) override
	Receive a functional snoop request packet from the peer. More...

void	recvTimingSnoopReq (PacketPtr pkt) override
	Receive a timing snoop request from the peer. More...

void	recvRetrySnoopResp () override
	Called by the peer if sendTimingSnoopResp was called on this protocol (causing recvTimingSnoopResp to be called on the peer) and was unsuccessful. More...

Protected Member Functions inherited from Port
	Port (const std::string &_name, PortID _id)
	Abstract base class for ports. More...

Protected Member Functions inherited from AtomicRequestProtocol
Tick	send (AtomicResponseProtocol *peer, PacketPtr pkt)
	Send an atomic request packet, where the data is moved and the state is updated in zero time, without interleaving with other memory accesses. More...

Tick	sendBackdoor (AtomicResponseProtocol *peer, PacketPtr pkt, MemBackdoorPtr &backdoor)
	Send an atomic request packet like above, but also request a backdoor to the data being accessed. More...

Protected Member Functions inherited from TimingRequestProtocol
bool	sendReq (TimingResponseProtocol *peer, PacketPtr pkt)
	Attempt to send a timing request to the peer by calling its corresponding receive function. More...

bool	trySend (TimingResponseProtocol *peer, PacketPtr pkt) const
	Check if the peer can handle a timing request. More...

bool	sendSnoopResp (TimingResponseProtocol *peer, PacketPtr pkt)
	Attempt to send a timing snoop response packet to it's peer by calling its corresponding receive function. More...

void	sendRetryResp (TimingResponseProtocol *peer)
	Send a retry to the peer that previously attempted a sendTimingResp to this protocol and failed. More...

Protected Member Functions inherited from FunctionalRequestProtocol
void	send (FunctionalResponseProtocol *peer, PacketPtr pkt) const
	Send a functional request packet, where the data is instantly updated everywhere in the memory system, without affecting the current state of any block or moving the block. More...

Protected Attributes inherited from MasterPort
SimObject &	owner

Protected Attributes inherited from Port
const PortID	id
	A numeric identifier to distinguish ports in a vector, and set to InvalidPortID in case this port is not part of a vector. More...

Port *	_peer
	A pointer to this port's peer. More...

bool	_connected
	Whether this port is currently connected to a peer port. More...

Detailed Description

IcachePort class that interfaces with L1 Instruction Cache.

Definition at line 224 of file trace_cpu.hh.

Constructor & Destructor Documentation

◆ IcachePort()

TraceCPU::IcachePort::IcachePort ( TraceCPU * _cpu )

inline

Default constructor.

Definition at line 228 of file trace_cpu.hh.

References recvTimingResp().

Member Function Documentation

◆ recvReqRetry()

void TraceCPU::IcachePort::recvReqRetry ( )

virtual

Handle a retry signalled by the cache if instruction read failed in the first attempt.

Implements TimingRequestProtocol.

Definition at line 1222 of file trace_cpu.cc.

References TraceCPU::icacheRetryRecvd(), and TraceCPU::ElasticDataGen::owner.

Referenced by TraceCPU::DcachePort::recvFunctionalSnoop(), and recvTimingSnoopReq().

◆ recvTimingResp()

bool TraceCPU::IcachePort::recvTimingResp ( PacketPtr pkt )

virtual

Receive the timing reponse and simply delete the packet since instruction fetch requests are issued as per the timing in the trace and responses are ignored.

Parameters

pkt	Pointer to packet received

Returns: true

Implements TimingRequestProtocol.

Definition at line 1212 of file trace_cpu.cc.

Referenced by TraceCPU::DcachePort::DcachePort(), and IcachePort().

◆ recvTimingSnoopReq()

void TraceCPU::IcachePort::recvTimingSnoopReq ( PacketPtr pkt )

inlinevirtual

Required functionally but do nothing.

Parameters

pkt	Pointer to packet received

Implements TimingRequestProtocol.

Definition at line 249 of file trace_cpu.hh.

References recvReqRetry().

Member Data Documentation

◆ owner

TraceCPU* TraceCPU::IcachePort::owner

private

Definition at line 258 of file trace_cpu.hh.

The documentation for this class was generated from the following files:

cpu/trace/trace_cpu.hh
cpu/trace/trace_cpu.cc

Public Member Functions

Private Attributes

Additional Inherited Members

Detailed Description

Constructor & Destructor Documentation

◆ IcachePort()

Member Function Documentation

◆ recvReqRetry()

◆ recvTimingResp()

◆ recvTimingSnoopReq()

Member Data Documentation

◆ owner