base.hh

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/*
 * Copyright (c) 2012-2013, 2015-2016, 2018-2019 ARM Limited
 * All rights reserved.
 *
 * The license below extends only to copyright in the software and shall
 * not be construed as granting a license to any other intellectual
 * property including but not limited to intellectual property relating
 * to a hardware implementation of the functionality of the software
 * licensed hereunder.  You may use the software subject to the license
 * terms below provided that you ensure that this notice is replicated
 * unmodified and in its entirety in all distributions of the software,
 * modified or unmodified, in source code or in binary form.
 *
 * Copyright (c) 2003-2005 The Regents of The University of Michigan
 * All rights reserved.
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 * modification, are permitted provided that the following conditions are
 * met: redistributions of source code must retain the above copyright
 * notice, this list of conditions and the following disclaimer;
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 */

#ifndef __MEM_CACHE_BASE_HH__
#define __MEM_CACHE_BASE_HH__

#include <cassert>
#include <cstdint>
#include <string>

#include "base/addr_range.hh"
#include "base/statistics.hh"
#include "base/trace.hh"
#include "base/types.hh"
#include "debug/Cache.hh"
#include "debug/CachePort.hh"
#include "enums/Clusivity.hh"
#include "mem/cache/cache_blk.hh"
#include "mem/cache/compressors/base.hh"
#include "mem/cache/mshr_queue.hh"
#include "mem/cache/tags/base.hh"
#include "mem/cache/write_queue.hh"
#include "mem/cache/write_queue_entry.hh"
#include "mem/packet.hh"
#include "mem/packet_queue.hh"
#include "mem/qport.hh"
#include "mem/request.hh"
#include "params/WriteAllocator.hh"
#include "sim/clocked_object.hh"
#include "sim/eventq.hh"
#include "sim/probe/probe.hh"
#include "sim/serialize.hh"
#include "sim/sim_exit.hh"
#include "sim/system.hh"

namespace Prefetcher {
    class Base;
}
class MSHR;
class MasterPort;
class QueueEntry;
struct BaseCacheParams;

class BaseCache : public ClockedObject
{
  protected:
    enum MSHRQueueIndex {
        MSHRQueue_MSHRs,
        MSHRQueue_WriteBuffer
    };

  public:
    enum BlockedCause {
        Blocked_NoMSHRs = MSHRQueue_MSHRs,
        Blocked_NoWBBuffers = MSHRQueue_WriteBuffer,
        Blocked_NoTargets,
        NUM_BLOCKED_CAUSES
    };

  protected:

    class CacheMasterPort : public QueuedMasterPort
    {

      public:

        void schedSendEvent(Tick time)
        {
            DPRINTF(CachePort, "Scheduling send event at %llu\n", time);
            reqQueue.schedSendEvent(time);
        }

      protected:

        CacheMasterPort(const std::string &_name, BaseCache *_cache,
                        ReqPacketQueue &_reqQueue,
                        SnoopRespPacketQueue &_snoopRespQueue) :
            QueuedMasterPort(_name, _cache, _reqQueue, _snoopRespQueue)
        { }

        virtual bool isSnooping() const { return true; }
    };

    class CacheReqPacketQueue : public ReqPacketQueue
    {

      protected:

        BaseCache &cache;
        SnoopRespPacketQueue &snoopRespQueue;

      public:

        CacheReqPacketQueue(BaseCache &cache, MasterPort &port,
                            SnoopRespPacketQueue &snoop_resp_queue,
                            const std::string &label) :
            ReqPacketQueue(cache, port, label), cache(cache),
            snoopRespQueue(snoop_resp_queue) { }

        virtual void sendDeferredPacket();

        bool checkConflictingSnoop(const PacketPtr pkt)
        {
            if (snoopRespQueue.checkConflict(pkt, cache.blkSize)) {
                DPRINTF(CachePort, "Waiting for snoop response to be "
                        "sent\n");
                Tick when = snoopRespQueue.deferredPacketReadyTime();
                schedSendEvent(when);
                return true;
            }
            return false;
        }
    };


    class MemSidePort : public CacheMasterPort
    {
      private:

        CacheReqPacketQueue _reqQueue;

        SnoopRespPacketQueue _snoopRespQueue;

        // a pointer to our specific cache implementation
        BaseCache *cache;

      protected:

        virtual void recvTimingSnoopReq(PacketPtr pkt);

        virtual bool recvTimingResp(PacketPtr pkt);

        virtual Tick recvAtomicSnoop(PacketPtr pkt);

        virtual void recvFunctionalSnoop(PacketPtr pkt);

      public:

        MemSidePort(const std::string &_name, BaseCache *_cache,
                    const std::string &_label);
    };

    class CacheSlavePort : public QueuedSlavePort
    {

      public:

        void setBlocked();

        void clearBlocked();

        bool isBlocked() const { return blocked; }

      protected:

        CacheSlavePort(const std::string &_name, BaseCache *_cache,
                       const std::string &_label);

        RespPacketQueue queue;

        bool blocked;

        bool mustSendRetry;

      private:

        void processSendRetry();

        EventFunctionWrapper sendRetryEvent;

    };

    class CpuSidePort : public CacheSlavePort
    {
      private:

        // a pointer to our specific cache implementation
        BaseCache *cache;

      protected:
        virtual bool recvTimingSnoopResp(PacketPtr pkt) override;

        virtual bool tryTiming(PacketPtr pkt) override;

        virtual bool recvTimingReq(PacketPtr pkt) override;

        virtual Tick recvAtomic(PacketPtr pkt) override;

        virtual void recvFunctional(PacketPtr pkt) override;

        virtual AddrRangeList getAddrRanges() const override;

      public:

        CpuSidePort(const std::string &_name, BaseCache *_cache,
                    const std::string &_label);

    };

    CpuSidePort cpuSidePort;
    MemSidePort memSidePort;

  protected:

    MSHRQueue mshrQueue;

    WriteQueue writeBuffer;

    BaseTags *tags;

    BaseCacheCompressor* compressor;

    Prefetcher::Base *prefetcher;

    ProbePointArg<PacketPtr> *ppHit;

    ProbePointArg<PacketPtr> *ppMiss;

    ProbePointArg<PacketPtr> *ppFill;

    WriteAllocator * const writeAllocator;

    TempCacheBlk *tempBlock;

    std::unique_ptr<Packet> pendingDelete;

    void markInService(MSHR *mshr, bool pending_modified_resp)
    {
        bool wasFull = mshrQueue.isFull();
        mshrQueue.markInService(mshr, pending_modified_resp);

        if (wasFull && !mshrQueue.isFull()) {
            clearBlocked(Blocked_NoMSHRs);
        }
    }

    void markInService(WriteQueueEntry *entry)
    {
        bool wasFull = writeBuffer.isFull();
        writeBuffer.markInService(entry);

        if (wasFull && !writeBuffer.isFull()) {
            clearBlocked(Blocked_NoWBBuffers);
        }
    }

    inline bool allocOnFill(MemCmd cmd) const
    {
        return clusivity == Enums::mostly_incl ||
            cmd == MemCmd::WriteLineReq ||
            cmd == MemCmd::ReadReq ||
            cmd == MemCmd::WriteReq ||
            cmd.isPrefetch() ||
            cmd.isLLSC();
    }

    Addr regenerateBlkAddr(CacheBlk* blk);

    Cycles calculateTagOnlyLatency(const uint32_t delay,
                                   const Cycles lookup_lat) const;
    Cycles calculateAccessLatency(const CacheBlk* blk, const uint32_t delay,
                                  const Cycles lookup_lat) const;

    virtual bool access(PacketPtr pkt, CacheBlk *&blk, Cycles &lat,
                        PacketList &writebacks);

    /*
     * Handle a timing request that hit in the cache
     *
     * @param ptk The request packet
     * @param blk The referenced block
     * @param request_time The tick at which the block lookup is compete
     */
    virtual void handleTimingReqHit(PacketPtr pkt, CacheBlk *blk,
                                    Tick request_time);

    /*
     * Handle a timing request that missed in the cache
     *
     * Implementation specific handling for different cache
     * implementations
     *
     * @param ptk The request packet
     * @param blk The referenced block
     * @param forward_time The tick at which we can process dependent requests
     * @param request_time The tick at which the block lookup is compete
     */
    virtual void handleTimingReqMiss(PacketPtr pkt, CacheBlk *blk,
                                     Tick forward_time,
                                     Tick request_time) = 0;

    /*
     * Handle a timing request that missed in the cache
     *
     * Common functionality across different cache implementations
     *
     * @param ptk The request packet
     * @param blk The referenced block
     * @param mshr Any existing mshr for the referenced cache block
     * @param forward_time The tick at which we can process dependent requests
     * @param request_time The tick at which the block lookup is compete
     */
    void handleTimingReqMiss(PacketPtr pkt, MSHR *mshr, CacheBlk *blk,
                             Tick forward_time, Tick request_time);

    virtual void recvTimingReq(PacketPtr pkt);

    void handleUncacheableWriteResp(PacketPtr pkt);

    virtual void serviceMSHRTargets(MSHR *mshr, const PacketPtr pkt,
                                    CacheBlk *blk) = 0;

    virtual void recvTimingResp(PacketPtr pkt);

    virtual void recvTimingSnoopReq(PacketPtr pkt) = 0;

    virtual void recvTimingSnoopResp(PacketPtr pkt) = 0;

    virtual Cycles handleAtomicReqMiss(PacketPtr pkt, CacheBlk *&blk,
                                       PacketList &writebacks) = 0;

    virtual Tick recvAtomic(PacketPtr pkt);

    virtual Tick recvAtomicSnoop(PacketPtr pkt) = 0;

    virtual void functionalAccess(PacketPtr pkt, bool from_cpu_side);

    void cmpAndSwap(CacheBlk *blk, PacketPtr pkt);

    QueueEntry* getNextQueueEntry();

    virtual void doWritebacks(PacketList& writebacks, Tick forward_time) = 0;

    virtual void doWritebacksAtomic(PacketList& writebacks) = 0;

    virtual PacketPtr createMissPacket(PacketPtr cpu_pkt, CacheBlk *blk,
                                       bool needs_writable,
                                       bool is_whole_line_write) const = 0;

    const bool writebackClean;

    PacketPtr tempBlockWriteback;

    void writebackTempBlockAtomic() {
        assert(tempBlockWriteback != nullptr);
        PacketList writebacks{tempBlockWriteback};
        doWritebacksAtomic(writebacks);
        tempBlockWriteback = nullptr;
    }

    EventFunctionWrapper writebackTempBlockAtomicEvent;

    bool updateCompressionData(CacheBlk *blk, const uint64_t* data,
                               PacketList &writebacks);

    virtual void satisfyRequest(PacketPtr pkt, CacheBlk *blk,
                                bool deferred_response = false,
                                bool pending_downgrade = false);

    void maintainClusivity(bool from_cache, CacheBlk *blk);

    bool handleEvictions(std::vector<CacheBlk*> &evict_blks,
        PacketList &writebacks);

    CacheBlk *handleFill(PacketPtr pkt, CacheBlk *blk,
                         PacketList &writebacks, bool allocate);

    CacheBlk *allocateBlock(const PacketPtr pkt, PacketList &writebacks);
    M5_NODISCARD virtual PacketPtr evictBlock(CacheBlk *blk) = 0;

    void evictBlock(CacheBlk *blk, PacketList &writebacks);

    void invalidateBlock(CacheBlk *blk);

    PacketPtr writebackBlk(CacheBlk *blk);

    PacketPtr writecleanBlk(CacheBlk *blk, Request::Flags dest, PacketId id);

    virtual void memWriteback() override;

    virtual void memInvalidate() override;

    bool isDirty() const;

    bool inRange(Addr addr) const;

    Tick nextQueueReadyTime() const;

    const unsigned blkSize;

    const Cycles lookupLatency;

    const Cycles dataLatency;

    const Cycles forwardLatency;

    const Cycles fillLatency;

    const Cycles responseLatency;

    const bool sequentialAccess;

    const int numTarget;

    bool forwardSnoops;

    const Enums::Clusivity clusivity;

    const bool isReadOnly;

    uint8_t blocked;

    uint64_t order;

    Cycles blockedCycle;

    MSHR *noTargetMSHR;

    Counter missCount;

    const AddrRangeList addrRanges;

  public:
    System *system;

    struct CacheCmdStats : public Stats::Group
    {
        CacheCmdStats(BaseCache &c, const std::string &name);

        void regStatsFromParent();

        const BaseCache &cache;

        Stats::Vector hits;
        Stats::Vector misses;
        Stats::Vector missLatency;
        Stats::Formula accesses;
        Stats::Formula missRate;
        Stats::Formula avgMissLatency;
        Stats::Vector mshr_hits;
        Stats::Vector mshr_misses;
        Stats::Vector mshr_uncacheable;
        Stats::Vector mshr_miss_latency;
        Stats::Vector mshr_uncacheable_lat;
        Stats::Formula mshrMissRate;
        Stats::Formula avgMshrMissLatency;
        Stats::Formula avgMshrUncacheableLatency;
    };

    struct CacheStats : public Stats::Group
    {
        CacheStats(BaseCache &c);

        void regStats() override;

        CacheCmdStats &cmdStats(const PacketPtr p) {
            return *cmd[p->cmdToIndex()];
        }

        const BaseCache &cache;

        Stats::Formula demandHits;
        Stats::Formula overallHits;

        Stats::Formula demandMisses;
        Stats::Formula overallMisses;

        Stats::Formula demandMissLatency;
        Stats::Formula overallMissLatency;

        Stats::Formula demandAccesses;
        Stats::Formula overallAccesses;

        Stats::Formula demandMissRate;
        Stats::Formula overallMissRate;

        Stats::Formula demandAvgMissLatency;
        Stats::Formula overallAvgMissLatency;

        Stats::Vector blocked_cycles;
        Stats::Vector blocked_causes;

        Stats::Formula avg_blocked;

        Stats::Scalar unusedPrefetches;

        Stats::Vector writebacks;

        Stats::Formula demandMshrHits;
        Stats::Formula overallMshrHits;

        Stats::Formula demandMshrMisses;
        Stats::Formula overallMshrMisses;

        Stats::Formula overallMshrUncacheable;

        Stats::Formula demandMshrMissLatency;
        Stats::Formula overallMshrMissLatency;

        Stats::Formula overallMshrUncacheableLatency;

        Stats::Formula demandMshrMissRate;
        Stats::Formula overallMshrMissRate;

        Stats::Formula demandAvgMshrMissLatency;
        Stats::Formula overallAvgMshrMissLatency;

        Stats::Formula overallAvgMshrUncacheableLatency;

        Stats::Scalar replacements;

        Stats::Scalar dataExpansions;

        std::vector<std::unique_ptr<CacheCmdStats>> cmd;
    } stats;

    void regProbePoints() override;

  public:
    BaseCache(const BaseCacheParams *p, unsigned blk_size);
    ~BaseCache();

    void init() override;

    Port &getPort(const std::string &if_name,
                  PortID idx=InvalidPortID) override;

    unsigned
    getBlockSize() const
    {
        return blkSize;
    }

    const AddrRangeList &getAddrRanges() const { return addrRanges; }

    MSHR *allocateMissBuffer(PacketPtr pkt, Tick time, bool sched_send = true)
    {
        MSHR *mshr = mshrQueue.allocate(pkt->getBlockAddr(blkSize), blkSize,
                                        pkt, time, order++,
                                        allocOnFill(pkt->cmd));

        if (mshrQueue.isFull()) {
            setBlocked((BlockedCause)MSHRQueue_MSHRs);
        }

        if (sched_send) {
            // schedule the send
            schedMemSideSendEvent(time);
        }

        return mshr;
    }

    void allocateWriteBuffer(PacketPtr pkt, Tick time)
    {
        // should only see writes or clean evicts here
        assert(pkt->isWrite() || pkt->cmd == MemCmd::CleanEvict);

        Addr blk_addr = pkt->getBlockAddr(blkSize);

        // If using compression, on evictions the block is decompressed and
        // the operation's latency is added to the payload delay. Consume
        // that payload delay here, meaning that the data is always stored
        // uncompressed in the writebuffer
        if (compressor) {
            time += pkt->payloadDelay;
            pkt->payloadDelay = 0;
        }

        WriteQueueEntry *wq_entry =
            writeBuffer.findMatch(blk_addr, pkt->isSecure());
        if (wq_entry && !wq_entry->inService) {
            DPRINTF(Cache, "Potential to merge writeback %s", pkt->print());
        }

        writeBuffer.allocate(blk_addr, blkSize, pkt, time, order++);

        if (writeBuffer.isFull()) {
            setBlocked((BlockedCause)MSHRQueue_WriteBuffer);
        }

        // schedule the send
        schedMemSideSendEvent(time);
    }

    bool isBlocked() const
    {
        return blocked != 0;
    }

    void setBlocked(BlockedCause cause)
    {
        uint8_t flag = 1 << cause;
        if (blocked == 0) {
            stats.blocked_causes[cause]++;
            blockedCycle = curCycle();
            cpuSidePort.setBlocked();
        }
        blocked |= flag;
        DPRINTF(Cache,"Blocking for cause %d, mask=%d\n", cause, blocked);
    }

    void clearBlocked(BlockedCause cause)
    {
        uint8_t flag = 1 << cause;
        blocked &= ~flag;
        DPRINTF(Cache,"Unblocking for cause %d, mask=%d\n", cause, blocked);
        if (blocked == 0) {
            stats.blocked_cycles[cause] += curCycle() - blockedCycle;
            cpuSidePort.clearBlocked();
        }
    }

    void schedMemSideSendEvent(Tick time)
    {
        memSidePort.schedSendEvent(time);
    }

    bool inCache(Addr addr, bool is_secure) const {
        return tags->findBlock(addr, is_secure);
    }

    bool hasBeenPrefetched(Addr addr, bool is_secure) const {
        CacheBlk *block = tags->findBlock(addr, is_secure);
        if (block) {
            return block->wasPrefetched();
        } else {
            return false;
        }
    }

    bool inMissQueue(Addr addr, bool is_secure) const {
        return mshrQueue.findMatch(addr, is_secure);
    }

    void incMissCount(PacketPtr pkt)
    {
        assert(pkt->req->masterId() < system->maxMasters());
        stats.cmdStats(pkt).misses[pkt->req->masterId()]++;
        pkt->req->incAccessDepth();
        if (missCount) {
            --missCount;
            if (missCount == 0)
                exitSimLoop("A cache reached the maximum miss count");
        }
    }
    void incHitCount(PacketPtr pkt)
    {
        assert(pkt->req->masterId() < system->maxMasters());
        stats.cmdStats(pkt).hits[pkt->req->masterId()]++;
    }

    bool coalesce() const;


    void writebackVisitor(CacheBlk &blk);

    void invalidateVisitor(CacheBlk &blk);

    virtual bool sendMSHRQueuePacket(MSHR* mshr);

    bool sendWriteQueuePacket(WriteQueueEntry* wq_entry);

    void serialize(CheckpointOut &cp) const override;
    void unserialize(CheckpointIn &cp) override;
};

class WriteAllocator : public SimObject {
  public:
    WriteAllocator(const WriteAllocatorParams *p) :
        SimObject(p),
        coalesceLimit(p->coalesce_limit * p->block_size),
        noAllocateLimit(p->no_allocate_limit * p->block_size),
        delayThreshold(p->delay_threshold)
    {
        reset();
    }

    bool coalesce() const {
        return mode != WriteMode::ALLOCATE;
    }

    bool allocate() const {
        return mode != WriteMode::NO_ALLOCATE;
    }

    void reset() {
        mode = WriteMode::ALLOCATE;
        byteCount = 0;
        nextAddr = 0;
    }

    bool delay(Addr blk_addr) {
        if (delayCtr[blk_addr] > 0) {
            --delayCtr[blk_addr];
            return true;
        } else {
            return false;
        }
    }

    void resetDelay(Addr blk_addr) {
        delayCtr.erase(blk_addr);
    }

    void updateMode(Addr write_addr, unsigned write_size, Addr blk_addr);

  private:
    enum class WriteMode : char {
        ALLOCATE,
        COALESCE,
        NO_ALLOCATE,
    };
    WriteMode mode;

    Addr nextAddr;

    uint32_t byteCount;

    const uint32_t coalesceLimit;
    const uint32_t noAllocateLimit;
    const uint32_t delayThreshold;

    std::unordered_map<Addr, Counter> delayCtr;
};

#endif //__MEM_CACHE_BASE_HH__