41 #include "debug/Decode.hh" 48 MinorCPUParams ¶ms,
56 nextStageReserve(next_stage_input_buffer),
57 outputWidth(params.executeInputWidth),
58 processMoreThanOneInput(params.decodeCycleInput),
59 decodeInfo(params.numThreads),
65 if (params.decodeInputBufferSize < 1) {
66 fatal(
"%s: decodeInputBufferSize must be >= 1 (%d)\n", name,
67 params.decodeInputBufferSize);
71 for (
ThreadID tid = 0; tid < params.numThreads; tid++) {
75 params.decodeInputBufferSize));
112 inst->staticInst, inst->pc, static_inst);
117 inst->traceData->setFetchSeq(inst->id.execSeqNum);
125 if (!
inp.outputWire->isBubble())
141 unsigned int output_index = 0;
151 if (inst->isBubble()) {
161 if (inst->isFault()) {
163 inst->fault->name());
185 output_inst->staticInst = static_micro_inst;
191 output_inst->predictedTaken = inst->predictedTaken;
192 output_inst->predictedTarget = inst->predictedTarget;
196 " %d output_index: %d lastMicroop: %s microopPC:" 207 parent_static_inst = static_inst;
219 " %d output_index: %d\n",
220 *output_inst, decode_info.
inputIndex, output_index);
222 parent_static_inst = static_inst;
230 output_inst->id.execSeqNum = decode_info.
execSeqNum;
233 dynInstAddTracing(output_inst, parent_static_inst, cpu);
242 insts_out.
insts[output_index] = output_inst;
290 if (!
inp.outputWire->isBubble())
301 case Enums::SingleThreaded:
302 priority_list.push_back(0);
304 case Enums::RoundRobin:
311 panic(
"Unknown fetch policy");
314 for (
auto tid : priority_list) {
332 return (*
inp.outputWire).isBubble();
338 std::ostringstream
data;
343 (*
out.inputWire).reportData(data);
#define panic(...)
This implements a cprintf based panic() function.
Data members after this line are cycle-to-cycle state.
decltype(nullptr) constexpr NoFault
Decode(const std::string &name, MinorCPU &cpu_, MinorCPUParams ¶ms, Latch< ForwardInstData >::Output inp_, Latch< ForwardInstData >::Input out_, std::vector< InputBuffer< ForwardInstData >> &next_stage_input_buffer)
std::vector< InputBuffer< ForwardInstData > > & nextStageReserve
Interface to reserve space in the next stage.
Latch< ForwardInstData >::Input out
Output port carrying micro-op decomposed instructions to Execute.
#define fatal(...)
This implements a cprintf based fatal() function.
const std::string & name()
Trace::InstTracer * getTracer()
Provide access to the tracer pointer.
ThreadID numThreads
Number of threads we're actually simulating (<= SMT_MAX_THREADS).
virtual InstRecord * getInstRecord(Tick when, ThreadContext *tc, const StaticInstPtr staticInst, TheISA::PCState pc, const StaticInstPtr macroStaticInst=NULL)=0
unsigned int inputIndex
Index into the inputBuffer's head marking the start of unhandled instructions.
unsigned int width() const
Number of instructions carried by this object.
void activity()
Records that there is activity this cycle.
TheISA::PCState microopPC
Minor contains all the definitions within the MinorCPU apart from the CPU class itself.
std::vector< InputBuffer< ForwardInstData > > inputBuffer
MinorCPU & cpu
Pointer back to the containing CPU.
bool isDrained()
Is this stage drained? For Decoed, draining is initiated by Execute halting Fetch1 causing Fetch2 to ...
std::vector< DecodeThreadInfo > decodeInfo
Decode collects macro-ops from Fetch2 and splits them into micro-ops passed to Execute.
InstSeqNum execSeqNum
Source of execSeqNums to number instructions.
Latch< ForwardInstData >::Output inp
Input port carrying macro instructions from Fetch2.
Tick curTick()
The current simulated tick.
ThreadID getScheduledThread()
Use the current threading policy to determine the next thread to decode from.
virtual StaticInstPtr fetchMicroop(MicroPC upc) const
Return the microop that goes with a particular micropc.
void activateStage(const int idx)
Marks a stage as active.
std::vector< ThreadID > randomPriority()
void resize(unsigned int width)
Resize a bubble/empty ForwardInstData and fill with bubbles.
bool isBubble() const
BubbleIF interface.
MinorDynInstPtr insts[MAX_FORWARD_INSTS]
Array of carried insts, ref counted.
Minor::MinorActivityRecorder * activityRecorder
Activity recording for pipeline.
bool processMoreThanOneInput
If true, more than one input word can be processed each cycle if there is room in the output to conta...
std::vector< ThreadID > roundRobinPriority(ThreadID priority)
Thread scheduling utility functions.
const ThreadID InvalidThreadID
int16_t ThreadID
Thread index/ID type.
Dynamic instruction for Minor.
void evaluate()
Pass on input/buffer data to the output if you can.
Enums::ThreadPolicy threadPolicy
Thread Scheduling Policy (RoundRobin, Random, etc)
virtual void advancePC(TheISA::PCState &pcState) const =0
virtual ThreadContext * getContext(int tn)
Given a thread num get tho thread context for it.
#define MINORTRACE(...)
DPRINTFN for MinorTrace reporting.
The constructed pipeline.
const ForwardInstData * getInput(ThreadID tid)
Get a piece of data to work on, or 0 if there is no data.
MinorCPU is an in-order CPU model with four fixed pipeline stages:
bool inMacroop
True when we're in the process of decomposing a micro-op and microopPC will be valid.
Forward flowing data between Fetch2,Decode,Execute carrying a packet of instructions of a width appro...
const std::string to_string(sc_enc enc)
void popInput(ThreadID tid)
Pop an element off the input buffer, if there are any.
bool isLastMicroop() const
unsigned int outputWidth
Width of output of this stage/input of next in instructions.
ThreadID threadId
Thread associated with these instructions.