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arch
power
pagetable.hh
Go to the documentation of this file.
1
/*
2
* Copyright (c) 2002-2005 The Regents of The University of Michigan
3
* Copyright (c) 2007 MIPS Technologies, Inc.
4
* Copyright (c) 2007-2008 The Florida State University
5
* Copyright (c) 2009 The University of Edinburgh
6
* All rights reserved.
7
*
8
* Redistribution and use in source and binary forms, with or without
9
* modification, are permitted provided that the following conditions are
10
* met: redistributions of source code must retain the above copyright
11
* notice, this list of conditions and the following disclaimer;
12
* redistributions in binary form must reproduce the above copyright
13
* notice, this list of conditions and the following disclaimer in the
14
* documentation and/or other materials provided with the distribution;
15
* neither the name of the copyright holders nor the names of its
16
* contributors may be used to endorse or promote products derived from
17
* this software without specific prior written permission.
18
*
19
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
20
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
21
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
22
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
23
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
24
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
25
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
26
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
27
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
28
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
29
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30
*/
31
32
#ifndef __ARCH_POWER_PAGETABLE_H__
33
#define __ARCH_POWER_PAGETABLE_H__
34
35
#include "
arch/power/isa_traits.hh
"
36
#include "
arch/power/utility.hh
"
37
38
namespace
PowerISA
39
{
40
41
static
inline
Addr
PteAddr
(
Addr
a
) {
return
(a &
PteMask
) <<
PteShift
; }
42
43
struct
VAddr
44
{
45
static
const
int
ImplBits
= 43;
46
static
const
Addr
ImplMask
= (
ULL
(1) <<
ImplBits
) - 1;
47
static
const
Addr
UnImplMask
= ~ImplMask;
48
49
Addr
addr
;
50
51
VAddr
(
Addr
a
)
52
: addr(a)
53
{}
54
55
operator
Addr
()
const
56
{
57
return
addr
;
58
}
59
60
const
VAddr
61
&
operator=
(
Addr
a
)
62
{
63
addr =
a
;
64
return
*
this
;
65
}
66
67
Addr
68
vpn
()
const
69
{
70
return
(addr & ImplMask) >>
PageShift
;
71
}
72
73
Addr
74
page
()
const
75
{
76
return
addr &
Page_Mask
;
77
}
78
79
Addr
80
offset
()
const
81
{
82
return
addr &
PageOffset
;
83
}
84
85
Addr
86
level3
()
const
87
{
88
return
PowerISA::PteAddr
(addr >>
PageShift
);
89
}
90
91
Addr
92
level2
()
const
93
{
94
return
PowerISA::PteAddr
(addr >> (
NPtePageShift
+
PageShift
));
95
}
96
97
Addr
98
level1
()
const
99
{
100
return
PowerISA::PteAddr
(addr >> (2 *
NPtePageShift
+
PageShift
));
101
}
102
};
103
104
// ITB/DTB page table entry
105
struct
PTE
106
{
107
// What parts of the VAddr (from bits 28..11) should be used in
108
// translation (includes Mask and MaskX from PageMask)
109
Addr
Mask
;
110
111
// Virtual Page Number (/2) (Includes VPN2 + VPN2X .. bits 31..11
112
// from EntryHi)
113
Addr
VPN
;
114
115
// Address Space ID (8 bits) // Lower 8 bits of EntryHi
116
uint8_t
asid
;
117
118
// Global Bit - Obtained by an *AND* of EntryLo0 and EntryLo1 G bit
119
bool
G
;
120
121
/* Contents of Entry Lo0 */
122
Addr
PFN0
;
// Physical Frame Number - Even
123
bool
D0
;
// Even entry Dirty Bit
124
bool
V0
;
// Even entry Valid Bit
125
uint8_t
C0
;
// Cache Coherency Bits - Even
126
127
/* Contents of Entry Lo1 */
128
Addr
PFN1
;
// Physical Frame Number - Odd
129
bool
D1
;
// Odd entry Dirty Bit
130
bool
V1
;
// Odd entry Valid Bit
131
uint8_t
C1
;
// Cache Coherency Bits (3 bits)
132
133
// The next few variables are put in as optimizations to reduce TLB
134
// lookup overheads. For a given Mask, what is the address shift amount
135
// and what is the OffsetMask
136
int
AddrShiftAmount
;
137
int
OffsetMask
;
138
139
bool
140
Valid
()
141
{
142
return
(V0 | V1);
143
};
144
145
void
serialize
(
CheckpointOut
&
cp
)
const
;
146
void
unserialize
(
CheckpointIn
&cp);
147
};
148
149
}
// namespace PowerISA
150
151
#endif // __ARCH_POWER_PAGETABLE_H__
152
PowerISA::PteMask
const Addr PteMask
Definition:
isa_traits.hh:53
PowerISA::PTE::C0
uint8_t C0
Definition:
pagetable.hh:125
PowerISA::PteAddr
static Addr PteAddr(Addr a)
Definition:
pagetable.hh:41
PowerISA::PTE::V0
bool V0
Definition:
pagetable.hh:124
PowerISA::VAddr::level2
Addr level2() const
Definition:
pagetable.hh:92
PowerISA::VAddr::operator=
const VAddr & operator=(Addr a)
Definition:
pagetable.hh:61
PowerISA::VAddr::addr
Addr addr
Definition:
pagetable.hh:49
isa_traits.hh
PowerISA::VAddr::VAddr
VAddr(Addr a)
Definition:
pagetable.hh:51
cp
Definition:
cprintf.cc:40
PowerISA::PTE::D1
bool D1
Definition:
pagetable.hh:129
utility.hh
PowerISA::PTE::asid
uint8_t asid
Definition:
pagetable.hh:116
PowerISA::VAddr::level3
Addr level3() const
Definition:
pagetable.hh:86
PowerISA::PTE::Valid
bool Valid()
Definition:
pagetable.hh:140
PowerISA::PTE::PFN1
Addr PFN1
Definition:
pagetable.hh:128
PowerISA
Definition:
decoder.cc:31
serialize
void serialize(const ThreadContext &tc, CheckpointOut &cp)
Thread context serialization helpers.
Definition:
thread_context.cc:158
PowerISA::PageOffset
const Addr PageOffset
Definition:
isa_traits.hh:48
PowerISA::VAddr::offset
Addr offset() const
Definition:
pagetable.hh:80
PowerISA::VAddr::ImplMask
static const Addr ImplMask
Definition:
pagetable.hh:46
PowerISA::PTE::VPN
Addr VPN
Definition:
pagetable.hh:113
PowerISA::VAddr::page
Addr page() const
Definition:
pagetable.hh:74
Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition:
types.hh:140
ULL
#define ULL(N)
uint64_t constant
Definition:
types.hh:48
CheckpointIn
Definition:
serialize.hh:67
X86ISA::a
Bitfield< 5 > a
Definition:
pagetable.hh:146
PowerISA::VAddr
Definition:
pagetable.hh:43
PowerISA::NPtePageShift
const Addr NPtePageShift
Definition:
isa_traits.hh:51
PowerISA::VAddr::vpn
Addr vpn() const
Definition:
pagetable.hh:68
PowerISA::PTE::C1
uint8_t C1
Definition:
pagetable.hh:131
PowerISA::Page_Mask
const Addr Page_Mask
Definition:
isa_traits.hh:47
CheckpointOut
std::ostream CheckpointOut
Definition:
serialize.hh:63
PowerISA::PTE::PFN0
Addr PFN0
Definition:
pagetable.hh:122
PowerISA::PTE::AddrShiftAmount
int AddrShiftAmount
Definition:
pagetable.hh:136
PowerISA::PTE::OffsetMask
int OffsetMask
Definition:
pagetable.hh:137
PowerISA::PTE::D0
bool D0
Definition:
pagetable.hh:123
PowerISA::VAddr::ImplBits
static const int ImplBits
Definition:
pagetable.hh:45
PowerISA::PTE::G
bool G
Definition:
pagetable.hh:119
unserialize
void unserialize(ThreadContext &tc, CheckpointIn &cp)
Definition:
thread_context.cc:199
PowerISA::PageShift
const Addr PageShift
Definition:
isa_traits.hh:45
PowerISA::VAddr::UnImplMask
static const Addr UnImplMask
Definition:
pagetable.hh:47
PowerISA::VAddr::level1
Addr level1() const
Definition:
pagetable.hh:98
PowerISA::PTE::Mask
Addr Mask
Definition:
pagetable.hh:109
PowerISA::PteShift
const Addr PteShift
Definition:
isa_traits.hh:50
PowerISA::PTE::V1
bool V1
Definition:
pagetable.hh:130
PowerISA::PTE
Definition:
pagetable.hh:105
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