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pagetable.hh
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28 
29 #ifndef __ARCH_SPARC_PAGETABLE_HH__
30 #define __ARCH_SPARC_PAGETABLE_HH__
31 
32 #include <cassert>
33 
34 #include "arch/sparc/isa_traits.hh"
35 #include "base/bitfield.hh"
36 #include "base/logging.hh"
37 
38 class Checkpoint;
39 
40 namespace SparcISA {
41 
42 struct VAddr
43 {
44  VAddr(Addr a) { panic("not implemented yet."); }
45 };
46 
47 class TteTag
48 {
49  private:
50  uint64_t entry;
51  bool populated;
52 
53  public:
54  TteTag() : entry(0), populated(false) {}
55  TteTag(uint64_t e) : entry(e), populated(true) {}
56 
57  const TteTag &
58  operator=(uint64_t e)
59  {
60  populated = true;
61  entry = e;
62  return *this;
63  }
64 
65  bool valid() const { assert(populated); return !bits(entry,62,62); }
66  Addr va() const { assert(populated); return bits(entry,41,0); }
67 };
68 
69 
71 {
72  public:
73  enum EntryType {
76  invalid
77  };
78 
79  private:
80  uint64_t entry;
82  uint64_t entry4u;
83  bool populated;
84 
85  public:
86  PageTableEntry() : entry(0), type(invalid), populated(false)
87  {}
88 
89  PageTableEntry(uint64_t e, EntryType t = sun4u)
90  : entry(e), type(t), populated(true)
91  {
92  populate(entry, type);
93  }
94 
95  void
96  populate(uint64_t e, EntryType t = sun4u)
97  {
98  entry = e;
99  type = t;
100  populated = true;
101 
102  // If we get a sun4v format TTE, turn it into a sun4u
103  if (type == sun4u)
104  entry4u = entry;
105  else {
106  entry4u = 0;
107  entry4u |= mbits(entry,63,63); // valid
108  entry4u |= bits(entry,1,0) << 61; // size[1:0]
109  entry4u |= bits(entry,62,62) << 60; // nfo
110  entry4u |= bits(entry,12,12) << 59; // ie
111  entry4u |= bits(entry,2,2) << 48; // size[2]
112  entry4u |= mbits(entry,39,13); // paddr
113  entry4u |= bits(entry,61,61) << 6;; // locked
114  entry4u |= bits(entry,10,10) << 5; // cp
115  entry4u |= bits(entry,9,9) << 4; // cv
116  entry4u |= bits(entry,11,11) << 3; // e
117  entry4u |= bits(entry,8,8) << 2; // p
118  entry4u |= bits(entry,6,6) << 1; // w
119  }
120  }
121 
122  void
124  {
125  populated = false;
126  }
127 
128  static int pageSizes[6];
129 
130  uint64_t operator()() const { assert(populated); return entry4u; }
131 
132  const PageTableEntry &
133  operator=(uint64_t e)
134  {
135  populated = true;
136  entry4u = e;
137  return *this;
138  }
139 
140  const PageTableEntry &
142  {
143  populated = true;
144  entry4u = e.entry4u;
145  type = e.type;
146  return *this;
147  }
148 
149  bool valid() const { return bits(entry4u,63,63) && populated; }
150 
151  uint8_t
152  _size() const
153  {
154  assert(populated);
155  return bits(entry4u, 62,61) | bits(entry4u, 48,48) << 2;
156  }
157 
158  Addr size() const { assert(_size() < 6); return pageSizes[_size()]; }
159  Addr sizeMask() const { return size() - 1; }
160  bool ie() const { return bits(entry4u, 59,59); }
161  Addr pfn() const { assert(populated); return bits(entry4u,39,13); }
162  Addr paddr() const { assert(populated); return mbits(entry4u, 39,13);}
163  bool locked() const { assert(populated); return bits(entry4u,6,6); }
164  bool cv() const { assert(populated); return bits(entry4u,4,4); }
165  bool cp() const { assert(populated); return bits(entry4u,5,5); }
166  bool priv() const { assert(populated); return bits(entry4u,2,2); }
167  bool writable() const { assert(populated); return bits(entry4u,1,1); }
168  bool nofault() const { assert(populated); return bits(entry4u,60,60); }
169  bool sideffect() const { assert(populated); return bits(entry4u,3,3); }
170  Addr paddrMask() const { assert(populated); return paddr() & ~sizeMask(); }
171 
172  Addr
174  {
175  assert(populated);
176  Addr mask = sizeMask();
177  return (paddr() & ~mask) | (vaddr & mask);
178  }
179 };
180 
181 struct TlbRange
182 {
187  bool real;
188 
189  inline bool
190  operator<(const TlbRange &r2) const
191  {
192  if (real && !r2.real)
193  return true;
194  if (!real && r2.real)
195  return false;
196 
197  if (!real && !r2.real) {
198  if (contextId < r2.contextId)
199  return true;
200  else if (contextId > r2.contextId)
201  return false;
202  }
203 
204  if (partitionId < r2.partitionId)
205  return true;
206  else if (partitionId > r2.partitionId)
207  return false;
208 
209  if (va < r2.va)
210  return true;
211  return false;
212  }
213 
214  inline bool
215  operator==(const TlbRange &r2) const
216  {
217  return va == r2.va &&
218  size == r2.size &&
219  contextId == r2.contextId &&
220  partitionId == r2.partitionId &&
221  real == r2.real;
222  }
223 };
224 
225 
226 struct TlbEntry
227 {
229  {}
230 
231  TlbEntry(Addr asn, Addr vaddr, Addr paddr,
232  bool uncacheable, bool read_only)
233  {
234  uint64_t entry = 0;
235  if (!read_only)
236  entry |= 1ULL << 1; // Writable
237  entry |= 0ULL << 2; // Available in nonpriveleged mode
238  entry |= 0ULL << 3; // No side effects
239  if (!uncacheable) {
240  entry |= 1ULL << 4; // Virtually cachable
241  entry |= 1ULL << 5; // Physically cachable
242  }
243  entry |= 0ULL << 6; // Not locked
244  entry |= mbits(paddr, 39, 13); // Physical address
245  entry |= 0ULL << 48; // size = 8k
246  entry |= 0uLL << 59; // Endianness not inverted
247  entry |= 0ULL << 60; // Not no fault only
248  entry |= 0ULL << 61; // size = 8k
249  entry |= 1ULL << 63; // valid
250  pte = PageTableEntry(entry);
251 
252  range.va = vaddr;
253  range.size = 8*(1<<10);
254  range.contextId = asn;
255  range.partitionId = 0;
256  range.real = false;
257 
258  valid = true;
259  }
260 
263  bool used;
264  bool valid;
265 
266  Addr
268  {
269  return pte.paddr();
270  }
271 
272  void
273  updateVaddr(Addr new_vaddr)
274  {
275  range.va = new_vaddr;
276  }
277 
278  void serialize(CheckpointOut &cp) const;
279  void unserialize(CheckpointIn &cp);
280 };
281 
282 } // namespace SparcISA
283 
284 #endif // __ARCH_SPARC_PAGE_TABLE_HH__
285 
Addr translate(Addr vaddr) const
Definition: pagetable.hh:173
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:163
bool operator==(const TlbRange &r2) const
Definition: pagetable.hh:215
uint64_t entry
Definition: pagetable.hh:50
Addr paddrMask() const
Definition: pagetable.hh:170
Definition: cprintf.cc:40
void updateVaddr(Addr new_vaddr)
Definition: pagetable.hh:273
void populate(uint64_t e, EntryType t=sun4u)
Definition: pagetable.hh:96
Addr va() const
Definition: pagetable.hh:66
bool valid() const
Definition: pagetable.hh:65
const PageTableEntry & operator=(const PageTableEntry &e)
Definition: pagetable.hh:141
uint64_t operator()() const
Definition: pagetable.hh:130
void serialize(const ThreadContext &tc, CheckpointOut &cp)
Thread context serialization helpers.
uint8_t _size() const
Definition: pagetable.hh:152
const PageTableEntry & operator=(uint64_t e)
Definition: pagetable.hh:133
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:140
#define ULL(N)
uint64_t constant
Definition: types.hh:48
Bitfield< 5 > a
Definition: pagetable.hh:146
VAddr(Addr a)
Definition: pagetable.hh:44
Bitfield< 9 > e
bool sideffect() const
Definition: pagetable.hh:169
std::ostream CheckpointOut
Definition: serialize.hh:63
Definition: asi.cc:31
TlbEntry(Addr asn, Addr vaddr, Addr paddr, bool uncacheable, bool read_only)
Definition: pagetable.hh:231
PageTableEntry(uint64_t e, EntryType t=sun4u)
Definition: pagetable.hh:89
void unserialize(ThreadContext &tc, CheckpointIn &cp)
Bitfield< 3, 0 > mask
Definition: types.hh:62
TteTag(uint64_t e)
Definition: pagetable.hh:55
PageTableEntry pte
Definition: pagetable.hh:262
Bitfield< 5 > t
const TteTag & operator=(uint64_t e)
Definition: pagetable.hh:58
T mbits(T val, int first, int last)
Mask off the given bits in place like bits() but without shifting.
Definition: bitfield.hh:95
T bits(T val, int first, int last)
Extract the bitfield from position &#39;first&#39; to &#39;last&#39; (inclusive) from &#39;val&#39; and right justify it...
Definition: bitfield.hh:71
bool operator<(const Time &l, const Time &r)
Definition: time.hh:216

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