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tb.h
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3  Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
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20 /*****************************************************************************
21 
22  tb.h --
23 
24  Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
25 
26  *****************************************************************************/
27 
28 /*****************************************************************************
29 
30  MODIFICATION LOG - modifiers, enter your name, affiliation, date and
31  changes you are making here.
32 
33  Name, Affiliation, Date:
34  Description of Modification:
35 
36  *****************************************************************************/
37 
38 /******************************************************************************/
39 /*************************** Testbench Function **********************/
40 /******************************************************************************/
41 /* */
42 /* The testbench module has the following hierarchy: */
43 /* */
44 /* testbench */
45 /* - RESET_STIM */
46 /* - DATA_GEN */
47 /* */
48 /******************************************************************************/
49 
50 struct testbench : public sc_module {
51  sc_signal<int> addr; // Address of input memory
52  sc_signal<bool> reset;
53  sc_signal<bool> ready;
54  signal_bool_vector8 data;
55  signal_bool_vector4 sum;
56  RESET_STIM rd1;
57  DATA_GEN dg1;
58  ADD_CHAIN ac1;
59  DISPLAY d1;
60 
61  /*** Constructor ***/
62  testbench ( const sc_module_name& NAME,
63  sc_clock& TICK )
64 
65  : sc_module(),
66  rd1 ("RD1", TICK, ready, reset, addr),
67  dg1 ("DG1", TICK, ready, data, addr),
68  ac1 ("AC1", TICK, reset, data, sum, ready),
69  d1 ("D1", ready, data, sum)
70 
71  {
72  end_module();
73  }
74 };
testbench
Definition: tb.h:50
testbench::addr
sc_signal< int > addr
Definition: tb.h:51
testbench::testbench
testbench(const sc_module_name &NAME, sc_clock &TICK)
Definition: tb.h:62
testbench::sum
signal_bool_vector4 sum
Definition: tb.h:55
signal_bool_vector4
sc_signal< bool_vector4 > signal_bool_vector4
Definition: common.h:46
testbench::dg1
DATA_GEN dg1
Definition: tb.h:57
signal_bool_vector8
sc_signal< sc_bv< 8 > > signal_bool_vector8
Definition: common.h:43
testbench::reset
sc_signal< bool > reset
Definition: tb.h:52
testbench::rd1
RESET_STIM rd1
Definition: tb.h:56
testbench::ac1
ADD_CHAIN ac1
Definition: tb.h:58
testbench::data
signal_bool_vector8 data
Definition: tb.h:54
testbench::ready
sc_signal< bool > ready
Definition: tb.h:53
testbench::d1
DISPLAY d1
Definition: tb.h:59
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