gem5
v20.1.0.0
systemc
tests
systemc
misc
synth
add_chain
add_chain.h
Go to the documentation of this file.
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/*****************************************************************************
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Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
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more contributor license agreements. See the NOTICE file distributed
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with this work for additional information regarding copyright ownership.
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Accellera licenses this file to you under the Apache License, Version 2.0
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(the "License"); you may not use this file except in compliance with the
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License. You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
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implied. See the License for the specific language governing
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permissions and limitations under the License.
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*****************************************************************************/
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/*****************************************************************************
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add_chain.h --
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Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
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*****************************************************************************/
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/*****************************************************************************
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MODIFICATION LOG - modifiers, enter your name, affiliation, date and
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changes you are making here.
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Name, Affiliation, Date:
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Description of Modification:
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*****************************************************************************/
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#include "
common.h
"
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/******************************************************************************/
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/*************************** add_chain Class Definition ********************/
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/******************************************************************************/
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SC_MODULE
( ADD_CHAIN )
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{
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SC_HAS_PROCESS
( ADD_CHAIN );
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sc_in_clk
clk;
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const
sc_signal<bool>& rst;
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const
signal_bool_vector8
& a_in;
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signal_bool_vector4
& sum_out;
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sc_signal<bool>& ready;
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ADD_CHAIN( sc_module_name NAME,
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sc_clock& TICK_P,
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const
sc_signal<bool>& RST,
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const
signal_bool_vector8
& A_IN,
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signal_bool_vector4
& SUM_OUT,
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sc_signal<bool>& READY
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)
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:
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rst (RST),
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a_in (A_IN),
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sum_out (SUM_OUT),
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ready (READY)
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{
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clk(TICK_P);
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SC_CTHREAD
( entry, clk.pos() );
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reset_signal_is(rst,
false
);
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}
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void
entry();
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};
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/******************************************************************************/
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/*************************** add_chain Entry Function **********************/
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/******************************************************************************/
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/******************************************************************************/
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void
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ADD_CHAIN::entry()
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{
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bool_vector4
sum
;
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bool_vector8
a
;
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/***** Reset Initialization *****/
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sum_out.write(0);
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ready.write(1);
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wait
();
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/***** MAIN LOOP *****/
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while
(
true
) {
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/***** Handshake *****/
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ready.write(0);
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wait
();
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/***** Computation *****/
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sum
= 0;
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a
= a_in.read();
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for
(
int
i
=0;
i
<=7;
i
=
i
+1) {
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sum
=
sum
.to_uint() +
a
[
i
].to_bool();
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}
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sum_out.write(
sum
);
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/***** Handshake *****/
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ready.write(1);
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wait
();
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}
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}
RiscvISA::sum
Bitfield< 18 > sum
Definition:
registers.hh:609
ArmISA::i
Bitfield< 7 > i
Definition:
miscregs_types.hh:63
signal_bool_vector4
sc_signal< bool_vector4 > signal_bool_vector4
Definition:
common.h:46
SC_MODULE
SC_MODULE(ADD_CHAIN)
Definition:
add_chain.h:44
ArmISA::a
Bitfield< 8 > a
Definition:
miscregs_types.hh:62
sc_core::sc_in_clk
sc_in< bool > sc_in_clk
Definition:
sc_clock.hh:116
sc_core::wait
void wait()
Definition:
sc_module.cc:653
bool_vector4
sc_bv< 4 > bool_vector4
Definition:
common.h:44
SC_HAS_PROCESS
#define SC_HAS_PROCESS(name)
Definition:
sc_module.hh:297
bool_vector8
sc_bv< 8 > bool_vector8
Definition:
common.h:45
common.h
SC_CTHREAD
#define SC_CTHREAD(name, clk)
Definition:
sc_module.hh:319
signal_bool_vector8
sc_signal< sc_bv< 8 > > signal_bool_vector8
Definition:
common.h:43
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