gem5  v20.1.0.0
add_chain.h
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3  Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
4  more contributor license agreements. See the NOTICE file distributed
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6  Accellera licenses this file to you under the Apache License, Version 2.0
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18  *****************************************************************************/
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20 /*****************************************************************************
21 
22  add_chain.h --
23 
24  Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
25 
26  *****************************************************************************/
27 
28 /*****************************************************************************
29 
30  MODIFICATION LOG - modifiers, enter your name, affiliation, date and
31  changes you are making here.
32 
33  Name, Affiliation, Date:
34  Description of Modification:
35 
36  *****************************************************************************/
37 
38 #include "common.h"
39 
40 /******************************************************************************/
41 /*************************** add_chain Class Definition ********************/
42 /******************************************************************************/
43 
44 SC_MODULE( ADD_CHAIN )
45 {
46  SC_HAS_PROCESS( ADD_CHAIN );
47 
48  sc_in_clk clk;
49 
50  const sc_signal<bool>& rst;
51  const signal_bool_vector8& a_in;
52  signal_bool_vector4& sum_out;
53  sc_signal<bool>& ready;
54 
55  ADD_CHAIN( sc_module_name NAME,
56  sc_clock& TICK_P,
57 
58  const sc_signal<bool>& RST,
59  const signal_bool_vector8& A_IN,
60  signal_bool_vector4& SUM_OUT,
61  sc_signal<bool>& READY
62  )
63  :
64  rst (RST),
65  a_in (A_IN),
66  sum_out (SUM_OUT),
67  ready (READY)
68  {
69  clk(TICK_P);
70  SC_CTHREAD( entry, clk.pos() );
71  reset_signal_is(rst, false);
72  }
73  void entry();
74 };
75 
76 /******************************************************************************/
77 /*************************** add_chain Entry Function **********************/
78 /******************************************************************************/
82 /******************************************************************************/
83 void
84 ADD_CHAIN::entry()
85 {
87  bool_vector8 a;
88 
89  /***** Reset Initialization *****/
90  sum_out.write(0);
91  ready.write(1);
92  wait();
93 
94  /***** MAIN LOOP *****/
95  while(true) {
96 
97  /***** Handshake *****/
98  ready.write(0);
99  wait();
100 
101  /***** Computation *****/
102  sum = 0;
103  a = a_in.read();
104 
105  for (int i=0; i<=7; i=i+1) {
106  sum = sum.to_uint() + a[i].to_bool();
107  }
108 
109  sum_out.write(sum);
110 
111  /***** Handshake *****/
112  ready.write(1);
113  wait();
114  }
115 }
RiscvISA::sum
Bitfield< 18 > sum
Definition: registers.hh:609
ArmISA::i
Bitfield< 7 > i
Definition: miscregs_types.hh:63
signal_bool_vector4
sc_signal< bool_vector4 > signal_bool_vector4
Definition: common.h:46
SC_MODULE
SC_MODULE(ADD_CHAIN)
Definition: add_chain.h:44
ArmISA::a
Bitfield< 8 > a
Definition: miscregs_types.hh:62
sc_core::sc_in_clk
sc_in< bool > sc_in_clk
Definition: sc_clock.hh:116
sc_core::wait
void wait()
Definition: sc_module.cc:653
bool_vector4
sc_bv< 4 > bool_vector4
Definition: common.h:44
SC_HAS_PROCESS
#define SC_HAS_PROCESS(name)
Definition: sc_module.hh:297
bool_vector8
sc_bv< 8 > bool_vector8
Definition: common.h:45
common.h
SC_CTHREAD
#define SC_CTHREAD(name, clk)
Definition: sc_module.hh:319
signal_bool_vector8
sc_signal< sc_bv< 8 > > signal_bool_vector8
Definition: common.h:43

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