gem5
v20.1.0.0
systemc
ext
tlm_core
1
analysis
analysis_port.hh
Go to the documentation of this file.
1
/*****************************************************************************
2
3
Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
4
more contributor license agreements. See the NOTICE file distributed
5
with this work for additional information regarding copyright ownership.
6
Accellera licenses this file to you under the Apache License, Version 2.0
7
(the "License"); you may not use this file except in compliance with the
8
License. You may obtain a copy of the License at
9
10
http://www.apache.org/licenses/LICENSE-2.0
11
12
Unless required by applicable law or agreed to in writing, software
13
distributed under the License is distributed on an "AS IS" BASIS,
14
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
15
implied. See the License for the specific language governing
16
permissions and limitations under the License.
17
18
*****************************************************************************/
19
20
#ifndef __SYSTEMC_EXT_TLM_CORE_1_ANALYSIS_ANALYSIS_PORT_HH__
21
#define __SYSTEMC_EXT_TLM_CORE_1_ANALYSIS_ANALYSIS_PORT_HH__
22
23
#include <algorithm>
24
#include <deque>
25
26
#include "
analysis_if.hh
"
27
28
namespace
tlm
29
{
30
31
template
<
typename
T>
32
class
tlm_analysis_port :
public
sc_core::sc_object
,
33
public
virtual
tlm_analysis_if<T>
34
{
35
public
:
36
tlm_analysis_port
() :
sc_core
::
sc_object
() {}
37
tlm_analysis_port
(
const
char
*nm) :
sc_core
::
sc_object
(nm) {}
38
39
// bind and () work for both interfaces and analysis ports, since
40
// analysis ports implement the analysis interface.
41
42
virtual
void
43
bind
(tlm_analysis_if<T> &_if)
44
{
45
m_interfaces
.push_back(&_if);
46
}
47
48
void
operator()
(tlm_analysis_if<T> &_if) {
bind
(_if); }
49
virtual
bool
50
unbind
(
tlm_analysis_if<T>
&_if)
51
{
52
typename
std::deque<tlm_analysis_if<T>
*>::iterator
i
=
53
std::remove(
m_interfaces
.begin(),
m_interfaces
.end(), &_if);
54
55
if
(
i
!=
m_interfaces
.end()) {
56
m_interfaces
.erase(
i
,
m_interfaces
.end());
57
return
1;
58
}
59
return
0;
60
}
61
62
void
63
write
(
const
T &
t
)
64
{
65
typename
std::deque<tlm_analysis_if<T>
*>::iterator
i
;
66
67
for
(
i
=
m_interfaces
.begin();
i
!=
m_interfaces
.end();
i
++) {
68
(*i)->write(
t
);
69
}
70
}
71
72
private
:
73
std::deque<tlm_analysis_if<T>
*>
m_interfaces
;
74
};
75
76
}
// namespace tlm
77
78
#endif
/* __SYSTEMC_EXT_TLM_CORE_1_ANALYSIS_ANALYSIS_PORT_HH__ */
ArmISA::i
Bitfield< 7 > i
Definition:
miscregs_types.hh:63
sc_core
Definition:
messages.cc:31
tlm::tlm_analysis_port::operator()
void operator()(tlm_analysis_if< T > &_if)
Definition:
analysis_port.hh:82
tlm::tlm_analysis_port::write
void write(const T &t)
Definition:
analysis_port.hh:97
tlm::tlm_analysis_if
Definition:
analysis_if.hh:46
analysis_if.hh
tlm
Definition:
analysis_fifo.hh:27
tlm::tlm_analysis_port::m_interfaces
std::deque< tlm_analysis_if< T > * > m_interfaces
Definition:
analysis_port.hh:107
sc_core::sc_object
Definition:
sc_object.hh:50
tlm::tlm_analysis_port::bind
virtual void bind(tlm_analysis_if< T > &_if)
Definition:
analysis_port.hh:77
ArmISA::t
Bitfield< 5 > t
Definition:
miscregs_types.hh:67
std::deque
STL deque class.
Definition:
stl.hh:44
sc_core::sc_object::sc_object
sc_object()
Definition:
sc_object.cc:133
tlm::tlm_analysis_port::tlm_analysis_port
tlm_analysis_port()
Definition:
analysis_port.hh:70
tlm::tlm_analysis_port::unbind
virtual bool unbind(tlm_analysis_if< T > &_if)
Definition:
analysis_port.hh:84
Generated on Wed Sep 30 2020 14:02:16 for gem5 by
doxygen
1.8.17