htm.hh

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/*
 * Copyright (c) 2020 ARM Limited
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 *
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 * property including but not limited to intellectual property relating
 * to a hardware implementation of the functionality of the software
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 * terms below provided that you ensure that this notice is replicated
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 * modified or unmodified, in source code or in binary form.
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/*
 * Gem5 Hardware Transactional Memory (HTM)
 *
 * Here we provide a brief note describing HTM support in Gem5 at
 * a high level.
 *
 * HTM is an architectural feature that enables speculative
 * concurrency in a shared-memory system; groups of instructions known as
 * transactions are executed as an atomic unit. The system allows that
 * transactions be executed concurrently but intervenes if a transaction's
 * atomicity/isolation is jeapordised and takes corrective action. In this
 * implementation, corrective active explicitely means rolling back a thread's
 * architectural state and reverting any memory updates to a point just
 * before the transaction began.
 *
 * This HTM implementation relies on--
 * (1) A checkpointing mechanism for architectural register state.
 * (2) Buffering speculative memory updates.
 *
 * The checkpointing mechanism is architecture dependent. Each ISA leveraging
 * HTM support must define a class HTMCheckpoint in src/arch/theISA/htm.hh.
 * Instances of this class live in O3's ThreadState and Atomic's SimpleThread.
 * It is up to the ISA to populate this instance when executing an instruction
 * that begins a new transaction.
 *
 * The buffering of speculative memory updates is currently implemented in
 * the MESI_Three_Level Ruby protocol. The core notifies the L0 cache
 * controller that a new transaction has started and the controller in turn
 * places itself in transactional state (htmTransactionalState := true).
 * When operating in transactional state, the usual MESI protocol changes
 * slightly. Lines loaded or stored are marked as part of a transaction's
 * read and write set respectively. If there is an invalidation request to
 * cache line in the read/write set, the transaction is marked as failed.
 * Similarly, if there is a read request by another core to a speculatively
 * written cache line, i.e. in the write set, the transaction is marked as
 * failed. If failed, all subsequent loads and stores from the core are
 * made benign, i.e. made into NOPS at the cache controller, and responses are
 * marked to indicate that the transactional state has failed. When the core
 * receives these marked responses, it generates a HtmFailureFault with the
 * reason for the transaction failure. Servicing this fault does two things--
 * (a) Restores the architectural checkpoint
 * (b) Sends an HTM abort signal to the cache controller
 *
 * The restoration includes all registers in the checkpoint as well as the
 * program counter of the instruction before the transaction started.
 *
 * The abort signal is sent to the L0 cache controller and resets the
 * failed transactional state. It resets the transactional read and write sets
 * and invalidates any speculatively written cache lines.  It also exits
 * the transactional state so that the MESI protocol operates as usual.
 *
 * Alternatively, if the instructions within a transaction complete without
 * triggering a HtmFailureFault, the transaction can be committed. The core
 * is responsible for notifying the cache controller that the transaction is
 * complete and the cache controller makes all speculative writes visible
 * to the rest of the system and exits the transactional state.
 *
 * Notifting the cache controller is done through HtmCmd Requests which are
 * a subtype of Load Requests.
 *
 * Most HTMs allow for a limited number of nested transactions, e.g. a nesting
 * depth of two would be inside a transaction started within another
 * transaction. The ExecContext class is extended with
 * getHtmTransactionalDepth() to return the current depth. For the
 * TimingSimpleCPU it is straightforward to track this, whereas for
 * O3DerivCPU it must be tracked in the frontend and commit stages as well as
 * be corrected on branch mispredictions. This is done in iew_impl.hh.
 */
 
 #ifndef __ARCH_GENERIC_HTM_HH__
 #define __ARCH_GENERIC_HTM_HH__
 
#include <cstdint>
#include <memory>
 
#include "mem/htm.hh"
 
class ThreadContext;
class BaseHTMCheckpoint;
 
typedef std::unique_ptr<BaseHTMCheckpoint> BaseHTMCheckpointPtr;
 
class BaseHTMCheckpoint
{
  private:
    static uint64_t globalHtmUid;
    uint64_t localHtmUid;
 
  public:
    BaseHTMCheckpoint() : localHtmUid(0), _valid(false)
    {
        reset();
    }
    virtual ~BaseHTMCheckpoint() {}
 
    virtual void
    save(ThreadContext *tc)
    {
        _valid = true;
    }
 
    virtual void
    restore(ThreadContext *tc, HtmFailureFaultCause cause)
    {
        reset();
    }
 
    bool valid() const { return _valid; }
 
    uint64_t
    newHtmUid()
    {
        localHtmUid = ++ globalHtmUid;
        return localHtmUid;
    }
 
    uint64_t
    getHtmUid() const
    {
        return localHtmUid;
    }
 
    void
    setHtmUid(uint64_t new_htm_uid)
    {
        localHtmUid = new_htm_uid;
    }
 
  protected:
    virtual void reset() { _valid = false; }
    bool _valid;
};
 
#endif // __ARCH_GENERIC_HTM_HH__