gem5
v20.1.0.0
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#include "arch/arm/faults.hh"
#include "arch/arm/isa_traits.hh"
#include "arch/arm/miscregs.hh"
#include "arch/arm/registers.hh"
#include "arch/arm/utility.hh"
#include "arch/generic/interrupts.hh"
#include "cpu/thread_context.hh"
#include "debug/Interrupt.hh"
#include "params/ArmInterrupts.hh"
Go to the source code of this file.
Classes | |
class | ArmISA::Interrupts |
Namespaces | |
ArmISA | |
Enumerations | |
enum | ArmISA::InterruptTypes { ArmISA::INT_RST, ArmISA::INT_ABT, ArmISA::INT_IRQ, ArmISA::INT_FIQ, ArmISA::INT_SEV, ArmISA::INT_VIRT_IRQ, ArmISA::INT_VIRT_FIQ, ArmISA::NumInterruptTypes } |