gem5  v20.1.0.0
registers.hh
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40 
41 #ifndef __ARCH_ARM_REGISTERS_HH__
42 #define __ARCH_ARM_REGISTERS_HH__
43 
44 #include "arch/arm/ccregs.hh"
45 #include "arch/arm/generated/max_inst_regs.hh"
46 #include "arch/arm/intregs.hh"
47 #include "arch/arm/miscregs.hh"
48 #include "arch/arm/types.hh"
50 #include "arch/generic/vec_reg.hh"
51 
52 namespace ArmISA {
53 
54 
55 // For a predicated instruction, we need all the
56 // destination registers to also be sources
57 const int MaxInstSrcRegs = ArmISAInst::MaxInstDestRegs +
59 using ArmISAInst::MaxInstDestRegs;
61 
62 // Number of VecElem per Vector Register considering only pre-SVE
63 // Advanced SIMD registers.
64 constexpr unsigned NumVecElemPerNeonVecReg = 4;
65 // Number of VecElem per Vector Register, computed based on the vector length
67 
68 using VecElem = uint32_t;
72 
78 
79 // Constants Related to the number of registers
80 // Int, Float, CC, Misc
82 const int NumIntRegs = NUM_INTREGS;
83 const int NumFloatRegs = 0; // Float values are stored in the VecRegs
84 const int NumCCRegs = NUM_CCREGS;
86 
87 // Vec, PredVec
88 // NumFloatV7ArchRegs: This in theory should be 32.
89 // However in A32 gem5 is splitting double register accesses in two
90 // subsequent single register ones. This means we would use a index
91 // bigger than 31 when accessing D16-D31.
92 const int NumFloatV7ArchRegs = 64; // S0-S31, D0-D31
93 const int NumVecV7ArchRegs = 16; // Q0-Q15
94 const int NumVecV8ArchRegs = 32; // V0-V31
95 const int NumVecSpecialRegs = 8;
96 const int NumVecIntrlvRegs = 4;
98 const int NumVecPredRegs = 18; // P0-P15, FFR, UREG0
99 
102 
103 // Semantically meaningful register indices
104 const int ReturnValueReg = 0;
105 const int ReturnValueReg1 = 1;
106 const int ReturnValueReg2 = 2;
107 const int NumArgumentRegs = 4;
108 const int NumArgumentRegs64 = 8;
109 const int ArgumentReg0 = 0;
110 const int ArgumentReg1 = 1;
111 const int ArgumentReg2 = 2;
112 const int ArgumentReg3 = 3;
113 const int FramePointerReg = 11;
116 const int PCReg = INTREG_PC;
117 
118 const int ZeroReg = INTREG_ZERO;
119 
120 // Vec, PredVec indices
123 const int INTRLVREG1 = INTRLVREG0 + 1;
124 const int INTRLVREG2 = INTRLVREG0 + 2;
125 const int INTRLVREG3 = INTRLVREG0 + 3;
126 const int VECREG_UREG0 = 32;
127 const int PREDREG_FFR = 16;
128 const int PREDREG_UREG0 = 17;
129 
133 
134 } // namespace ArmISA
135 
136 #endif
ArmISA::VECREG_UREG0
const int VECREG_UREG0
Definition: registers.hh:126
ArmISA::NumIntArchRegs
const int NumIntArchRegs
Definition: registers.hh:81
ArmISA::INTRLVREG1
const int INTRLVREG1
Definition: registers.hh:123
ArmISA::INTREG_PC
@ INTREG_PC
Definition: intregs.hh:72
VecPredRegContainer
Generic predicate register container.
Definition: vec_pred_reg.hh:47
ArmISA::INTREG_LR
@ INTREG_LR
Definition: intregs.hh:70
ArmISA::ArgumentReg2
const int ArgumentReg2
Definition: registers.hh:111
ArmISA::SyscallNumReg
const int SyscallNumReg
Definition: registers.hh:130
ArmISA::INTREG_ZERO
@ INTREG_ZERO
Definition: intregs.hh:112
ArmISA::MaxSveVecLenInWords
constexpr unsigned MaxSveVecLenInWords
Definition: types.hh:815
ArmISA::ArgumentReg1
const int ArgumentReg1
Definition: registers.hh:110
ArmISA::NumVecV8ArchRegs
const int NumVecV8ArchRegs
Definition: registers.hh:94
ArmISA
Definition: ccregs.hh:41
ArmISA::ReturnValueReg
const int ReturnValueReg
Definition: registers.hh:104
types.hh
ArmISA::INTREG_SP
@ INTREG_SP
Definition: intregs.hh:68
ArmISA::MaxInstSrcRegs
const int MaxInstSrcRegs
Definition: registers.hh:57
VecRegT::Container
typename std::conditional< Const, const VecRegContainer< size()>, VecRegContainer< size()> >::type Container
Container type alias.
Definition: vec_reg.hh:182
ArmISA::NumVecSpecialRegs
const int NumVecSpecialRegs
Definition: registers.hh:95
ArmISA::NumArgumentRegs64
const int NumArgumentRegs64
Definition: registers.hh:108
ArmISA::ReturnValueReg2
const int ReturnValueReg2
Definition: registers.hh:106
ArmISA::ArgumentReg3
const int ArgumentReg3
Definition: registers.hh:112
ArmISA::SyscallPseudoReturnReg
const int SyscallPseudoReturnReg
Definition: registers.hh:131
ArmISA::NUM_CCREGS
@ NUM_CCREGS
Definition: ccregs.hh:51
ArmISA::PREDREG_FFR
const int PREDREG_FFR
Definition: registers.hh:127
ArmISA::INTRLVREG2
const int INTRLVREG2
Definition: registers.hh:124
ArmISA::VecElem
uint32_t VecElem
Definition: registers.hh:68
ArmISA::INTRLVREG3
const int INTRLVREG3
Definition: registers.hh:125
ArmISA::PREDREG_UREG0
const int PREDREG_UREG0
Definition: registers.hh:128
VecPredRegT
Predicate register view.
Definition: vec_pred_reg.hh:66
ArmISA::ArgumentReg0
const int ArgumentReg0
Definition: registers.hh:109
ArmISA::ZeroReg
const int ZeroReg
Definition: registers.hh:118
ArmISA::NumVecElemPerVecReg
constexpr unsigned NumVecElemPerVecReg
Definition: registers.hh:66
VecPredRegT::Container
typename std::conditional< Const, const VecPredRegContainer< NUM_BITS, Packed >, VecPredRegContainer< NUM_BITS, Packed > >::type Container
Container type alias.
Definition: vec_pred_reg.hh:78
ArmISA::VecPredRegHasPackedRepr
constexpr unsigned VecPredRegHasPackedRepr
Definition: types.hh:820
ArmISA::NumArgumentRegs
const int NumArgumentRegs
Definition: registers.hh:107
ArmISA::FramePointerReg
const int FramePointerReg
Definition: registers.hh:113
ArmISA::ReturnValueReg1
const int ReturnValueReg1
Definition: registers.hh:105
ArmISA::SyscallSuccessReg
const int SyscallSuccessReg
Definition: registers.hh:132
intregs.hh
ArmISA::NumVecPredRegs
const int NumVecPredRegs
Definition: registers.hh:98
ArmISA::INTRLVREG0
const int INTRLVREG0
Definition: registers.hh:122
ccregs.hh
ArmISA::NumFloatRegs
const int NumFloatRegs
Definition: registers.hh:83
vec_pred_reg.hh
ArmISA::NumIntRegs
const int NumIntRegs
Definition: registers.hh:82
vec_reg.hh
miscregs.hh
ArmISA::NumFloatV7ArchRegs
const int NumFloatV7ArchRegs
Definition: registers.hh:92
ArmISA::NUM_ARCH_INTREGS
@ NUM_ARCH_INTREGS
Definition: intregs.hh:124
ArmISA::NumCCRegs
const int NumCCRegs
Definition: registers.hh:84
ArmISA::StackPointerReg
const int StackPointerReg
Definition: registers.hh:114
ArmISA::NUM_INTREGS
@ NUM_INTREGS
Definition: intregs.hh:123
ArmISA::NumVecElemPerNeonVecReg
constexpr unsigned NumVecElemPerNeonVecReg
Definition: registers.hh:64
RiscvISA::MaxMiscDestRegs
const int MaxMiscDestRegs
Definition: registers.hh:62
ArmISA::NUM_MISCREGS
@ NUM_MISCREGS
Definition: miscregs.hh:1088
ArmISA::NumVecIntrlvRegs
const int NumVecIntrlvRegs
Definition: registers.hh:96
ArmISA::VecSpecialElem
const int VecSpecialElem
Definition: registers.hh:121
ArmISA::ReturnAddressReg
const int ReturnAddressReg
Definition: registers.hh:115
ArmISA::PCReg
const int PCReg
Definition: registers.hh:116
ArmISA::TotalNumRegs
const int TotalNumRegs
Definition: registers.hh:100
ArmISA::NumVecRegs
const int NumVecRegs
Definition: registers.hh:97
ArmISA::NumMiscRegs
const int NumMiscRegs
Definition: registers.hh:85
VecRegContainer
Vector Register Abstraction This generic class is the model in a particularization of MVC,...
Definition: vec_reg.hh:156
VecRegT
Vector Register Abstraction This generic class is a view in a particularization of MVC,...
Definition: vec_reg.hh:170
ArmISA::NumVecV7ArchRegs
const int NumVecV7ArchRegs
Definition: registers.hh:93

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