gem5  v20.1.0.0
ram.h
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3  Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
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20 /*****************************************************************************
21 
22  ram.h --
23 
24  Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
25 
26  *****************************************************************************/
27 
28 /*****************************************************************************
29 
30  MODIFICATION LOG - modifiers, enter your name, affiliation, date and
31  changes you are making here.
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33  Name, Affiliation, Date:
34  Description of Modification:
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36  *****************************************************************************/
37 
38 /* Filename ram.h */
39 /* This is the interface file for synchronous process 'ram' */
40 
41 #include "common.h"
42 
43 SC_MODULE( ram )
44 {
45  SC_HAS_PROCESS( ram );
46 
47  sc_in_clk clk;
48 
49  const signal_bool_vector32& datain; //input
50  const sc_signal<bool>& cs; //input
51  const sc_signal<bool>& we; //input
52  const signal_bool_vector10& addr; //input
53  signal_bool_vector32& dataout; //output
54 
55  // Internal variable
56  int memory[4000];
57 
58  // Parameter
59  const int wait_cycles; // Number of cycles it takes to access memory
60 
61  //Constructor
62  ram(sc_module_name NAME,
63  sc_clock& TICK,
64  const signal_bool_vector32& DATAIN,
65  const sc_signal<bool>& CS,
66  const sc_signal<bool>& WE,
67  const signal_bool_vector10& ADDR,
68  signal_bool_vector32& DATAOUT,
69  const int WAIT_CYCLES = 1)
70  : datain(DATAIN), cs(CS), we(WE),
71  addr(ADDR), dataout(DATAOUT), wait_cycles(WAIT_CYCLES)
72  {
73  clk(TICK);
74  SC_CTHREAD( entry, clk.pos() );
75  }
76 
77  // Process functionality in member function below
78  void entry();
79 };
80 
81 
memory
Definition: mem.h:38
signal_bool_vector10
sc_signal< sc_bv< 10 > > signal_bool_vector10
Definition: common.h:43
SC_MODULE
SC_MODULE(ram)
Definition: ram.h:43
X86ISA::CS
const uint8_t CS
Definition: decoder_tables.cc:43
signal_bool_vector32
sc_signal< sc_bv< 32 > > signal_bool_vector32
Definition: common.h:44
sc_core::sc_in_clk
sc_in< bool > sc_in_clk
Definition: sc_clock.hh:116
SC_HAS_PROCESS
#define SC_HAS_PROCESS(name)
Definition: sc_module.hh:297
addr
ip6_addr_t addr
Definition: inet.hh:423
SC_CTHREAD
#define SC_CTHREAD(name, clk)
Definition: sc_module.hh:319
common.h

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