X86ISA Namespace Reference

This is exposed globally, independent of the ISA. More...

Namespaces
	ACPI
	ConditionTests
	IntelMP
	SMBios

Classes
class	AlignmentCheck
class	BoundRange
class	Breakpoint
class	Cmos
struct	CpuidResult
class	DebugException
class	Decoder
class	DeviceNotAvailable
class	DivideError
class	DoubleFault
class	E820Entry
class	E820Table
struct	EmulEnv
class	ExternalInterrupt
struct	ExtMachInst
class	FpOp
	Base classes for FpOps which provides a generateDisassembly method. More...
class	FsLinux
class	FsWorkload
class	GeneralProtection
class	GpuTLB
class	I386LinuxProcess
class	I386Process
class	I8042
class	I82094AA
class	I8237
class	I8254
class	I8259
class	InitInterrupt
struct	InstRegIndex
	Class for register indices passed to instruction constructors. More...
class	Interrupts
class	IntRequestPort
class	IntResponsePort
class	InvalidOpcode
class	InvalidTSS
class	ISA
class	LdStOp
	Base class for load and store ops using one register. More...
class	LdStSplitOp
	Base class for load and store ops using two registers, we will call them split ops for this reason. More...
class	LongModePTE
class	MachineCheck
class	MacroopBase
class	MediaOpBase
class	MediaOpImm
class	MediaOpReg
class	MemOp
	Base class for memory ops. More...
class	NonMaskableInterrupt
class	OverflowTrap
class	PageFault
class	PCState
class	RegOp
class	RegOpBase
	Base classes for RegOps which provides a generateDisassembly method. More...
class	RegOpImm
class	RemoteGDB
class	SecurityException
class	SegDescriptorLimit
class	SegmentNotPresent
class	SIMDFloatingPointFault
class	SoftwareInterrupt
class	Speaker
class	StackFault
class	StackTrace
class	StartupInterrupt
class	SystemManagementInterrupt
class	TLB
struct	TlbEntry
class	UnimpInstFault
class	Walker
class	X86_64LinuxProcess
class	X86_64Process
class	X86Abort
class	X86Fault
class	X86FaultBase
class	X86Interrupt
class	X86MicroopBase
class	X86Process
class	X86StaticInst
	Base class for all X86 static instructions. More...
class	X86Trap
class	X87FpExceptionPending

Typedefs
using	VecElem = ::DummyVecElem
using	VecReg = ::DummyVecReg
using	ConstVecReg = ::DummyConstVecReg
using	VecRegContainer = ::DummyVecRegContainer
using	VecPredReg = ::DummyVecPredReg
using	ConstVecPredReg = ::DummyConstVecPredReg
using	VecPredRegContainer = ::DummyVecPredRegContainer
typedef MsrMap::value_type	MsrVal
typedef std::unordered_map< Addr, MiscRegIndex >	MsrMap
typedef uint64_t	MachInst

Enumerations
enum	StandardCpuidFunction {   VendorAndLargestStdFunc, FamilyModelStepping, CacheAndTLB, SerialNumber,   CacheParams, MonitorMwait, ThermalPowerMgmt, ExtendedFeatures,   NumStandardCpuidFuncs }
enum	ExtendedCpuidFunctions {   VendorAndLargestExtFunc, FamilyModelSteppingBrandFeatures, NameString1, NameString2,   NameString3, L1CacheAndTLB, L2L3CacheAndL2TLB, APMInfo,   LongModeAddressSize, NumExtendedCpuidFuncs }
enum	SizeType {   NoImm, NI = NoImm, ByteImm, BY = ByteImm,   WordImm, WO = WordImm, DWordImm, DW = DWordImm,   QWordImm, QW = QWordImm, OWordImm, OW = OWordImm,   VWordImm, VW = VWordImm, ZWordImm, ZW = ZWordImm,   Enter, EN = Enter, Pointer, PO = Pointer }
enum	MediaFlag { MediaMultHiOp = 1, MediaSignedOp = 64, MediaScalarOp = 128 }
enum	FlagBit { CPL0FlagBit = 1, AddrSizeFlagBit = 2, StoreCheck = 4 }
enum	X86AuxiliaryVectorTypes { M5_AT_SYSINFO = 32, M5_AT_SYSINFO_EHDR = 33 }
enum	DependenceTags { FP_Reg_Base = 128, CC_Reg_Base = FP_Reg_Base + NumFloatRegs, Misc_Reg_Base = CC_Reg_Base + NumCCRegs, Max_Reg_Index = Misc_Reg_Base + NumMiscRegs }
enum	ApicRegIndex {   APIC_ID, APIC_VERSION, APIC_TASK_PRIORITY, APIC_ARBITRATION_PRIORITY,   APIC_PROCESSOR_PRIORITY, APIC_EOI, APIC_LOGICAL_DESTINATION, APIC_DESTINATION_FORMAT,   APIC_SPURIOUS_INTERRUPT_VECTOR, APIC_IN_SERVICE_BASE, APIC_TRIGGER_MODE_BASE = APIC_IN_SERVICE_BASE + 16, APIC_INTERRUPT_REQUEST_BASE = APIC_TRIGGER_MODE_BASE + 16,   APIC_ERROR_STATUS = APIC_INTERRUPT_REQUEST_BASE + 16, APIC_INTERRUPT_COMMAND_LOW, APIC_INTERRUPT_COMMAND_HIGH, APIC_LVT_TIMER,   APIC_LVT_THERMAL_SENSOR, APIC_LVT_PERFORMANCE_MONITORING_COUNTERS, APIC_LVT_LINT0, APIC_LVT_LINT1,   APIC_LVT_ERROR, APIC_INITIAL_COUNT, APIC_CURRENT_COUNT, APIC_DIVIDE_CONFIGURATION,   APIC_INTERNAL_STATE, NUM_APIC_REGS }
enum	CCRegIndex {   CCREG_ZAPS, CCREG_CFOF, CCREG_DF, CCREG_ECF,   CCREG_EZF, NUM_CCREGS }
enum	FloatRegIndex {   FLOATREG_MMX_BASE, FLOATREG_FPR_BASE = FLOATREG_MMX_BASE, FLOATREG_MMX0 = FLOATREG_MMX_BASE, FLOATREG_MMX1,   FLOATREG_MMX2, FLOATREG_MMX3, FLOATREG_MMX4, FLOATREG_MMX5,   FLOATREG_MMX6, FLOATREG_MMX7, FLOATREG_FPR0 = FLOATREG_FPR_BASE, FLOATREG_FPR1,   FLOATREG_FPR2, FLOATREG_FPR3, FLOATREG_FPR4, FLOATREG_FPR5,   FLOATREG_FPR6, FLOATREG_FPR7, FLOATREG_XMM_BASE = FLOATREG_MMX_BASE + NumMMXRegs, FLOATREG_XMM0_LOW = FLOATREG_XMM_BASE,   FLOATREG_XMM0_HIGH, FLOATREG_XMM1_LOW, FLOATREG_XMM1_HIGH, FLOATREG_XMM2_LOW,   FLOATREG_XMM2_HIGH, FLOATREG_XMM3_LOW, FLOATREG_XMM3_HIGH, FLOATREG_XMM4_LOW,   FLOATREG_XMM4_HIGH, FLOATREG_XMM5_LOW, FLOATREG_XMM5_HIGH, FLOATREG_XMM6_LOW,   FLOATREG_XMM6_HIGH, FLOATREG_XMM7_LOW, FLOATREG_XMM7_HIGH, FLOATREG_XMM8_LOW,   FLOATREG_XMM8_HIGH, FLOATREG_XMM9_LOW, FLOATREG_XMM9_HIGH, FLOATREG_XMM10_LOW,   FLOATREG_XMM10_HIGH, FLOATREG_XMM11_LOW, FLOATREG_XMM11_HIGH, FLOATREG_XMM12_LOW,   FLOATREG_XMM12_HIGH, FLOATREG_XMM13_LOW, FLOATREG_XMM13_HIGH, FLOATREG_XMM14_LOW,   FLOATREG_XMM14_HIGH, FLOATREG_XMM15_LOW, FLOATREG_XMM15_HIGH, FLOATREG_MICROFP_BASE = FLOATREG_XMM_BASE + 2 * NumXMMRegs,   FLOATREG_MICROFP0 = FLOATREG_MICROFP_BASE, FLOATREG_MICROFP1, FLOATREG_MICROFP2, FLOATREG_MICROFP3,   FLOATREG_MICROFP4, FLOATREG_MICROFP5, FLOATREG_MICROFP6, FLOATREG_MICROFP7,   NUM_FLOATREGS = FLOATREG_MICROFP_BASE + NumMicroFpRegs }
enum	CondFlagBit {   CFBit = 1 << 0, PFBit = 1 << 2, ECFBit = 1 << 3, AFBit = 1 << 4,   EZFBit = 1 << 5, ZFBit = 1 << 6, SFBit = 1 << 7, DFBit = 1 << 10,   OFBit = 1 << 11 }
enum	RFLAGBit {   TFBit = 1 << 8, IFBit = 1 << 9, NTBit = 1 << 14, RFBit = 1 << 16,   VMBit = 1 << 17, ACBit = 1 << 18, VIFBit = 1 << 19, VIPBit = 1 << 20,   IDBit = 1 << 21 }
enum	X87StatusBit {   IEBit = 1 << 0, DEBit = 1 << 1, ZEBit = 1 << 2, OEBit = 1 << 3,   UEBit = 1 << 4, PEBit = 1 << 5, StackFaultBit = 1 << 6, ErrSummaryBit = 1 << 7,   CC0Bit = 1 << 8, CC1Bit = 1 << 9, CC2Bit = 1 << 10, CC3Bit = 1 << 14,   BusyBit = 1 << 15 }
enum	MiscRegIndex {   MISCREG_CR_BASE, MISCREG_CR0 = MISCREG_CR_BASE, MISCREG_CR1, MISCREG_CR2,   MISCREG_CR3, MISCREG_CR4, MISCREG_CR5, MISCREG_CR6,   MISCREG_CR7, MISCREG_CR8, MISCREG_CR9, MISCREG_CR10,   MISCREG_CR11, MISCREG_CR12, MISCREG_CR13, MISCREG_CR14,   MISCREG_CR15, MISCREG_DR_BASE = MISCREG_CR_BASE + NumCRegs, MISCREG_DR0 = MISCREG_DR_BASE, MISCREG_DR1,   MISCREG_DR2, MISCREG_DR3, MISCREG_DR4, MISCREG_DR5,   MISCREG_DR6, MISCREG_DR7, MISCREG_RFLAGS = MISCREG_DR_BASE + NumDRegs, MISCREG_M5_REG,   MISCREG_TSC, MISCREG_MTRRCAP, MISCREG_SYSENTER_CS, MISCREG_SYSENTER_ESP,   MISCREG_SYSENTER_EIP, MISCREG_MCG_CAP, MISCREG_MCG_STATUS, MISCREG_MCG_CTL,   MISCREG_DEBUG_CTL_MSR, MISCREG_LAST_BRANCH_FROM_IP, MISCREG_LAST_BRANCH_TO_IP, MISCREG_LAST_EXCEPTION_FROM_IP,   MISCREG_LAST_EXCEPTION_TO_IP, MISCREG_MTRR_PHYS_BASE_BASE, MISCREG_MTRR_PHYS_BASE_0 = MISCREG_MTRR_PHYS_BASE_BASE, MISCREG_MTRR_PHYS_BASE_1,   MISCREG_MTRR_PHYS_BASE_2, MISCREG_MTRR_PHYS_BASE_3, MISCREG_MTRR_PHYS_BASE_4, MISCREG_MTRR_PHYS_BASE_5,   MISCREG_MTRR_PHYS_BASE_6, MISCREG_MTRR_PHYS_BASE_7, MISCREG_MTRR_PHYS_BASE_END, MISCREG_MTRR_PHYS_MASK_BASE = MISCREG_MTRR_PHYS_BASE_END,   MISCREG_MTRR_PHYS_MASK_0 = MISCREG_MTRR_PHYS_MASK_BASE, MISCREG_MTRR_PHYS_MASK_1, MISCREG_MTRR_PHYS_MASK_2, MISCREG_MTRR_PHYS_MASK_3,   MISCREG_MTRR_PHYS_MASK_4, MISCREG_MTRR_PHYS_MASK_5, MISCREG_MTRR_PHYS_MASK_6, MISCREG_MTRR_PHYS_MASK_7,   MISCREG_MTRR_PHYS_MASK_END, MISCREG_MTRR_FIX_64K_00000 = MISCREG_MTRR_PHYS_MASK_END, MISCREG_MTRR_FIX_16K_80000, MISCREG_MTRR_FIX_16K_A0000,   MISCREG_MTRR_FIX_4K_C0000, MISCREG_MTRR_FIX_4K_C8000, MISCREG_MTRR_FIX_4K_D0000, MISCREG_MTRR_FIX_4K_D8000,   MISCREG_MTRR_FIX_4K_E0000, MISCREG_MTRR_FIX_4K_E8000, MISCREG_MTRR_FIX_4K_F0000, MISCREG_MTRR_FIX_4K_F8000,   MISCREG_PAT, MISCREG_DEF_TYPE, MISCREG_MC_CTL_BASE, MISCREG_MC0_CTL = MISCREG_MC_CTL_BASE,   MISCREG_MC1_CTL, MISCREG_MC2_CTL, MISCREG_MC3_CTL, MISCREG_MC4_CTL,   MISCREG_MC5_CTL, MISCREG_MC6_CTL, MISCREG_MC7_CTL, MISCREG_MC_CTL_END,   MISCREG_MC_STATUS_BASE = MISCREG_MC_CTL_END, MISCREG_MC0_STATUS = MISCREG_MC_STATUS_BASE, MISCREG_MC1_STATUS, MISCREG_MC2_STATUS,   MISCREG_MC3_STATUS, MISCREG_MC4_STATUS, MISCREG_MC5_STATUS, MISCREG_MC6_STATUS,   MISCREG_MC7_STATUS, MISCREG_MC_STATUS_END, MISCREG_MC_ADDR_BASE = MISCREG_MC_STATUS_END, MISCREG_MC0_ADDR = MISCREG_MC_ADDR_BASE,   MISCREG_MC1_ADDR, MISCREG_MC2_ADDR, MISCREG_MC3_ADDR, MISCREG_MC4_ADDR,   MISCREG_MC5_ADDR, MISCREG_MC6_ADDR, MISCREG_MC7_ADDR, MISCREG_MC_ADDR_END,   MISCREG_MC_MISC_BASE = MISCREG_MC_ADDR_END, MISCREG_MC0_MISC = MISCREG_MC_MISC_BASE, MISCREG_MC1_MISC, MISCREG_MC2_MISC,   MISCREG_MC3_MISC, MISCREG_MC4_MISC, MISCREG_MC5_MISC, MISCREG_MC6_MISC,   MISCREG_MC7_MISC, MISCREG_MC_MISC_END, MISCREG_EFER = MISCREG_MC_MISC_END, MISCREG_STAR,   MISCREG_LSTAR, MISCREG_CSTAR, MISCREG_SF_MASK, MISCREG_KERNEL_GS_BASE,   MISCREG_TSC_AUX, MISCREG_PERF_EVT_SEL_BASE, MISCREG_PERF_EVT_SEL0 = MISCREG_PERF_EVT_SEL_BASE, MISCREG_PERF_EVT_SEL1,   MISCREG_PERF_EVT_SEL2, MISCREG_PERF_EVT_SEL3, MISCREG_PERF_EVT_SEL_END, MISCREG_PERF_EVT_CTR_BASE = MISCREG_PERF_EVT_SEL_END,   MISCREG_PERF_EVT_CTR0 = MISCREG_PERF_EVT_CTR_BASE, MISCREG_PERF_EVT_CTR1, MISCREG_PERF_EVT_CTR2, MISCREG_PERF_EVT_CTR3,   MISCREG_PERF_EVT_CTR_END, MISCREG_SYSCFG = MISCREG_PERF_EVT_CTR_END, MISCREG_IORR_BASE_BASE, MISCREG_IORR_BASE0 = MISCREG_IORR_BASE_BASE,   MISCREG_IORR_BASE1, MISCREG_IORR_BASE_END, MISCREG_IORR_MASK_BASE = MISCREG_IORR_BASE_END, MISCREG_IORR_MASK0 = MISCREG_IORR_MASK_BASE,   MISCREG_IORR_MASK1, MISCREG_IORR_MASK_END, MISCREG_TOP_MEM = MISCREG_IORR_MASK_END, MISCREG_TOP_MEM2,   MISCREG_VM_CR, MISCREG_IGNNE, MISCREG_SMM_CTL, MISCREG_VM_HSAVE_PA,   MISCREG_SEG_SEL_BASE, MISCREG_ES = MISCREG_SEG_SEL_BASE, MISCREG_CS, MISCREG_SS,   MISCREG_DS, MISCREG_FS, MISCREG_GS, MISCREG_HS,   MISCREG_TSL, MISCREG_TSG, MISCREG_LS, MISCREG_MS,   MISCREG_TR, MISCREG_IDTR, MISCREG_SEG_BASE_BASE = MISCREG_SEG_SEL_BASE + NUM_SEGMENTREGS, MISCREG_ES_BASE = MISCREG_SEG_BASE_BASE,   MISCREG_CS_BASE, MISCREG_SS_BASE, MISCREG_DS_BASE, MISCREG_FS_BASE,   MISCREG_GS_BASE, MISCREG_HS_BASE, MISCREG_TSL_BASE, MISCREG_TSG_BASE,   MISCREG_LS_BASE, MISCREG_MS_BASE, MISCREG_TR_BASE, MISCREG_IDTR_BASE,   MISCREG_SEG_EFF_BASE_BASE = MISCREG_SEG_BASE_BASE + NUM_SEGMENTREGS, MISCREG_ES_EFF_BASE = MISCREG_SEG_EFF_BASE_BASE, MISCREG_CS_EFF_BASE, MISCREG_SS_EFF_BASE,   MISCREG_DS_EFF_BASE, MISCREG_FS_EFF_BASE, MISCREG_GS_EFF_BASE, MISCREG_HS_EFF_BASE,   MISCREG_TSL_EFF_BASE, MISCREG_TSG_EFF_BASE, MISCREG_LS_EFF_BASE, MISCREG_MS_EFF_BASE,   MISCREG_TR_EFF_BASE, MISCREG_IDTR_EFF_BASE, MISCREG_SEG_LIMIT_BASE = MISCREG_SEG_EFF_BASE_BASE + NUM_SEGMENTREGS, MISCREG_ES_LIMIT = MISCREG_SEG_LIMIT_BASE,   MISCREG_CS_LIMIT, MISCREG_SS_LIMIT, MISCREG_DS_LIMIT, MISCREG_FS_LIMIT,   MISCREG_GS_LIMIT, MISCREG_HS_LIMIT, MISCREG_TSL_LIMIT, MISCREG_TSG_LIMIT,   MISCREG_LS_LIMIT, MISCREG_MS_LIMIT, MISCREG_TR_LIMIT, MISCREG_IDTR_LIMIT,   MISCREG_SEG_ATTR_BASE = MISCREG_SEG_LIMIT_BASE + NUM_SEGMENTREGS, MISCREG_ES_ATTR = MISCREG_SEG_ATTR_BASE, MISCREG_CS_ATTR, MISCREG_SS_ATTR,   MISCREG_DS_ATTR, MISCREG_FS_ATTR, MISCREG_GS_ATTR, MISCREG_HS_ATTR,   MISCREG_TSL_ATTR, MISCREG_TSG_ATTR, MISCREG_LS_ATTR, MISCREG_MS_ATTR,   MISCREG_TR_ATTR, MISCREG_IDTR_ATTR, MISCREG_X87_TOP, MISCREG_MXCSR,   MISCREG_FCW, MISCREG_FSW, MISCREG_FTW, MISCREG_FTAG,   MISCREG_FISEG, MISCREG_FIOFF, MISCREG_FOSEG, MISCREG_FOOFF,   MISCREG_FOP, MISCREG_APIC_BASE, MISCREG_PCI_CONFIG_ADDRESS, NUM_MISCREGS }
enum	SegmentRegIndex {   SEGMENT_REG_ES, SEGMENT_REG_CS, SEGMENT_REG_SS, SEGMENT_REG_DS,   SEGMENT_REG_FS, SEGMENT_REG_GS, SEGMENT_REG_HS, SEGMENT_REG_TSL,   SEGMENT_REG_TSG, SEGMENT_REG_LS, SEGMENT_REG_MS, SYS_SEGMENT_REG_TR,   SYS_SEGMENT_REG_IDTR, NUM_SEGMENTREGS }
enum	Prefixes {   NoOverride, ESOverride, CSOverride, SSOverride,   DSOverride, FSOverride, GSOverride, RexPrefix,   OperandSizeOverride, AddressSizeOverride, Lock, Rep,   Repne, Vex2Prefix, Vex3Prefix, XopPrefix }
enum	X86SubMode {   SixtyFourBitMode, CompatabilityMode, ProtectedMode, Virtual8086Mode,   RealMode }

Functions
uint64_t	stringToRegister (const char *str)
bool	doCpuid (ThreadContext *tc, uint32_t function, uint32_t index, CpuidResult &result)
void	installSegDesc (ThreadContext *tc, SegmentRegIndex seg, SegDescriptor desc, bool longmode)
ApicRegIndex	decodeAddr (Addr paddr)
	BitUnion32 (TriggerIntMessage) Bitfield< 7
	EndBitUnion (TriggerIntMessage) namespace DeliveryMode
static PacketPtr	buildIntTriggerPacket (int id, TriggerIntMessage message)
static Fault	initiateMemRead (ExecContext *xc, Trace::InstRecord *traceData, Addr addr, unsigned dataSize, Request::Flags flags)
	Initiate a read from memory in timing mode. More...
static void	getMem (PacketPtr pkt, uint64_t &mem, unsigned dataSize, Trace::InstRecord *traceData)
template<typename T , size_t N>
static void	getPackedMem (PacketPtr pkt, std::array< uint64_t, N > &mem, unsigned dataSize)
template<size_t N>
static void	getMem (PacketPtr pkt, std::array< uint64_t, N > &mem, unsigned dataSize, Trace::InstRecord *traceData)
static Fault	readMemAtomic (ExecContext *xc, Trace::InstRecord *traceData, Addr addr, uint64_t &mem, unsigned dataSize, Request::Flags flags)
template<typename T , size_t N>
static Fault	readPackedMemAtomic (ExecContext *xc, Addr addr, std::array< uint64_t, N > &mem, unsigned flags)
template<size_t N>
static Fault	readMemAtomic (ExecContext *xc, Trace::InstRecord *traceData, Addr addr, std::array< uint64_t, N > &mem, unsigned dataSize, unsigned flags)
template<typename T , size_t N>
static Fault	writePackedMem (ExecContext *xc, std::array< uint64_t, N > &mem, Addr addr, unsigned flags, uint64_t *res)
static Fault	writeMemTiming (ExecContext *xc, Trace::InstRecord *traceData, uint64_t mem, unsigned dataSize, Addr addr, Request::Flags flags, uint64_t *res)
template<size_t N>
static Fault	writeMemTiming (ExecContext *xc, Trace::InstRecord *traceData, std::array< uint64_t, N > &mem, unsigned dataSize, Addr addr, unsigned flags, uint64_t *res)
static Fault	writeMemAtomic (ExecContext *xc, Trace::InstRecord *traceData, uint64_t mem, unsigned dataSize, Addr addr, Request::Flags flags, uint64_t *res)
template<size_t N>
static Fault	writeMemAtomic (ExecContext *xc, Trace::InstRecord *traceData, std::array< uint64_t, N > &mem, unsigned dataSize, Addr addr, unsigned flags, uint64_t *res)
	BitUnion64 (VAddr) Bitfield< 20
	EndBitUnion (VAddr) BitUnion64(PageTableEntry) Bitfield< 63 > nx
	EndBitUnion (PageTableEntry) template< int first
void	m5PageFault (ThreadContext *tc)
static ApicRegIndex	APIC_IN_SERVICE (int index)
static ApicRegIndex	APIC_TRIGGER_MODE (int index)
static ApicRegIndex	APIC_INTERRUPT_REQUEST (int index)
	BitUnion32 (InterruptCommandRegLow) Bitfield< 7
	EndBitUnion (InterruptCommandRegLow) BitUnion32(InterruptCommandRegHigh) Bitfield< 31
static FloatRegIndex	FLOATREG_MMX (int index)
static FloatRegIndex	FLOATREG_FPR (int index)
static FloatRegIndex	FLOATREG_XMM_LOW (int index)
static FloatRegIndex	FLOATREG_XMM_HIGH (int index)
static FloatRegIndex	FLOATREG_MICROFP (int index)
static FloatRegIndex	FLOATREG_STACK (int index, int top)
	BitUnion64 (X86IntReg) Bitfield< 63
	EndBitUnion (X86IntReg) enum IntRegIndex
static IntRegIndex	INTREG_MICRO (int index)
static IntRegIndex	INTREG_IMPLICIT (int index)
static IntRegIndex	INTREG_FOLDED (int index, int foldBit)
static bool	isValidMiscReg (int index)
static MiscRegIndex	MISCREG_CR (int index)
static MiscRegIndex	MISCREG_DR (int index)
static MiscRegIndex	MISCREG_MTRR_PHYS_BASE (int index)
static MiscRegIndex	MISCREG_MTRR_PHYS_MASK (int index)
static MiscRegIndex	MISCREG_MC_CTL (int index)
static MiscRegIndex	MISCREG_MC_STATUS (int index)
static MiscRegIndex	MISCREG_MC_ADDR (int index)
static MiscRegIndex	MISCREG_MC_MISC (int index)
static MiscRegIndex	MISCREG_PERF_EVT_SEL (int index)
static MiscRegIndex	MISCREG_PERF_EVT_CTR (int index)
static MiscRegIndex	MISCREG_IORR_BASE (int index)
static MiscRegIndex	MISCREG_IORR_MASK (int index)
static MiscRegIndex	MISCREG_SEG_SEL (int index)
static MiscRegIndex	MISCREG_SEG_BASE (int index)
static MiscRegIndex	MISCREG_SEG_EFF_BASE (int index)
static MiscRegIndex	MISCREG_SEG_LIMIT (int index)
static MiscRegIndex	MISCREG_SEG_ATTR (int index)
	BitUnion64 (CCFlagBits) Bitfield< 11 > of
	A type to describe the condition code bits of the RFLAGS register, plus two flags, EZF and ECF, which are only visible to microcode. More...
	EndBitUnion (CCFlagBits) BitUnion64(RFLAGS) Bitfield< 21 > id
	RFLAGS. More...
	EndBitUnion (RFLAGS) BitUnion64(HandyM5Reg) Bitfield< 0 > mode
	EndBitUnion (HandyM5Reg) BitUnion64(CR0) Bitfield< 31 > pg
	Control registers. More...
	EndBitUnion (CR0) BitUnion64(CR2) Bitfield< 31
	EndBitUnion (CR2) BitUnion64(CR3) Bitfield< 51
	EndBitUnion (CR3) BitUnion64(CR4) Bitfield< 18 > osxsave
	EndBitUnion (CR4) BitUnion64(CR8) Bitfield< 3
	EndBitUnion (CR8) BitUnion64(DR6) Bitfield< 0 > b0
	EndBitUnion (DR6) BitUnion64(DR7) Bitfield< 0 > l0
	EndBitUnion (DR7) BitUnion64(MTRRcap) Bitfield< 7
	EndBitUnion (MTRRcap) BitUnion64(SysenterCS) Bitfield< 15
	SYSENTER configuration registers. More...
	EndBitUnion (SysenterCS) BitUnion64(SysenterESP) Bitfield< 31
	EndBitUnion (SysenterESP) BitUnion64(SysenterEIP) Bitfield< 31
	EndBitUnion (SysenterEIP) BitUnion64(McgCap) Bitfield< 7
	Global machine check registers. More...
	EndBitUnion (McgCap) BitUnion64(McgStatus) Bitfield< 0 > ripv
	EndBitUnion (McgStatus) BitUnion64(DebugCtlMsr) Bitfield< 0 > lbr
	EndBitUnion (DebugCtlMsr) BitUnion64(MtrrPhysBase) Bitfield< 7
	EndBitUnion (MtrrPhysBase) BitUnion64(MtrrPhysMask) Bitfield< 11 > valid
	EndBitUnion (MtrrPhysMask) BitUnion64(MtrrFixed) EndBitUnion(MtrrFixed) BitUnion64(Pat) EndBitUnion(Pat) BitUnion64(MtrrDefType) Bitfield< 7
	EndBitUnion (MtrrDefType) BitUnion64(McStatus) Bitfield< 15
	Machine check. More...
	EndBitUnion (McStatus) BitUnion64(McCtl) EndBitUnion(McCtl) BitUnion64(Efer) Bitfield< 0 > sce
	EndBitUnion (Efer) BitUnion64(Star) Bitfield< 31
	EndBitUnion (Star) BitUnion64(SfMask) Bitfield< 31
	EndBitUnion (SfMask) BitUnion64(PerfEvtSel) Bitfield< 7
	EndBitUnion (PerfEvtSel) BitUnion32(Syscfg) Bitfield< 18 > mfde
	EndBitUnion (Syscfg) BitUnion64(IorrBase) Bitfield< 3 > wr
	EndBitUnion (IorrBase) BitUnion64(IorrMask) Bitfield< 11 > v
	EndBitUnion (IorrMask) BitUnion64(Tom) Bitfield< 51
	EndBitUnion (Tom) BitUnion64(VmCrMsr) Bitfield< 0 > dpd
	EndBitUnion (VmCrMsr) BitUnion64(IgnneMsr) Bitfield< 0 > ignne
	EndBitUnion (IgnneMsr) BitUnion64(SmmCtlMsr) Bitfield< 0 > dismiss
	EndBitUnion (SmmCtlMsr) BitUnion64(SegSelector) Bitfield< 63
	Segment Selector. More...
	EndBitUnion (SegSelector) class SegDescriptorBase
	Segment Descriptors. More...
	BitUnion64 (SegDescriptor) Bitfield< 63
	SubBitUnion (type, 43, 40) Bitfield< 43 > codeOrData
	EndSubBitUnion (type) EndBitUnion(SegDescriptor) BitUnion64(TSSlow) Bitfield< 63
	TSS Descriptor (long mode - 128 bits) the lower 64 bits. More...
	EndBitUnion (TSShigh) BitUnion64(SegAttr) Bitfield< 1
	EndBitUnion (SegAttr) BitUnion64(GateDescriptor) Bitfield< 63
	EndBitUnion (GateDescriptor) BitUnion64(GateDescriptorLow) Bitfield< 63
	Long Mode Gate Descriptor. More...
	EndBitUnion (GateDescriptorLow) BitUnion64(GateDescriptorHigh) Bitfield< 31
	EndBitUnion (GateDescriptorHigh) BitUnion64(GDTR) EndBitUnion(GDTR) BitUnion64(IDTR) EndBitUnion(IDTR) BitUnion64(LDTR) EndBitUnion(LDTR) BitUnion64(TR) EndBitUnion(TR) BitUnion64(LocalApicBase) Bitfield< 51
	Descriptor-Table Registers. More...
const MsrMap	msrMap (msrMapData, msrMapData+msrMapSize)
bool	msrAddrToIndex (MiscRegIndex &regNum, Addr addr)
	Find and return the misc reg corresponding to an MSR address. More...
	BitUnion8 (LegacyPrefixVector) Bitfield< 7
	EndBitUnion (LegacyPrefixVector) BitUnion8(ModRM) Bitfield< 7
	EndBitUnion (ModRM) BitUnion8(Sib) Bitfield< 7
	EndBitUnion (Sib) BitUnion8(Rex) Bitfield< 6 > present
	EndBitUnion (Rex) BitUnion8(Vex2Of3) Bitfield< 7 > r
	EndBitUnion (Vex2Of3) BitUnion8(Vex3Of3) Bitfield< 7 > w
	EndBitUnion (Vex3Of3) BitUnion8(Vex2Of2) Bitfield< 7 > r
	EndBitUnion (Vex2Of2) BitUnion8(VexInfo) Bitfield< 6
	EndBitUnion (VexInfo) enum OpcodeType
static const char *	opcodeTypeToStr (OpcodeType type)
	BitUnion8 (Opcode) Bitfield< 7
	EndBitUnion (Opcode) BitUnion8(OperatingMode) Bitfield< 3 > mode
	EndBitUnion (OperatingMode) enum X86Mode
static std::ostream &	operator<< (std::ostream &os, const ExtMachInst &emi)
static bool	operator== (const ExtMachInst &emi1, const ExtMachInst &emi2)
uint64_t	getArgument (ThreadContext *tc, int &number, uint16_t size, bool fp)
void	copyMiscRegs (ThreadContext *src, ThreadContext *dest)
void	copyRegs (ThreadContext *src, ThreadContext *dest)
uint64_t	getRFlags (ThreadContext *tc)
	Reconstruct the rflags register from the internal gem5 register state. More...
void	setRFlags (ThreadContext *tc, uint64_t val)
	Set update the rflags register and internal gem5 state. More...
uint8_t	convX87TagsToXTags (uint16_t ftw)
	Convert an x87 tag word to abridged tag format. More...
uint16_t	convX87XTagsToTags (uint8_t ftwx)
	Convert an x87 xtag word to normal tags format. More...
uint16_t	genX87Tags (uint16_t ftw, uint8_t top, int8_t spm)
	Generate and updated x87 tag register after a push/pop operation. More...
double	loadFloat80 (const void *mem)
	Load an 80-bit float from memory and convert it to double. More...
void	storeFloat80 (void *mem, double value)
	Convert and store a double as an 80-bit float. More...
PCState	buildRetPC (const PCState &curPC, const PCState &callPC)
static bool	inUserMode (ThreadContext *tc)
void	advancePC (PCState &pc, const StaticInstPtr &inst)
uint64_t	getExecutingAsid (ThreadContext *tc)
static Addr	x86IOAddress (const uint32_t port)
static Addr	x86PciConfigAddress (const uint32_t addr)
static Addr	x86LocalAPICAddress (const uint8_t id, const uint16_t addr)
static Addr	x86InterruptAddress (const uint8_t id, const uint16_t addr)
template<class T >
PacketPtr	buildIntPacket (Addr addr, T payload)

Variables
static const int	vendorStringSize = 13
static const char	vendorString [vendorStringSize] = "M5 Simulator"
static const int	nameStringSize = 48
static const char	nameString [nameStringSize] = "Fake M5 x86_64 CPU"
const uint8_t	CS = CSOverride
const uint8_t	DS = DSOverride
const uint8_t	ES = ESOverride
const uint8_t	FS = FSOverride
const uint8_t	GS = GSOverride
const uint8_t	SS = SSOverride
const uint8_t	OO = OperandSizeOverride
const uint8_t	AO = AddressSizeOverride
const uint8_t	LO = Lock
const uint8_t	RE = Rep
const uint8_t	RN = Repne
const uint8_t	RX = RexPrefix
const uint8_t	V2 = Vex2Prefix
const uint8_t	V3 = Vex3Prefix
const Addr	syscallCodeVirtAddr = 0xffff800000000000
const Addr	GDTVirtAddr = 0xffff800000001000
const Addr	IDTVirtAddr = 0xffff800000002000
const Addr	TSSVirtAddr = 0xffff800000003000
const Addr	TSSPhysAddr = 0x63000
const Addr	ISTVirtAddr = 0xffff800000004000
const Addr	PFHandlerVirtAddr = 0xffff800000005000
const Addr	MMIORegionVirtAddr = 0xffffc90000000000
const Addr	MMIORegionPhysAddr = 0xffff0000
const StaticInstPtr	badMicroop
	destination
Bitfield< 15, 8 >	vector
Bitfield< 18, 16 >	deliveryMode
Bitfield< 19 >	destMode
Bitfield< 20 >	level
Bitfield< 21 >	trigger
static const Addr	TriggerIntOffset = 0
const ByteOrder	GuestByteOrder = ByteOrder::little
const Addr	PageShift = 12
const Addr	PageBytes = ULL(1) << PageShift
const Request::FlagsType M5_VAR_USED	SegmentFlagMask = mask(4)
const int	FlagShift = 4
	longl1
Bitfield< 29, 21 >	longl2
Bitfield< 38, 30 >	longl3
Bitfield< 47, 39 >	longl4
Bitfield< 20, 12 >	pael1
Bitfield< 29, 21 >	pael2
Bitfield< 31, 30 >	pael3
Bitfield< 21, 12 >	norml1
Bitfield< 31, 22 >	norml2
Bitfield< 51, 12 >	base
Bitfield< 11, 9 >	avl
Bitfield< 8 >	g
Bitfield< 7 >	ps
Bitfield< 6 >	d
Bitfield< 5 >	a
Bitfield< 4 >	pcd
Bitfield< 3 >	pwt
Bitfield< 2 >	u
Bitfield< 1 >	w
Bitfield< 0 >	p
const int	NumMiscRegs = NUM_MISCREGS
const int	NumIntArchRegs = NUM_INTREGS
const int	NumIntRegs = NumIntArchRegs + NumMicroIntRegs + NumImplicitIntRegs
const int	NumCCRegs = NUM_CCREGS
const int	NumFloatRegs
const int	NumVecRegs = 1
const int	NumVecPredRegs = 1
const int	ZeroReg = NUM_INTREGS
const int	StackPointerReg = INTREG_RSP
const int	ReturnAddressReg = 0
const int	ReturnValueReg = INTREG_RAX
const int	FramePointerReg = INTREG_RBP
const int	SyscallPseudoReturnReg = INTREG_RDX
constexpr unsigned	NumVecElemPerVecReg = ::DummyNumVecElemPerVecReg
constexpr size_t	VecRegSizeBytes = ::DummyVecRegSizeBytes
constexpr size_t	VecPredRegSizeBits = ::DummyVecPredRegSizeBits
constexpr bool	VecPredRegHasPackedRepr = ::DummyVecPredRegHasPackedRepr
Bitfield< 12 >	deliveryStatus
Bitfield< 19, 18 >	destShorthand
	R
SignedBitfield< 63, 0 >	SR
Bitfield< 31, 0 >	E
SignedBitfield< 31, 0 >	SE
Bitfield< 15, 0 >	X
SignedBitfield< 15, 0 >	SX
Bitfield< 15, 8 >	H
SignedBitfield< 15, 8 >	SH
Bitfield< 7, 0 >	L
SignedBitfield< 7, 0 >	SL
static const IntRegIndex	IntFoldBit = (IntRegIndex)(1 << 6)
const uint32_t	cfofMask = CFBit | OFBit
const uint32_t	ccFlagMask = PFBit | AFBit | ZFBit | SFBit
Bitfield< 7 >	sf
Bitfield< 6 >	zf
Bitfield< 5 >	ezf
Bitfield< 4 >	af
Bitfield< 3 >	ecf
Bitfield< 2 >	pf
Bitfield< 0 >	cf
Bitfield< 20 >	vip
Bitfield< 19 >	vif
Bitfield< 18 >	ac
Bitfield< 17 >	vm
Bitfield< 16 >	rf
Bitfield< 14 >	nt
Bitfield< 13, 12 >	iopl
Bitfield< 11 >	of
Bitfield< 10 >	df
Bitfield< 9 >	intf
Bitfield< 8 >	tf
Bitfield< 3, 1 >	submode
Bitfield< 5, 4 >	cpl
Bitfield< 6 >	paging
Bitfield< 7 >	prot
Bitfield< 9, 8 >	defOp
Bitfield< 11, 10 >	altOp
Bitfield< 13, 12 >	defAddr
Bitfield< 15, 14 >	altAddr
Bitfield< 17, 16 >	stack
Bitfield< 30 >	cd
Bitfield< 29 >	nw
Bitfield< 18 >	am
Bitfield< 16 >	wp
Bitfield< 5 >	ne
Bitfield< 4 >	et
Bitfield< 3 >	ts
Bitfield< 2 >	em
Bitfield< 1 >	mp
Bitfield< 0 >	pe
	legacy
	longPdtb
Bitfield< 31, 12 >	pdtb
Bitfield< 31, 5 >	paePdtb
Bitfield< 16 >	fsgsbase
Bitfield< 10 >	osxmmexcpt
Bitfield< 9 >	osfxsr
Bitfield< 8 >	pce
Bitfield< 7 >	pge
Bitfield< 6 >	mce
Bitfield< 5 >	pae
Bitfield< 4 >	pse
Bitfield< 3 >	de
Bitfield< 2 >	tsd
Bitfield< 1 >	pvi
Bitfield< 0 >	vme
	tpr
Bitfield< 1 >	b1
Bitfield< 2 >	b2
Bitfield< 3 >	b3
Bitfield< 13 >	bd
Bitfield< 14 >	bs
Bitfield< 15 >	bt
Bitfield< 1 >	g0
Bitfield< 2 >	l1
Bitfield< 3 >	g1
Bitfield< 4 >	l2
Bitfield< 5 >	g2
Bitfield< 6 >	l3
Bitfield< 7 >	g3
Bitfield< 8 >	le
Bitfield< 9 >	ge
Bitfield< 13 >	gd
Bitfield< 17, 16 >	rw0
Bitfield< 19, 18 >	len0
Bitfield< 21, 20 >	rw1
Bitfield< 23, 22 >	len1
Bitfield< 25, 24 >	rw2
Bitfield< 27, 26 >	len2
Bitfield< 29, 28 >	rw3
Bitfield< 31, 30 >	len3
	vcnt
Bitfield< 8 >	fix
Bitfield< 10 >	wc
	targetCS
	targetESP
	targetEIP
	count
Bitfield< 8 >	MCGCP
Bitfield< 1 >	eipv
Bitfield< 2 >	mcip
Bitfield< 1 >	btf
Bitfield< 2 >	pb0
Bitfield< 3 >	pb1
Bitfield< 4 >	pb2
Bitfield< 5 >	pb3
	type
Bitfield< 51, 12 >	physbase
Bitfield< 51, 12 >	physmask
Bitfield< 10 >	fe
Bitfield< 11 >	e
	mcaErrorCode
Bitfield< 31, 16 >	modelSpecificCode
Bitfield< 56, 32 >	otherInfo
Bitfield< 57 >	pcc
Bitfield< 58 >	addrv
Bitfield< 59 >	miscv
Bitfield< 60 >	en
Bitfield< 61 >	uc
Bitfield< 62 >	over
Bitfield< 63 >	val
Bitfield< 8 >	lme
Bitfield< 10 >	lma
Bitfield< 11 >	nxe
Bitfield< 12 >	svme
Bitfield< 14 >	ffxsr
	targetEip
Bitfield< 47, 32 >	syscallCsAndSs
Bitfield< 63, 48 >	sysretCsAndSs
	mask
	eventMask
Bitfield< 15, 8 >	unitMask
Bitfield< 16 >	usr
Bitfield< 17 >	os
Bitfield< 19 >	pc
Bitfield< 20 >	intEn
Bitfield< 23 >	inv
Bitfield< 31, 24 >	counterMask
Bitfield< 19 >	mfdm
Bitfield< 20 >	mvdm
Bitfield< 21 >	tom2
Bitfield< 4 >	rd
	physAddr
Bitfield< 1 >	rInit
Bitfield< 2 >	disA20M
Bitfield< 1 >	enter
Bitfield< 2 >	smiCycle
Bitfield< 3 >	exit
Bitfield< 4 >	rsmCycle
	esi
Bitfield< 15, 3 >	si
Bitfield< 2 >	ti
Bitfield< 1, 0 >	rpl
	baseHigh
Bitfield< 39, 16 >	baseLow
Bitfield< 54 >	b
Bitfield< 53 >	l
Bitfield< 51, 48 >	limitHigh
Bitfield< 15, 0 >	limitLow
BitfieldType< SegDescriptorLimit >	limit
Bitfield< 46, 45 >	dpl
Bitfield< 44 >	s
Bitfield< 42 >	c
Bitfield< 41 >	r
Bitfield< 2 >	unusable
Bitfield< 3 >	defaultSize
Bitfield< 4 >	longMode
Bitfield< 6 >	granularity
Bitfield< 7 >	present
Bitfield< 12 >	writable
Bitfield< 13 >	readable
Bitfield< 14 >	expandDown
Bitfield< 15 >	system
	offsetHigh
Bitfield< 15, 0 >	offsetLow
Bitfield< 31, 16 >	selector
Bitfield< 35, 32 >	IST
	offset
Bitfield< 11 >	enable
Bitfield< 8 >	bsp
const MsrMap::value_type	msrMapData []
static const unsigned	msrMapSize = sizeof(msrMapData) / sizeof(msrMapData[0])
const MsrMap	msrMap
	Map between MSR addresses and their corresponding misc registers. More...
	decodeVal
Bitfield< 7 >	repne
Bitfield< 6 >	rep
Bitfield< 5 >	lock
Bitfield< 4 >	op
Bitfield< 3 >	addr
Bitfield< 2, 0 >	seg
	mod
Bitfield< 5, 3 >	reg
Bitfield< 2, 0 >	rm
	scale
Bitfield< 5, 3 >	index
Bitfield< 1 >	x
Bitfield< 4, 0 >	m
Bitfield< 6, 3 >	v
	top5
Bitfield< 2, 0 >	bottom3
const int	NumMicroIntRegs = 16
const int	NumImplicitIntRegs = 6
const int	NumMMXRegs = 8
const int	NumXMMRegs = 16
const int	NumMicroFpRegs = 8
const int	NumCRegs = 16
const int	NumDRegs = 8
const int	NumSegments = 6
const int	NumSysSegments = 4
const Addr	IntAddrPrefixMask = ULL(0xffffffff00000000)
const Addr	IntAddrPrefixCPUID = ULL(0x100000000)
const Addr	IntAddrPrefixMSR = ULL(0x200000000)
const Addr	IntAddrPrefixIO = ULL(0x300000000)
const Addr	PhysAddrPrefixIO = ULL(0x8000000000000000)
const Addr	PhysAddrPrefixPciConfig = ULL(0xC000000000000000)
const Addr	PhysAddrPrefixLocalAPIC = ULL(0x2000000000000000)
const Addr	PhysAddrPrefixInterrupts = ULL(0xA000000000000000)
const Addr	PhysAddrAPICRangeSize = 1 << 12

Detailed Description

This is exposed globally, independent of the ISA.

Typedef Documentation

ConstVecPredReg

using X86ISA::ConstVecPredReg = typedef ::DummyConstVecPredReg

Definition at line 105 of file registers.hh.

ConstVecReg

using X86ISA::ConstVecReg = typedef ::DummyConstVecReg

Definition at line 98 of file registers.hh.

MachInst

typedef uint64_t X86ISA::MachInst

Definition at line 52 of file types.hh.

MsrMap

typedef std::unordered_map<Addr, MiscRegIndex> X86ISA::MsrMap

Definition at line 40 of file msr.hh.

MsrVal

typedef MsrMap::value_type X86ISA::MsrVal

Definition at line 34 of file msr.cc.

VecElem

using X86ISA::VecElem = typedef ::DummyVecElem

Definition at line 96 of file registers.hh.

VecPredReg

using X86ISA::VecPredReg = typedef ::DummyVecPredReg

Definition at line 104 of file registers.hh.

VecPredRegContainer

using X86ISA::VecPredRegContainer = typedef ::DummyVecPredRegContainer

Definition at line 106 of file registers.hh.

VecReg

using X86ISA::VecReg = typedef ::DummyVecReg

Definition at line 97 of file registers.hh.

VecRegContainer

using X86ISA::VecRegContainer = typedef ::DummyVecRegContainer

Definition at line 99 of file registers.hh.

Enumeration Type Documentation

ApicRegIndex

enum X86ISA::ApicRegIndex

Enumerator
APIC_ID
APIC_VERSION
APIC_TASK_PRIORITY
APIC_ARBITRATION_PRIORITY
APIC_PROCESSOR_PRIORITY
APIC_EOI
APIC_LOGICAL_DESTINATION
APIC_DESTINATION_FORMAT
APIC_SPURIOUS_INTERRUPT_VECTOR
APIC_IN_SERVICE_BASE
APIC_TRIGGER_MODE_BASE
APIC_INTERRUPT_REQUEST_BASE
APIC_ERROR_STATUS
APIC_INTERRUPT_COMMAND_LOW
APIC_INTERRUPT_COMMAND_HIGH
APIC_LVT_TIMER
APIC_LVT_THERMAL_SENSOR
APIC_LVT_PERFORMANCE_MONITORING_COUNTERS
APIC_LVT_LINT0
APIC_LVT_LINT1
APIC_LVT_ERROR
APIC_INITIAL_COUNT
APIC_CURRENT_COUNT
APIC_DIVIDE_CONFIGURATION
APIC_INTERNAL_STATE
NUM_APIC_REGS

Definition at line 36 of file apic.hh.

CCRegIndex

enum X86ISA::CCRegIndex

Enumerator
CCREG_ZAPS
CCREG_CFOF
CCREG_DF
CCREG_ECF
CCREG_EZF
NUM_CCREGS

Definition at line 45 of file ccr.hh.

CondFlagBit

enum X86ISA::CondFlagBit

Enumerator
CFBit
PFBit
ECFBit
AFBit
EZFBit
ZFBit
SFBit
DFBit
OFBit

Definition at line 54 of file misc.hh.

DependenceTags

enum X86ISA::DependenceTags

Enumerator
FP_Reg_Base
CC_Reg_Base
Misc_Reg_Base
Max_Reg_Index

Definition at line 67 of file registers.hh.

ExtendedCpuidFunctions

enum X86ISA::ExtendedCpuidFunctions

Enumerator
VendorAndLargestExtFunc
FamilyModelSteppingBrandFeatures
NameString1
NameString2
NameString3
L1CacheAndTLB
L2L3CacheAndL2TLB
APMInfo
LongModeAddressSize
NumExtendedCpuidFuncs

Definition at line 47 of file cpuid.cc.

FlagBit

enum X86ISA::FlagBit

Enumerator
CPL0FlagBit
AddrSizeFlagBit
StoreCheck

Definition at line 51 of file ldstflags.hh.

FloatRegIndex

enum X86ISA::FloatRegIndex

Enumerator
FLOATREG_MMX_BASE
FLOATREG_FPR_BASE
FLOATREG_MMX0
FLOATREG_MMX1
FLOATREG_MMX2
FLOATREG_MMX3
FLOATREG_MMX4
FLOATREG_MMX5
FLOATREG_MMX6
FLOATREG_MMX7
FLOATREG_FPR0
FLOATREG_FPR1
FLOATREG_FPR2
FLOATREG_FPR3
FLOATREG_FPR4
FLOATREG_FPR5
FLOATREG_FPR6
FLOATREG_FPR7
FLOATREG_XMM_BASE
FLOATREG_XMM0_LOW
FLOATREG_XMM0_HIGH
FLOATREG_XMM1_LOW
FLOATREG_XMM1_HIGH
FLOATREG_XMM2_LOW
FLOATREG_XMM2_HIGH
FLOATREG_XMM3_LOW
FLOATREG_XMM3_HIGH
FLOATREG_XMM4_LOW
FLOATREG_XMM4_HIGH
FLOATREG_XMM5_LOW
FLOATREG_XMM5_HIGH
FLOATREG_XMM6_LOW
FLOATREG_XMM6_HIGH
FLOATREG_XMM7_LOW
FLOATREG_XMM7_HIGH
FLOATREG_XMM8_LOW
FLOATREG_XMM8_HIGH
FLOATREG_XMM9_LOW
FLOATREG_XMM9_HIGH
FLOATREG_XMM10_LOW
FLOATREG_XMM10_HIGH
FLOATREG_XMM11_LOW
FLOATREG_XMM11_HIGH
FLOATREG_XMM12_LOW
FLOATREG_XMM12_HIGH
FLOATREG_XMM13_LOW
FLOATREG_XMM13_HIGH
FLOATREG_XMM14_LOW
FLOATREG_XMM14_HIGH
FLOATREG_XMM15_LOW
FLOATREG_XMM15_HIGH
FLOATREG_MICROFP_BASE
FLOATREG_MICROFP0
FLOATREG_MICROFP1
FLOATREG_MICROFP2
FLOATREG_MICROFP3
FLOATREG_MICROFP4
FLOATREG_MICROFP5
FLOATREG_MICROFP6
FLOATREG_MICROFP7
NUM_FLOATREGS

Definition at line 46 of file float.hh.

MediaFlag

enum X86ISA::MediaFlag

Enumerator
MediaMultHiOp
MediaSignedOp
MediaScalarOp

Definition at line 36 of file micromediaop.hh.

MiscRegIndex

enum X86ISA::MiscRegIndex

Enumerator
MISCREG_CR_BASE
MISCREG_CR0
MISCREG_CR1
MISCREG_CR2
MISCREG_CR3
MISCREG_CR4
MISCREG_CR5
MISCREG_CR6
MISCREG_CR7
MISCREG_CR8
MISCREG_CR9
MISCREG_CR10
MISCREG_CR11
MISCREG_CR12
MISCREG_CR13
MISCREG_CR14
MISCREG_CR15
MISCREG_DR_BASE
MISCREG_DR0
MISCREG_DR1
MISCREG_DR2
MISCREG_DR3
MISCREG_DR4
MISCREG_DR5
MISCREG_DR6
MISCREG_DR7
MISCREG_RFLAGS
MISCREG_M5_REG
MISCREG_TSC
MISCREG_MTRRCAP
MISCREG_SYSENTER_CS
MISCREG_SYSENTER_ESP
MISCREG_SYSENTER_EIP
MISCREG_MCG_CAP
MISCREG_MCG_STATUS
MISCREG_MCG_CTL
MISCREG_DEBUG_CTL_MSR
MISCREG_LAST_BRANCH_FROM_IP
MISCREG_LAST_BRANCH_TO_IP
MISCREG_LAST_EXCEPTION_FROM_IP
MISCREG_LAST_EXCEPTION_TO_IP
MISCREG_MTRR_PHYS_BASE_BASE
MISCREG_MTRR_PHYS_BASE_0
MISCREG_MTRR_PHYS_BASE_1
MISCREG_MTRR_PHYS_BASE_2
MISCREG_MTRR_PHYS_BASE_3
MISCREG_MTRR_PHYS_BASE_4
MISCREG_MTRR_PHYS_BASE_5
MISCREG_MTRR_PHYS_BASE_6
MISCREG_MTRR_PHYS_BASE_7
MISCREG_MTRR_PHYS_BASE_END
MISCREG_MTRR_PHYS_MASK_BASE
MISCREG_MTRR_PHYS_MASK_0
MISCREG_MTRR_PHYS_MASK_1
MISCREG_MTRR_PHYS_MASK_2
MISCREG_MTRR_PHYS_MASK_3
MISCREG_MTRR_PHYS_MASK_4
MISCREG_MTRR_PHYS_MASK_5
MISCREG_MTRR_PHYS_MASK_6
MISCREG_MTRR_PHYS_MASK_7
MISCREG_MTRR_PHYS_MASK_END
MISCREG_MTRR_FIX_64K_00000
MISCREG_MTRR_FIX_16K_80000
MISCREG_MTRR_FIX_16K_A0000
MISCREG_MTRR_FIX_4K_C0000
MISCREG_MTRR_FIX_4K_C8000
MISCREG_MTRR_FIX_4K_D0000
MISCREG_MTRR_FIX_4K_D8000
MISCREG_MTRR_FIX_4K_E0000
MISCREG_MTRR_FIX_4K_E8000
MISCREG_MTRR_FIX_4K_F0000
MISCREG_MTRR_FIX_4K_F8000
MISCREG_PAT
MISCREG_DEF_TYPE
MISCREG_MC_CTL_BASE
MISCREG_MC0_CTL
MISCREG_MC1_CTL
MISCREG_MC2_CTL
MISCREG_MC3_CTL
MISCREG_MC4_CTL
MISCREG_MC5_CTL
MISCREG_MC6_CTL
MISCREG_MC7_CTL
MISCREG_MC_CTL_END
MISCREG_MC_STATUS_BASE
MISCREG_MC0_STATUS
MISCREG_MC1_STATUS
MISCREG_MC2_STATUS
MISCREG_MC3_STATUS
MISCREG_MC4_STATUS
MISCREG_MC5_STATUS
MISCREG_MC6_STATUS
MISCREG_MC7_STATUS
MISCREG_MC_STATUS_END
MISCREG_MC_ADDR_BASE
MISCREG_MC0_ADDR
MISCREG_MC1_ADDR
MISCREG_MC2_ADDR
MISCREG_MC3_ADDR
MISCREG_MC4_ADDR
MISCREG_MC5_ADDR
MISCREG_MC6_ADDR
MISCREG_MC7_ADDR
MISCREG_MC_ADDR_END
MISCREG_MC_MISC_BASE
MISCREG_MC0_MISC
MISCREG_MC1_MISC
MISCREG_MC2_MISC
MISCREG_MC3_MISC
MISCREG_MC4_MISC
MISCREG_MC5_MISC
MISCREG_MC6_MISC
MISCREG_MC7_MISC
MISCREG_MC_MISC_END
MISCREG_EFER
MISCREG_STAR
MISCREG_LSTAR
MISCREG_CSTAR
MISCREG_SF_MASK
MISCREG_KERNEL_GS_BASE
MISCREG_TSC_AUX
MISCREG_PERF_EVT_SEL_BASE
MISCREG_PERF_EVT_SEL0
MISCREG_PERF_EVT_SEL1
MISCREG_PERF_EVT_SEL2
MISCREG_PERF_EVT_SEL3
MISCREG_PERF_EVT_SEL_END
MISCREG_PERF_EVT_CTR_BASE
MISCREG_PERF_EVT_CTR0
MISCREG_PERF_EVT_CTR1
MISCREG_PERF_EVT_CTR2
MISCREG_PERF_EVT_CTR3
MISCREG_PERF_EVT_CTR_END
MISCREG_SYSCFG
MISCREG_IORR_BASE_BASE
MISCREG_IORR_BASE0
MISCREG_IORR_BASE1
MISCREG_IORR_BASE_END
MISCREG_IORR_MASK_BASE
MISCREG_IORR_MASK0
MISCREG_IORR_MASK1
MISCREG_IORR_MASK_END
MISCREG_TOP_MEM
MISCREG_TOP_MEM2
MISCREG_VM_CR
MISCREG_IGNNE
MISCREG_SMM_CTL
MISCREG_VM_HSAVE_PA
MISCREG_SEG_SEL_BASE
MISCREG_ES
MISCREG_CS
MISCREG_SS
MISCREG_DS
MISCREG_FS
MISCREG_GS
MISCREG_HS
MISCREG_TSL
MISCREG_TSG
MISCREG_LS
MISCREG_MS
MISCREG_TR
MISCREG_IDTR
MISCREG_SEG_BASE_BASE
MISCREG_ES_BASE
MISCREG_CS_BASE
MISCREG_SS_BASE
MISCREG_DS_BASE
MISCREG_FS_BASE
MISCREG_GS_BASE
MISCREG_HS_BASE
MISCREG_TSL_BASE
MISCREG_TSG_BASE
MISCREG_LS_BASE
MISCREG_MS_BASE
MISCREG_TR_BASE
MISCREG_IDTR_BASE
MISCREG_SEG_EFF_BASE_BASE
MISCREG_ES_EFF_BASE
MISCREG_CS_EFF_BASE
MISCREG_SS_EFF_BASE
MISCREG_DS_EFF_BASE
MISCREG_FS_EFF_BASE
MISCREG_GS_EFF_BASE
MISCREG_HS_EFF_BASE
MISCREG_TSL_EFF_BASE
MISCREG_TSG_EFF_BASE
MISCREG_LS_EFF_BASE
MISCREG_MS_EFF_BASE
MISCREG_TR_EFF_BASE
MISCREG_IDTR_EFF_BASE
MISCREG_SEG_LIMIT_BASE
MISCREG_ES_LIMIT
MISCREG_CS_LIMIT
MISCREG_SS_LIMIT
MISCREG_DS_LIMIT
MISCREG_FS_LIMIT
MISCREG_GS_LIMIT
MISCREG_HS_LIMIT
MISCREG_TSL_LIMIT
MISCREG_TSG_LIMIT
MISCREG_LS_LIMIT
MISCREG_MS_LIMIT
MISCREG_TR_LIMIT
MISCREG_IDTR_LIMIT
MISCREG_SEG_ATTR_BASE
MISCREG_ES_ATTR
MISCREG_CS_ATTR
MISCREG_SS_ATTR
MISCREG_DS_ATTR
MISCREG_FS_ATTR
MISCREG_GS_ATTR
MISCREG_HS_ATTR
MISCREG_TSL_ATTR
MISCREG_TSG_ATTR
MISCREG_LS_ATTR
MISCREG_MS_ATTR
MISCREG_TR_ATTR
MISCREG_IDTR_ATTR
MISCREG_X87_TOP
MISCREG_MXCSR
MISCREG_FCW
MISCREG_FSW
MISCREG_FTW
MISCREG_FTAG
MISCREG_FISEG
MISCREG_FIOFF
MISCREG_FOSEG
MISCREG_FOOFF
MISCREG_FOP
MISCREG_APIC_BASE
MISCREG_PCI_CONFIG_ADDRESS
NUM_MISCREGS

Definition at line 100 of file misc.hh.

Prefixes

enum X86ISA::Prefixes

Enumerator
NoOverride
ESOverride
CSOverride
SSOverride
DSOverride
FSOverride
GSOverride
RexPrefix
OperandSizeOverride
AddressSizeOverride
Lock
Rep
Repne
Vex2Prefix
Vex3Prefix
XopPrefix

Definition at line 54 of file types.hh.

RFLAGBit

enum X86ISA::RFLAGBit

Enumerator
TFBit
IFBit
NTBit
RFBit
VMBit
ACBit
VIFBit
VIPBit
IDBit

Definition at line 69 of file misc.hh.

SegmentRegIndex

enum X86ISA::SegmentRegIndex

Enumerator
SEGMENT_REG_ES
SEGMENT_REG_CS
SEGMENT_REG_SS
SEGMENT_REG_DS
SEGMENT_REG_FS
SEGMENT_REG_GS
SEGMENT_REG_HS
SEGMENT_REG_TSL
SEGMENT_REG_TSG
SEGMENT_REG_LS
SEGMENT_REG_MS
SYS_SEGMENT_REG_TR
SYS_SEGMENT_REG_IDTR
NUM_SEGMENTREGS

Definition at line 43 of file segment.hh.

SizeType

enum X86ISA::SizeType

Enumerator
NoImm
NI
ByteImm
BY
WordImm
WO
DWordImm
DW
QWordImm
QW
OWordImm
OW
VWordImm
VW
ZWordImm
ZW
Enter
EN
Pointer
PO

Definition at line 167 of file decoder_tables.cc.

StandardCpuidFunction

enum X86ISA::StandardCpuidFunction

Enumerator
VendorAndLargestStdFunc
FamilyModelStepping
CacheAndTLB
SerialNumber
CacheParams
MonitorMwait
ThermalPowerMgmt
ExtendedFeatures
NumStandardCpuidFuncs

Definition at line 35 of file cpuid.cc.

X86AuxiliaryVectorTypes

enum X86ISA::X86AuxiliaryVectorTypes

Enumerator
M5_AT_SYSINFO
M5_AT_SYSINFO_EHDR

Definition at line 53 of file process.hh.

X86SubMode

enum X86ISA::X86SubMode

Enumerator
SixtyFourBitMode
CompatabilityMode
ProtectedMode
Virtual8086Mode
RealMode

Definition at line 189 of file types.hh.

X87StatusBit

enum X86ISA::X87StatusBit

Enumerator
IEBit
DEBit
ZEBit
OEBit
UEBit
PEBit
StackFaultBit
ErrSummaryBit
CC0Bit
CC1Bit
CC2Bit
CC3Bit
BusyBit

Definition at line 81 of file misc.hh.

Function Documentation

advancePC()

void X86ISA::advancePC ( PCState &  pc, const StaticInstPtr &  inst  )

inline

Definition at line 75 of file utility.hh.

References StaticInst::advancePC(), and pc.

APIC_IN_SERVICE()

static ApicRegIndex X86ISA::APIC_IN_SERVICE ( int  index )

inlinestatic

Definition at line 73 of file apic.hh.

References APIC_IN_SERVICE_BASE, and index.

Referenced by decodeAddr(), and X86ISA::Interrupts::setReg().

APIC_INTERRUPT_REQUEST()

static ApicRegIndex X86ISA::APIC_INTERRUPT_REQUEST ( int  index )

inlinestatic

Definition at line 85 of file apic.hh.

References APIC_INTERRUPT_REQUEST_BASE, and index.

Referenced by decodeAddr(), and X86ISA::Interrupts::setReg().

APIC_TRIGGER_MODE()

static ApicRegIndex X86ISA::APIC_TRIGGER_MODE ( int  index )

inlinestatic

Definition at line 79 of file apic.hh.

References APIC_TRIGGER_MODE_BASE, and index.

Referenced by decodeAddr(), X86ISA::Interrupts::readReg(), and X86ISA::Interrupts::setReg().

BitUnion32() [1/2]

X86ISA::BitUnion32

(

InterruptCommandRegLow

)

BitUnion32() [2/2]

X86ISA::BitUnion32

(

TriggerIntMessage

)

BitUnion64() [1/4]

X86ISA::BitUnion64

(

CCFlagBits

)

A type to describe the condition code bits of the RFLAGS register, plus two flags, EZF and ECF, which are only visible to microcode.

BitUnion64() [2/4]

X86ISA::BitUnion64

(

SegDescriptor

)

BitUnion64() [3/4]

X86ISA::BitUnion64

(

VAddr

)

BitUnion64() [4/4]

X86ISA::BitUnion64

(

X86IntReg

)

BitUnion8() [1/2]

X86ISA::BitUnion8

(

LegacyPrefixVector

)

BitUnion8() [2/2]

X86ISA::BitUnion8

(

Opcode

)

buildIntPacket()

template<class T >

PacketPtr X86ISA::buildIntPacket	(	Addr	addr,
		T	payload
	)

Definition at line 86 of file intdev.hh.

References addr, Packet::allocate(), Request::intRequestorId, Packet::setRaw(), Request::UNCACHEABLE, and MemCmd::WriteReq.

Referenced by buildIntTriggerPacket().

buildIntTriggerPacket()

static PacketPtr X86ISA::buildIntTriggerPacket ( int  id, TriggerIntMessage  message  )

inlinestatic

Definition at line 79 of file intmessage.hh.

References addr, buildIntPacket(), TriggerIntOffset, and x86InterruptAddress().

Referenced by X86ISA::Interrupts::setReg(), and X86ISA::I82094AA::signalInterrupt().

buildRetPC()

PCState X86ISA::buildRetPC ( const PCState &  curPC, const PCState &  callPC  )

inline

Definition at line 49 of file utility.hh.

References X86ISA::PCState::uEnd().

convX87TagsToXTags()

uint8_t X86ISA::convX87TagsToXTags

(

uint16_t

ftw

)

Convert an x87 tag word to abridged tag format.

Convert from the x87 tag representation to the tag abridged representation used in the FXSAVE area. The classic format uses 2 bits per stack position to indicate if a position is valid, zero, special, or empty. The abridged format only stores whether a position is empty or not.

Parameters

ftw	Tag word in classic x87 format.

Returns

Tag word in the abridged format.

Definition at line 142 of file utility.cc.

References ArmISA::i.

Referenced by updateKvmStateFPUCommon().

convX87XTagsToTags()

uint16_t X86ISA::convX87XTagsToTags

(

uint8_t

ftwx

)

Convert an x87 xtag word to normal tags format.

Convert from the abridged x87 tag representation used in the FXSAVE area to a full x87 tag. The classic format uses 2 bits per stack position to indicate if a position is valid, zero, special, or empty. The abridged format only stores whether a position is empty or not.

Todo:

Reconstruct the correct state of stack positions instead of just valid/invalid.

Parameters

ftwx	Tag word in the abridged format.

Returns

Tag word in classic x87 format.

Definition at line 167 of file utility.cc.

References ArmISA::i.

Referenced by updateThreadContextFPUCommon().

copyMiscRegs()

void X86ISA::copyMiscRegs	(	ThreadContext *	src,
		ThreadContext *	dest
	)

Definition at line 73 of file utility.cc.

References BaseTLB::flushAll(), ThreadContext::getDTBPtr(), ThreadContext::getITBPtr(), ArmISA::i, isValidMiscReg(), MISCREG_TSC, NUM_MISCREGS, ThreadContext::readMiscReg(), ThreadContext::readMiscRegNoEffect(), ThreadContext::setMiscReg(), and ThreadContext::setMiscRegNoEffect().

Referenced by copyRegs().

copyRegs()

void X86ISA::copyRegs	(	ThreadContext *	src,
		ThreadContext *	dest
	)

Definition at line 94 of file utility.cc.

References copyMiscRegs(), ArmISA::i, NumCCRegs, NumFloatRegs, NumIntRegs, ThreadContext::pcState(), ThreadContext::readCCRegFlat(), ThreadContext::readFloatRegFlat(), ThreadContext::readIntRegFlat(), ThreadContext::setCCRegFlat(), ThreadContext::setFloatRegFlat(), and ThreadContext::setIntRegFlat().

Referenced by X86Linux::archClone().

decodeAddr()

ApicRegIndex X86ISA::decodeAddr

(

Addr

paddr

)

Definition at line 81 of file interrupts.cc.

References APIC_ARBITRATION_PRIORITY, APIC_CURRENT_COUNT, APIC_DESTINATION_FORMAT, APIC_DIVIDE_CONFIGURATION, APIC_EOI, APIC_ERROR_STATUS, APIC_ID, APIC_IN_SERVICE(), APIC_INITIAL_COUNT, APIC_INTERRUPT_COMMAND_HIGH, APIC_INTERRUPT_COMMAND_LOW, APIC_INTERRUPT_REQUEST(), APIC_LOGICAL_DESTINATION, APIC_LVT_ERROR, APIC_LVT_LINT0, APIC_LVT_LINT1, APIC_LVT_PERFORMANCE_MONITORING_COUNTERS, APIC_LVT_THERMAL_SENSOR, APIC_LVT_TIMER, APIC_PROCESSOR_PRIORITY, APIC_SPURIOUS_INTERRUPT_VECTOR, APIC_TASK_PRIORITY, APIC_TRIGGER_MODE(), APIC_VERSION, mask, and panic.

Referenced by X86ISA::Interrupts::read(), and X86ISA::Interrupts::write().

doCpuid()

bool X86ISA::doCpuid	(	ThreadContext *	tc,
		uint32_t	function,
		uint32_t	index,
		CpuidResult &	result
	)

Definition at line 87 of file cpuid.cc.

References APMInfo, bits(), ExtendedFeatures, FamilyModelStepping, FamilyModelSteppingBrandFeatures, L1CacheAndTLB, L2L3CacheAndL2TLB, LongModeAddressSize, nameString, NameString1, NameString2, NameString3, nameStringSize, NumExtendedCpuidFuncs, NumStandardCpuidFuncs, offset, stringToRegister(), VendorAndLargestExtFunc, VendorAndLargestStdFunc, vendorString, vendorStringSize, and warn.

Referenced by X86KvmCPU::updateCPUID().

EndBitUnion() [1/53]

X86ISA::EndBitUnion

(

CCFlagBits

)

RFLAGS.

EndBitUnion() [2/53]

X86ISA::EndBitUnion

(

CR0

)

EndBitUnion() [3/53]

X86ISA::EndBitUnion

(

CR2

)

EndBitUnion() [4/53]

X86ISA::EndBitUnion

(

CR3

)

EndBitUnion() [5/53]

X86ISA::EndBitUnion

(

CR4

)

EndBitUnion() [6/53]

X86ISA::EndBitUnion

(

CR8

)

EndBitUnion() [7/53]

X86ISA::EndBitUnion

(

DebugCtlMsr

)

EndBitUnion() [8/53]

X86ISA::EndBitUnion

(

DR6

)

EndBitUnion() [9/53]

X86ISA::EndBitUnion

(

DR7

)

EndBitUnion() [10/53]

X86ISA::EndBitUnion

(

Efer

)

EndBitUnion() [11/53]

X86ISA::EndBitUnion

(

GateDescriptor

)

Long Mode Gate Descriptor.

EndBitUnion() [12/53]

X86ISA::EndBitUnion

(

GateDescriptorHigh

)

Descriptor-Table Registers.

Task Register Local APIC Base Register

EndBitUnion() [13/53]

X86ISA::EndBitUnion

(

GateDescriptorLow

)

EndBitUnion() [14/53]

X86ISA::EndBitUnion

(

HandyM5Reg

)

Control registers.

EndBitUnion() [15/53]

X86ISA::EndBitUnion

(

IgnneMsr

)

EndBitUnion() [16/53]

X86ISA::EndBitUnion

(

InterruptCommandRegLow

)

EndBitUnion() [17/53]

X86ISA::EndBitUnion

(

IorrBase

)

EndBitUnion() [18/53]

X86ISA::EndBitUnion

(

IorrMask

)

EndBitUnion() [19/53]

X86ISA::EndBitUnion

(

LegacyPrefixVector

)

EndBitUnion() [20/53]

X86ISA::EndBitUnion

(

McgCap

)

EndBitUnion() [21/53]

X86ISA::EndBitUnion

(

McgStatus

)

EndBitUnion() [22/53]

X86ISA::EndBitUnion

(

McStatus

)

EndBitUnion() [23/53]

X86ISA::EndBitUnion

(

ModRM

)

EndBitUnion() [24/53]

X86ISA::EndBitUnion

(

MTRRcap

)

SYSENTER configuration registers.

EndBitUnion() [25/53]

X86ISA::EndBitUnion

(

MtrrDefType

)

Machine check.

EndBitUnion() [26/53]

X86ISA::EndBitUnion

(

MtrrPhysBase

)

EndBitUnion() [27/53]

X86ISA::EndBitUnion

(

MtrrPhysMask

)

EndBitUnion() [28/53]

X86ISA::EndBitUnion

(

Opcode

)

EndBitUnion() [29/53]

X86ISA::EndBitUnion

(

OperatingMode

)

Definition at line 182 of file types.hh.

EndBitUnion() [30/53]

X86ISA::EndBitUnion

(

PageTableEntry

)

EndBitUnion() [31/53]

X86ISA::EndBitUnion

(

PerfEvtSel

)

EndBitUnion() [32/53]

X86ISA::EndBitUnion

(

Rex

)

EndBitUnion() [33/53]

X86ISA::EndBitUnion

(

RFLAGS

)

EndBitUnion() [34/53]

X86ISA::EndBitUnion

(

SegAttr

)

EndBitUnion() [35/53]

X86ISA::EndBitUnion

(

SegSelector

)

Segment Descriptors.

Definition at line 863 of file misc.hh.

References base, bits(), and replaceBits().

EndBitUnion() [36/53]

X86ISA::EndBitUnion

(

SfMask

)

EndBitUnion() [37/53]

X86ISA::EndBitUnion

(

Sib

)

EndBitUnion() [38/53]

X86ISA::EndBitUnion

(

SmmCtlMsr

)

Segment Selector.

EndBitUnion() [39/53]

X86ISA::EndBitUnion

(

Star

)

EndBitUnion() [40/53]

X86ISA::EndBitUnion

(

Syscfg

)

EndBitUnion() [41/53]

X86ISA::EndBitUnion

(

SysenterCS

)

EndBitUnion() [42/53]

X86ISA::EndBitUnion

(

SysenterEIP

)

Global machine check registers.

EndBitUnion() [43/53]

X86ISA::EndBitUnion

(

SysenterESP

)

EndBitUnion() [44/53]

X86ISA::EndBitUnion

(

Tom

)

EndBitUnion() [45/53]

X86ISA::EndBitUnion

(

TriggerIntMessage

)

Definition at line 49 of file intmessage.hh.

References ArmISA::mode.

EndBitUnion() [46/53]

X86ISA::EndBitUnion

(

TSShigh

)

EndBitUnion() [47/53]

X86ISA::EndBitUnion

(

VAddr

)

EndBitUnion() [48/53]

X86ISA::EndBitUnion

(

Vex2Of2

)

EndBitUnion() [49/53]

X86ISA::EndBitUnion

(

Vex2Of3

)

EndBitUnion() [50/53]

X86ISA::EndBitUnion

(

Vex3Of3

)

EndBitUnion() [51/53]

X86ISA::EndBitUnion

(

VexInfo

)

Definition at line 145 of file types.hh.

EndBitUnion() [52/53]

X86ISA::EndBitUnion

(

VmCrMsr

)

EndBitUnion() [53/53]

X86ISA::EndBitUnion

(

X86IntReg

)

Definition at line 59 of file int.hh.

References ArmISA::INTREG_R10, ArmISA::INTREG_R11, ArmISA::INTREG_R12, ArmISA::INTREG_R13, ArmISA::INTREG_R14, ArmISA::INTREG_R15, ArmISA::INTREG_R8, ArmISA::INTREG_R9, ArmISA::INTREG_SP, and ArmISA::NUM_INTREGS.

EndSubBitUnion()

X86ISA::EndSubBitUnion

(

type

)

TSS Descriptor (long mode - 128 bits) the lower 64 bits.

TSS Descriptor (long mode - 128 bits) the upper 64 bits.

FLOATREG_FPR()

static FloatRegIndex X86ISA::FLOATREG_FPR ( int  index )

inlinestatic

Definition at line 123 of file float.hh.

References FLOATREG_FPR_BASE, and index.

Referenced by FLOATREG_STACK(), updateKvmStateFPUCommon(), and updateThreadContextFPUCommon().

FLOATREG_MICROFP()

static FloatRegIndex X86ISA::FLOATREG_MICROFP ( int  index )

inlinestatic

Definition at line 141 of file float.hh.

References FLOATREG_MICROFP_BASE, and index.

FLOATREG_MMX()

static FloatRegIndex X86ISA::FLOATREG_MMX ( int  index )

inlinestatic

Definition at line 117 of file float.hh.

References FLOATREG_MMX_BASE, and index.

Referenced by Trace::X86NativeTrace::ThreadState::update().

FLOATREG_STACK()

static FloatRegIndex X86ISA::FLOATREG_STACK ( int  index, int  top  )

inlinestatic

Definition at line 147 of file float.hh.

References FLOATREG_FPR(), and index.

Referenced by X86ISA::ISA::flattenFloatIndex().

FLOATREG_XMM_HIGH()

static FloatRegIndex X86ISA::FLOATREG_XMM_HIGH ( int  index )

inlinestatic

Definition at line 135 of file float.hh.

References FLOATREG_XMM_BASE, and index.

Referenced by updateKvmStateFPUCommon(), and updateThreadContextFPUCommon().

FLOATREG_XMM_LOW()

static FloatRegIndex X86ISA::FLOATREG_XMM_LOW ( int  index )

inlinestatic

Definition at line 129 of file float.hh.

References FLOATREG_XMM_BASE, and index.

Referenced by updateKvmStateFPUCommon(), and updateThreadContextFPUCommon().

genX87Tags()

uint16_t X86ISA::genX87Tags	(	uint16_t	ftw,
		uint8_t	top,
		int8_t	spm
	)

Generate and updated x87 tag register after a push/pop operation.

Note

There is currently no support for setting other tags than valid and invalid. A real x87 will set the tag value to zero or special for some special floating point values.

Parameters

ftw	Current value of the FTW register.
top	Current x87 TOP value.
spm	Stack displacement.

Returns

New value of the FTW register.

Definition at line 188 of file utility.cc.

References ArmISA::i.

getArgument()

uint64_t X86ISA::getArgument	(	ThreadContext *	tc,
		int &	number,
		uint16_t	size,
		bool	fp
	)

Definition at line 51 of file utility.cc.

References ArmISA::fp, ArmISA::INTREG_R8, ArmISA::INTREG_R9, panic, and ThreadContext::readIntReg().

getExecutingAsid()

uint64_t X86ISA::getExecutingAsid ( ThreadContext *  tc )

inline

Definition at line 81 of file utility.hh.

getMem() [1/2]

template<size_t N>

static void X86ISA::getMem ( PacketPtr  pkt, std::array< uint64_t, N > &  mem, unsigned  dataSize, Trace::InstRecord *  traceData  )

static

Definition at line 86 of file memhelpers.hh.

References mem, panic, and Trace::InstRecord::setData().

getMem() [2/2]

static void X86ISA::getMem ( PacketPtr  pkt, uint64_t &  mem, unsigned  dataSize, Trace::InstRecord *  traceData  )

static

Definition at line 52 of file memhelpers.hh.

References Packet::getLE(), mem, panic, and Trace::InstRecord::setData().

getPackedMem()

template<typename T , size_t N>

static void X86ISA::getPackedMem ( PacketPtr  pkt, std::array< uint64_t, N > &  mem, unsigned  dataSize  )

static

Definition at line 77 of file memhelpers.hh.

References Packet::getLE(), ArmISA::i, and mem.

getRFlags()

uint64_t X86ISA::getRFlags

(

ThreadContext *

tc

)

Reconstruct the rflags register from the internal gem5 register state.

gem5 stores rflags in several different registers to avoid pipeline dependencies. In order to get the true rflags value, we can't simply read the value of MISCREG_RFLAGS. Instead, we need to read out various state from microcode registers and merge that with MISCREG_RFLAGS.

Parameters

tc	Thread context to read rflags from.

Returns

rflags as seen by the guest.

Definition at line 110 of file utility.cc.

References CCREG_CFOF, CCREG_DF, CCREG_ZAPS, MISCREG_RFLAGS, ThreadContext::readCCReg(), and ThreadContext::readMiscRegNoEffect().

Referenced by X86KvmCPU::updateKvmStateRegs().

initiateMemRead()

static Fault X86ISA::initiateMemRead ( ExecContext *  xc, Trace::InstRecord *  traceData, Addr  addr, unsigned  dataSize, Request::Flags  flags  )

static

Initiate a read from memory in timing mode.

Definition at line 45 of file memhelpers.hh.

References addr, and ExecContext::initiateMemRead().

installSegDesc()

void X86ISA::installSegDesc	(	ThreadContext *	tc,
		SegmentRegIndex	seg,
		SegDescriptor	desc,
		bool	longmode
	)

Definition at line 61 of file fs_workload.cc.

References ArmISA::attr, MISCREG_SEG_ATTR(), MISCREG_SEG_BASE(), MISCREG_SEG_EFF_BASE(), MISCREG_SEG_LIMIT(), seg, SEGMENT_REG_FS, SEGMENT_REG_GS, SEGMENT_REG_TSL, ThreadContext::setMiscReg(), and SYS_SEGMENT_REG_TR.

Referenced by X86ISA::FsWorkload::initState(), and X86ISA::X86_64Process::initState().

INTREG_FOLDED()

static IntRegIndex X86ISA::INTREG_FOLDED ( int  index, int  foldBit  )

inlinestatic

Definition at line 166 of file int.hh.

References index.

INTREG_IMPLICIT()

static IntRegIndex X86ISA::INTREG_IMPLICIT ( int  index )

inlinestatic

Definition at line 160 of file int.hh.

References index, ArmISA::NUM_INTREGS, and NumMicroIntRegs.

INTREG_MICRO()

static IntRegIndex X86ISA::INTREG_MICRO ( int  index )

inlinestatic

Definition at line 154 of file int.hh.

References index, and ArmISA::NUM_INTREGS.

Referenced by X86ISA::X86FaultBase::invoke().

inUserMode()

static bool X86ISA::inUserMode ( ThreadContext *  tc )

inlinestatic

Definition at line 60 of file utility.hh.

References FullSystem, MISCREG_M5_REG, and ThreadContext::readMiscRegNoEffect().

isValidMiscReg()

static bool X86ISA::isValidMiscReg ( int  index )

inlinestatic

Definition at line 402 of file misc.hh.

References index, MISCREG_CR0, MISCREG_CR1, MISCREG_CR15, MISCREG_CR4, MISCREG_CR8, and NUM_MISCREGS.

Referenced by copyMiscRegs(), X86ISA::ISA::readMiscRegNoEffect(), and X86ISA::ISA::setMiscRegNoEffect().

loadFloat80()

double X86ISA::loadFloat80

(

const void *

mem

)

Load an 80-bit float from memory and convert it to double.

Parameters

mem	Pointer to an 80-bit float.

Returns

double representation of the 80-bit float.

Definition at line 208 of file utility.cc.

Referenced by dumpFpuCommon(), and updateThreadContextFPUCommon().

m5PageFault()

void X86ISA::m5PageFault

(

ThreadContext *

tc

)

Definition at line 47 of file pseudo_inst.cc.

References DPRINTF, ThreadContext::getProcessPtr(), ThreadContext::getVirtProxy(), MipsISA::is, ISTVirtAddr, MISCREG_CR2, p, PageBytes, panic, PortProxy::readBlob(), and ThreadContext::readMiscReg().

Referenced by PseudoInst::pseudoInstWork().

MISCREG_CR()

static MiscRegIndex X86ISA::MISCREG_CR ( int  index )

inlinestatic

Definition at line 411 of file misc.hh.

References index, MISCREG_CR_BASE, and NumCRegs.

MISCREG_DR()

static MiscRegIndex X86ISA::MISCREG_DR ( int  index )

inlinestatic

Definition at line 418 of file misc.hh.

References index, MISCREG_DR_BASE, and NumDRegs.

MISCREG_IORR_BASE()

static MiscRegIndex X86ISA::MISCREG_IORR_BASE ( int  index )

inlinestatic

Definition at line 489 of file misc.hh.

References index, MISCREG_IORR_BASE_BASE, and MISCREG_IORR_BASE_END.

MISCREG_IORR_MASK()

static MiscRegIndex X86ISA::MISCREG_IORR_MASK ( int  index )

inlinestatic

Definition at line 497 of file misc.hh.

References index, MISCREG_IORR_MASK_BASE, and MISCREG_IORR_MASK_END.

MISCREG_MC_ADDR()

static MiscRegIndex X86ISA::MISCREG_MC_ADDR ( int  index )

inlinestatic

Definition at line 457 of file misc.hh.

References index, MISCREG_MC_ADDR_BASE, and MISCREG_MC_ADDR_END.

MISCREG_MC_CTL()

static MiscRegIndex X86ISA::MISCREG_MC_CTL ( int  index )

inlinestatic

Definition at line 441 of file misc.hh.

References index, MISCREG_MC_CTL_BASE, and MISCREG_MC_CTL_END.

MISCREG_MC_MISC()

static MiscRegIndex X86ISA::MISCREG_MC_MISC ( int  index )

inlinestatic

Definition at line 465 of file misc.hh.

References index, MISCREG_MC_MISC_BASE, and MISCREG_MC_MISC_END.

MISCREG_MC_STATUS()

static MiscRegIndex X86ISA::MISCREG_MC_STATUS ( int  index )

inlinestatic

Definition at line 449 of file misc.hh.

References index, MISCREG_MC_STATUS_BASE, and MISCREG_MC_STATUS_END.

MISCREG_MTRR_PHYS_BASE()

static MiscRegIndex X86ISA::MISCREG_MTRR_PHYS_BASE ( int  index )

inlinestatic

Definition at line 425 of file misc.hh.

References index, MISCREG_MTRR_PHYS_BASE_BASE, and MISCREG_MTRR_PHYS_BASE_END.

MISCREG_MTRR_PHYS_MASK()

static MiscRegIndex X86ISA::MISCREG_MTRR_PHYS_MASK ( int  index )

inlinestatic

Definition at line 433 of file misc.hh.

References index, MISCREG_MTRR_PHYS_MASK_BASE, and MISCREG_MTRR_PHYS_MASK_END.

MISCREG_PERF_EVT_CTR()

static MiscRegIndex X86ISA::MISCREG_PERF_EVT_CTR ( int  index )

inlinestatic

Definition at line 481 of file misc.hh.

References index, MISCREG_PERF_EVT_CTR_BASE, and MISCREG_PERF_EVT_CTR_END.

MISCREG_PERF_EVT_SEL()

static MiscRegIndex X86ISA::MISCREG_PERF_EVT_SEL ( int  index )

inlinestatic

Definition at line 473 of file misc.hh.

References index, MISCREG_PERF_EVT_SEL_BASE, and MISCREG_PERF_EVT_SEL_END.

MISCREG_SEG_ATTR()

static MiscRegIndex X86ISA::MISCREG_SEG_ATTR ( int  index )

inlinestatic

Definition at line 533 of file misc.hh.

References index, MISCREG_SEG_ATTR_BASE, and NUM_SEGMENTREGS.

Referenced by X86ISA::X86_64Process::initState(), X86ISA::I386Process::initState(), installSegDesc(), X86ISA::InitInterrupt::invoke(), setContextSegment(), setKvmSegmentReg(), X86ISA::TLB::translate(), and X86ISA::GpuTLB::translate().

MISCREG_SEG_BASE()

static MiscRegIndex X86ISA::MISCREG_SEG_BASE ( int  index )

inlinestatic

Definition at line 512 of file misc.hh.

References index, MISCREG_SEG_BASE_BASE, and NUM_SEGMENTREGS.

Referenced by X86ISA::X86_64Process::initState(), X86ISA::I386Process::initState(), installSegDesc(), X86ISA::InitInterrupt::invoke(), setContextSegment(), setKvmDTableReg(), setKvmSegmentReg(), X86ISA::TLB::translate(), and X86ISA::GpuTLB::translate().

MISCREG_SEG_EFF_BASE()

static MiscRegIndex X86ISA::MISCREG_SEG_EFF_BASE ( int  index )

inlinestatic

Definition at line 519 of file misc.hh.

References index, MISCREG_SEG_EFF_BASE_BASE, and NUM_SEGMENTREGS.

Referenced by X86ISA::X86_64Process::initState(), X86ISA::I386Process::initState(), installSegDesc(), X86ISA::InitInterrupt::invoke(), and X86ISA::ISA::setMiscReg().

MISCREG_SEG_LIMIT()

static MiscRegIndex X86ISA::MISCREG_SEG_LIMIT ( int  index )

inlinestatic

Definition at line 526 of file misc.hh.

References index, MISCREG_SEG_LIMIT_BASE, and NUM_SEGMENTREGS.

Referenced by X86ISA::I386Process::initState(), installSegDesc(), X86ISA::InitInterrupt::invoke(), setContextSegment(), setKvmDTableReg(), setKvmSegmentReg(), X86ISA::TLB::translate(), and X86ISA::GpuTLB::translate().

MISCREG_SEG_SEL()

static MiscRegIndex X86ISA::MISCREG_SEG_SEL ( int  index )

inlinestatic

Definition at line 505 of file misc.hh.

References index, MISCREG_SEG_SEL_BASE, and NUM_SEGMENTREGS.

Referenced by X86ISA::I386Process::initState(), X86ISA::InitInterrupt::invoke(), setContextSegment(), setKvmSegmentReg(), X86ISA::TLB::translate(), and X86ISA::GpuTLB::translate().

msrAddrToIndex()

bool X86ISA::msrAddrToIndex	(	MiscRegIndex &	regNum,
		Addr	addr
	)

Find and return the misc reg corresponding to an MSR address.

Look for an MSR (addr) in msrMap and return the corresponding misc reg in regNum. The value of regNum is undefined if the MSR was not found.

Parameters

regNum	misc reg index (out).
addr	MSR address

Returns

True if the MSR was found, false otherwise.

Definition at line 147 of file msr.cc.

References addr, and msrMap.

Referenced by X86ISA::TLB::translateInt(), and X86ISA::GpuTLB::translateInt().

msrMap()

const MsrMap X86ISA::msrMap	(	msrMapData	,
		msrMapData+	msrMapSize
	)

opcodeTypeToStr()

static const char* X86ISA::opcodeTypeToStr ( OpcodeType  type )

inlinestatic

Definition at line 156 of file types.hh.

References type.

Referenced by operator<<().

operator<<()

static std::ostream& X86ISA::operator<< ( std::ostream &  os, const ExtMachInst &  emi  )

inlinestatic

Definition at line 237 of file types.hh.

References ccprintf(), X86ISA::ExtMachInst::displacement, X86ISA::ExtMachInst::dispSize, X86ISA::ExtMachInst::immediate, X86ISA::ExtMachInst::legacy, X86ISA::ExtMachInst::modRM, X86ISA::ExtMachInst::op, X86ISA::ExtMachInst::opcode, opcodeTypeToStr(), os, X86ISA::ExtMachInst::rex, X86ISA::ExtMachInst::sib, X86ISA::ExtMachInst::type, and X86ISA::ExtMachInst::vex.

operator==()

static bool X86ISA::operator== ( const ExtMachInst &  emi1, const ExtMachInst &  emi2  )

inlinestatic

Definition at line 254 of file types.hh.

References X86ISA::ExtMachInst::addrSize, X86ISA::ExtMachInst::displacement, X86ISA::ExtMachInst::dispSize, X86ISA::ExtMachInst::immediate, X86ISA::ExtMachInst::legacy, X86ISA::ExtMachInst::mode, X86ISA::ExtMachInst::modRM, X86ISA::ExtMachInst::op, X86ISA::ExtMachInst::opcode, X86ISA::ExtMachInst::opSize, X86ISA::ExtMachInst::rex, X86ISA::ExtMachInst::sib, X86ISA::ExtMachInst::stackSize, X86ISA::ExtMachInst::type, and X86ISA::ExtMachInst::vex.

readMemAtomic() [1/2]

template<size_t N>

static Fault X86ISA::readMemAtomic ( ExecContext *  xc, Trace::InstRecord *  traceData, Addr  addr, std::array< uint64_t, N > &  mem, unsigned  dataSize, unsigned  flags  )

static

Definition at line 139 of file memhelpers.hh.

References addr, mem, NoFault, panic, and Trace::InstRecord::setData().

readMemAtomic() [2/2]

static Fault X86ISA::readMemAtomic ( ExecContext *  xc, Trace::InstRecord *  traceData, Addr  addr, uint64_t &  mem, unsigned  dataSize, Request::Flags  flags  )

static

Definition at line 105 of file memhelpers.hh.

References addr, letoh(), mem, NoFault, ExecContext::readMem(), and Trace::InstRecord::setData().

readPackedMemAtomic()

template<typename T , size_t N>

static Fault X86ISA::readPackedMemAtomic ( ExecContext *  xc, Addr  addr, std::array< uint64_t, N > &  mem, unsigned  flags  )

static

Definition at line 123 of file memhelpers.hh.

References addr, ArmISA::i, letoh(), mem, NoFault, and ExecContext::readMem().

setRFlags()

void X86ISA::setRFlags	(	ThreadContext *	tc,
		uint64_t	val
	)

Set update the rflags register and internal gem5 state.

Note

This function does not update MISCREG_M5_REG. You might need to update this register by writing anything to MISCREG_M5_REG with side-effects.

See also

X86ISA::getRFlags()

Parameters

tc	Thread context to update
val	New rflags value to store in TC

Definition at line 126 of file utility.cc.

References ccFlagMask, CCREG_CFOF, CCREG_DF, CCREG_ECF, CCREG_EZF, CCREG_ZAPS, cfofMask, DFBit, MISCREG_RFLAGS, ThreadContext::setCCReg(), ThreadContext::setMiscReg(), and val.

Referenced by X86KvmCPU::updateThreadContextRegs().

storeFloat80()

void X86ISA::storeFloat80	(	void *	mem,
		double	value
	)

Convert and store a double as an 80-bit float.

Parameters

mem	Pointer to destination for the 80-bit float.
value	Double precision float to store.

Definition at line 217 of file utility.cc.

Referenced by updateKvmStateFPUCommon().

stringToRegister()

uint64_t X86ISA::stringToRegister

(

const char *

str

)

Definition at line 76 of file cpuid.cc.

References reg.

Referenced by doCpuid().

SubBitUnion()

X86ISA::SubBitUnion	(	type	,
		43	,
		40
	)

writeMemAtomic() [1/2]

template<size_t N>

static Fault X86ISA::writeMemAtomic ( ExecContext *  xc, Trace::InstRecord *  traceData, std::array< uint64_t, N > &  mem, unsigned  dataSize, Addr  addr, unsigned  flags, uint64_t *  res  )

static

Definition at line 220 of file memhelpers.hh.

References addr, letoh(), mem, NoFault, panic, and Trace::InstRecord::setData().

writeMemAtomic() [2/2]

static Fault X86ISA::writeMemAtomic ( ExecContext *  xc, Trace::InstRecord *  traceData, uint64_t  mem, unsigned  dataSize, Addr  addr, Request::Flags  flags, uint64_t *  res  )

static

Definition at line 204 of file memhelpers.hh.

References addr, htole(), letoh(), mem, NoFault, Trace::InstRecord::setData(), and ExecContext::writeMem().

writeMemTiming() [1/2]

template<size_t N>

static Fault X86ISA::writeMemTiming ( ExecContext *  xc, Trace::InstRecord *  traceData, std::array< uint64_t, N > &  mem, unsigned  dataSize, Addr  addr, unsigned  flags, uint64_t *  res  )

static

Definition at line 186 of file memhelpers.hh.

References addr, mem, panic, and Trace::InstRecord::setData().

writeMemTiming() [2/2]

static Fault X86ISA::writeMemTiming ( ExecContext *  xc, Trace::InstRecord *  traceData, uint64_t  mem, unsigned  dataSize, Addr  addr, Request::Flags  flags, uint64_t *  res  )

static

Definition at line 174 of file memhelpers.hh.

References addr, htole(), mem, Trace::InstRecord::setData(), and ExecContext::writeMem().

writePackedMem()

template<typename T , size_t N>

static Fault X86ISA::writePackedMem ( ExecContext *  xc, std::array< uint64_t, N > &  mem, Addr  addr, unsigned  flags, uint64_t *  res  )

static

Definition at line 162 of file memhelpers.hh.

References addr, htole(), ArmISA::i, mem, and ExecContext::writeMem().

x86InterruptAddress()

static Addr X86ISA::x86InterruptAddress ( const uint8_t  id, const uint16_t  addr  )

inlinestatic

Definition at line 100 of file x86_traits.hh.

References addr, PhysAddrAPICRangeSize, and PhysAddrPrefixInterrupts.

Referenced by buildIntTriggerPacket(), X86ISA::Interrupts::getIntAddrRange(), and X86ISA::Interrupts::recvMessage().

x86IOAddress()

static Addr X86ISA::x86IOAddress ( const uint32_t  port )

inlinestatic

Definition at line 81 of file x86_traits.hh.

References PhysAddrPrefixIO.

Referenced by X86KvmCPU::handleKvmExitIO().

x86LocalAPICAddress()

static Addr X86ISA::x86LocalAPICAddress ( const uint8_t  id, const uint16_t  addr  )

inlinestatic

Definition at line 93 of file x86_traits.hh.

References addr, and PhysAddrPrefixLocalAPIC.

Referenced by X86ISA::TLB::finalizePhysical(), X86ISA::Interrupts::setThreadContext(), and X86ISA::GpuTLB::translate().

x86PciConfigAddress()

static Addr X86ISA::x86PciConfigAddress ( const uint32_t  addr )

inlinestatic

Definition at line 87 of file x86_traits.hh.

References addr, and PhysAddrPrefixPciConfig.

Referenced by X86KvmCPU::handleKvmExitIO().

Variable Documentation

a

Bitfield< 40 > X86ISA::a

Definition at line 146 of file pagetable.hh.

ac

Bitfield<18> X86ISA::ac

Definition at line 561 of file misc.hh.

Referenced by MipsISA::dspDpaq(), MipsISA::dspDpsq(), MipsISA::dspMaq(), MipsISA::dspMulsaq(), and ArmISA::FsLinux::initState().

addr

Bitfield<3> X86ISA::addr

Definition at line 79 of file types.hh.

Referenced by buildIntPacket(), buildIntTriggerPacket(), X86ISA::PageFault::describe(), initiateMemRead(), X86ISA::PageFault::invoke(), isCanonicalAddress(), msrAddrToIndex(), X86ISA::LongModePTE::paddr(), X86ISA::I8042::read(), readMemAtomic(), readPackedMemAtomic(), X86ISA::TLB::setConfigAddress(), X86ISA::GpuTLB::setConfigAddress(), X86ISA::IntelMP::FloatingPointer::setTableAddr(), X86ISA::SMBios::SMBiosTable::setTableAddr(), X86ISA::Walker::WalkerState::setupWalk(), X86ISA::Walker::WalkerState::startFunctional(), X86ISA::Walker::startFunctional(), X86ISA::TLB::translateFunctional(), X86ISA::I8042::write(), writeMemAtomic(), writeMemTiming(), X86ISA::IntelMP::BaseConfigEntry::writeOut(), X86ISA::IntelMP::ExtConfigEntry::writeOut(), X86ISA::SMBios::BiosInformation::writeOut(), X86ISA::IntelMP::ConfigTable::writeOut(), X86ISA::IntelMP::Processor::writeOut(), X86ISA::IntelMP::Bus::writeOut(), X86ISA::IntelMP::IOAPIC::writeOut(), X86ISA::SMBios::SMBiosTable::writeOut(), X86ISA::IntelMP::IntAssignment::writeOut(), X86ISA::IntelMP::AddrSpaceMapping::writeOut(), X86ISA::IntelMP::BusHierarchy::writeOut(), X86ISA::IntelMP::CompatAddrSpaceMod::writeOut(), X86ISA::SMBios::SMBiosStructure::writeOutStrings(), writePackedMem(), x86InterruptAddress(), x86LocalAPICAddress(), and x86PciConfigAddress().

addrv

Bitfield<58> X86ISA::addrv

Definition at line 764 of file misc.hh.

af

Bitfield< 4 > X86ISA::af

Definition at line 548 of file misc.hh.

altAddr

Bitfield<15, 14> X86ISA::altAddr

Definition at line 586 of file misc.hh.

altOp

Bitfield<11, 10> X86ISA::altOp

Definition at line 584 of file misc.hh.

am

Bitfield<18> X86ISA::am

Definition at line 597 of file misc.hh.

AO

const uint8_t X86ISA::AO = AddressSizeOverride

Definition at line 51 of file decoder_tables.cc.

avl

Bitfield< 5 > X86ISA::avl

Definition at line 142 of file pagetable.hh.

b

Bitfield< 5 > X86ISA::b

Definition at line 919 of file misc.hh.

b1

Bitfield<1> X86ISA::b1

Definition at line 647 of file misc.hh.

b2

Bitfield<2> X86ISA::b2

Definition at line 648 of file misc.hh.

b3

Bitfield<3> X86ISA::b3

Definition at line 649 of file misc.hh.

badMicroop

const StaticInstPtr X86ISA::badMicroop

Initial value:

=
    new X86ISAInst::MicroDebug(dummyMachInst, "panic", "BAD",
        StaticInst::IsMicroop | StaticInst::IsLastMicroop,
        new GenericISA::M5PanicFault("Invalid microop!"))

Definition at line 57 of file badmicroop.cc.

Referenced by X86ISAInst::MicrocodeRom::fetchMicroop(), and X86ISA::MacroopBase::fetchMicroop().

base

Bitfield< 2, 0 > X86ISA::base

Definition at line 141 of file pagetable.hh.

Referenced by Iris::BaseCPU::BaseCPU(), Stats::Hdf5::beginGroup(), ArmISA::BigFpMemImmOp::BigFpMemImmOp(), ArmISA::BigFpMemPostOp::BigFpMemPostOp(), ArmISA::BigFpMemPreOp::BigFpMemPreOp(), ArmISA::BigFpMemRegOp::BigFpMemRegOp(), X86ISA::Interrupts::clearRegArrayBit(), FastModel::CortexA76Cluster::CortexA76Cluster(), SMMUTranslationProcess::doReadPTE(), dumpDmesgEntry(), IdeController::EndBitUnion(), EndBitUnion(), ArmISA::ArmStaticInst::extendReg64(), X86ISA::Interrupts::findRegArrayMSB(), sc_dt::scfx_rep::from_string(), ArmISA::SysDC64::generateDisassembly(), ArmISA::RfeOp::generateDisassembly(), ArmISA::MemoryDImm64::generateDisassembly(), ArmISA::MemoryDImmEx64::generateDisassembly(), ArmISA::MemoryEx64::generateDisassembly(), GuestABI::Argument< Aapcs32Vfp, HA, typename std::enable_if< IsAapcs32HomogeneousAggregate< HA >::value >::type >::get(), X86ISA::Interrupts::getRegArrayBit(), ArmISA::RemoteGDB::AArch64GdbRegCache::getRegs(), ArmISA::ArmFault::getVector(), ArmISA::Reset::getVector(), X86ISA::FsWorkload::initState(), Compressor::DictionaryCompressor< T >::DeltaPattern< DeltaSizeBits >::isValidDelta(), Stats::VectorPrint::operator()(), Stats::DistPrint::operator()(), Stats::SparseHistPrint::operator()(), BitfieldBackend::BitUnionOperators< Base >::operator<(), BitfieldBackend::BitUnionOperators< Base >::operator==(), Gicv3Its::pageAddress(), sc_gem5::Object::pickUniqueName(), sc_gem5::pickUniqueName(), ArmISA::Memory::printInst(), X86ISA::X86StaticInst::printMem(), ItsProcess::readDeviceTable(), ItsProcess::readIrqCollectionTable(), X86ISA::ISA::readMiscReg(), PacketFifoEntry::serialize(), EthPacketData::serialize(), EtherLink::Link::serialize(), MC146818::serialize(), Loader::SymbolTable::serialize(), Intel8254Timer::Counter::serialize(), Time::serialize(), PacketFifo::serialize(), Intel8254Timer::serialize(), X86ISA::Interrupts::setRegArrayBit(), ArmISA::RemoteGDB::AArch64GdbRegCache::setRegs(), ArmISA::ArmStaticInst::shift_carry_imm(), ArmISA::ArmStaticInst::shift_carry_rs(), ArmISA::ArmStaticInst::shift_rm_imm(), ArmISA::ArmStaticInst::shift_rm_rs(), ArmISA::ArmStaticInst::shiftReg64(), ArmISA::Memory64::startDisassembly(), SyscallTable32::SyscallTable32(), SyscallTable64::SyscallTable64(), MemTest::tick(), X86ISA::TLB::translate(), X86ISA::GpuTLB::translate(), PacketFifoEntry::unserialize(), EthPacketData::unserialize(), EtherLink::Link::unserialize(), Loader::SymbolTable::unserialize(), MC146818::unserialize(), Intel8254Timer::Counter::unserialize(), Time::unserialize(), PacketFifo::unserialize(), Intel8254Timer::unserialize(), Packet::writeData(), ItsProcess::writeDeviceTable(), ItsProcess::writeIrqCollectionTable(), and X86ISA::SMBios::SMBiosTable::writeOut().

baseHigh

X86ISA::baseHigh

Definition at line 914 of file misc.hh.

baseLow

Bitfield< 39, 16 > X86ISA::baseLow

Definition at line 915 of file misc.hh.

bd

Bitfield<13> X86ISA::bd

Definition at line 650 of file misc.hh.

bottom3

Bitfield<2,0> X86ISA::bottom3

Definition at line 176 of file types.hh.

bs

Bitfield<14> X86ISA::bs

Definition at line 651 of file misc.hh.

bsp

Bitfield<8> X86ISA::bsp

Definition at line 1052 of file misc.hh.

bt

Bitfield<15> X86ISA::bt

Definition at line 652 of file misc.hh.

btf

Bitfield<1> X86ISA::btf

Definition at line 715 of file misc.hh.

c

Bitfield< 42 > X86ISA::c

Definition at line 933 of file misc.hh.

ccFlagMask

const uint32_t X86ISA::ccFlagMask = PFBit | AFBit | ZFBit | SFBit

Definition at line 67 of file misc.hh.

Referenced by setRFlags().

cd

Bitfield<30> X86ISA::cd

Definition at line 595 of file misc.hh.

cf

Bitfield< 0 > X86ISA::cf

Definition at line 551 of file misc.hh.

cfofMask

const uint32_t X86ISA::cfofMask = CFBit | OFBit

Definition at line 66 of file misc.hh.

Referenced by setRFlags().

count

Bitfield< 36, 32 > X86ISA::count

Definition at line 703 of file misc.hh.

Referenced by FlashDevice::accessDevice(), sc_gem5::VcdTraceFile::addTraceVal(), Aapcs32Vfp::State::allocate(), DefaultCommit< Impl >::commitInsts(), countBoolVec(), FastModel::SCGIC::Terminator::countUnbound(), InstructionQueue< Impl >::doSquash(), Gcn3ISA::dppInstImpl(), IGbE::drain(), FunctionProfile::dump(), GuestABI::dumpArgsFrom(), Loader::ElfObject::ElfObject(), UFSHostDevice::finalUTP(), Gcn3ISA::firstOppositeSignBit(), BloomFilter::MultiBitSel::getCount(), BloomFilter::Multi::getCount(), Iris::ThreadContext::getCurrentInstCount(), MultiperspectivePerceptron::BLURRYPATH::getHash(), LocalBP::getPrediction(), BloomFilter::Multi::getTotalCount(), BloomFilter::Base::getTotalCount(), X86KvmCPU::handleKvmExitIO(), FlashDevice::initializeFlash(), InstructionQueue< Impl >::insert(), InstructionQueue< Impl >::insertNonSpec(), BloomFilter::Multi::isSet(), UFSHostDevice::manageReadTransfer(), UFSHostDevice::manageWriteTransfer(), System::Threads::numActive(), InstructionQueue< Impl >::numFreeEntries(), System::Threads::numRunning(), MipsISA::Interrupts::onCpuTimerInterrupt(), StackDistCalc::printStack(), Prefetcher::Queued::processMissingTranslations(), AddressProfiler::profileRetry(), SimpleDisk::read(), Intel8254Timer::Counter::read(), UFSHostDevice::UFSSCSIDevice::readFlash(), readvFunc(), FlashDevice::remap(), UFSHostDevice::requestHandler(), FutexMap::requeue(), InstructionQueue< Impl >::resetState(), SafeRead(), SafeWrite(), SC_MODULE(), O3ThreadContext< Impl >::scheduleInstCountEvent(), CheckerThreadContext< TC >::scheduleInstCountEvent(), Iris::ThreadContext::scheduleInstCountEvent(), SimpleThread::scheduleInstCountEvent(), InstructionQueue< Impl >::scheduleReadyInsts(), UFSHostDevice::UFSSCSIDevice::SCSICMDHandle(), UFSHostDevice::SCSIResume(), FlashDevice::serialize(), EmulationPageTable::serialize(), MemState::serialize(), Sinic::Device::serialize(), ActivityRecorder::setActivityCount(), UFSHostDevice::UFSSCSIDevice::statusCheck(), Iris::BaseCPU::totalInsts(), FlashDevice::unserialize(), EmulationPageTable::unserialize(), MemState::unserialize(), ActivityRecorder::validate(), Checker< O3CPUImpl >::verify(), sc_gem5::Process::waitCount(), InstructionQueue< Impl >::wakeDependents(), FutexMap::wakeup(), UFSHostDevice::UFSSCSIDevice::writeFlash(), and writevFunc().

counterMask

Bitfield<31,24> X86ISA::counterMask

Definition at line 809 of file misc.hh.

cpl

Bitfield<5, 4> X86ISA::cpl

Definition at line 580 of file misc.hh.

CS

const uint8_t X86ISA::CS = CSOverride

Definition at line 43 of file decoder_tables.cc.

Referenced by SC_MODULE().

d

Bitfield< 54 > X86ISA::d

Definition at line 145 of file pagetable.hh.

de

Bitfield<3> X86ISA::de

Definition at line 635 of file misc.hh.

Referenced by dumpDmesgEntry(), and OutputDirectory::remove().

decodeVal

X86ISA::decodeVal

Definition at line 74 of file types.hh.

defAddr

Bitfield<13, 12> X86ISA::defAddr

Definition at line 585 of file misc.hh.

defaultSize

Bitfield<3> X86ISA::defaultSize

Definition at line 988 of file misc.hh.

defOp

Bitfield<9, 8> X86ISA::defOp

Definition at line 583 of file misc.hh.

deliveryMode

Bitfield< 10, 8 > X86ISA::deliveryMode

Definition at line 45 of file intmessage.hh.

Referenced by X86ISA::Interrupts::requestInterrupt().

deliveryStatus

Bitfield<12> X86ISA::deliveryStatus

Definition at line 94 of file apic.hh.

destination

X86ISA::destination

Definition at line 43 of file intmessage.hh.

Referenced by GarnetSyntheticTraffic::generatePkt(), UFSHostDevice::readDevice(), UFSHostDevice::transferDone(), and UFSHostDevice::writeDevice().

destMode

Bitfield< 11 > X86ISA::destMode

Definition at line 46 of file intmessage.hh.

destShorthand

Bitfield<19, 18> X86ISA::destShorthand

Definition at line 97 of file apic.hh.

df

Bitfield<10> X86ISA::df

Definition at line 567 of file misc.hh.

disA20M

Bitfield<2> X86ISA::disA20M

Definition at line 837 of file misc.hh.

dpl

Bitfield< 46, 45 > X86ISA::dpl

Definition at line 926 of file misc.hh.

DS

const uint8_t X86ISA::DS = DSOverride

Definition at line 44 of file decoder_tables.cc.

E

Bitfield<31,0> X86ISA::E

Definition at line 51 of file int.hh.

Referenced by ArmISA::ArmStaticInst::cSwap().

e

Bitfield< 42 > X86ISA::e

Definition at line 753 of file misc.hh.

Referenced by dumpKvm().

ecf

Bitfield<3> X86ISA::ecf

Definition at line 549 of file misc.hh.

eipv

Bitfield<1> X86ISA::eipv

Definition at line 709 of file misc.hh.

em

Bitfield<2> X86ISA::em

Definition at line 602 of file misc.hh.

Referenced by Consumer::scheduleEvent(), and Consumer::scheduleEventAbsolute().

en

Bitfield< 22 > X86ISA::en

Definition at line 766 of file misc.hh.

enable

Bitfield<11> X86ISA::enable

Definition at line 1051 of file misc.hh.

Referenced by ArmISA::addPACDA(), ArmISA::addPACDB(), ArmISA::addPACIA(), ArmISA::addPACIB(), ArmISA::authDA(), ArmISA::authDB(), ArmISA::authIA(), ArmISA::authIB(), Gicv3CPUInterface::setMiscReg(), ArmISA::BrkPoint::testLinkedBk(), ArmISA::PMU::updateAllCounters(), and Gicv3Distributor::write().

enter

Bitfield<1> X86ISA::enter

Definition at line 846 of file misc.hh.

ES

const uint8_t X86ISA::ES = ESOverride

Definition at line 45 of file decoder_tables.cc.

esi

X86ISA::esi

Definition at line 859 of file misc.hh.

et

Bitfield<4> X86ISA::et

Definition at line 600 of file misc.hh.

eventMask

X86ISA::eventMask

Definition at line 800 of file misc.hh.

exit

Bitfield<3> X86ISA::exit

Definition at line 848 of file misc.hh.

Referenced by SimpleATTarget1::beginResponse(), RoutingUnit::lookupRoutingTable(), main(), SimpleBusAT< NR_OF_INITIATORS, NR_OF_TARGETS >::RequestThread(), SimpleBusAT< NR_OF_INITIATORS, NR_OF_TARGETS >::ResponseThread(), Sinic::Device::rxKick(), NSGigE::rxKick(), ArmISA::ArmStaticInst::shift_carry_imm(), ArmISA::ArmStaticInst::shift_carry_rs(), ArmISA::ArmStaticInst::shift_rm_imm(), ArmISA::ArmStaticInst::shift_rm_rs(), ArmISA::ArmStaticInst::shiftReg64(), Sinic::Device::txKick(), NSGigE::txKick(), and usage().

expandDown

Bitfield<14> X86ISA::expandDown

Definition at line 996 of file misc.hh.

Referenced by X86ISA::TLB::translate(), and X86ISA::GpuTLB::translate().

ezf

Bitfield<5> X86ISA::ezf

Definition at line 547 of file misc.hh.

fe

Bitfield<10> X86ISA::fe

Definition at line 752 of file misc.hh.

ffxsr

Bitfield<14> X86ISA::ffxsr

Definition at line 786 of file misc.hh.

fix

Bitfield<8> X86ISA::fix

Definition at line 680 of file misc.hh.

FlagShift

const int X86ISA::FlagShift = 4

Definition at line 50 of file ldstflags.hh.

Referenced by Sequencer::makeRequest(), X86ISA::GpuTLB::pagingProtectionChecks(), X86ISA::TLB::translate(), and X86ISA::GpuTLB::translate().

FramePointerReg

const int X86ISA::FramePointerReg = INTREG_RBP

Definition at line 89 of file registers.hh.

FS

const uint8_t X86ISA::FS = FSOverride

Definition at line 46 of file decoder_tables.cc.

fsgsbase

Bitfield<16> X86ISA::fsgsbase

Definition at line 625 of file misc.hh.

g

Bitfield< 55 > X86ISA::g

Definition at line 143 of file pagetable.hh.

Referenced by X86ISA::SegDescriptorLimit::setter().

g0

Bitfield<1> X86ISA::g0

Definition at line 657 of file misc.hh.

g1

Bitfield<3> X86ISA::g1

Definition at line 659 of file misc.hh.

g2

Bitfield<5> X86ISA::g2

Definition at line 661 of file misc.hh.

g3

Bitfield<7> X86ISA::g3

Definition at line 663 of file misc.hh.

gd

Bitfield<13> X86ISA::gd

Definition at line 666 of file misc.hh.

GDTVirtAddr

const Addr X86ISA::GDTVirtAddr = 0xffff800000001000

Definition at line 70 of file fs_workload.hh.

Referenced by X86ISA::X86_64Process::initState().

ge

Bitfield<9> X86ISA::ge

Definition at line 665 of file misc.hh.

granularity

Bitfield<6> X86ISA::granularity

Definition at line 991 of file misc.hh.

GS

const uint8_t X86ISA::GS = GSOverride

Definition at line 47 of file decoder_tables.cc.

GuestByteOrder

const ByteOrder X86ISA::GuestByteOrder = ByteOrder::little

Definition at line 45 of file isa_traits.hh.

Referenced by X86ISA::X86Process::argsInit().

H

Bitfield<15,8> X86ISA::H

Definition at line 55 of file int.hh.

IDTVirtAddr

const Addr X86ISA::IDTVirtAddr = 0xffff800000002000

Definition at line 71 of file fs_workload.hh.

Referenced by X86ISA::X86_64Process::initState().

index

Bitfield<5,3> X86ISA::index

Definition at line 93 of file types.hh.

Referenced by APIC_IN_SERVICE(), APIC_INTERRUPT_REQUEST(), APIC_TRIGGER_MODE(), FLOATREG_FPR(), FLOATREG_MICROFP(), FLOATREG_MMX(), FLOATREG_STACK(), FLOATREG_XMM_HIGH(), FLOATREG_XMM_LOW(), INTREG_FOLDED(), INTREG_IMPLICIT(), INTREG_MICRO(), X86ISA::InitInterrupt::invoke(), isValidMiscReg(), X86ISA::X86StaticInst::merge(), MISCREG_CR(), MISCREG_DR(), MISCREG_IORR_BASE(), MISCREG_IORR_MASK(), MISCREG_MC_ADDR(), MISCREG_MC_CTL(), MISCREG_MC_MISC(), MISCREG_MC_STATUS(), MISCREG_MTRR_PHYS_BASE(), MISCREG_MTRR_PHYS_MASK(), MISCREG_PERF_EVT_CTR(), MISCREG_PERF_EVT_SEL(), MISCREG_SEG_ATTR(), MISCREG_SEG_BASE(), MISCREG_SEG_EFF_BASE(), MISCREG_SEG_LIMIT(), MISCREG_SEG_SEL(), X86ISA::X86StaticInst::pick(), X86ISA::X86StaticInst::printMem(), X86ISA::I82094AA::readReg(), X86ISA::X86StaticInst::signedPick(), and X86ISA::I82094AA::writeReg().

IntAddrPrefixCPUID

const Addr X86ISA::IntAddrPrefixCPUID = ULL(0x100000000)

Definition at line 68 of file x86_traits.hh.

Referenced by X86ISA::TLB::translateInt(), and X86ISA::GpuTLB::translateInt().

IntAddrPrefixIO

const Addr X86ISA::IntAddrPrefixIO = ULL(0x300000000)

Definition at line 70 of file x86_traits.hh.

Referenced by X86ISA::TLB::translateInt(), and X86ISA::GpuTLB::translateInt().

IntAddrPrefixMask

const Addr X86ISA::IntAddrPrefixMask = ULL(0xffffffff00000000)

Definition at line 67 of file x86_traits.hh.

Referenced by X86ISA::TLB::translateInt(), and X86ISA::GpuTLB::translateInt().

IntAddrPrefixMSR

const Addr X86ISA::IntAddrPrefixMSR = ULL(0x200000000)

Definition at line 69 of file x86_traits.hh.

Referenced by X86ISA::TLB::translateInt(), and X86ISA::GpuTLB::translateInt().

intEn

Bitfield<20> X86ISA::intEn

Definition at line 806 of file misc.hh.

intf

Bitfield<9> X86ISA::intf

Definition at line 568 of file misc.hh.

IntFoldBit

const IntRegIndex X86ISA::IntFoldBit = (IntRegIndex)(1 << 6)

static

Definition at line 151 of file int.hh.

Referenced by X86ISA::ISA::flattenIntIndex(), X86ISA::X86StaticInst::merge(), X86ISA::X86StaticInst::pick(), X86ISA::X86StaticInst::printReg(), and X86ISA::X86StaticInst::signedPick().

inv

Bitfield<23> X86ISA::inv

Definition at line 808 of file misc.hh.

Referenced by Prefetcher::Base::observeAccess().

iopl

Bitfield<13, 12> X86ISA::iopl

Definition at line 565 of file misc.hh.

IST

Bitfield<35, 32> X86ISA::IST

Definition at line 1018 of file misc.hh.

ISTVirtAddr

const Addr X86ISA::ISTVirtAddr = 0xffff800000004000

Definition at line 74 of file fs_workload.hh.

Referenced by X86ISA::X86_64Process::initState(), and m5PageFault().

L

Bitfield<7, 0> X86ISA::L

Definition at line 57 of file int.hh.

Referenced by ArmProcess32::ArmProcess32(), ArmProcess64::ArmProcess64(), ArmISA::TableWalker::doLongDescriptor(), GPUComputeDriver::gpuVmApeBase(), GPUComputeDriver::gpuVmApeLimit(), KvmDevice::ioctl(), Kvm::ioctl(), PerfKvmCounter::ioctl(), KvmVM::ioctl(), BaseKvmCPU::ioctl(), MipsProcess::MipsProcess(), PowerProcess::PowerProcess(), RiscvProcess32::RiscvProcess32(), RiscvProcess64::RiscvProcess64(), and GPUComputeDriver::scratchApeBase().

l

Bitfield< 2 > X86ISA::l

Definition at line 920 of file misc.hh.

l1

Bitfield<2> X86ISA::l1

Definition at line 658 of file misc.hh.

Referenced by operator<().

l2

Bitfield<4> X86ISA::l2

Definition at line 660 of file misc.hh.

Referenced by operator<().

l3

Bitfield<6> X86ISA::l3

Definition at line 662 of file misc.hh.

le

Bitfield<8> X86ISA::le

Definition at line 664 of file misc.hh.

Referenced by sc_gem5::DynamicSensitivityEventOrList::notifyWork().

legacy

X86ISA::legacy

Definition at line 609 of file misc.hh.

len0

Bitfield<19, 18> X86ISA::len0

Definition at line 668 of file misc.hh.

Referenced by tlm::no_b1(), tlm::tlm_from_hostendian_word(), and tlm::tlm_to_hostendian_word().

len1

Bitfield<23, 22> X86ISA::len1

Definition at line 670 of file misc.hh.

len2

Bitfield<27, 26> X86ISA::len2

Definition at line 672 of file misc.hh.

len3

Bitfield<31, 30> X86ISA::len3

Definition at line 674 of file misc.hh.

level

Bitfield< 14 > X86ISA::level

Definition at line 47 of file intmessage.hh.

Referenced by Trie< Key, Value >::Node::dump(), SparcISA::Interrupts::getInterrupt(), getsockoptFunc(), StackDistCalc::getSum(), V7LPageTableOps::index(), V8PageTableOps4k::index(), V8PageTableOps16k::index(), V8PageTableOps64k::index(), SparcISA::Interrupts::InterruptLevel(), SparcISA::SparcFaultBase::invoke(), V7LPageTableOps::isLeaf(), V8PageTableOps4k::isLeaf(), V8PageTableOps16k::isLeaf(), V8PageTableOps64k::isLeaf(), V7LPageTableOps::isValid(), V8PageTableOps4k::isValid(), V8PageTableOps16k::isValid(), V8PageTableOps64k::isValid(), WalkCache::lookup(), V7LPageTableOps::nextLevelPointer(), V8PageTableOps4k::nextLevelPointer(), V8PageTableOps16k::nextLevelPointer(), V8PageTableOps64k::nextLevelPointer(), V7LPageTableOps::pageMask(), V8PageTableOps4k::pageMask(), V8PageTableOps16k::pageMask(), V8PageTableOps64k::pageMask(), WalkCache::pickEntryIdxToReplace(), WalkCache::pickSetIdx(), X86ISA::Interrupts::requestInterrupt(), StackDistCalc::sanityCheckTree(), setsockoptFunc(), RiscvISA::Walker::WalkerState::setupWalk(), RiscvISA::Walker::WalkerState::stepWalk(), SMMUTranslationProcess::translateStage1And2(), SMMUTranslationProcess::translateStage2(), StackDistCalc::updateSum(), StackDistCalc::updateSumsLeavesToRoot(), SMMUTranslationProcess::walkCacheLookup(), SMMUTranslationProcess::walkCacheUpdate(), V7LPageTableOps::walkMask(), V8PageTableOps4k::walkMask(), V8PageTableOps16k::walkMask(), V8PageTableOps64k::walkMask(), SMMUTranslationProcess::walkStage1And2(), and SMMUTranslationProcess::walkStage2().

limit

BitfieldType< SegDescriptorLimit > X86ISA::limit

Definition at line 924 of file misc.hh.

Referenced by sc_dt::sc_uint_base::check_value(), sc_dt::sc_int_base::check_value(), EndBitUnion(), X86ISA::SegDescriptorLimit::getter(), MemFootprintProbe::insertAddr(), Compressor::DictionaryCompressor< T >::DeltaPattern< DeltaSizeBits >::isValidDelta(), ProtoInputStream::read(), X86ISA::SegDescriptorLimit::setter(), sc_core::sc_report_handler::stop_after(), X86ISA::TLB::translate(), and X86ISA::GpuTLB::translate().

limitHigh

Bitfield< 51, 48 > X86ISA::limitHigh

Definition at line 922 of file misc.hh.

limitLow

Bitfield< 15, 0 > X86ISA::limitLow

Definition at line 923 of file misc.hh.

lma

Bitfield<10> X86ISA::lma

Definition at line 783 of file misc.hh.

lme

Bitfield<8> X86ISA::lme

Definition at line 782 of file misc.hh.

LO

const uint8_t X86ISA::LO = Lock

Definition at line 52 of file decoder_tables.cc.

lock

Bitfield<5> X86ISA::lock

Definition at line 77 of file types.hh.

Referenced by DistIface::Sync::abort(), sc_gem5::Scheduler::asyncRequestUpdate(), doSimLoop(), BaseKvmCPU::drain(), DrainManager::drainableCount(), DistIface::SyncNode::progress(), DistIface::SyncSwitch::progress(), DrainManager::registerDrainable(), DistIface::SyncNode::requestCkpt(), DistIface::SyncNode::requestExit(), DistIface::SyncNode::run(), DistIface::SyncSwitch::run(), sc_gem5::Scheduler::runUpdate(), EventQueue::serviceOne(), DrainManager::unregisterDrainable(), and Barrier::wait().

longl1

X86ISA::longl1

Definition at line 123 of file pagetable.hh.

longl2

Bitfield<29, 21> X86ISA::longl2

Definition at line 124 of file pagetable.hh.

longl3

Bitfield<38, 30> X86ISA::longl3

Definition at line 125 of file pagetable.hh.

longl4

Bitfield<47, 39> X86ISA::longl4

Definition at line 126 of file pagetable.hh.

longMode

Bitfield<4> X86ISA::longMode

Definition at line 989 of file misc.hh.

longPdtb

X86ISA::longPdtb

Definition at line 613 of file misc.hh.

m

Bitfield<4, 0> X86ISA::m

Definition at line 113 of file types.hh.

mask

X86ISA::mask

Definition at line 796 of file misc.hh.

Referenced by X86ISA::RemoteGDB::acc(), X86ISA::ISA::clear(), X86ISA::Decoder::decode(), decodeAddr(), X86ISA::Decoder::getImmediate(), X86ISA::SegDescriptorLimit::getter(), X86ISA::Interrupts::read(), X86ISA::ISA::setMiscRegNoEffect(), X86ISA::SegDescriptorLimit::setter(), X86ISA::Walker::WalkerState::stepWalk(), X86ISA::TLB::translate(), X86ISA::TLB::translateInt(), X86ISA::GpuTLB::translateInt(), X86ISA::I8259::write(), and X86ISA::Interrupts::write().

mcaErrorCode

X86ISA::mcaErrorCode

Definition at line 760 of file misc.hh.

mce

Bitfield<6> X86ISA::mce

Definition at line 632 of file misc.hh.

MCGCP

Bitfield<8> X86ISA::MCGCP

Definition at line 704 of file misc.hh.

mcip

Bitfield<2> X86ISA::mcip

Definition at line 710 of file misc.hh.

mfdm

Bitfield<19> X86ISA::mfdm

Definition at line 814 of file misc.hh.

miscv

Bitfield<59> X86ISA::miscv

Definition at line 765 of file misc.hh.

MMIORegionPhysAddr

const Addr X86ISA::MMIORegionPhysAddr = 0xffff0000

Definition at line 77 of file fs_workload.hh.

Referenced by X86ISA::X86_64Process::initState().

MMIORegionVirtAddr

const Addr X86ISA::MMIORegionVirtAddr = 0xffffc90000000000

Definition at line 76 of file fs_workload.hh.

Referenced by X86ISA::X86_64Process::initState().

mod

X86ISA::mod

Definition at line 86 of file types.hh.

Referenced by X86ISA::IntelMP::CompatAddrSpaceMod::writeOut().

modelSpecificCode

Bitfield<31,16> X86ISA::modelSpecificCode

Definition at line 761 of file misc.hh.

mp

Bitfield<1> X86ISA::mp

Definition at line 603 of file misc.hh.

msrMap

const MsrMap X86ISA::msrMap

Map between MSR addresses and their corresponding misc registers.

Note

This map is usually only used when enumeration of supported MSRs is needed (e.g., in virtualized CPUs). Code that needs to look-up specific MSRs should use msrAddrToIndex().

Referenced by X86KvmCPU::getMsrIntersection(), msrAddrToIndex(), X86KvmCPU::updateKvmStateMSRs(), and X86KvmCPU::updateThreadContextMSRs().

msrMapData

const MsrMap::value_type X86ISA::msrMapData[]

Definition at line 36 of file msr.cc.

msrMapSize

const unsigned X86ISA::msrMapSize = sizeof(msrMapData) / sizeof(msrMapData[0])

static

Definition at line 142 of file msr.cc.

mvdm

Bitfield<20> X86ISA::mvdm

Definition at line 815 of file misc.hh.

nameString

const char X86ISA::nameString[nameStringSize] = "Fake M5 x86_64 CPU"

static

Definition at line 73 of file cpuid.cc.

Referenced by doCpuid().

nameStringSize

const int X86ISA::nameStringSize = 48

static

Definition at line 72 of file cpuid.cc.

Referenced by doCpuid().

ne

Bitfield<5> X86ISA::ne

Definition at line 599 of file misc.hh.

norml1

Bitfield<21, 12> X86ISA::norml1

Definition at line 132 of file pagetable.hh.

norml2

Bitfield<31, 22> X86ISA::norml2

Definition at line 133 of file pagetable.hh.

nt

Bitfield<14> X86ISA::nt

Definition at line 564 of file misc.hh.

NumCCRegs

const int X86ISA::NumCCRegs = NUM_CCREGS

Definition at line 59 of file registers.hh.

Referenced by copyRegs().

NumCRegs

const int X86ISA::NumCRegs = 16

Definition at line 61 of file x86_traits.hh.

Referenced by MISCREG_CR().

NumDRegs

const int X86ISA::NumDRegs = 8

Definition at line 62 of file x86_traits.hh.

Referenced by MISCREG_DR().

NumFloatRegs

const int X86ISA::NumFloatRegs

Initial value:

=
    NumMMXRegs + 2 * NumXMMRegs + NumMicroFpRegs + 8

Definition at line 63 of file registers.hh.

Referenced by copyRegs().

NumImplicitIntRegs

const int X86ISA::NumImplicitIntRegs = 6

Definition at line 49 of file x86_traits.hh.

NumIntArchRegs

const int X86ISA::NumIntArchRegs = NUM_INTREGS

Definition at line 57 of file registers.hh.

NumIntRegs

const int X86ISA::NumIntRegs = NumIntArchRegs + NumMicroIntRegs + NumImplicitIntRegs

Definition at line 58 of file registers.hh.

Referenced by copyRegs().

NumMicroFpRegs

const int X86ISA::NumMicroFpRegs = 8

Definition at line 59 of file x86_traits.hh.

Referenced by X86ISA::X86StaticInst::printReg().

NumMicroIntRegs

const int X86ISA::NumMicroIntRegs = 16

Definition at line 47 of file x86_traits.hh.

Referenced by INTREG_IMPLICIT().

NumMiscRegs

const int X86ISA::NumMiscRegs = NUM_MISCREGS

Definition at line 55 of file registers.hh.

Referenced by X86ISA::ISA::clear(), X86ISA::ISA::serialize(), and X86ISA::ISA::unserialize().

NumMMXRegs

const int X86ISA::NumMMXRegs = 8

Definition at line 57 of file x86_traits.hh.

Referenced by X86ISA::X86StaticInst::printReg().

NumSegments

const int X86ISA::NumSegments = 6

Definition at line 64 of file x86_traits.hh.

NumSysSegments

const int X86ISA::NumSysSegments = 4

Definition at line 65 of file x86_traits.hh.

NumVecElemPerVecReg

constexpr unsigned X86ISA::NumVecElemPerVecReg = ::DummyNumVecElemPerVecReg

constexpr

Definition at line 100 of file registers.hh.

NumVecPredRegs

const int X86ISA::NumVecPredRegs = 1

Definition at line 79 of file registers.hh.

NumVecRegs

const int X86ISA::NumVecRegs = 1

Definition at line 77 of file registers.hh.

NumXMMRegs

const int X86ISA::NumXMMRegs = 16

Definition at line 58 of file x86_traits.hh.

Referenced by X86ISA::X86StaticInst::printReg().

nw

Bitfield<29> X86ISA::nw

Definition at line 596 of file misc.hh.

nxe

Bitfield<11> X86ISA::nxe

Definition at line 784 of file misc.hh.

of

Bitfield<11> X86ISA::of

Definition at line 566 of file misc.hh.

offset

X86ISA::offset

Definition at line 1024 of file misc.hh.

Referenced by doCpuid(), X86ISA::Interrupts::findRegArrayMSB(), X86ISA::FsWorkload::initState(), X86ISA::I8237::read(), X86ISA::I8254::read(), X86ISA::I82094AA::read(), X86ISA::Interrupts::read(), X86ISA::I82094AA::readReg(), X86ISA::Interrupts::recvMessage(), X86ISA::Interrupts::setReg(), X86ISA::TLB::translate(), X86ISA::GpuTLB::translate(), X86ISA::I8237::write(), X86ISA::I8254::write(), X86ISA::I82094AA::write(), X86ISA::Interrupts::write(), X86ISA::IntelMP::ConfigTable::writeOut(), X86ISA::SMBios::SMBiosTable::writeOut(), X86ISA::SMBios::SMBiosStructure::writeOutStrings(), and X86ISA::I82094AA::writeReg().

offsetHigh

X86ISA::offsetHigh

Definition at line 1001 of file misc.hh.

offsetLow

Bitfield< 15, 0 > X86ISA::offsetLow

Definition at line 1002 of file misc.hh.

OO

const uint8_t X86ISA::OO = OperandSizeOverride

Definition at line 50 of file decoder_tables.cc.

op

Bitfield<4> X86ISA::op

Definition at line 78 of file types.hh.

Referenced by ArmISA::Crypto::_sha1Op(), ArmSemihosting::call32(), ArmSemihosting::call64(), MipsISA::dspCmp(), MipsISA::dspCmpg(), MipsISA::dspCmpgd(), ArmISA::flushToZero(), ArmISA::fp16_FPConvertNaN_32(), ArmISA::fp16_FPConvertNaN_64(), ArmISA::fp32_FPConvertNaN_16(), ArmISA::fp32_FPConvertNaN_64(), ArmISA::fp64_FPConvertNaN_16(), ArmISA::fp64_FPConvertNaN_32(), ArmISA::fplibAbs(), ArmISA::fplibConvert(), ArmISA::fplibExpA(), ArmISA::fplibFixedToFP(), ArmISA::fplibFPToFixed(), ArmISA::fplibFPToFixedJS(), ArmISA::fplibNeg(), ArmISA::fplibRecipEstimate(), ArmISA::fplibRecpX(), ArmISA::fplibRoundInt(), ArmISA::fplibRSqrtEstimate(), ArmISA::fplibSqrt(), ArmISA::fpRecipEstimate(), ArmISA::fprSqrtEstimate(), futexFunc(), Loader::SymbolTable::mask(), Loader::SymbolTable::offset(), Loader::SymbolTable::operate(), Stats::UnaryNode< Op >::result(), Stats::BinaryNode< Op >::result(), Stats::SumNode< Op >::result(), ArmISA::ArmStaticInst::satInt(), SC_MODULE(), ArmISA::Crypto::sha1Op(), ArmISA::simd_modified_imm(), sys_getsysinfoFunc(), sys_setsysinfoFunc(), Stats::BinaryNode< Op >::total(), Stats::SumNode< Op >::total(), ArmSemihosting::unrecognizedCall(), ArmISA::unsignedRecipEstimate(), ArmISA::unsignedRSqrtEstimate(), ArmISA::ArmStaticInst::uSatInt(), ArmISA::vcvtFpDFpH(), ArmISA::vcvtFpHFp(), ArmISA::vcvtFpHFpD(), ArmISA::vcvtFpHFpS(), ArmISA::vcvtFpSFpH(), and ArmISA::vfpFlushToZero().

os

Bitfield<17> X86ISA::os

Definition at line 803 of file misc.hh.

Referenced by arrayParamOut(), sc_dt::b_xor(), BitfieldBackend::bitfieldBackendPrinter(), Trie< Key, Value >::Node::dump(), ProfileNode::dump(), sc_dt::sc_fxnum_bitref::dump(), FunctionProfile::dump(), sc_core::sc_fifo< T >::dump(), sc_dt::sc_fxnum_fast_bitref::dump(), sc_gem5::ScSignalBaseT< sc_dt::sc_logic, WRITER_POLICY >::dump(), sc_dt::scfx_rep::dump(), sc_dt::sc_fxnum_subref::dump(), Trie< Addr, TlbEntry >::dump(), GuestABI::dumpArgsFrom(), dumpDmesgEntry(), IdeController::EndBitUnion(), OutputDirectory::findOrCreate(), sc_gem5::UniqueNameGen::gen(), sc_dt::scfx_params::iwl(), Minor::LSQ::StoreBuffer::minorTrace(), OutputDirectory::open(), sc_dt::sc_bit::operator!(), Minor::operator<<(), sc_dt::operator<<(), Loader::operator<<(), GuestABI::operator<<(), sc_core::operator<<(), GenericISA::operator<<(), operator<<(), operator<<(), sc_dt::sc_bitref_r< T >::operator~(), sc_gem5::VcdTraceScope::output(), sc_gem5::VcdTraceValBool::output(), sc_gem5::VcdTraceValFloat< T >::output(), sc_gem5::VcdTraceValScLogic::output(), sc_gem5::VcdTraceValFxval< T >::output(), sc_gem5::VcdTraceValEvent::output(), sc_gem5::VcdTraceValTime::output(), paramOut(), sc_core::sc_time::print(), WriteQueueEntry::TargetList::print(), sc_dt::sc_fxnum_bitref::print(), sc_core::sc_fifo< T >::print(), WriteQueueEntry::print(), sc_dt::sc_uint_bitref_r::print(), sc_gem5::ScSignalBaseT< sc_dt::sc_logic, WRITER_POLICY >::print(), sc_dt::sc_int_bitref_r::print(), sc_dt::scfx_rep::print(), MSHR::TargetList::print(), sc_dt::sc_uint_subref_r::print(), sc_dt::sc_int_subref_r::print(), sc_dt::sc_concatref::print(), MSHR::print(), CacheBlkPrintWrapper::print(), sc_dt::sc_unsigned_bitref_r::print(), sc_dt::sc_signed_bitref_r::print(), sc_dt::sc_unsigned_subref_r::print(), sc_dt::sc_uint_base::print(), sc_dt::sc_signed_subref_r::print(), sc_dt::sc_int_base::print(), sc_dt::sc_unsigned::print(), sc_dt::sc_signed::print(), ArmISA::ArmStaticInst::printCCReg(), ArmISA::ArmStaticInst::printCondition(), ArmISA::ArmStaticInst::printDataInst(), ArmISA::Memory::printDest(), ArmISA::MemoryExImm::printDest(), ArmISA::MemoryDImm::printDest(), ArmISA::MemoryExDImm::printDest(), ArmISA::MemoryDReg::printDest(), SparcISA::SparcStaticInst::printDestReg(), X86ISA::X86StaticInst::printDestReg(), ArmISA::ArmStaticInst::printExtendOperand(), ArmISA::ArmStaticInst::printFloatReg(), ArmISA::Memory::printInst(), ArmISA::ArmStaticInst::printIntReg(), X86ISA::X86StaticInst::printMem(), ArmISA::ArmStaticInst::printMemSymbol(), ArmISA::ArmStaticInst::printMiscReg(), X86ISA::X86StaticInst::printMnemonic(), SparcISA::SparcStaticInst::printMnemonic(), ArmISA::ArmStaticInst::printMnemonic(), MsrBase::printMsrBase(), ArmISA::MemoryImm::printOffset(), ArmISA::MemoryReg::printOffset(), ArmISA::ArmStaticInst::printPFflags(), SparcISA::IntOp::printPseudoOps(), SparcISA::IntOpImm::printPseudoOps(), PowerISA::PowerStaticInst::printReg(), SparcISA::SparcStaticInst::printReg(), X86ISA::X86StaticInst::printReg(), SparcISA::SparcStaticInst::printRegArray(), Minor::printRegName(), X86ISA::X86StaticInst::printSegment(), ArmISA::ArmStaticInst::printShiftOperand(), SparcISA::SparcStaticInst::printSrcReg(), X86ISA::X86StaticInst::printSrcReg(), ArmISA::ArmStaticInst::printTarget(), sc_gem5::VcdTraceValBase::printVal(), ArmISA::ArmStaticInst::printVecPredReg(), ArmISA::ArmStaticInst::printVecReg(), Linux::DmesgDump::process(), Linux::KernelPanic::process(), Minor::ReportTraitsAdaptor< ElemType >::reportData(), Minor::ReportTraitsPtrAdaptor< PtrType >::reportData(), Minor::Fetch1::FetchRequest::reportData(), Minor::BranchData::reportData(), Minor::QueuedInst::reportData(), Minor::ForwardLineData::reportData(), Minor::LSQ::LSQRequest::reportData(), Minor::MinorDynInst::reportData(), Minor::ForwardInstData::reportData(), CxxConfigManager::serialize(), showParam(), ArmISA::Memory64::startDisassembly(), sc_dt::sc_fxval::to_bin(), sc_dt::sc_fxnum_fast::to_bin(), sc_dt::sc_fxval::to_string(), sc_dt::sc_fxval_fast::to_string(), sc_dt::sc_fxnum::to_string(), sc_dt::sc_fxnum_fast::to_string(), and PseudoInst::writefile().

osfxsr

Bitfield<9> X86ISA::osfxsr

Definition at line 629 of file misc.hh.

osxmmexcpt

Bitfield<10> X86ISA::osxmmexcpt

Definition at line 627 of file misc.hh.

otherInfo

Bitfield<56,32> X86ISA::otherInfo

Definition at line 762 of file misc.hh.

over

Bitfield<62> X86ISA::over

Definition at line 768 of file misc.hh.

p

Bitfield< 1, 0 > X86ISA::p

Definition at line 151 of file pagetable.hh.

Referenced by X86ISA::SMBios::BiosInformation::BiosInformation(), X86ISA::IntelMP::BusHierarchy::BusHierarchy(), X86ISA::X86Process::clone(), X86ISA::X86_64Process::clone(), X86ISA::I386Process::clone(), X86ISA::IntelMP::CompatAddrSpaceMod::CompatAddrSpaceMod(), X86ISA::I8042::I8042(), X86ISA::I82094AA::I82094AA(), X86ISA::I8254::I8254(), X86ISA::I8259::I8259(), X86ISA::IntelMP::IOAPIC::IOAPIC(), X86ISA::GpuTLB::issueTLBLookup(), m5PageFault(), X86ISA::LongModePTE::present(), X86ISA::IntelMP::Processor::Processor(), X86ISA::LongModePTE::read(), X86ISA::GpuTLB::CpuSidePort::recvFunctional(), X86ISA::SMBios::SMBiosTable::SMBiosTable(), X86ISA::TLB::TLB(), X86ISA::TLB::translate(), X86ISA::GpuTLB::translate(), X86ISA::GpuTLB::translationReturn(), and X86ISA::LongModePTE::write().

pae

Bitfield<5> X86ISA::pae

Definition at line 633 of file misc.hh.

pael1

Bitfield<20, 12> X86ISA::pael1

Definition at line 128 of file pagetable.hh.

pael2

Bitfield<29, 21> X86ISA::pael2

Definition at line 129 of file pagetable.hh.

pael3

Bitfield<31, 30> X86ISA::pael3

Definition at line 130 of file pagetable.hh.

paePdtb

Bitfield<31, 5> X86ISA::paePdtb

Definition at line 617 of file misc.hh.

PageBytes

const Addr X86ISA::PageBytes = ULL(1) << PageShift

Definition at line 48 of file isa_traits.hh.

Referenced by X86ISA::X86Process::argsInit(), X86ISA::TLB::finalizePhysical(), X86ISA::Interrupts::getAddrRanges(), X86ISA::I386Process::I386Process(), X86ISA::X86_64Process::initState(), X86ISA::I386Process::initState(), m5PageFault(), X86ISA::GpuTLB::translate(), and X86ISA::X86_64Process::X86_64Process().

PageShift

const Addr X86ISA::PageShift = 12

Definition at line 47 of file isa_traits.hh.

Referenced by X86ISA::LongModePTE::paddr(), and X86ISA::LongModePTE::tableSize().

paging

Bitfield<6> X86ISA::paging

Definition at line 581 of file misc.hh.

pb0

Bitfield<2> X86ISA::pb0

Definition at line 716 of file misc.hh.

pb1

Bitfield<3> X86ISA::pb1

Definition at line 717 of file misc.hh.

pb2

Bitfield<4> X86ISA::pb2

Definition at line 718 of file misc.hh.

pb3

Bitfield<5> X86ISA::pb3

Definition at line 719 of file misc.hh.

pc

Bitfield<19> X86ISA::pc

Definition at line 805 of file misc.hh.

Referenced by advancePC(), X86ISA::X86FaultBase::invoke(), X86ISA::X86Trap::invoke(), X86ISA::InitInterrupt::invoke(), and X86ISA::Decoder::moreBytes().

pcc

Bitfield<57> X86ISA::pcc

Definition at line 763 of file misc.hh.

pcd

Bitfield< 4 > X86ISA::pcd

Definition at line 147 of file pagetable.hh.

pce

Bitfield<8> X86ISA::pce

Definition at line 630 of file misc.hh.

pdtb

Bitfield<31, 12> X86ISA::pdtb

Definition at line 615 of file misc.hh.

pe

Bitfield<0> X86ISA::pe

Definition at line 604 of file misc.hh.

Referenced by EtherLink::Link::serialize().

pf

Bitfield< 2 > X86ISA::pf

Definition at line 550 of file misc.hh.

Referenced by Prefetcher::Multi::getPacket(), Cache::handleTimingReqMiss(), Prefetcher::Multi::nextPrefetchReadyTime(), ComputeUnit::DTLBPort::recvTimingResp(), and Prefetcher::Multi::setCache().

PFHandlerVirtAddr

const Addr X86ISA::PFHandlerVirtAddr = 0xffff800000005000

Definition at line 75 of file fs_workload.hh.

Referenced by X86ISA::X86_64Process::initState().

pge

Bitfield<7> X86ISA::pge

Definition at line 631 of file misc.hh.

physAddr

X86ISA::physAddr

Definition at line 831 of file misc.hh.

Referenced by TraceCPU::ElasticDataGen::GraphNode::writeElementAsTrace().

PhysAddrAPICRangeSize

const Addr X86ISA::PhysAddrAPICRangeSize = 1 << 12

Definition at line 78 of file x86_traits.hh.

Referenced by X86ISA::Interrupts::getIntAddrRange(), and x86InterruptAddress().

PhysAddrPrefixInterrupts

const Addr X86ISA::PhysAddrPrefixInterrupts = ULL(0xA000000000000000)

Definition at line 75 of file x86_traits.hh.

Referenced by x86InterruptAddress().

PhysAddrPrefixIO

const Addr X86ISA::PhysAddrPrefixIO = ULL(0x8000000000000000)

Definition at line 72 of file x86_traits.hh.

Referenced by X86ISA::TLB::translateInt(), X86ISA::GpuTLB::translateInt(), and x86IOAddress().

PhysAddrPrefixLocalAPIC

const Addr X86ISA::PhysAddrPrefixLocalAPIC = ULL(0x2000000000000000)

Definition at line 74 of file x86_traits.hh.

Referenced by x86LocalAPICAddress().

PhysAddrPrefixPciConfig

const Addr X86ISA::PhysAddrPrefixPciConfig = ULL(0xC000000000000000)

Definition at line 73 of file x86_traits.hh.

Referenced by X86ISA::TLB::translateInt(), X86ISA::GpuTLB::translateInt(), and x86PciConfigAddress().

physbase

Bitfield< 51, 12 > X86ISA::physbase

Definition at line 728 of file misc.hh.

physmask

Bitfield< 51, 12 > X86ISA::physmask

Definition at line 733 of file misc.hh.

present

Bitfield< 0 > X86ISA::present

Definition at line 992 of file misc.hh.

Referenced by X86ISA::Walker::WalkerState::pageFault(), X86ISA::PageFault::PageFault(), PersistentTable::persistentRequestLock(), and X86ISA::LongModePTE::reset().

prot

Bitfield<7> X86ISA::prot

Definition at line 582 of file misc.hh.

Referenced by mmap2Func(), mmapFunc(), socketFunc(), and socketpairFunc().

ps

Bitfield<7> X86ISA::ps

Definition at line 144 of file pagetable.hh.

pse

Bitfield<4> X86ISA::pse

Definition at line 634 of file misc.hh.

pvi

Bitfield<1> X86ISA::pvi

Definition at line 637 of file misc.hh.

pwt

Bitfield< 3 > X86ISA::pwt

Definition at line 148 of file pagetable.hh.

R

X86ISA::R

Definition at line 49 of file int.hh.

Referenced by SC_MODULE().

r

Bitfield< 2 > X86ISA::r

Definition at line 934 of file misc.hh.

Referenced by X86ISA::RemoteGDB::X86GdbRegCache::getRegs(), X86ISA::LongModePTE::readonly(), X86ISA::RemoteGDB::X86GdbRegCache::setRegs(), and X86ISA::RemoteGDB::AMD64GdbRegCache::setRegs().

rd

Bitfield<4> X86ISA::rd

Definition at line 821 of file misc.hh.

RE

const uint8_t X86ISA::RE = Rep

Definition at line 53 of file decoder_tables.cc.

Referenced by SC_MODULE().

readable

Bitfield<13> X86ISA::readable

Definition at line 995 of file misc.hh.

reg

Bitfield<5,3> X86ISA::reg

Definition at line 87 of file types.hh.

Referenced by ArmISA::AArch32isUndefinedGenericTimer(), SimpleFreeList::addReg(), Trace::TarmacTracerRecordV8::addRegEntry(), Trace::TarmacTracerRecord::addRegEntry(), SimpleFreeList::addRegs(), Minor::Scoreboard::canInstIssue(), ArmISA::canReadAArch64SysReg(), ArmISA::canReadCoprocReg(), ArmISA::canWriteAArch64SysReg(), ArmISA::canWriteCoprocReg(), Minor::Scoreboard::clearInstDests(), ArmV8KvmCPU::dump(), Minor::Scoreboard::execSeqNumToWaitFor(), Minor::Scoreboard::findIndex(), RiscvISA::ISA::flattenCCIndex(), X86ISA::ISA::flattenCCIndex(), PowerISA::ISA::flattenCCIndex(), MipsISA::ISA::flattenCCIndex(), SparcISA::ISA::flattenCCIndex(), ArmISA::ISA::flattenCCIndex(), RiscvISA::ISA::flattenFloatIndex(), X86ISA::ISA::flattenFloatIndex(), PowerISA::ISA::flattenFloatIndex(), MipsISA::ISA::flattenFloatIndex(), SparcISA::ISA::flattenFloatIndex(), ArmISA::ISA::flattenFloatIndex(), PowerISA::ISA::flattenIntIndex(), X86ISA::ISA::flattenIntIndex(), RiscvISA::ISA::flattenIntIndex(), MipsISA::ISA::flattenIntIndex(), SparcISA::ISA::flattenIntIndex(), ArmISA::ISA::flattenIntIndex(), ArmISA::flattenIntRegModeIndex(), RiscvISA::ISA::flattenMiscIndex(), X86ISA::ISA::flattenMiscIndex(), PowerISA::ISA::flattenMiscIndex(), MipsISA::ISA::flattenMiscIndex(), SparcISA::ISA::flattenMiscIndex(), ArmISA::ISA::flattenMiscIndex(), Minor::flattenRegIndex(), RiscvISA::ISA::flattenVecElemIndex(), X86ISA::ISA::flattenVecElemIndex(), PowerISA::ISA::flattenVecElemIndex(), MipsISA::ISA::flattenVecElemIndex(), SparcISA::ISA::flattenVecElemIndex(), ArmISA::ISA::flattenVecElemIndex(), RiscvISA::ISA::flattenVecIndex(), PowerISA::ISA::flattenVecIndex(), X86ISA::ISA::flattenVecIndex(), MipsISA::ISA::flattenVecIndex(), SparcISA::ISA::flattenVecIndex(), ArmISA::ISA::flattenVecIndex(), RiscvISA::ISA::flattenVecPredIndex(), X86ISA::ISA::flattenVecPredIndex(), PowerISA::ISA::flattenVecPredIndex(), MipsISA::ISA::flattenVecPredIndex(), SparcISA::ISA::flattenVecPredIndex(), ArmISA::ISA::flattenVecPredIndex(), MrsOp::generateDisassembly(), Trace::TarmacTracerRecord::genRegister(), GuestABI::Argument< Aapcs32Vfp, Float, typename std::enable_if< std::is_floating_point< Float >::value >::type >::get(), GuestABI::Argument< Aapcs32Vfp, HA, typename std::enable_if< IsAapcs32HomogeneousAggregate< HA >::value >::type >::get(), KvmKernelGicV2::getGicReg(), BaseKvmCPU::getOneReg(), PhysRegFile::getRegElemIds(), ArmV8KvmCPU::getSysRegMap(), PhysRegFile::getTrueId(), CheckerThreadContext< TC >::getWritableVecPredReg(), SimpleThread::getWritableVecPredReg(), SimpleThread::getWritableVecPredRegFlat(), Minor::ExecContext::getWritableVecPredRegOperand(), CheckerCPU::getWritableVecPredRegOperand(), SimpleExecContext::getWritableVecPredRegOperand(), CheckerThreadContext< TC >::getWritableVecReg(), SimpleThread::getWritableVecReg(), SimpleThread::getWritableVecRegFlat(), Minor::ExecContext::getWritableVecRegOperand(), CheckerCPU::getWritableVecRegOperand(), SimpleExecContext::getWritableVecRegOperand(), ArmISA::ISA::InitReg(), ArmISA::intRegInMode(), ArmISA::isSP(), ArmISA::MacroMemOp::MacroMemOp(), ArmISA::makeSP(), ArmISA::makeZero(), Minor::Scoreboard::markupInstDests(), ArmISA::TableWalker::memAttrsLPAE(), X86ISA::X86StaticInst::merge(), Trace::TarmacTracerRecord::mergeCCEntry(), CustomNoMaliGpu::onReset(), Net::EthAddr::operator uint64_t(), X86ISA::X86StaticInst::pick(), ArmISA::preUnflattenMiscReg(), SparcISA::SparcStaticInst::printDestReg(), X86ISA::X86StaticInst::printDestReg(), MsrBase::printMsrBase(), PowerISA::PowerStaticInst::printReg(), SparcISA::SparcStaticInst::printReg(), X86ISA::X86StaticInst::printReg(), Minor::printRegName(), SparcISA::SparcStaticInst::printSrcReg(), X86ISA::X86StaticInst::printSrcReg(), EnergyCtrl::read(), X86ISA::Interrupts::read(), Sinic::Device::read(), NSGigE::read(), CheckerCPU::readCCRegOperand(), SimpleExecContext::readCCRegOperand(), Minor::ExecContext::readCCRegOperand(), Minor::ExecContext::readFloatRegOperandBits(), SimpleExecContext::readFloatRegOperandBits(), CheckerCPU::readFloatRegOperandBits(), Minor::ExecContext::readIntRegOperand(), SimpleExecContext::readIntRegOperand(), CheckerCPU::readIntRegOperand(), GenericTimer::readMiscReg(), GenericTimerISA::readMiscReg(), ArmISA::ISA::readMiscRegNoEffect(), BaseO3DynInst< Impl >::readMiscRegOperand(), SimpleExecContext::readMiscRegOperand(), Minor::ExecContext::readMiscRegOperand(), CheckerCPU::readMiscRegOperand(), NoMaliGpu::readReg(), X86ISA::Interrupts::readReg(), X86ISA::Cmos::readRegister(), MipsISA::readRegOtherThread(), NoMaliGpu::readRegRaw(), CheckerCPU::readVec16BitLaneOperand(), Minor::ExecContext::readVec16BitLaneOperand(), CheckerThreadContext< TC >::readVec16BitLaneReg(), SimpleThread::readVec16BitLaneReg(), CheckerCPU::readVec32BitLaneOperand(), Minor::ExecContext::readVec32BitLaneOperand(), CheckerThreadContext< TC >::readVec32BitLaneReg(), SimpleThread::readVec32BitLaneReg(), CheckerCPU::readVec64BitLaneOperand(), Minor::ExecContext::readVec64BitLaneOperand(), CheckerThreadContext< TC >::readVec64BitLaneReg(), SimpleThread::readVec64BitLaneReg(), CheckerCPU::readVec8BitLaneOperand(), Minor::ExecContext::readVec8BitLaneOperand(), CheckerThreadContext< TC >::readVec8BitLaneReg(), SimpleThread::readVec8BitLaneReg(), O3ThreadContext< Impl >::readVecElem(), CheckerThreadContext< TC >::readVecElem(), SimpleThread::readVecElem(), SimpleThread::readVecElemFlat(), Minor::ExecContext::readVecElemOperand(), CheckerCPU::readVecElemOperand(), SimpleExecContext::readVecElemOperand(), SimpleThread::readVecLane(), SimpleThread::readVecLaneFlat(), SimpleExecContext::readVecLaneOperand(), CheckerThreadContext< TC >::readVecPredReg(), Iris::ThreadContext::readVecPredReg(), SimpleThread::readVecPredReg(), SimpleThread::readVecPredRegFlat(), Minor::ExecContext::readVecPredRegOperand(), CheckerCPU::readVecPredRegOperand(), SimpleExecContext::readVecPredRegOperand(), CheckerThreadContext< TC >::readVecReg(), Iris::ThreadContext::readVecReg(), SimpleThread::readVecReg(), SimpleThread::readVecRegFlat(), Minor::ExecContext::readVecRegOperand(), CheckerCPU::readVecRegOperand(), SimpleExecContext::readVecRegOperand(), RiscvISA::registerName(), Sinic::Device::serialize(), SimpleExecContext::setCCRegOperand(), CheckerCPU::setCCRegOperand(), Minor::ExecContext::setCCRegOperand(), SimpleExecContext::setFloatRegOperandBits(), Minor::ExecContext::setFloatRegOperandBits(), CheckerCPU::setFloatRegOperandBits(), KvmKernelGicV2::setGicReg(), SimpleExecContext::setIntRegOperand(), Minor::ExecContext::setIntRegOperand(), CheckerCPU::setIntRegOperand(), GenericTimer::setMiscReg(), GenericTimerISA::setMiscReg(), ArmISA::ISA::setMiscRegNoEffect(), BaseO3DynInst< Impl >::setMiscRegOperand(), SimpleExecContext::setMiscRegOperand(), Minor::ExecContext::setMiscRegOperand(), CheckerCPU::setMiscRegOperand(), BaseKvmCPU::setOneReg(), X86ISA::Interrupts::setReg(), X86ISA::Interrupts::setRegNoEffect(), MipsISA::setRegOtherThread(), O3ThreadContext< Impl >::setVecElem(), CheckerThreadContext< TC >::setVecElem(), SimpleThread::setVecElem(), SimpleThread::setVecElemFlat(), Minor::ExecContext::setVecElemOperand(), SimpleExecContext::setVecElemOperand(), CheckerCPU::setVecElemOperand(), O3ThreadContext< Impl >::setVecLane(), CheckerThreadContext< TC >::setVecLane(), SimpleThread::setVecLane(), SimpleThread::setVecLaneFlat(), CheckerCPU::setVecLaneOperandT(), Minor::ExecContext::setVecLaneOperandT(), SimpleExecContext::setVecLaneOperandT(), SimpleThread::setVecLaneT(), O3ThreadContext< Impl >::setVecPredReg(), CheckerThreadContext< TC >::setVecPredReg(), SimpleThread::setVecPredReg(), SimpleThread::setVecPredRegFlat(), Minor::ExecContext::setVecPredRegOperand(), SimpleExecContext::setVecPredRegOperand(), CheckerCPU::setVecPredRegOperand(), O3ThreadContext< Impl >::setVecReg(), CheckerThreadContext< TC >::setVecReg(), SimpleThread::setVecReg(), SimpleThread::setVecRegFlat(), Minor::ExecContext::setVecRegOperand(), SimpleExecContext::setVecRegOperand(), CheckerCPU::setVecRegOperand(), X86ISA::X86StaticInst::signedPick(), MipsISA::simdPack(), MipsISA::simdUnpack(), ArmISA::snsBankedIndex(), ArmISA::ISA::snsBankedIndex64(), ArmISA::snsBankedIndex64(), GuestABI::Result< Aapcs32Vfp, Float, typename std::enable_if< std::is_floating_point< Float >::value >::type >::store(), GuestABI::Result< Aapcs32Vfp, HA, typename std::enable_if< IsAapcs32HomogeneousAggregate< HA >::value >::type >::store(), stringToRegister(), ArmISA::unflattenMiscReg(), Sinic::Device::unserialize(), ArmV8KvmCPU::updateKvmState(), ArmKvmCPU::updateKvmStateCoProc(), ArmKvmCPU::updateTCStateCoProc(), ArmV8KvmCPU::updateThreadContext(), VectorRegisterFile::VectorRegisterFile(), EnergyCtrl::write(), X86ISA::Interrupts::write(), NSGigE::write(), NoMaliGpu::writeReg(), X86ISA::Cmos::writeRegister(), and NoMaliGpu::writeRegRaw().

rep

Bitfield<6> X86ISA::rep

Definition at line 76 of file types.hh.

Referenced by sc_gem5::VcdTraceValBase::printVal().

repne

Bitfield<7> X86ISA::repne

Definition at line 75 of file types.hh.

ReturnAddressReg

const int X86ISA::ReturnAddressReg = 0

Definition at line 87 of file registers.hh.

ReturnValueReg

const int X86ISA::ReturnValueReg = INTREG_RAX

Definition at line 88 of file registers.hh.

rf

Bitfield<16> X86ISA::rf

Definition at line 563 of file misc.hh.

Referenced by RegisterFile::MarkRegBusyScbEvent::process().

rInit

Bitfield<1> X86ISA::rInit

Definition at line 836 of file misc.hh.

rm

Bitfield<2,0> X86ISA::rm

Definition at line 88 of file types.hh.

Referenced by X86ISA::EmulEnv::doModRM().

RN

const uint8_t X86ISA::RN = Repne

Definition at line 54 of file decoder_tables.cc.

rpl

Bitfield<1, 0> X86ISA::rpl

Definition at line 862 of file misc.hh.

rsmCycle

Bitfield<4> X86ISA::rsmCycle

Definition at line 849 of file misc.hh.

rw0

Bitfield<17, 16> X86ISA::rw0

Definition at line 667 of file misc.hh.

rw1

Bitfield<21, 20> X86ISA::rw1

Definition at line 669 of file misc.hh.

rw2

Bitfield<25, 24> X86ISA::rw2

Definition at line 671 of file misc.hh.

rw3

Bitfield<29, 28> X86ISA::rw3

Definition at line 673 of file misc.hh.

RX

const uint8_t X86ISA::RX = RexPrefix

Definition at line 55 of file decoder_tables.cc.

s

Bitfield<44> X86ISA::s

Definition at line 927 of file misc.hh.

Referenced by Float16::Float16(), and Float16::operator float().

scale

X86ISA::scale

Definition at line 92 of file types.hh.

Referenced by ArmISA::fp16_muladd(), ArmISA::fp32_muladd(), ArmISA::fp64_muladd(), MultiperspectivePerceptron::BLURRYPATH::getHash(), X86ISA::X86StaticInst::printMem(), sc_core::sc_time::sc_time(), ArmISA::vfpSFixedToFpD(), ArmISA::vfpSFixedToFpS(), ArmISA::vfpUFixedToFpD(), and ArmISA::vfpUFixedToFpS().

SE

SignedBitfield<31,0> X86ISA::SE

Definition at line 52 of file int.hh.

seg

Bitfield<2,0> X86ISA::seg

Definition at line 82 of file types.hh.

Referenced by Loader::MemoryImage::addSegment(), Loader::MemoryImage::addSegments(), checkSeg(), Loader::MemoryImage::contains(), dumpKvm(), Loader::ElfObject::ElfObject(), forceSegAccessed(), X86ISA::X86_64Process::initState(), X86ISA::I386Process::initState(), installSegDesc(), X86ISA::InitInterrupt::invoke(), Loader::MemoryImage::maxAddr(), Loader::MemoryImage::MemoryImage(), Loader::MemoryImage::minAddr(), Loader::MemoryImage::move(), Loader::operator<<(), X86ISA::GpuTLB::tlbLookup(), X86ISA::TLB::translate(), X86ISA::GpuTLB::translate(), Loader::MemoryImage::write(), and Loader::MemoryImage::writeSegment().

SegmentFlagMask

const Request::FlagsType M5_VAR_USED X86ISA::SegmentFlagMask = mask(4)

Definition at line 49 of file ldstflags.hh.

Referenced by X86ISA::GpuTLB::tlbLookup(), X86ISA::TLB::translate(), and X86ISA::GpuTLB::translate().

selector

Bitfield< 31, 16 > X86ISA::selector

Definition at line 1003 of file misc.hh.

Referenced by Gcn3ISA::Inst_VOP3__V_PERM_B32::execute().

sf

Bitfield< 7 > X86ISA::sf

Definition at line 545 of file misc.hh.

SH

SignedBitfield<15,8> X86ISA::SH

Definition at line 56 of file int.hh.

si

Bitfield<15, 3> X86ISA::si

Definition at line 860 of file misc.hh.

Referenced by X86ISA::Decoder::decode().

SL

SignedBitfield<7, 0> X86ISA::SL

Definition at line 58 of file int.hh.

smiCycle

Bitfield<2> X86ISA::smiCycle

Definition at line 847 of file misc.hh.

SR

SignedBitfield<63,0> X86ISA::SR

Definition at line 50 of file int.hh.

SS

const uint8_t X86ISA::SS = SSOverride

Definition at line 48 of file decoder_tables.cc.

stack

Bitfield<17, 16> X86ISA::stack

Definition at line 587 of file misc.hh.

Referenced by X86Linux::archClone(), RiscvLinux64::archClone(), SparcLinux::archClone(), ArmLinux32::archClone(), RiscvLinux32::archClone(), ArmLinux64::archClone(), FunctionProfile::consume(), and setupAltStack().

StackPointerReg

const int X86ISA::StackPointerReg = INTREG_RSP

Definition at line 85 of file registers.hh.

Referenced by X86Linux::archClone(), and X86ISA::X86Process::argsInit().

submode

Bitfield< 2, 0 > X86ISA::submode

Definition at line 579 of file misc.hh.

svme

Bitfield<12> X86ISA::svme

Definition at line 785 of file misc.hh.

SX

SignedBitfield<15,0> X86ISA::SX

Definition at line 54 of file int.hh.

syscallCodeVirtAddr

const Addr X86ISA::syscallCodeVirtAddr = 0xffff800000000000

Definition at line 69 of file fs_workload.hh.

Referenced by X86ISA::X86_64Process::initState().

syscallCsAndSs

Bitfield<47,32> X86ISA::syscallCsAndSs

Definition at line 791 of file misc.hh.

SyscallPseudoReturnReg

const int X86ISA::SyscallPseudoReturnReg = INTREG_RDX

Definition at line 93 of file registers.hh.

sysretCsAndSs

Bitfield<63,48> X86ISA::sysretCsAndSs

Definition at line 792 of file misc.hh.

system

Bitfield<15> X86ISA::system

Definition at line 997 of file misc.hh.

Referenced by sc_gem5::TlmToGem5Bridge< BITWIDTH >::before_end_of_elaboration(), exitImpl(), ArmISA::ISA::initializeMiscRegMetadata(), FullO3CPU< O3CPUImpl >::insertThread(), FullO3CPU< O3CPUImpl >::instDone(), Iob::Iob(), sc_gem5::Gem5ToTlmBridge< BITWIDTH >::nb_transport_bw(), sc_gem5::Gem5ToTlmBridge< BITWIDTH >::recvTimingReq(), and FullO3CPU< O3CPUImpl >::verifyMemoryMode().

targetCS

X86ISA::targetCS

Definition at line 688 of file misc.hh.

targetEIP

X86ISA::targetEIP

Definition at line 696 of file misc.hh.

targetEip

X86ISA::targetEip

Definition at line 790 of file misc.hh.

targetESP

X86ISA::targetESP

Definition at line 692 of file misc.hh.

tf

Bitfield<8> X86ISA::tf

Definition at line 569 of file misc.hh.

Referenced by sc_core::sc_in< sc_dt::sc_lv< W > >::add_trace(), sc_core::sc_inout< sc_dt::sc_lv< W > >::add_trace(), sc_core::sc_in< bool >::add_trace(), sc_core::sc_inout< bool >::add_trace(), sc_core::sc_in< sc_dt::sc_logic >::add_trace(), sc_core::sc_inout< sc_dt::sc_logic >::add_trace(), sc_gem5::Scheduler::registerTraceFile(), sc_core::sc_close_vcd_trace_file(), sc_core::sc_create_vcd_trace_file(), sc_core::sc_trace(), sc_core::sc_trace< bool >(), sc_core::sc_trace< sc_dt::sc_logic >(), sc_core::sc_trace_delta_cycles(), sc_core::sc_write_comment(), sc_gem5::Scheduler::trace(), and sc_gem5::Scheduler::unregisterTraceFile().

ti

Bitfield<2> X86ISA::ti

Definition at line 861 of file misc.hh.

tom2

Bitfield<21> X86ISA::tom2

Definition at line 816 of file misc.hh.

top5

X86ISA::top5

Definition at line 175 of file types.hh.

tpr

X86ISA::tpr

Definition at line 642 of file misc.hh.

trigger

Bitfield< 15 > X86ISA::trigger

Definition at line 48 of file intmessage.hh.

Referenced by Prefetcher::PIF::CompactorEntry::distanceFromTrigger(), Prefetcher::PIF::CompactorEntry::getPredictedAddresses(), Prefetcher::PIF::CompactorEntry::hasAddress(), Prefetcher::PIF::CompactorEntry::inSameSpatialRegion(), and X86ISA::IntelMP::IntAssignment::IntAssignment().

TriggerIntOffset

const Addr X86ISA::TriggerIntOffset = 0

static

Definition at line 76 of file intmessage.hh.

Referenced by buildIntTriggerPacket().

ts

Bitfield<3> X86ISA::ts

Definition at line 601 of file misc.hh.

tsd

Bitfield<2> X86ISA::tsd

Definition at line 636 of file misc.hh.

TSSPhysAddr

const Addr X86ISA::TSSPhysAddr = 0x63000

Definition at line 73 of file fs_workload.hh.

TSSVirtAddr

const Addr X86ISA::TSSVirtAddr = 0xffff800000003000

Definition at line 72 of file fs_workload.hh.

Referenced by X86ISA::X86_64Process::initState().

type

Bitfield< 43, 40 > X86ISA::type

Definition at line 727 of file misc.hh.

Referenced by opcodeTypeToStr(), X86ISA::IntelMP::BaseConfigEntry::writeOut(), and X86ISA::IntelMP::ExtConfigEntry::writeOut().

u

Bitfield<2> X86ISA::u

Definition at line 149 of file pagetable.hh.

Referenced by X86ISA::LongModePTE::uncacheable().

uc

Bitfield<61> X86ISA::uc

Definition at line 767 of file misc.hh.

unitMask

Bitfield<15,8> X86ISA::unitMask

Definition at line 801 of file misc.hh.

unusable

Bitfield<2> X86ISA::unusable

Definition at line 987 of file misc.hh.

usr

Bitfield<16> X86ISA::usr

Definition at line 802 of file misc.hh.

Referenced by NoMaliGpu::_interrupt(), and NoMaliGpu::_reset().

v

Bitfield< 6, 3 > X86ISA::v

Definition at line 120 of file types.hh.

V2

const uint8_t X86ISA::V2 = Vex2Prefix

Definition at line 56 of file decoder_tables.cc.

V3

const uint8_t X86ISA::V3 = Vex3Prefix

Definition at line 57 of file decoder_tables.cc.

val

Bitfield<63> X86ISA::val

Definition at line 769 of file misc.hh.

Referenced by ArmISA::ISA::addressTranslation(), ArmISA::ISA::addressTranslation64(), alignToPowerOfTwo(), ArmISA::AbortFault< DataAbort >::annotate(), ArmISA::DataAbort::annotate(), ArmISA::Watchpoint::annotate(), sc_core::sc_module::async_reset_signal_is(), bcdize(), bits(), bitsToFloat(), bitsToFloat32(), bitsToFloat64(), ArmISA::bitsToFp(), BitfieldBackend::BitUnionOperators< Base >::BitUnionOperators(), Trace::NativeTrace::checkReg(), composeBitVector(), MultiperspectivePerceptron::computeOutput(), sc_dt::sc_uint_subref_r::concat_get_data(), sc_dt::sc_int_subref_r::concat_get_data(), sc_dt::sc_uint_base::concat_get_data(), sc_dt::sc_int_base::concat_get_data(), sc_dt::sc_int_subref_r::concat_get_uint64(), Stats::constant(), Stats::constantVector(), MuxingKvmGic::copyCpuRegister(), MuxingKvmGic::copyDistRegister(), GenericTimerMem::counterCtrlWrite(), Gcn3ISA::countZeroBits(), Gcn3ISA::countZeroBitsMsb(), ArmISA::ArmStaticInst::cpsrWriteByInstr(), ArmISA::ArmStaticInst::cSwap(), ArmISA::FpOp::dblHi(), ArmISA::FpOp::dblLow(), Stats::StatStor::dec(), Stats::AvgStor::dec(), GenericISA::DelaySlotPCState< MachInst >::DelaySlotPCState(), GenericISA::DelaySlotUPCState< MachInst >::DelaySlotUPCState(), PerfKvmCounterConfig::disabled(), ArmV8KvmCPU::dump(), GenericTimer::CoreTimers::EventStream::eventTargetValue(), PerfKvmCounterConfig::exclude_host(), PerfKvmCounterConfig::exclude_hv(), MipsISA::ISA::filterCP0Write(), Gcn3ISA::findFirstOne(), Gcn3ISA::findFirstOneMsb(), Gcn3ISA::findFirstZero(), findLsbSet(), findMsbSet(), Gcn3ISA::firstOppositeSignBit(), ArmISA::fixDest(), ArmISA::fixDivDest(), ArmISA::fixFpDFpSDest(), ArmISA::fixFpSFpDDest(), floatToBits(), floatToBits32(), floatToBits64(), ArmISA::fpToBits(), futexFunc(), Gicv3CPUInterface::generateSGI(), GuestABI::Argument< Aapcs32, Composite, typename std::enable_if< IsAapcs32Composite< Composite >::value >::type >::get(), GuestABI::Argument< Aapcs64, Composite, typename std::enable_if< IsAapcs64Composite< Composite >::value &&!IsAapcs64Hxa< Composite >::value >::type >::get(), GuestABI::Argument< Aapcs32Vfp, Float, typename std::enable_if< std::is_floating_point< Float >::value >::type >::get(), GuestABI::Argument< Aapcs32Vfp, HA, typename std::enable_if< IsAapcs32HomogeneousAggregate< HA >::value >::type >::get(), TAGEBase::getGHR(), getsockoptFunc(), HSAQueueEntry::globalWgId(), BloomFilter::H3::hash(), ArmISA::highFromDouble(), Stats::StatStor::inc(), Stats::AvgStor::inc(), ArmISA::PMU::PMUEvent::increment(), Trie< Addr, TlbEntry >::insert(), insertBits(), PowerISA::FloatOp::isNan(), RiscvISA::isquietnan< double >(), RiscvISA::isquietnan< float >(), ArmISA::AbortFault< DataAbort >::iss(), ArmISA::DataAbort::iss(), RiscvISA::issignalingnan< double >(), RiscvISA::issignalingnan< float >(), ArmISA::isSnan(), GuestABI::Aapcs32ArgumentBase::loadFromStack(), sc_dt::sc_fxnum::lock_observer(), ArmISA::lowFromDouble(), sc_core::sc_report::make_warnings_errors(), mbits(), X86ISA::X86StaticInst::merge(), mod(), GenericISA::DelaySlotPCState< MachInst >::nnpc(), ProbeListenerArg< T, Arg >::notify(), ArmISA::PMU::RegularEvent::RegularProbe::notify(), GenericISA::SimplePCState< MachInst >::npc(), ArmISA::number_of_ones(), GenericISA::UPCState< MachInst >::nupc(), GenericISA::DelaySlotUPCState< MachInst >::nupc(), sc_dt::sc_uint_subref_r::operator uint_type(), sc_dt::sc_int_subref_r::operator uint_type(), std::hash< BitUnionType< T > >::operator()(), BitfieldTypeImpl< Base >::operator=(), BitfieldType< Base >::operator=(), BitfieldWOType< Base >::operator=(), BitfieldBackend::BitUnionOperators< Base >::operator=(), sc_dt::sc_uint_subref::operator=(), sc_dt::sc_int_subref::operator=(), sc_gem5::VcdTraceValTime::output(), sc_gem5::VcdTraceValInt< T >::output(), sc_dt::overflow(), GenericISA::SimplePCState< MachInst >::pc(), X86ISA::PCState::PCState(), DefaultCommit< Impl >::pcState(), O3ThreadContext< Impl >::pcState(), Minor::ExecContext::pcState(), CheckerThreadContext< TC >::pcState(), Iris::ThreadContext::pcState(), SimpleExecContext::pcState(), CheckerCPU::pcState(), FullO3CPU< O3CPUImpl >::pcState(), SimpleThread::pcState(), BaseDynInst< Impl >::pcState(), GenericISA::PCStateBase::PCStateBase(), O3ThreadContext< Impl >::pcStateNoRecord(), Iris::ThreadContext::pcStateNoRecord(), CheckerThreadContext< TC >::pcStateNoRecord(), SimpleThread::pcStateNoRecord(), PerfKvmCounterConfig::pinned(), popCount(), CircularQueue< Prefetcher::STeMS::RegionMissOrderBufferEntry >::push_back(), Gcn3ISA::quadMask(), DistIface::rankParam(), X86ISA::Interrupts::read(), VncServer::read(), Gicv3Distributor::read(), Gcn3ISA::GPUISA::readConstVal(), FastModel::CortexA76TC::readIntRegFlat(), RiscvISA::ISA::readMiscReg(), ArmISA::PMU::readMiscReg(), ArmISA::ISA::readMiscReg(), ArmISA::ISA::readMiscRegNoEffect(), X86ISA::Interrupts::readReg(), X86ISA::Cmos::readRegister(), PhysRegFile::readVecElem(), CheckerCPU::recordPCChange(), Trie< Addr, TlbEntry >::remove(), replaceBits(), sc_core::sc_module::reset_signal_is(), Sp804::Timer::restartCounter(), CpuLocalTimer::Timer::restartTimerCounter(), CpuLocalTimer::Timer::restartWatchdogCounter(), reverseBits(), roundDown(), MipsISA::roundFP(), Gcn3ISA::roundNearestEven(), ArmISA::roundNEven(), roundUp(), RiscvISA::PCState::rv32(), Stats::DistStor::sample(), Stats::HistStor::sample(), Stats::SampleStor::sample(), Stats::AvgSampleStor::sample(), Stats::SparseHistStor::sample(), Shader::ScheduleAdd(), Flags< FlagsType >< FlagsType >::set(), GenericISA::SimplePCState< MachInst >::set(), GenericISA::UPCState< MachInst >::set(), X86ISA::PCState::set(), GenericISA::DelaySlotPCState< MachInst >::set(), GenericISA::DelaySlotUPCState< MachInst >::set(), Stats::StatStor::set(), Stats::AvgStor::set(), FastModel::CortexA76::set_evs_param(), FastModel::CortexA76Cluster::set_evs_param(), VecPredRegT< VecElem, NumElems, Packed, Const >::set_raw(), ArmISA::ArmStaticInst::setAIWNextPC(), FullO3CPU< O3CPUImpl >::setArchCCReg(), FullO3CPU< O3CPUImpl >::setArchFloatReg(), FullO3CPU< O3CPUImpl >::setArchIntReg(), FullO3CPU< O3CPUImpl >::setArchVecElem(), FullO3CPU< O3CPUImpl >::setArchVecLane(), FullO3CPU< O3CPUImpl >::setArchVecPredReg(), FullO3CPU< O3CPUImpl >::setArchVecReg(), Gicv3CPUInterface::setBankedMiscReg(), ArmISA::SelfDebug::setbSDD(), MipsISA::setCauseIP(), O3ThreadContext< Impl >::setCCReg(), PhysRegFile::setCCReg(), CheckerThreadContext< TC >::setCCReg(), Iris::ThreadContext::setCCReg(), FullO3CPU< O3CPUImpl >::setCCReg(), SimpleThread::setCCReg(), FastModel::CortexA76TC::setCCRegFlat(), O3ThreadContext< Impl >::setCCRegFlat(), Iris::ThreadContext::setCCRegFlat(), CheckerThreadContext< TC >::setCCRegFlat(), SimpleThread::setCCRegFlat(), SimpleExecContext::setCCRegOperand(), CheckerCPU::setCCRegOperand(), BaseO3DynInst< Impl >::setCCRegOperand(), Minor::ExecContext::setCCRegOperand(), BaseDynInst< Impl >::setCCRegOperand(), ArchTimer::setCompareValue(), ArchTimer::setControl(), ArmISA::PMU::setControlReg(), ArmISA::PMU::setCounterTypeRegister(), ArmISA::PMU::setCounterValue(), Trace::InstRecord::setFaulting(), PhysRegFile::setFloatReg(), O3ThreadContext< Impl >::setFloatReg(), CheckerThreadContext< TC >::setFloatReg(), FullO3CPU< O3CPUImpl >::setFloatReg(), SimpleThread::setFloatReg(), O3ThreadContext< Impl >::setFloatRegFlat(), CheckerThreadContext< TC >::setFloatRegFlat(), SimpleThread::setFloatRegFlat(), SimpleExecContext::setFloatRegOperandBits(), Minor::ExecContext::setFloatRegOperandBits(), CheckerCPU::setFloatRegOperandBits(), BaseO3DynInst< Impl >::setFloatRegOperandBits(), BaseDynInst< Impl >::setFloatRegOperandBits(), SparcISA::ISA::setFSReg(), Request::setHtmAbortCause(), RiscvISA::Interrupts::setIE(), AbstractCacheEntry::setInHtmReadSet(), AbstractCacheEntry::setInHtmWriteSet(), Request::setInstCount(), PhysRegFile::setIntReg(), O3ThreadContext< Impl >::setIntReg(), CheckerThreadContext< TC >::setIntReg(), Iris::ThreadContext::setIntReg(), FullO3CPU< O3CPUImpl >::setIntReg(), SimpleThread::setIntReg(), FastModel::CortexA76TC::setIntRegFlat(), O3ThreadContext< Impl >::setIntRegFlat(), Iris::ThreadContext::setIntRegFlat(), CheckerThreadContext< TC >::setIntRegFlat(), SimpleThread::setIntRegFlat(), SimpleExecContext::setIntRegOperand(), Minor::ExecContext::setIntRegOperand(), CheckerCPU::setIntRegOperand(), BaseO3DynInst< Impl >::setIntRegOperand(), BaseDynInst< Impl >::setIntRegOperand(), RiscvISA::Interrupts::setIP(), ArmISA::ArmStaticInst::setIWNextPC(), ArmISA::SelfDebug::setMDBGen(), ArmISA::SelfDebug::setMDSCRvals(), Minor::MinorDynInst::setMemAccPredicate(), Minor::ExecContext::setMemAccPredicate(), CheckerCPU::setMemAccPredicate(), SimpleExecContext::setMemAccPredicate(), SimpleThread::setMemAccPredicate(), BaseDynInst< Impl >::setMemAccPredicate(), X86ISA::ISA::setMiscReg(), RiscvISA::ISA::setMiscReg(), ArmISA::DummyISADevice::setMiscReg(), MipsISA::ISA::setMiscReg(), ArmISA::PMU::setMiscReg(), BaseO3DynInst< Impl >::setMiscReg(), SparcISA::ISA::setMiscReg(), GenericTimer::setMiscReg(), Gicv3CPUInterface::setMiscReg(), FullO3CPU< O3CPUImpl >::setMiscReg(), GenericTimerISA::setMiscReg(), Minor::ExecContext::setMiscReg(), O3ThreadContext< Impl >::setMiscReg(), SimpleExecContext::setMiscReg(), Iris::ThreadContext::setMiscReg(), CheckerThreadContext< TC >::setMiscReg(), ArmISA::ISA::setMiscReg(), CheckerCPU::setMiscReg(), SimpleThread::setMiscReg(), X86ISA::ISA::setMiscRegNoEffect(), RiscvISA::ISA::setMiscRegNoEffect(), MipsISA::ISA::setMiscRegNoEffect(), SparcISA::ISA::setMiscRegNoEffect(), FullO3CPU< O3CPUImpl >::setMiscRegNoEffect(), O3ThreadContext< Impl >::setMiscRegNoEffect(), Iris::ThreadContext::setMiscRegNoEffect(), CheckerThreadContext< TC >::setMiscRegNoEffect(), ArmISA::ISA::setMiscRegNoEffect(), CheckerCPU::setMiscRegNoEffect(), SimpleThread::setMiscRegNoEffect(), BaseO3DynInst< Impl >::setMiscRegOperand(), SimpleExecContext::setMiscRegOperand(), Minor::ExecContext::setMiscRegOperand(), CheckerCPU::setMiscRegOperand(), ArmISA::ArmStaticInst::setNextPC(), GenericISA::SimplePCState< MachInst >::setNPC(), ThreadContext::setNPC(), X86ISA::PCState::setNPC(), CheckerThreadContext< TC >::setNPC(), ArchTimer::setOffset(), Trace::InstRecord::setPredicate(), Minor::MinorDynInst::setPredicate(), Minor::ExecContext::setPredicate(), CheckerCPU::setPredicate(), SimpleExecContext::setPredicate(), SimpleThread::setPredicate(), BaseDynInst< Impl >::setPredicate(), X86ISA::Interrupts::setReg(), MipsISA::ISA::setRegMask(), X86ISA::Interrupts::setRegNoEffect(), MipsISA::setRegOtherThread(), setRFlags(), BitfieldBackend::Unsigned< Storage, first, last >::setter(), BitfieldBackend::Signed< Storage, first, last >::setter(), ArchTimer::setTimerValue(), ArmISA::PMU::CounterState::setValue(), O3ThreadContext< Impl >::setVecElem(), PhysRegFile::setVecElem(), CheckerThreadContext< TC >::setVecElem(), FullO3CPU< O3CPUImpl >::setVecElem(), SimpleThread::setVecElem(), O3ThreadContext< Impl >::setVecElemFlat(), CheckerThreadContext< TC >::setVecElemFlat(), SimpleThread::setVecElemFlat(), Minor::ExecContext::setVecElemOperand(), SimpleExecContext::setVecElemOperand(), CheckerCPU::setVecElemOperand(), BaseO3DynInst< Impl >::setVecElemOperand(), BaseDynInst< Impl >::setVecElemOperand(), PhysRegFile::setVecLane(), O3ThreadContext< Impl >::setVecLane(), CheckerThreadContext< TC >::setVecLane(), SimpleThread::setVecLane(), FullO3CPU< O3CPUImpl >::setVecLane(), O3ThreadContext< Impl >::setVecLaneFlat(), SimpleThread::setVecLaneFlat(), CheckerCPU::setVecLaneOperand(), Minor::ExecContext::setVecLaneOperand(), SimpleExecContext::setVecLaneOperand(), BaseO3DynInst< Impl >::setVecLaneOperand(), CheckerCPU::setVecLaneOperandT(), Minor::ExecContext::setVecLaneOperandT(), SimpleExecContext::setVecLaneOperandT(), BaseO3DynInst< Impl >::setVecLaneOperandT(), SimpleThread::setVecLaneT(), O3ThreadContext< Impl >::setVecPredReg(), PhysRegFile::setVecPredReg(), CheckerThreadContext< TC >::setVecPredReg(), FullO3CPU< O3CPUImpl >::setVecPredReg(), SimpleThread::setVecPredReg(), O3ThreadContext< Impl >::setVecPredRegFlat(), CheckerThreadContext< TC >::setVecPredRegFlat(), SimpleThread::setVecPredRegFlat(), Minor::ExecContext::setVecPredRegOperand(), SimpleExecContext::setVecPredRegOperand(), CheckerCPU::setVecPredRegOperand(), BaseO3DynInst< Impl >::setVecPredRegOperand(), BaseDynInst< Impl >::setVecPredRegOperand(), PhysRegFile::setVecReg(), O3ThreadContext< Impl >::setVecReg(), CheckerThreadContext< TC >::setVecReg(), FullO3CPU< O3CPUImpl >::setVecReg(), SimpleThread::setVecReg(), O3ThreadContext< Impl >::setVecRegFlat(), CheckerThreadContext< TC >::setVecRegFlat(), SimpleThread::setVecRegFlat(), Minor::ExecContext::setVecRegOperand(), SimpleExecContext::setVecRegOperand(), CheckerCPU::setVecRegOperand(), BaseO3DynInst< Impl >::setVecRegOperand(), BaseDynInst< Impl >::setVecRegOperand(), sext(), GenericISA::SimplePCState< MachInst >::SimplePCState(), DistIface::sizeParam(), ArmISA::ArmStaticInst::spsrWriteByInstr(), GuestABI::Result< ABI, SyscallReturn, typename std::enable_if< std::is_base_of< ArmFreebsdProcessBits::SyscallABI, ABI >::value >::type >::store(), GuestABI::Result< ABI, SyscallReturn, typename std::enable_if< std::is_base_of< SparcProcess::SyscallABI, ABI >::value >::type >::store(), GuestABI::enable_if< std::is_integral< Integer >::value &&(sizeof(Integer)< sizeof(uint32_t)) >::type >::store(), GuestABI::Result< Aapcs32, Composite, typename std::enable_if< IsAapcs32Composite< Composite >::value >::type >::store(), GuestABI::Result< Aapcs64, Composite, typename std::enable_if< IsAapcs64Composite< Composite >::value &&!IsAapcs64Hxa< Composite >::value >::type >::store(), GuestABI::Result< Aapcs32Vfp, HA, typename std::enable_if< IsAapcs32HomogeneousAggregate< HA >::value >::type >::store(), Stats::sum(), TEST(), MipsISA::truncFP(), PortProxy::tryMemsetBlob(), unbcdize(), GenericISA::UPCState< MachInst >::upc(), GenericISA::DelaySlotUPCState< MachInst >::upc(), GenericISA::UPCState< MachInst >::UPCState(), Stats::ScalarPrint::update(), ArmISA::BrkPoint::updateControl(), ArmISA::WatchPoint::updateControl(), ArmISA::SelfDebug::updateDBGBCR(), ArmISA::SelfDebug::updateDBGWCR(), GPUDispatcher::updateInvCounter(), ArmISA::SelfDebug::updateOSLock(), HSAQueueEntry::updateOutstandingInvs(), HSAQueueEntry::updateOutstandingWbs(), GPUDispatcher::updateWbCounter(), Stats::ValueToString(), ArmISA::vfpFpToFixed(), ArmISA::vfpSFixedToFpD(), ArmISA::vfpSFixedToFpS(), ArmISA::vfpUFixedToFpD(), ArmISA::vfpUFixedToFpS(), HSAQueueEntry::wgId(), Gcn3ISA::wholeQuadMode(), X86ISA::Speaker::write(), X86ISA::I8259::write(), Gicv3Its::write(), CopyEngine::write(), ArmSemihosting::InPlaceArg::write(), X86ISA::Interrupts::write(), VncServer::write(), ArmISA::PMU::SWIncrementEvent::write(), IGbE::write(), X86ISA::I8254::writeControl(), GPUExecContext::writeMiscReg(), writeOutField(), X86ISA::Cmos::writeRegister(), writeVal(), sc_dt::sc_uint_base::xor_reduce(), sc_dt::sc_int_base::xor_reduce(), and BaseO3DynInst< Impl >::~BaseO3DynInst().

vcnt

X86ISA::vcnt

Definition at line 679 of file misc.hh.

VecPredRegHasPackedRepr

constexpr bool X86ISA::VecPredRegHasPackedRepr = ::DummyVecPredRegHasPackedRepr

constexpr

Definition at line 108 of file registers.hh.

VecPredRegSizeBits

constexpr size_t X86ISA::VecPredRegSizeBits = ::DummyVecPredRegSizeBits

constexpr

Definition at line 107 of file registers.hh.

VecRegSizeBytes

constexpr size_t X86ISA::VecRegSizeBytes = ::DummyVecRegSizeBytes

constexpr

Definition at line 101 of file registers.hh.

vector

X86ISA::vector

Definition at line 44 of file intmessage.hh.

Referenced by Iob::generateIpi(), Iob::receiveDeviceInterrupt(), X86ISA::Interrupts::requestInterrupt(), Iob::serialize(), Iob::unserialize(), and Iob::writeIob().

vendorString

const char X86ISA::vendorString[vendorStringSize] = "M5 Simulator"

static

Definition at line 71 of file cpuid.cc.

Referenced by doCpuid().

vendorStringSize

const int X86ISA::vendorStringSize = 13

static

Definition at line 70 of file cpuid.cc.

Referenced by doCpuid().

vif

Bitfield<19> X86ISA::vif

Definition at line 560 of file misc.hh.

vip

Bitfield<20> X86ISA::vip

Definition at line 559 of file misc.hh.

vm

Bitfield<17> X86ISA::vm

Definition at line 562 of file misc.hh.

vme

Bitfield<0> X86ISA::vme

Definition at line 638 of file misc.hh.

w

Bitfield< 3 > X86ISA::w

Definition at line 150 of file pagetable.hh.

wc

Bitfield<10> X86ISA::wc

Definition at line 681 of file misc.hh.

wp

Bitfield<16> X86ISA::wp

Definition at line 598 of file misc.hh.

writable

Bitfield<12> X86ISA::writable

Definition at line 994 of file misc.hh.

X

Bitfield<15,0> X86ISA::X

Definition at line 53 of file int.hh.

Referenced by ArmISA::Crypto::_sha1Op(), ArmISA::addPACDA(), ArmISA::addPACDB(), ArmISA::addPACGA(), ArmISA::addPACIA(), ArmISA::addPACIB(), sc_dt::sc_proxy< sc_bv_base >::assign_(), sc_dt::assign_v_(), ArmISA::authDA(), ArmISA::authDB(), ArmISA::authIA(), ArmISA::authIB(), sc_dt::b_and_assign_(), sc_dt::b_or_assign_(), sc_dt::sc_proxy< sc_bv_base >::check_bounds(), ArmISA::Crypto::choose(), sc_dt::sc_lv_base::clean_tail(), TAGEBase::handleAllocAndUReset(), ArmISA::Crypto::load2Reg(), ArmISA::Crypto::load3Reg(), sc_dt::sc_proxy< sc_bv_base >::lrotate(), ArmISA::Crypto::majority(), ArmISA::Crypto::parity(), SC_MODULE(), ArmISA::Crypto::sha1H(), ArmISA::Crypto::sha1Op(), ArmISA::Crypto::sha1Su0(), ArmISA::Crypto::sha1Su1(), ArmISA::Crypto::sha256H(), ArmISA::Crypto::sha256H2(), ArmISA::Crypto::sha256Op(), ArmISA::Crypto::sha256Su0(), ArmISA::Crypto::sha256Su1(), ArmISA::Crypto::sigma0(), ArmISA::Crypto::sigma1(), ArmISA::Crypto::store1Reg(), and sc_dt::sc_proxy< sc_bv_base >::xor_reduce().

x

Bitfield< 6 > X86ISA::x

Definition at line 103 of file types.hh.

Referenced by X86ISA::TLB::serialize(), X86ISA::TLB::TLB(), and X86ISA::TLB::unserialize().

ZeroReg

const int X86ISA::ZeroReg = NUM_INTREGS

Definition at line 84 of file registers.hh.

Referenced by X86ISA::X86StaticInst::printMem().

zf

Bitfield< 6 > X86ISA::zf

Definition at line 546 of file misc.hh.