gem5  v20.1.0.0
ArmISA::ISA Member List

This is the complete list of members for ArmISA::ISA, including all inherited members.

_decoderFlavorArmISA::ISAprotected
_drainManagerDrainableprivate
_drainStateDrainablemutableprivate
_paramsSimObjectprotected
_vecRegRenameModeArmISA::ISAprotected
addressTranslation(TLB::ArmTranslationType tran_type, BaseTLB::Mode mode, Request::Flags flags, RegVal val)ArmISA::ISAprotected
addressTranslation64(TLB::ArmTranslationType tran_type, BaseTLB::Mode mode, Request::Flags flags, RegVal val)ArmISA::ISAprotected
addStat(Stats::Info *info)Stats::Group
addStatGroup(const char *name, Group *block)Stats::Group
afterStartupArmISA::ISAprotected
assert32()ArmISA::ISAinlineprivate
assert64()ArmISA::ISAinlineprivate
clear()ArmISA::ISA
clear32(const ArmISAParams *p, const SCTLR &sctlr_rst)ArmISA::ISAprotected
clear64(const ArmISAParams *p)ArmISA::ISAprotected
currentSection()Serializablestatic
decoderFlavor() constArmISA::ISAinline
deschedule(Event &event)EventManagerinline
deschedule(Event *event)EventManagerinline
dmDrain()Drainableprivate
dmDrainResume()Drainableprivate
drain() overrideSimObjectinlinevirtual
Drainable()Drainableprotected
drainResume()Drainableinlineprotectedvirtual
drainState() constDrainableinline
dummyDeviceArmISA::ISAprotected
EventManager(EventManager &em)EventManagerinline
EventManager(EventManager *em)EventManagerinline
EventManager(EventQueue *eq)EventManagerinline
eventqEventManagerprotected
eventQueue() constEventManagerinline
find(const char *name)SimObjectstatic
flattenCCIndex(int reg) constArmISA::ISAinline
flattenFloatIndex(int reg) constArmISA::ISAinline
flattenIntIndex(int reg) constArmISA::ISAinline
flattenMiscIndex(int reg) constArmISA::ISAinline
flattenRegId(const RegId &regId) constArmISA::ISAinline
flattenVecElemIndex(int reg) constArmISA::ISAinline
flattenVecIndex(int reg) constArmISA::ISAinline
flattenVecPredIndex(int reg) constArmISA::ISAinline
getCurSveVecLenInBits() constArmISA::ISA
getCurSveVecLenInBitsAtReset() constArmISA::ISAinline
getGenericTimer()ArmISA::ISAprotected
getGICv3CPUInterface()ArmISA::ISAprotected
getMiscIndices(int misc_reg) constArmISA::ISAinline
getPort(const std::string &if_name, PortID idx=InvalidPortID)SimObjectvirtual
getProbeManager()SimObject
getSelfDebug() constArmISA::ISAinline
getSelfDebug(ThreadContext *tc)ArmISA::ISAinlinestatic
getStatGroups() constStats::Group
getStats() constStats::Group
gicv3CpuInterfaceArmISA::ISAprotected
Group()=deleteStats::Group
Group(const Group &)=deleteStats::Group
Group(Group *parent, const char *name=nullptr)Stats::Group
haveCryptoArmISA::ISAprotected
haveGICv3CpuIfc() constArmISA::ISAinline
haveLargeAsid64ArmISA::ISAprotected
haveLPAEArmISA::ISAprotected
haveLSEArmISA::ISAprotected
havePANArmISA::ISAprotected
haveSecEL2ArmISA::ISAprotected
haveSecurityArmISA::ISAprotected
haveSVEArmISA::ISAprotected
haveTMEArmISA::ISAprotected
haveVirtualizationArmISA::ISAprotected
highestELIs64ArmISA::ISAprotected
impdefAsNopArmISA::ISAprotected
init()SimObjectvirtual
initializeMiscRegMetadata()ArmISA::ISAprotected
initID32(const ArmISAParams *p)ArmISA::ISAprotected
initID64(const ArmISAParams *p)ArmISA::ISAprotected
InitReg(uint32_t reg)ArmISA::ISAinlineprotected
initState()SimObjectvirtual
intRegMapArmISA::ISAprotected
ISA(Params *p)ArmISA::ISA
loadState(CheckpointIn &cp)SimObjectvirtual
lookUpMiscRegArmISA::ISAprotectedstatic
memInvalidate()SimObjectinlinevirtual
memWriteback()SimObjectinlinevirtual
mergedParentStats::Groupprivate
mergedStatGroupsStats::Groupprivate
mergeStatGroup(Group *block)Stats::Groupprivate
miscRegsArmISA::ISAprotected
name() constSimObjectinlinevirtual
notifyFork()Drainableinlinevirtual
operator=(const Group &)=deleteStats::Group
params() constArmISA::ISA
Params typedefArmISA::ISA
pathSerializableprivatestatic
physAddrRangeArmISA::ISAprotected
pmuArmISA::ISAprotected
preDumpStats()Stats::Groupvirtual
probeManagerSimObjectprivate
readMiscReg(int misc_reg)ArmISA::ISA
readMiscRegNoEffect(int misc_reg) constArmISA::ISA
redirectRegVHE(ThreadContext *tc, int misc_reg)ArmISA::ISAinline
regProbeListeners()SimObjectvirtual
regProbePoints()SimObjectvirtual
regStats()Stats::Groupvirtual
reschedule(Event &event, Tick when, bool always=false)EventManagerinline
reschedule(Event *event, Tick when, bool always=false)EventManagerinline
resetStats()Stats::Groupvirtual
resolveStat(std::string name) constStats::Group
schedule(Event &event, Tick when)EventManagerinline
schedule(Event *event, Tick when)EventManagerinline
selfDebugArmISA::ISAprotected
Serializable()Serializable
serialize(CheckpointOut &cp) const overrideArmISA::ISAinlinevirtual
serializeAll(CheckpointOut &cp)SimObjectstatic
Serializable::serializeAll(const std::string &cpt_dir)Serializablestatic
serializeSection(CheckpointOut &cp, const char *name) constSerializable
serializeSection(CheckpointOut &cp, const std::string &name) constSerializableinline
setCurTick(Tick newVal)EventManagerinline
setMiscReg(int misc_reg, RegVal val)ArmISA::ISA
setMiscRegNoEffect(int misc_reg, RegVal val)ArmISA::ISA
setThreadContext(ThreadContext *_tc)BaseISAinlinevirtual
setupThreadContext()ArmISA::ISA
signalDrainDone() constDrainableinlineprotected
SimObject(const Params *_params)BaseISAprotected
SimObject::SimObject(const Params *_params)SimObject
SimObjectList typedefSimObjectprivate
simObjectListSimObjectprivatestatic
snsBankedIndex64(MiscRegIndex reg, bool ns) constArmISA::ISAinline
startup() overrideArmISA::ISAvirtual
statGroupsStats::Groupprivate
statsStats::Groupprivate
sveVLArmISA::ISAprotected
systemArmISA::ISAprotected
takeOverFrom(ThreadContext *new_tc, ThreadContext *old_tc) overrideArmISA::ISAvirtual
tcBaseISAprotected
timerArmISA::ISAprotected
unserialize(CheckpointIn &cp) overrideArmISA::ISAinlinevirtual
unserializeGlobals(CheckpointIn &cp)Serializablestatic
unserializeSection(CheckpointIn &cp, const char *name)Serializable
unserializeSection(CheckpointIn &cp, const std::string &name)Serializableinline
updateRegMap(CPSR cpsr)ArmISA::ISAinlineprotected
vecRegRenameMode() constArmISA::ISAinline
wakeupEventQueue(Tick when=(Tick) -1)EventManagerinline
zeroSveVecRegUpperPart(VecRegContainer &vc, unsigned eCount)ArmISA::ISAstatic
~Drainable()Drainableprotectedvirtual
~Group()Stats::Groupvirtual
~Serializable()Serializablevirtual
~SimObject()SimObjectvirtual
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