gem5  v20.1.0.0
BaseDynInst< Impl > Member List

This is the complete list of members for BaseDynInst< Impl >, including all inherited members.

_destRegIdxBaseDynInst< Impl >protected
_flatDestRegIdxBaseDynInst< Impl >protected
_prevDestRegIdxBaseDynInst< Impl >protected
_readySrcRegIdxBaseDynInst< Impl >protected
_srcRegIdxBaseDynInst< Impl >protected
amoMem(Addr addr, uint8_t *data, unsigned int size, Request::Flags flags, AtomicOpFunctorPtr amo_op)ExecContextinlinevirtual
armMonitor(Addr address) overrideBaseDynInst< Impl >inlinevirtual
AtCommit enum valueBaseDynInst< Impl >protected
BaseDynInst(const StaticInstPtr &staticInst, const StaticInstPtr &macroop, TheISA::PCState pc, TheISA::PCState predPC, InstSeqNum seq_num, ImplCPU *cpu)BaseDynInst< Impl >
BaseDynInst(const StaticInstPtr &staticInst, const StaticInstPtr &macroop)BaseDynInst< Impl >
BaseDynInstPtr typedefBaseDynInst< Impl >
BlockingInst enum valueBaseDynInst< Impl >protected
branchTarget() constBaseDynInst< Impl >inline
CanCommit enum valueBaseDynInst< Impl >protected
CanIssue enum valueBaseDynInst< Impl >protected
clearCanCommit()BaseDynInst< Impl >inline
clearCanIssue()BaseDynInst< Impl >inline
clearHtmTransactionalState()BaseDynInst< Impl >inline
clearInIQ()BaseDynInst< Impl >inline
clearInROB()BaseDynInst< Impl >inline
clearIssued()BaseDynInst< Impl >inline
clearSerializeAfter()BaseDynInst< Impl >inline
clearSerializeBefore()BaseDynInst< Impl >inline
Committed enum valueBaseDynInst< Impl >protected
Completed enum valueBaseDynInst< Impl >protected
contextId() constBaseDynInst< Impl >inline
countRefCountedmutableprivate
cpuBaseDynInst< Impl >
cpuId() constBaseDynInst< Impl >inline
decref() constRefCountedinline
demapDataPage(Addr vaddr, uint64_t asn)BaseDynInst< Impl >inline
demapInstPage(Addr vaddr, uint64_t asn)BaseDynInst< Impl >inline
demapPage(Addr vaddr, uint64_t asn) overrideBaseDynInst< Impl >inlinevirtual
destRegIdx(int i) constBaseDynInst< Impl >inline
doneTargCalc()BaseDynInst< Impl >inline
dump()BaseDynInst< Impl >
dump(std::string &outstring)BaseDynInst< Impl >
DynInstPtr typedefBaseDynInst< Impl >
eaSrcsReady() constBaseDynInst< Impl >
effAddrBaseDynInst< Impl >
EffAddrValid enum valueBaseDynInst< Impl >protected
effAddrValid() constBaseDynInst< Impl >inline
effAddrValid(bool b)BaseDynInst< Impl >inline
effSizeBaseDynInst< Impl >
Executed enum valueBaseDynInst< Impl >protected
faultBaseDynInst< Impl >
Flags enum nameBaseDynInst< Impl >protected
flattenDestReg(int idx, const RegId &flattened_dest)BaseDynInst< Impl >inline
flattenedDestRegIdx(int idx) constBaseDynInst< Impl >inline
getAddrMonitor() overrideBaseDynInst< Impl >inlinevirtual
getCpuPtr()BaseDynInst< Impl >inline
getFault() constBaseDynInst< Impl >inline
getFault()BaseDynInst< Impl >inline
getHtmTransactionalDepth() const overrideBaseDynInst< Impl >inlinevirtual
getHtmTransactionUid() const overrideBaseDynInst< Impl >inlinevirtual
getInstListIt()BaseDynInst< Impl >inline
getWritableVecPredRegOperand(const StaticInst *si, int idx)=0ExecContextpure virtual
getWritableVecRegOperand(const StaticInst *si, int idx)=0ExecContextpure virtual
hasRequest() constBaseDynInst< Impl >inline
HitExternalSnoop enum valueBaseDynInst< Impl >protected
hitExternalSnoop() constBaseDynInst< Impl >inline
hitExternalSnoop(bool f)BaseDynInst< Impl >inline
htmDepthBaseDynInst< Impl >private
HtmFromTransaction enum valueBaseDynInst< Impl >protected
htmUidBaseDynInst< Impl >private
ImplCPU typedefBaseDynInst< Impl >
ImplState typedefBaseDynInst< Impl >
incref() constRefCountedinline
inHtmTransactionalState() const overrideBaseDynInst< Impl >inlinevirtual
initiateHtmCmd(Request::Flags flags) overrideBaseDynInst< Impl >virtual
initiateMemAMO(Addr addr, unsigned size, Request::Flags flags, AtomicOpFunctorPtr amo_op) overrideBaseDynInst< Impl >
ExecContext::initiateMemAMO(Addr addr, unsigned int size, Request::Flags flags, AtomicOpFunctorPtr amo_op)ExecContextinlinevirtual
initiateMemRead(Addr addr, unsigned size, Request::Flags flags, const std::vector< bool > &byte_enable=std::vector< bool >()) overrideBaseDynInst< Impl >
ExecContext::initiateMemRead(Addr addr, unsigned int size, Request::Flags flags, const std::vector< bool > &byte_enable=std::vector< bool >())ExecContextinlinevirtual
initVars()BaseDynInst< Impl >private
instAddr() constBaseDynInst< Impl >inline
instFlagsBaseDynInst< Impl >private
instListItBaseDynInst< Impl >
instResultBaseDynInst< Impl >protected
IqEntry enum valueBaseDynInst< Impl >protected
isAtCommit()BaseDynInst< Impl >inline
isAtomic() constBaseDynInst< Impl >inline
isCall() constBaseDynInst< Impl >inline
isCommitted() constBaseDynInst< Impl >inline
isCompleted() constBaseDynInst< Impl >inline
isCondCtrl() constBaseDynInst< Impl >inline
isCondDelaySlot() constBaseDynInst< Impl >inline
isControl() constBaseDynInst< Impl >inline
isDataPrefetch() constBaseDynInst< Impl >inline
isDelayedCommit() constBaseDynInst< Impl >inline
isDirectCtrl() constBaseDynInst< Impl >inline
isExecuted() constBaseDynInst< Impl >inline
isFirstMicroop() constBaseDynInst< Impl >inline
isFloating() constBaseDynInst< Impl >inline
isHtmCancel() constBaseDynInst< Impl >inline
isHtmCmd() constBaseDynInst< Impl >inline
isHtmStart() constBaseDynInst< Impl >inline
isHtmStop() constBaseDynInst< Impl >inline
isIndirectCtrl() constBaseDynInst< Impl >inline
isInIQ() constBaseDynInst< Impl >inline
isInLSQ() constBaseDynInst< Impl >inline
isInROB() constBaseDynInst< Impl >inline
isInstPrefetch() constBaseDynInst< Impl >inline
isInteger() constBaseDynInst< Impl >inline
isIprAccess() constBaseDynInst< Impl >inline
isIssued() constBaseDynInst< Impl >inline
isLastMicroop() constBaseDynInst< Impl >inline
isLoad() constBaseDynInst< Impl >inline
isMacroop() constBaseDynInst< Impl >inline
isMemBarrier() constBaseDynInst< Impl >inline
isMemRef() constBaseDynInst< Impl >inline
isMicroBranch() constBaseDynInst< Impl >inline
isMicroop() constBaseDynInst< Impl >inline
isNonSpeculative() constBaseDynInst< Impl >inline
isNop() constBaseDynInst< Impl >inline
isPinnedRegsRenamed() constBaseDynInst< Impl >inline
isPinnedRegsSquashDone() constBaseDynInst< Impl >inline
isPinnedRegsWritten() constBaseDynInst< Impl >inline
isQuiesce() constBaseDynInst< Impl >inline
isReadySrcRegIdx(int idx) constBaseDynInst< Impl >inline
isResultReady() constBaseDynInst< Impl >inline
isReturn() constBaseDynInst< Impl >inline
isSerializeAfter() constBaseDynInst< Impl >inline
isSerializeBefore() constBaseDynInst< Impl >inline
isSerializeHandled()BaseDynInst< Impl >inline
isSerializing() constBaseDynInst< Impl >inline
isSquashAfter() constBaseDynInst< Impl >inline
isSquashed() constBaseDynInst< Impl >inline
isSquashedInIQ() constBaseDynInst< Impl >inline
isSquashedInLSQ() constBaseDynInst< Impl >inline
isSquashedInROB() constBaseDynInst< Impl >inline
isStore() constBaseDynInst< Impl >inline
isStoreConditional() constBaseDynInst< Impl >inline
IsStrictlyOrdered enum valueBaseDynInst< Impl >protected
Issued enum valueBaseDynInst< Impl >protected
isSyscall() constBaseDynInst< Impl >inline
isTempSerializeAfter()BaseDynInst< Impl >inline
isTempSerializeBefore()BaseDynInst< Impl >inline
isThreadSync() constBaseDynInst< Impl >inline
isTranslationDelayed() constBaseDynInst< Impl >inline
isUncondCtrl() constBaseDynInst< Impl >inline
isUnverifiable() constBaseDynInst< Impl >inline
isVector() constBaseDynInst< Impl >inline
isWriteBarrier() constBaseDynInst< Impl >inline
ListIt typedefBaseDynInst< Impl >
lqIdxBaseDynInst< Impl >
lqItBaseDynInst< Impl >
LQIterator typedefBaseDynInst< Impl >
LsqEntry enum valueBaseDynInst< Impl >protected
LSQRequestPtr typedefBaseDynInst< Impl >
macroopBaseDynInst< Impl >
markSrcRegReady()BaseDynInst< Impl >
markSrcRegReady(RegIndex src_idx)BaseDynInst< Impl >
MaxFlags enum valueBaseDynInst< Impl >protected
MaxInstDestRegs enum valueBaseDynInst< Impl >
MaxInstSrcRegs enum valueBaseDynInst< Impl >
MemAccPredicate enum valueBaseDynInst< Impl >protected
memDataBaseDynInst< Impl >
MemOpDone enum valueBaseDynInst< Impl >protected
memOpDone() constBaseDynInst< Impl >inline
memOpDone(bool f)BaseDynInst< Impl >inline
memReqFlagsBaseDynInst< Impl >
microPC() constBaseDynInst< Impl >inline
mispredicted()BaseDynInst< Impl >inline
mwait(PacketPtr pkt) overrideBaseDynInst< Impl >inlinevirtual
mwaitAtomic(ThreadContext *tc) overrideBaseDynInst< Impl >inlinevirtual
newHtmTransactionUid() const overrideBaseDynInst< Impl >inlinevirtual
nextInstAddr() constBaseDynInst< Impl >inline
NotAnInst enum valueBaseDynInst< Impl >protected
notAnInst() constBaseDynInst< Impl >inline
numCCDestRegs() constBaseDynInst< Impl >inline
numDestRegs() constBaseDynInst< Impl >inline
numFPDestRegs() constBaseDynInst< Impl >inline
numIntDestRegs() constBaseDynInst< Impl >inline
numSrcRegs() constBaseDynInst< Impl >inline
NumStatus enum valueBaseDynInst< Impl >protected
numVecDestRegs() constBaseDynInst< Impl >inline
numVecElemDestRegs() constBaseDynInst< Impl >inline
numVecPredDestRegs() constBaseDynInst< Impl >inline
opClass() constBaseDynInst< Impl >inline
operator=(const RefCounted &)RefCountedprivate
pcBaseDynInst< Impl >protected
PCState typedefExecContext
pcState() const overrideBaseDynInst< Impl >inlinevirtual
pcState(const TheISA::PCState &val) overrideBaseDynInst< Impl >inlinevirtual
physEffAddrBaseDynInst< Impl >
PinnedRegsRenamed enum valueBaseDynInst< Impl >protected
PinnedRegsSquashDone enum valueBaseDynInst< Impl >protected
PinnedRegsWritten enum valueBaseDynInst< Impl >protected
popResult(InstResult dflt=InstResult())BaseDynInst< Impl >inline
PossibleLoadViolation enum valueBaseDynInst< Impl >protected
possibleLoadViolation() constBaseDynInst< Impl >inline
possibleLoadViolation(bool f)BaseDynInst< Impl >inline
Predicate enum valueBaseDynInst< Impl >protected
predInstAddr()BaseDynInst< Impl >inline
predMicroPC()BaseDynInst< Impl >inline
predNextInstAddr()BaseDynInst< Impl >inline
predPCBaseDynInst< Impl >
PredTaken enum valueBaseDynInst< Impl >protected
prevDestRegIdx(int idx) constBaseDynInst< Impl >inline
readCCRegOperand(const StaticInst *si, int idx)=0ExecContextpure virtual
readFloatRegOperandBits(const StaticInst *si, int idx)=0ExecContextpure virtual
readIntRegOperand(const StaticInst *si, int idx)=0ExecContextpure virtual
readMem(Addr addr, uint8_t *data, unsigned int size, Request::Flags flags, const std::vector< bool > &byte_enable=std::vector< bool >())ExecContextinlinevirtual
readMemAccPredicate() const overrideBaseDynInst< Impl >inlinevirtual
readMiscReg(int misc_reg)=0ExecContextpure virtual
readMiscRegOperand(const StaticInst *si, int idx)=0ExecContextpure virtual
readPredicate() const overrideBaseDynInst< Impl >inlinevirtual
readPredTaken()BaseDynInst< Impl >inline
readPredTarg()BaseDynInst< Impl >inline
readStCondFailures() const overrideBaseDynInst< Impl >inlinevirtual
readVec16BitLaneOperand(const StaticInst *si, int idx) const =0ExecContextpure virtual
readVec32BitLaneOperand(const StaticInst *si, int idx) const =0ExecContextpure virtual
readVec64BitLaneOperand(const StaticInst *si, int idx) const =0ExecContextpure virtual
readVec8BitLaneOperand(const StaticInst *si, int idx) const =0ExecContextpure virtual
readVecElemOperand(const StaticInst *si, int idx) const =0ExecContextpure virtual
readVecPredRegOperand(const StaticInst *si, int idx) const =0ExecContextpure virtual
readVecRegOperand(const StaticInst *si, int idx) const =0ExecContextpure virtual
readyRegsBaseDynInst< Impl >
readyToCommit() constBaseDynInst< Impl >inline
readyToIssue() constBaseDynInst< Impl >inline
RecordResult enum valueBaseDynInst< Impl >protected
recordResult(bool f)BaseDynInst< Impl >inline
RecoverInst enum valueBaseDynInst< Impl >protected
RefCounted(const RefCounted &)RefCountedprivate
RefCounted()RefCountedinline
removeInLSQ()BaseDynInst< Impl >inline
renamedDestRegIdx(int idx) constBaseDynInst< Impl >inline
renameDestReg(int idx, PhysRegIdPtr renamed_dest, PhysRegIdPtr previous_rename)BaseDynInst< Impl >inline
renamedSrcRegIdx(int idx) constBaseDynInst< Impl >inline
renameSrcReg(int idx, PhysRegIdPtr renamed_src)BaseDynInst< Impl >inline
ReqMade enum valueBaseDynInst< Impl >protected
reqToVerifyBaseDynInst< Impl >
requestorId() constBaseDynInst< Impl >inline
ResultReady enum valueBaseDynInst< Impl >protected
resultSize()BaseDynInst< Impl >inline
RobEntry enum valueBaseDynInst< Impl >protected
savedReqBaseDynInst< Impl >
seqNumBaseDynInst< Impl >
SerializeAfter enum valueBaseDynInst< Impl >protected
SerializeBefore enum valueBaseDynInst< Impl >protected
SerializeHandled enum valueBaseDynInst< Impl >protected
setAtCommit()BaseDynInst< Impl >inline
setCanCommit()BaseDynInst< Impl >inline
setCanIssue()BaseDynInst< Impl >inline
setCCRegOperand(const StaticInst *si, int idx, RegVal val) overrideBaseDynInst< Impl >inlinevirtual
setCommitted()BaseDynInst< Impl >inline
setCompleted()BaseDynInst< Impl >inline
setExecuted()BaseDynInst< Impl >inline
setFloatRegOperandBits(const StaticInst *si, int idx, RegVal val) overrideBaseDynInst< Impl >inlinevirtual
setHtmTransactionalState(uint64_t htm_uid, uint64_t htm_depth)BaseDynInst< Impl >inline
setInIQ()BaseDynInst< Impl >inline
setInLSQ()BaseDynInst< Impl >inline
setInROB()BaseDynInst< Impl >inline
setInstListIt(ListIt _instListIt)BaseDynInst< Impl >inline
setIntRegOperand(const StaticInst *si, int idx, RegVal val) overrideBaseDynInst< Impl >inlinevirtual
setIssued()BaseDynInst< Impl >inline
setMemAccPredicate(bool val) overrideBaseDynInst< Impl >inlinevirtual
setMiscReg(int misc_reg, RegVal val)=0ExecContextpure virtual
setMiscRegOperand(const StaticInst *si, int idx, RegVal val)=0ExecContextpure virtual
setNotAnInst()BaseDynInst< Impl >inline
setPinnedRegsRenamed()BaseDynInst< Impl >inline
setPinnedRegsSquashDone()BaseDynInst< Impl >inline
setPinnedRegsWritten()BaseDynInst< Impl >inline
setPredicate(bool val) overrideBaseDynInst< Impl >inlinevirtual
setPredTaken(bool predicted_taken)BaseDynInst< Impl >inline
setPredTarg(const TheISA::PCState &_predPC)BaseDynInst< Impl >inline
setRequest()BaseDynInst< Impl >inline
setResultReady()BaseDynInst< Impl >inline
setScalarResult(T &&t)BaseDynInst< Impl >inline
setSerializeAfter()BaseDynInst< Impl >inline
setSerializeBefore()BaseDynInst< Impl >inline
setSerializeHandled()BaseDynInst< Impl >inline
setSquashed()BaseDynInst< Impl >
setSquashedInIQ()BaseDynInst< Impl >inline
setSquashedInLSQ()BaseDynInst< Impl >inline
setSquashedInROB()BaseDynInst< Impl >inline
setStCondFailures(unsigned int sc_failures) overrideBaseDynInst< Impl >inlinevirtual
setThreadState(ImplState *state)BaseDynInst< Impl >inline
setTid(ThreadID tid)BaseDynInst< Impl >inline
setVecElemOperand(const StaticInst *si, int idx, const VecElem val) overrideBaseDynInst< Impl >inlinevirtual
setVecElemResult(T &&t)BaseDynInst< Impl >inline
setVecLaneOperand(const StaticInst *si, int idx, const LaneData< LaneSize::Byte > &val)=0ExecContextpure virtual
setVecLaneOperand(const StaticInst *si, int idx, const LaneData< LaneSize::TwoByte > &val)=0ExecContextpure virtual
setVecLaneOperand(const StaticInst *si, int idx, const LaneData< LaneSize::FourByte > &val)=0ExecContextpure virtual
setVecLaneOperand(const StaticInst *si, int idx, const LaneData< LaneSize::EightByte > &val)=0ExecContextpure virtual
setVecPredRegOperand(const StaticInst *si, int idx, const VecPredRegContainer &val) overrideBaseDynInst< Impl >inlinevirtual
setVecPredResult(T &&t)BaseDynInst< Impl >inline
setVecRegOperand(const StaticInst *si, int idx, const VecRegContainer &val) overrideBaseDynInst< Impl >inlinevirtual
setVecResult(T &&t)BaseDynInst< Impl >inline
socketId() constBaseDynInst< Impl >inline
sqIdxBaseDynInst< Impl >
sqItBaseDynInst< Impl >
SQIterator typedefBaseDynInst< Impl >
Squashed enum valueBaseDynInst< Impl >protected
SquashedInIQ enum valueBaseDynInst< Impl >protected
SquashedInLSQ enum valueBaseDynInst< Impl >protected
SquashedInROB enum valueBaseDynInst< Impl >protected
srcRegIdx(int i) constBaseDynInst< Impl >inline
staticInstBaseDynInst< Impl >
statusBaseDynInst< Impl >private
Status enum nameBaseDynInst< Impl >protected
strictlyOrdered() constBaseDynInst< Impl >inline
strictlyOrdered(bool so)BaseDynInst< Impl >inline
syscall()=0ExecContextpure virtual
tcBase() const overrideBaseDynInst< Impl >inlinevirtual
threadBaseDynInst< Impl >
threadNumberBaseDynInst< Impl >
ThreadsyncWait enum valueBaseDynInst< Impl >protected
traceDataBaseDynInst< Impl >
TranslationCompleted enum valueBaseDynInst< Impl >protected
translationCompleted() constBaseDynInst< Impl >inline
translationCompleted(bool f)BaseDynInst< Impl >inline
TranslationStarted enum valueBaseDynInst< Impl >protected
translationStarted() constBaseDynInst< Impl >inline
translationStarted(bool f)BaseDynInst< Impl >inline
VecElem typedefExecContext
VecPredRegContainer typedefExecContext
VecRegContainer typedefBaseDynInst< Impl >
writeMem(uint8_t *data, unsigned size, Addr addr, Request::Flags flags, uint64_t *res, const std::vector< bool > &byte_enable=std::vector< bool >()) overrideBaseDynInst< Impl >
ExecContext::writeMem(uint8_t *data, unsigned int size, Addr addr, Request::Flags flags, uint64_t *res, const std::vector< bool > &byte_enable=std::vector< bool >())=0ExecContextpure virtual
~BaseDynInst()BaseDynInst< Impl >
~RefCounted()RefCountedinlinevirtual
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