The ExecContext is an abstract base class the provides the interface used by the ISA to manipulate the state of the CPU model. More...

#include <exec_context.hh>

Inheritance diagram for ExecContext:

Public Types
typedef TheISA::PCState	PCState

using	VecRegContainer = TheISA::VecRegContainer

using	VecElem = TheISA::VecElem

using	VecPredRegContainer = TheISA::VecPredRegContainer

Public Member Functions
virtual ThreadContext *	tcBase () const =0
	Returns a pointer to the ThreadContext. More...

Integer Register Interfaces
virtual RegVal	readIntRegOperand (const StaticInst *si, int idx)=0
	Reads an integer register. More...

virtual void	setIntRegOperand (const StaticInst *si, int idx, RegVal val)=0
	Sets an integer register to a value. More...

Floating Point Register Interfaces
virtual RegVal	readFloatRegOperandBits (const StaticInst *si, int idx)=0
	Reads a floating point register in its binary format, instead of by value. More...

virtual void	setFloatRegOperandBits (const StaticInst *si, int idx, RegVal val)=0
	Sets the bits of a floating point register of single width to a binary value. More...


virtual const VecRegContainer &	readVecRegOperand (const StaticInst *si, int idx) const =0
	Vector Register Interfaces. More...

virtual VecRegContainer &	getWritableVecRegOperand (const StaticInst *si, int idx)=0
	Gets destination vector register operand for modification. More...

virtual void	setVecRegOperand (const StaticInst *si, int idx, const VecRegContainer &val)=0
	Sets a destination vector register operand to a value. More...


virtual ConstVecLane8	readVec8BitLaneOperand (const StaticInst *si, int idx) const =0
	Vector Register Lane Interfaces. More...

virtual ConstVecLane16	readVec16BitLaneOperand (const StaticInst *si, int idx) const =0
	Reads source vector 16bit operand. More...

virtual ConstVecLane32	readVec32BitLaneOperand (const StaticInst *si, int idx) const =0
	Reads source vector 32bit operand. More...

virtual ConstVecLane64	readVec64BitLaneOperand (const StaticInst *si, int idx) const =0
	Reads source vector 64bit operand. More...

virtual void	setVecLaneOperand (const StaticInst *si, int idx, const LaneData< LaneSize::Byte > &val)=0
	Write a lane of the destination vector operand. More...

virtual void	setVecLaneOperand (const StaticInst *si, int idx, const LaneData< LaneSize::TwoByte > &val)=0

virtual void	setVecLaneOperand (const StaticInst *si, int idx, const LaneData< LaneSize::FourByte > &val)=0

virtual void	setVecLaneOperand (const StaticInst *si, int idx, const LaneData< LaneSize::EightByte > &val)=0


virtual VecElem	readVecElemOperand (const StaticInst *si, int idx) const =0
	Vector Elem Interfaces. More...

virtual void	setVecElemOperand (const StaticInst *si, int idx, const VecElem val)=0
	Sets a vector register to a value. More...


virtual const VecPredRegContainer &	readVecPredRegOperand (const StaticInst *si, int idx) const =0
	Predicate registers interface. More...

virtual VecPredRegContainer &	getWritableVecPredRegOperand (const StaticInst *si, int idx)=0
	Gets destination predicate register operand for modification. More...

virtual void	setVecPredRegOperand (const StaticInst *si, int idx, const VecPredRegContainer &val)=0
	Sets a destination predicate register operand to a value. More...

Condition Code Registers
virtual RegVal	readCCRegOperand (const StaticInst *si, int idx)=0

virtual void	setCCRegOperand (const StaticInst *si, int idx, RegVal val)=0

Misc Register Interfaces
virtual RegVal	readMiscRegOperand (const StaticInst *si, int idx)=0

virtual void	setMiscRegOperand (const StaticInst *si, int idx, RegVal val)=0

virtual RegVal	readMiscReg (int misc_reg)=0
	Reads a miscellaneous register, handling any architectural side effects due to reading that register. More...

virtual void	setMiscReg (int misc_reg, RegVal val)=0
	Sets a miscellaneous register, handling any architectural side effects due to writing that register. More...

PC Control
virtual PCState	pcState () const =0

virtual void	pcState (const PCState &val)=0

Memory Interface
virtual Fault	readMem (Addr addr, uint8_t *data, unsigned int size, Request::Flags flags, const std::vector< bool > &byte_enable=std::vector< bool >())
	Perform an atomic memory read operation. More...

virtual Fault	initiateMemRead (Addr addr, unsigned int size, Request::Flags flags, const std::vector< bool > &byte_enable=std::vector< bool >())
	Initiate a timing memory read operation. More...

virtual Fault	initiateHtmCmd (Request::Flags flags)=0
	Initiate an HTM command, e.g. More...

virtual Fault	writeMem (uint8_t data, unsigned int size, Addr addr, Request::Flags flags, uint64_t res, const std::vector< bool > &byte_enable=std::vector< bool >())=0
	For atomic-mode contexts, perform an atomic memory write operation. More...

virtual Fault	amoMem (Addr addr, uint8_t *data, unsigned int size, Request::Flags flags, AtomicOpFunctorPtr amo_op)
	For atomic-mode contexts, perform an atomic AMO (a.k.a., Atomic Read-Modify-Write Memory Operation) More...

virtual Fault	initiateMemAMO (Addr addr, unsigned int size, Request::Flags flags, AtomicOpFunctorPtr amo_op)
	For timing-mode contexts, initiate an atomic AMO (atomic read-modify-write memory operation) More...

virtual void	setStCondFailures (unsigned int sc_failures)=0
	Sets the number of consecutive store conditional failures. More...

virtual unsigned int	readStCondFailures () const =0
	Returns the number of consecutive store conditional failures. More...

SysCall Emulation Interfaces
virtual void	syscall ()=0
	Executes a syscall. More...

ARM-Specific Interfaces
virtual bool	readPredicate () const =0

virtual void	setPredicate (bool val)=0

virtual bool	readMemAccPredicate () const =0

virtual void	setMemAccPredicate (bool val)=0

virtual uint64_t	newHtmTransactionUid () const =0

virtual uint64_t	getHtmTransactionUid () const =0

virtual bool	inHtmTransactionalState () const =0

virtual uint64_t	getHtmTransactionalDepth () const =0

X86-Specific Interfaces
virtual void	demapPage (Addr vaddr, uint64_t asn)=0
	Invalidate a page in the DTLB and ITLB. More...

virtual void	armMonitor (Addr address)=0

virtual bool	mwait (PacketPtr pkt)=0

virtual void	mwaitAtomic (ThreadContext *tc)=0

virtual AddressMonitor *	getAddrMonitor ()=0

Detailed Description

The ExecContext is an abstract base class the provides the interface used by the ISA to manipulate the state of the CPU model.

Register accessor methods in this class typically provide the index of the instruction's operand (e.g., 0 or 1), not the architectural register index, to simplify the implementation of register renaming. The architectural register index can be found by indexing into the instruction's own operand index table.

Note: The methods in this class typically take a raw pointer to the StaticInst is provided instead of a ref-counted StaticInstPtr to reduce overhead as an argument. This is fine as long as the implementation doesn't copy the pointer into any long-term storage (which is pretty hard to imagine they would have reason to do).

Definition at line 70 of file exec_context.hh.

Member Typedef Documentation

◆ PCState

typedef TheISA::PCState ExecContext::PCState

Definition at line 72 of file exec_context.hh.

◆ VecElem

using ExecContext::VecElem = TheISA::VecElem

Definition at line 75 of file exec_context.hh.

◆ VecPredRegContainer

using ExecContext::VecPredRegContainer = TheISA::VecPredRegContainer

Definition at line 76 of file exec_context.hh.

◆ VecRegContainer

using ExecContext::VecRegContainer = TheISA::VecRegContainer

Definition at line 74 of file exec_context.hh.

Member Function Documentation

◆ amoMem()

virtual Fault ExecContext::amoMem	(	Addr	addr,
		uint8_t *	data,
		unsigned int	size,
		Request::Flags	flags,
		AtomicOpFunctorPtr	amo_op
	)

inlinevirtual

For atomic-mode contexts, perform an atomic AMO (a.k.a., Atomic Read-Modify-Write Memory Operation)

Reimplemented in SimpleExecContext.

Definition at line 273 of file exec_context.hh.

References panic.

◆ armMonitor()

virtual void ExecContext::armMonitor ( Addr address )

pure virtual

Implemented in BaseDynInst< Impl >, SimpleExecContext, CheckerCPU, and Minor::ExecContext.

◆ demapPage()

virtual void ExecContext::demapPage	(	Addr	vaddr,
		uint64_t	asn
	)

pure virtual

Invalidate a page in the DTLB and ITLB.

Implemented in SimpleExecContext, CheckerCPU, Minor::ExecContext, and BaseDynInst< Impl >.

◆ getAddrMonitor()

virtual AddressMonitor* ExecContext::getAddrMonitor ( )

pure virtual

Implemented in BaseDynInst< Impl >, SimpleExecContext, CheckerCPU, and Minor::ExecContext.

◆ getHtmTransactionalDepth()

virtual uint64_t ExecContext::getHtmTransactionalDepth ( ) const

pure virtual

Implemented in BaseDynInst< Impl >, SimpleExecContext, CheckerCPU, and Minor::ExecContext.

◆ getHtmTransactionUid()

virtual uint64_t ExecContext::getHtmTransactionUid ( ) const

pure virtual

Implemented in BaseDynInst< Impl >, SimpleExecContext, CheckerCPU, and Minor::ExecContext.

◆ getWritableVecPredRegOperand()

virtual VecPredRegContainer& ExecContext::getWritableVecPredRegOperand	(	const StaticInst *	si,
		int	idx
	)

pure virtual

Gets destination predicate register operand for modification.

Implemented in BaseO3DynInst< Impl >, SimpleExecContext, CheckerCPU, and Minor::ExecContext.

◆ getWritableVecRegOperand()

virtual VecRegContainer& ExecContext::getWritableVecRegOperand	(	const StaticInst *	si,
		int	idx
	)

pure virtual

Gets destination vector register operand for modification.

Implemented in BaseO3DynInst< Impl >, SimpleExecContext, CheckerCPU, and Minor::ExecContext.

◆ inHtmTransactionalState()

virtual bool ExecContext::inHtmTransactionalState ( ) const

pure virtual

Implemented in BaseDynInst< Impl >, SimpleExecContext, CheckerCPU, and Minor::ExecContext.

◆ initiateHtmCmd()

virtual Fault ExecContext::initiateHtmCmd ( Request::Flags flags )

pure virtual

Initiate an HTM command, e.g.

tell Ruby we're starting/stopping a transaction

Implemented in SimpleExecContext, CheckerCPU, BaseDynInst< Impl >, and Minor::ExecContext.

◆ initiateMemAMO()

virtual Fault ExecContext::initiateMemAMO	(	Addr	addr,
		unsigned int	size,
		Request::Flags	flags,
		AtomicOpFunctorPtr	amo_op
	)

inlinevirtual

For timing-mode contexts, initiate an atomic AMO (atomic read-modify-write memory operation)

Reimplemented in SimpleExecContext, and Minor::ExecContext.

Definition at line 284 of file exec_context.hh.

References panic.

◆ initiateMemRead()

virtual Fault ExecContext::initiateMemRead	(	Addr	addr,
		unsigned int	size,
		Request::Flags	flags,
		const std::vector< bool > &	byte_enable = `std::vector<bool>()`
	)

inlinevirtual

Initiate a timing memory read operation.

Must be overridden for exec contexts that support timing memory mode. Not pure virtual since exec contexts that only support atomic memory mode need not override (though in that case this function should never be called).

Reimplemented in SimpleExecContext, and Minor::ExecContext.

Definition at line 248 of file exec_context.hh.

References panic.

Referenced by X86ISA::initiateMemRead().

◆ mwait()

virtual bool ExecContext::mwait ( PacketPtr pkt )

pure virtual

Implemented in BaseDynInst< Impl >, SimpleExecContext, CheckerCPU, and Minor::ExecContext.

◆ mwaitAtomic()

virtual void ExecContext::mwaitAtomic ( ThreadContext * tc )

pure virtual

Implemented in BaseDynInst< Impl >, SimpleExecContext, CheckerCPU, and Minor::ExecContext.

◆ newHtmTransactionUid()

virtual uint64_t ExecContext::newHtmTransactionUid ( ) const

pure virtual

Implemented in BaseDynInst< Impl >, SimpleExecContext, CheckerCPU, and Minor::ExecContext.

◆ pcState() [1/2]

virtual PCState ExecContext::pcState ( ) const

pure virtual

Implemented in BaseDynInst< Impl >, CheckerCPU, SimpleExecContext, and Minor::ExecContext.

Referenced by DecoderFaultInst::execute(), DebugStep::execute(), ArmISA::ArmStaticInst::readPC(), ArmISA::ArmStaticInst::setAIWNextPC(), ArmISA::ArmStaticInst::setIWNextPC(), and ArmISA::ArmStaticInst::setNextPC().

◆ pcState() [2/2]

virtual void ExecContext::pcState ( const PCState & val )

pure virtual

Implemented in BaseDynInst< Impl >, CheckerCPU, Minor::ExecContext, and SimpleExecContext.

◆ readCCRegOperand()

virtual RegVal ExecContext::readCCRegOperand	(	const StaticInst *	si,
		int	idx
	)

pure virtual

Implemented in Minor::ExecContext, BaseO3DynInst< Impl >, SimpleExecContext, and CheckerCPU.

◆ readFloatRegOperandBits()

virtual RegVal ExecContext::readFloatRegOperandBits	(	const StaticInst *	si,
		int	idx
	)

pure virtual

Reads a floating point register in its binary format, instead of by value.

Implemented in BaseO3DynInst< Impl >, CheckerCPU, SimpleExecContext, and Minor::ExecContext.

◆ readIntRegOperand()

virtual RegVal ExecContext::readIntRegOperand	(	const StaticInst *	si,
		int	idx
	)

pure virtual

Reads an integer register.

Implemented in BaseO3DynInst< Impl >, CheckerCPU, SimpleExecContext, and Minor::ExecContext.

◆ readMem()

virtual Fault ExecContext::readMem	(	Addr	addr,
		uint8_t *	data,
		unsigned int	size,
		Request::Flags	flags,
		const std::vector< bool > &	byte_enable = `std::vector<bool>()`
	)

inlinevirtual

Perform an atomic memory read operation.

Must be overridden for exec contexts that support atomic memory mode. Not pure virtual since exec contexts that only support timing memory mode need not override (though in that case this function should never be called).

Reimplemented in SimpleExecContext.

Definition at line 234 of file exec_context.hh.

References panic.

Referenced by X86ISA::readMemAtomic(), and X86ISA::readPackedMemAtomic().

◆ readMemAccPredicate()

virtual bool ExecContext::readMemAccPredicate ( ) const

pure virtual

Implemented in BaseDynInst< Impl >, SimpleExecContext, CheckerCPU, and Minor::ExecContext.

◆ readMiscReg()

virtual RegVal ExecContext::readMiscReg ( int misc_reg )

pure virtual

Reads a miscellaneous register, handling any architectural side effects due to reading that register.

Implemented in CheckerCPU, SimpleExecContext, Minor::ExecContext, and BaseO3DynInst< Impl >.

◆ readMiscRegOperand()

virtual RegVal ExecContext::readMiscRegOperand	(	const StaticInst *	si,
		int	idx
	)

pure virtual

Implemented in CheckerCPU, Minor::ExecContext, SimpleExecContext, and BaseO3DynInst< Impl >.

◆ readPredicate()

virtual bool ExecContext::readPredicate ( ) const

pure virtual

Implemented in BaseDynInst< Impl >, SimpleExecContext, CheckerCPU, and Minor::ExecContext.

◆ readStCondFailures()

virtual unsigned int ExecContext::readStCondFailures ( ) const

pure virtual

Returns the number of consecutive store conditional failures.

Implemented in BaseDynInst< Impl >, CheckerCPU, SimpleExecContext, and Minor::ExecContext.

◆ readVec16BitLaneOperand()

virtual ConstVecLane16 ExecContext::readVec16BitLaneOperand	(	const StaticInst *	si,
		int	idx
	)		const

pure virtual

Reads source vector 16bit operand.

Implemented in BaseO3DynInst< Impl >, SimpleExecContext, Minor::ExecContext, and CheckerCPU.

◆ readVec32BitLaneOperand()

virtual ConstVecLane32 ExecContext::readVec32BitLaneOperand	(	const StaticInst *	si,
		int	idx
	)		const

pure virtual

Reads source vector 32bit operand.

Implemented in BaseO3DynInst< Impl >, SimpleExecContext, Minor::ExecContext, and CheckerCPU.

◆ readVec64BitLaneOperand()

virtual ConstVecLane64 ExecContext::readVec64BitLaneOperand	(	const StaticInst *	si,
		int	idx
	)		const

pure virtual

Reads source vector 64bit operand.

Implemented in BaseO3DynInst< Impl >, SimpleExecContext, Minor::ExecContext, and CheckerCPU.

◆ readVec8BitLaneOperand()

virtual ConstVecLane8 ExecContext::readVec8BitLaneOperand	(	const StaticInst *	si,
		int	idx
	)		const

pure virtual

Vector Register Lane Interfaces.

Reads source vector 8bit operand.

Implemented in BaseO3DynInst< Impl >, SimpleExecContext, Minor::ExecContext, and CheckerCPU.

◆ readVecElemOperand()

virtual VecElem ExecContext::readVecElemOperand	(	const StaticInst *	si,
		int	idx
	)		const

pure virtual

Vector Elem Interfaces.

Reads an element of a vector register.

Implemented in BaseO3DynInst< Impl >, SimpleExecContext, CheckerCPU, and Minor::ExecContext.

◆ readVecPredRegOperand()

virtual const VecPredRegContainer& ExecContext::readVecPredRegOperand	(	const StaticInst *	si,
		int	idx
	)		const

pure virtual

Predicate registers interface.

Reads source predicate register operand.

Implemented in BaseO3DynInst< Impl >, SimpleExecContext, CheckerCPU, and Minor::ExecContext.

◆ readVecRegOperand()

virtual const VecRegContainer& ExecContext::readVecRegOperand	(	const StaticInst *	si,
		int	idx
	)		const

pure virtual

Vector Register Interfaces.

Reads source vector register operand.

Implemented in BaseO3DynInst< Impl >, SimpleExecContext, CheckerCPU, and Minor::ExecContext.

◆ setCCRegOperand()

virtual void ExecContext::setCCRegOperand	(	const StaticInst *	si,
		int	idx,
		RegVal	val
	)

pure virtual

Implemented in BaseDynInst< Impl >, Minor::ExecContext, BaseO3DynInst< Impl >, CheckerCPU, and SimpleExecContext.

◆ setFloatRegOperandBits()

virtual void ExecContext::setFloatRegOperandBits	(	const StaticInst *	si,
		int	idx,
		RegVal	val
	)

pure virtual

Sets the bits of a floating point register of single width to a binary value.

Implemented in BaseDynInst< Impl >, BaseO3DynInst< Impl >, CheckerCPU, Minor::ExecContext, and SimpleExecContext.

◆ setIntRegOperand()

virtual void ExecContext::setIntRegOperand	(	const StaticInst *	si,
		int	idx,
		RegVal	val
	)

pure virtual

Sets an integer register to a value.

Implemented in BaseDynInst< Impl >, BaseO3DynInst< Impl >, CheckerCPU, Minor::ExecContext, and SimpleExecContext.

◆ setMemAccPredicate()

virtual void ExecContext::setMemAccPredicate ( bool val )

pure virtual

Implemented in BaseDynInst< Impl >, SimpleExecContext, CheckerCPU, and Minor::ExecContext.

◆ setMiscReg()

virtual void ExecContext::setMiscReg	(	int	misc_reg,
		RegVal	val
	)

pure virtual

Sets a miscellaneous register, handling any architectural side effects due to writing that register.

Implemented in CheckerCPU, SimpleExecContext, Minor::ExecContext, and BaseO3DynInst< Impl >.

◆ setMiscRegOperand()

virtual void ExecContext::setMiscRegOperand	(	const StaticInst *	si,
		int	idx,
		RegVal	val
	)

pure virtual

Implemented in CheckerCPU, Minor::ExecContext, SimpleExecContext, and BaseO3DynInst< Impl >.

◆ setPredicate()

virtual void ExecContext::setPredicate ( bool val )

pure virtual

Implemented in BaseDynInst< Impl >, SimpleExecContext, CheckerCPU, and Minor::ExecContext.

◆ setStCondFailures()

virtual void ExecContext::setStCondFailures ( unsigned int sc_failures )

pure virtual

Sets the number of consecutive store conditional failures.

Implemented in Minor::ExecContext, BaseDynInst< Impl >, CheckerCPU, and SimpleExecContext.

◆ setVecElemOperand()

virtual void ExecContext::setVecElemOperand	(	const StaticInst *	si,
		int	idx,
		const VecElem	val
	)

pure virtual

Sets a vector register to a value.

Implemented in BaseDynInst< Impl >, BaseO3DynInst< Impl >, CheckerCPU, SimpleExecContext, and Minor::ExecContext.

◆ setVecLaneOperand() [1/4]

virtual void ExecContext::setVecLaneOperand	(	const StaticInst *	si,
		int	idx,
		const LaneData< LaneSize::Byte > &	val
	)

pure virtual

Write a lane of the destination vector operand.

Implemented in BaseO3DynInst< Impl >, SimpleExecContext, Minor::ExecContext, and CheckerCPU.

◆ setVecLaneOperand() [2/4]

virtual void ExecContext::setVecLaneOperand	(	const StaticInst *	si,
		int	idx,
		const LaneData< LaneSize::EightByte > &	val
	)

pure virtual

Implemented in BaseO3DynInst< Impl >, SimpleExecContext, Minor::ExecContext, and CheckerCPU.

◆ setVecLaneOperand() [3/4]

virtual void ExecContext::setVecLaneOperand	(	const StaticInst *	si,
		int	idx,
		const LaneData< LaneSize::FourByte > &	val
	)

pure virtual

Implemented in BaseO3DynInst< Impl >, SimpleExecContext, Minor::ExecContext, and CheckerCPU.

◆ setVecLaneOperand() [4/4]

virtual void ExecContext::setVecLaneOperand	(	const StaticInst *	si,
		int	idx,
		const LaneData< LaneSize::TwoByte > &	val
	)

pure virtual

Implemented in BaseO3DynInst< Impl >, SimpleExecContext, Minor::ExecContext, and CheckerCPU.

◆ setVecPredRegOperand()

virtual void ExecContext::setVecPredRegOperand	(	const StaticInst *	si,
		int	idx,
		const VecPredRegContainer &	val
	)

pure virtual

Sets a destination predicate register operand to a value.

Implemented in BaseDynInst< Impl >, BaseO3DynInst< Impl >, CheckerCPU, and SimpleExecContext.

◆ setVecRegOperand()

virtual void ExecContext::setVecRegOperand	(	const StaticInst *	si,
		int	idx,
		const VecRegContainer &	val
	)

pure virtual

Sets a destination vector register operand to a value.

Implemented in BaseDynInst< Impl >, BaseO3DynInst< Impl >, CheckerCPU, and SimpleExecContext.

◆ syscall()

virtual void ExecContext::syscall ( )

pure virtual

Executes a syscall.

Implemented in CheckerCPU, SimpleExecContext, Minor::ExecContext, and BaseO3DynInst< Impl >.

◆ tcBase()

virtual ThreadContext* ExecContext::tcBase ( ) const

pure virtual

Returns a pointer to the ThreadContext.

Implemented in BaseDynInst< Impl >, CheckerCPU, SimpleExecContext, and Minor::ExecContext.

Referenced by DebugStep::execute(), MiscRegImplDefined64::execute(), McrMrcMiscInst::execute(), McrMrcImplDefined::execute(), MipsISA::readRegOtherThread(), MipsISA::setRegOtherThread(), and ArmISA::ArmStaticInst::softwareBreakpoint32().

◆ writeMem()

virtual Fault ExecContext::writeMem	(	uint8_t *	data,
		unsigned int	size,
		Addr	addr,
		Request::Flags	flags,
		uint64_t *	res,
		const std::vector< bool > &	byte_enable = `std::vector< bool >()`
	)

pure virtual

For atomic-mode contexts, perform an atomic memory write operation.

For timing-mode contexts, initiate a timing memory write operation.

Implemented in SimpleExecContext, and Minor::ExecContext.

Referenced by X86ISA::writeMemAtomic(), X86ISA::writeMemTiming(), and X86ISA::writePackedMem().

The documentation for this class was generated from the following file:

cpu/exec_context.hh

Public Types

Public Member Functions

Detailed Description

Member Typedef Documentation

◆ PCState

◆ VecElem

◆ VecPredRegContainer

◆ VecRegContainer

Member Function Documentation

◆ amoMem()

◆ armMonitor()

◆ demapPage()

◆ getAddrMonitor()

◆ getHtmTransactionalDepth()

◆ getHtmTransactionUid()

◆ getWritableVecPredRegOperand()

◆ getWritableVecRegOperand()

◆ inHtmTransactionalState()

◆ initiateHtmCmd()

◆ initiateMemAMO()

◆ initiateMemRead()

◆ mwait()

◆ mwaitAtomic()

◆ newHtmTransactionUid()

◆ pcState() [1/2]

◆ pcState() [2/2]

◆ readCCRegOperand()

◆ readFloatRegOperandBits()

◆ readIntRegOperand()

◆ readMem()

◆ readMemAccPredicate()

◆ readMiscReg()

◆ readMiscRegOperand()

◆ readPredicate()

◆ readStCondFailures()

◆ readVec16BitLaneOperand()

◆ readVec32BitLaneOperand()

◆ readVec64BitLaneOperand()

◆ readVec8BitLaneOperand()

◆ readVecElemOperand()

◆ readVecPredRegOperand()

◆ readVecRegOperand()

◆ setCCRegOperand()

◆ setFloatRegOperandBits()

◆ setIntRegOperand()

◆ setMemAccPredicate()

◆ setMiscReg()

◆ setMiscRegOperand()

◆ setPredicate()

◆ setStCondFailures()

◆ setVecElemOperand()

◆ setVecLaneOperand() [1/4]

◆ setVecLaneOperand() [2/4]

◆ setVecLaneOperand() [3/4]

◆ setVecLaneOperand() [4/4]

◆ setVecPredRegOperand()

◆ setVecRegOperand()

◆ syscall()

◆ tcBase()

◆ writeMem()