gem5
v20.1.0.0
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#include <exported_clock_rate_control.hh>
Public Types | |
typedef tlm::tlm_base_target_socket< 64, ClockRateControlFwIf, ClockRateControlBwIf > | Base |
Public Types inherited from tlm::tlm_base_target_socket< 64, ClockRateControlFwIf, ClockRateControlBwIf > | |
typedef ClockRateControlFwIf | fw_interface_type |
typedef ClockRateControlBwIf | bw_interface_type |
typedef sc_core::sc_port< bw_interface_type, 1, sc_core::SC_ONE_OR_MORE_BOUND > | port_type |
typedef sc_core::sc_export< fw_interface_type > | export_type |
typedef tlm_base_initiator_socket_b< BUSWIDTH, fw_interface_type, bw_interface_type > | base_initiator_socket_type |
typedef tlm_base_target_socket_b< BUSWIDTH, fw_interface_type, bw_interface_type > | base_type |
Additional Inherited Members | |
Protected Attributes inherited from tlm::tlm_base_target_socket< 64, ClockRateControlFwIf, ClockRateControlBwIf > | |
port_type | m_port |
Definition at line 96 of file exported_clock_rate_control.hh.
typedef tlm::tlm_base_target_socket<64, ClockRateControlFwIf, ClockRateControlBwIf> ClockRateControlTargetSocket::Base |
Definition at line 102 of file exported_clock_rate_control.hh.
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inlineoverride |
Definition at line 116 of file exported_clock_rate_control.hh.
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inlineoverride |
Definition at line 110 of file exported_clock_rate_control.hh.