FullO3CPU< Impl > Member List

This is the complete list of members for FullO3CPU< Impl >, including all inherited members.

_cacheLineSize	BaseCPU	protected
_cpuId	BaseCPU	protected
_dataRequestorId	BaseCPU	protected
_instRequestorId	BaseCPU	protected
_pid	BaseCPU	protected
_socketId	BaseCPU	protected
_status	FullO3CPU< Impl >
_switchedOut	BaseCPU	protected
_taskId	BaseCPU	protected
activateContext(ThreadID tid) override	FullO3CPU< Impl >	virtual
activateStage(const StageIdx idx)	FullO3CPU< Impl >	inline
activateThread(ThreadID tid)	FullO3CPU< Impl >
activeThreads	FullO3CPU< Impl >	protected
activityRec	FullO3CPU< Impl >	private
activityThisCycle()	FullO3CPU< Impl >	inline
addInst(const DynInstPtr &inst)	FullO3CPU< Impl >
addressMonitor	BaseCPU	private
addThreadToExitingList(ThreadID tid)	FullO3CPU< Impl >
armMonitor(ThreadID tid, Addr address)	BaseCPU
BaseCPU(Params *params, bool is_checker=false)	BaseCPU
BaseO3CPU(BaseCPUParams *params)	BaseO3CPU
Blocked enum value	FullO3CPU< Impl >
cacheLineSize() const	BaseCPU	inline
ccRegfileReads	FullO3CPU< Impl >
ccRegfileWrites	FullO3CPU< Impl >
checker	FullO3CPU< Impl >
checkInterrupts(ThreadID tid) const	BaseCPU	inline
cleanUpRemovedInsts()	FullO3CPU< Impl >
clearInterrupt(ThreadID tid, int int_num, int index)	BaseCPU	inline
clearInterrupts(ThreadID tid)	BaseCPU	inline
commit	FullO3CPU< Impl >	protected
commitDrained(ThreadID tid)	FullO3CPU< Impl >
CommitIdx enum value	FullO3CPU< Impl >
commitRenameMap	FullO3CPU< Impl >	protected
committedInsts	FullO3CPU< Impl >
committedOps	FullO3CPU< Impl >
contextToThread(ContextID cid)	BaseCPU	inline
cpi	FullO3CPU< Impl >
CPU_STATE_ON enum value	BaseCPU	protected
CPU_STATE_SLEEP enum value	BaseCPU	protected
CPU_STATE_WAKEUP enum value	BaseCPU	protected
cpuId() const	BaseCPU	inline
cpuList	BaseCPU	privatestatic
CPUPolicy typedef	FullO3CPU< Impl >
CPUState enum name	BaseCPU	protected
cpuWaitList	FullO3CPU< Impl >
currentFunctionEnd	BaseCPU	private
currentFunctionStart	BaseCPU	private
dataRequestorId() const	BaseCPU	inline
deactivateStage(const StageIdx idx)	FullO3CPU< Impl >	inline
deactivateThread(ThreadID tid)	FullO3CPU< Impl >
decode	FullO3CPU< Impl >	protected
DecodeIdx enum value	FullO3CPU< Impl >
decodeQueue	FullO3CPU< Impl >
DecodeStruct typedef	FullO3CPU< Impl >
demapDataPage(Addr vaddr, uint64_t asn)	FullO3CPU< Impl >	inline
demapInstPage(Addr vaddr, uint64_t asn)	FullO3CPU< Impl >	inline
demapPage(Addr vaddr, uint64_t asn)	FullO3CPU< Impl >	inline
deschedulePowerGatingEvent()	BaseCPU
drain() override	FullO3CPU< Impl >
drainResume() override	FullO3CPU< Impl >
drainSanityCheck() const	FullO3CPU< Impl >	private
dtb	FullO3CPU< Impl >
dumpInsts()	FullO3CPU< Impl >
DynInstPtr typedef	FullO3CPU< Impl >
enableFunctionTrace()	BaseCPU	private
enterPwrGating()	BaseCPU	protected
enterPwrGatingEvent	BaseCPU	protected
exitingThreads	FullO3CPU< Impl >	protected
exitThreads()	FullO3CPU< Impl >
fetch	FullO3CPU< Impl >	protected
FetchIdx enum value	FullO3CPU< Impl >
fetchQueue	FullO3CPU< Impl >
FetchStruct typedef	FullO3CPU< Impl >
findContext(ThreadContext *tc)	BaseCPU
flushTLBs()	BaseCPU
fpRegfileReads	FullO3CPU< Impl >
fpRegfileWrites	FullO3CPU< Impl >
freeList	FullO3CPU< Impl >	protected
FullO3CPU(DerivO3CPUParams *params)	FullO3CPU< Impl >
functionEntryTick	BaseCPU	private
functionTraceStream	BaseCPU	private
functionTracingEnabled	BaseCPU	private
getAndIncrementInstSeq()	FullO3CPU< Impl >	inline
getContext(int tn)	BaseCPU	inlinevirtual
getCpuAddrMonitor(ThreadID tid)	BaseCPU	inline
getCurrentInstCount(ThreadID tid)	BaseCPU
getDataPort() override	FullO3CPU< Impl >	inlinevirtual
getFreeTid()	FullO3CPU< Impl >
getInstPort() override	FullO3CPU< Impl >	inlinevirtual
getInterruptController(ThreadID tid)	BaseCPU	inline
getInterrupts()	FullO3CPU< Impl >
getPid() const	BaseCPU	inline
getPort(const std::string &if_name, PortID idx=InvalidPortID) override	BaseCPU
getSendFunctional()	BaseCPU	inlinevirtual
getTracer()	BaseCPU	inline
getWritableArchVecPredReg(int reg_idx, ThreadID tid)	FullO3CPU< Impl >
getWritableArchVecReg(int reg_idx, ThreadID tid)	FullO3CPU< Impl >
getWritableVecPredReg(PhysRegIdPtr reg_idx)	FullO3CPU< Impl >
getWritableVecReg(PhysRegIdPtr reg_idx)	FullO3CPU< Impl >
globalSeqNum	FullO3CPU< Impl >
halt()	FullO3CPU< Impl >	inline
haltContext(ThreadID tid) override	FullO3CPU< Impl >	virtual
Halted enum value	FullO3CPU< Impl >
htmSendAbortSignal(ThreadID tid, uint64_t htm_uid, HtmFailureFaultCause cause)	FullO3CPU< Impl >
Idle enum value	FullO3CPU< Impl >
idleCycles	FullO3CPU< Impl >
iew	FullO3CPU< Impl >	protected
IEWIdx enum value	FullO3CPU< Impl >
iewQueue	FullO3CPU< Impl >
IEWStruct typedef	FullO3CPU< Impl >
ImplState typedef	FullO3CPU< Impl >
init() override	FullO3CPU< Impl >
insertThread(ThreadID tid)	FullO3CPU< Impl >
instAddr(ThreadID tid)	FullO3CPU< Impl >
instCnt	BaseCPU	protected
instCount()	BaseCPU	inline
instcount	FullO3CPU< Impl >
instDone(ThreadID tid, const DynInstPtr &inst)	FullO3CPU< Impl >
instList	FullO3CPU< Impl >
instRequestorId() const	BaseCPU	inline
interrupts	BaseCPU	protected
intRegfileReads	FullO3CPU< Impl >
intRegfileWrites	FullO3CPU< Impl >
invldPid	BaseCPU	static
ipc	FullO3CPU< Impl >
isa	FullO3CPU< Impl >	protected
isCpuDrained() const	FullO3CPU< Impl >	private
isDraining() const	FullO3CPU< Impl >	inline
isThreadExiting(ThreadID tid) const	FullO3CPU< Impl >
itb	FullO3CPU< Impl >
lastActivatedCycle	FullO3CPU< Impl >
lastRunningCycle	FullO3CPU< Impl >
ListIt typedef	FullO3CPU< Impl >
LSQRequest typedef	FullO3CPU< Impl >
microPC(ThreadID tid)	FullO3CPU< Impl >
miscRegfileReads	FullO3CPU< Impl >
miscRegfileWrites	FullO3CPU< Impl >
mwait(ThreadID tid, PacketPtr pkt)	BaseCPU
mwaitAtomic(ThreadID tid, ThreadContext *tc, BaseTLB *dtb)	BaseCPU
nextInstAddr(ThreadID tid)	FullO3CPU< Impl >
numActiveThreads()	FullO3CPU< Impl >	inline
numContexts()	BaseCPU	inline
numCycles	BaseCPU
numSimulatedCPUs()	BaseCPU	inlinestatic
numSimulatedInsts()	BaseCPU	inlinestatic
numSimulatedInsts()	BaseCPU	inlinestatic
numSimulatedOps()	BaseCPU	inlinestatic
numSimulatedOps()	BaseCPU	inlinestatic
NumStages enum value	FullO3CPU< Impl >
numThreads	BaseCPU
numWorkItemsCompleted	BaseCPU
numWorkItemsStarted	BaseCPU
O3CPU typedef	FullO3CPU< Impl >
O3ThreadContext< Impl > class	FullO3CPU< Impl >	friend
params() const	BaseCPU	inline
Params typedef	BaseCPU
PCMask	BaseCPU	static
pcState(const TheISA::PCState &newPCState, ThreadID tid)	FullO3CPU< Impl >
pcState(ThreadID tid)	FullO3CPU< Impl >
pmuProbePoint(const char *name)	BaseCPU	protected
postInterrupt(ThreadID tid, int int_num, int index)	BaseCPU
powerGatingOnIdle	BaseCPU	protected
ppActiveCycles	BaseCPU	protected
ppAllCycles	BaseCPU	protected
ppDataAccessComplete	FullO3CPU< Impl >
ppInstAccessComplete	FullO3CPU< Impl >
ppRetiredBranches	BaseCPU	protected
ppRetiredInsts	BaseCPU	protected
ppRetiredInstsPC	BaseCPU	protected
ppRetiredLoads	BaseCPU	protected
ppRetiredStores	BaseCPU	protected
ppSleeping	BaseCPU	protected
previousCycle	BaseCPU	protected
previousState	BaseCPU	protected
probeInstCommit(const StaticInstPtr &inst, Addr pc)	BaseCPU	virtual
processInterrupts(const Fault &interrupt)	FullO3CPU< Impl >
pushRequest(const DynInstPtr &inst, bool isLoad, uint8_t *data, unsigned int size, Addr addr, Request::Flags flags, uint64_t *res, AtomicOpFunctorPtr amo_op=nullptr, const std::vector< bool > &byte_enable=std::vector< bool >())	FullO3CPU< Impl >	inline
pwrGatingLatency	BaseCPU	protected
quiesceCycles	FullO3CPU< Impl >
read(LSQRequest *req, int load_idx)	FullO3CPU< Impl >	inline
readArchCCReg(int reg_idx, ThreadID tid)	FullO3CPU< Impl >
readArchFloatReg(int reg_idx, ThreadID tid)	FullO3CPU< Impl >
readArchIntReg(int reg_idx, ThreadID tid)	FullO3CPU< Impl >
readArchVecElem(const RegIndex &reg_idx, const ElemIndex &ldx, ThreadID tid) const	FullO3CPU< Impl >
readArchVecLane(int reg_idx, int lId, ThreadID tid) const	FullO3CPU< Impl >	inline
readArchVecPredReg(int reg_idx, ThreadID tid) const	FullO3CPU< Impl >
readArchVecReg(int reg_idx, ThreadID tid) const	FullO3CPU< Impl >
readCCReg(PhysRegIdPtr phys_reg)	FullO3CPU< Impl >
readFloatReg(PhysRegIdPtr phys_reg)	FullO3CPU< Impl >
readIntReg(PhysRegIdPtr phys_reg)	FullO3CPU< Impl >
readMiscReg(int misc_reg, ThreadID tid)	FullO3CPU< Impl >
readMiscRegNoEffect(int misc_reg, ThreadID tid) const	FullO3CPU< Impl >
readVecElem(PhysRegIdPtr reg_idx) const	FullO3CPU< Impl >
readVecLane(PhysRegIdPtr phys_reg) const	FullO3CPU< Impl >	inline
readVecLane(PhysRegIdPtr phys_reg) const	FullO3CPU< Impl >	inline
readVecPredReg(PhysRegIdPtr reg_idx) const	FullO3CPU< Impl >
readVecReg(PhysRegIdPtr reg_idx) const	FullO3CPU< Impl >
regFile	FullO3CPU< Impl >	protected
registerThreadContexts()	BaseCPU
regProbePoints() override	FullO3CPU< Impl >
regStats() override	FullO3CPU< Impl >
removeFrontInst(const DynInstPtr &inst)	FullO3CPU< Impl >
removeInstsNotInROB(ThreadID tid)	FullO3CPU< Impl >
removeInstsThisCycle	FullO3CPU< Impl >
removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid)	FullO3CPU< Impl >
removeList	FullO3CPU< Impl >
removeThread(ThreadID tid)	FullO3CPU< Impl >
rename	FullO3CPU< Impl >	protected
RenameIdx enum value	FullO3CPU< Impl >
renameMap	FullO3CPU< Impl >	protected
renameQueue	FullO3CPU< Impl >
RenameStruct typedef	FullO3CPU< Impl >
rob	FullO3CPU< Impl >	protected
Running enum value	FullO3CPU< Impl >
scheduleInstStop(ThreadID tid, Counter insts, const char *cause)	BaseCPU
schedulePowerGatingEvent()	BaseCPU
scheduleThreadExitEvent(ThreadID tid)	FullO3CPU< Impl >
scheduleTickEvent(Cycles delay)	FullO3CPU< Impl >	inlineprivate
scoreboard	FullO3CPU< Impl >	protected
serialize(CheckpointOut &cp) const override	BaseCPU
serializeThread(CheckpointOut &cp, ThreadID tid) const override	FullO3CPU< Impl >	virtual
setArchCCReg(int reg_idx, RegVal val, ThreadID tid)	FullO3CPU< Impl >
setArchFloatReg(int reg_idx, RegVal val, ThreadID tid)	FullO3CPU< Impl >
setArchIntReg(int reg_idx, RegVal val, ThreadID tid)	FullO3CPU< Impl >
setArchVecElem(const RegIndex &reg_idx, const ElemIndex &ldx, const VecElem &val, ThreadID tid)	FullO3CPU< Impl >
setArchVecLane(int reg_idx, int lId, ThreadID tid, const LD &val)	FullO3CPU< Impl >	inline
setArchVecPredReg(int reg_idx, const VecPredRegContainer &val, ThreadID tid)	FullO3CPU< Impl >
setArchVecReg(int reg_idx, const VecRegContainer &val, ThreadID tid)	FullO3CPU< Impl >
setCCReg(PhysRegIdPtr phys_reg, RegVal val)	FullO3CPU< Impl >
setFloatReg(PhysRegIdPtr phys_reg, RegVal val)	FullO3CPU< Impl >
setIntReg(PhysRegIdPtr phys_reg, RegVal val)	FullO3CPU< Impl >
setMiscReg(int misc_reg, RegVal val, ThreadID tid)	FullO3CPU< Impl >
setMiscRegNoEffect(int misc_reg, RegVal val, ThreadID tid)	FullO3CPU< Impl >
setPid(uint32_t pid)	BaseCPU	inline
setVecElem(PhysRegIdPtr reg_idx, const VecElem &val)	FullO3CPU< Impl >
setVecLane(PhysRegIdPtr phys_reg, const LD &val)	FullO3CPU< Impl >	inline
setVecPredReg(PhysRegIdPtr reg_idx, const VecPredRegContainer &val)	FullO3CPU< Impl >
setVecReg(PhysRegIdPtr reg_idx, const VecRegContainer &val)	FullO3CPU< Impl >
setVectorsAsReady(ThreadID tid)	FullO3CPU< Impl >
socketId() const	BaseCPU	inline
squashFromTC(ThreadID tid)	FullO3CPU< Impl >
squashInstIt(const ListIt &instIt, ThreadID tid)	FullO3CPU< Impl >	inline
StageIdx enum name	FullO3CPU< Impl >
startup() override	FullO3CPU< Impl >
Status enum name	FullO3CPU< Impl >
suspendContext(ThreadID tid) override	FullO3CPU< Impl >	virtual
switchedOut() const	BaseCPU	inline
SwitchedOut enum value	FullO3CPU< Impl >
switchOut() override	FullO3CPU< Impl >	virtual
switchRenameMode(ThreadID tid, UnifiedFreeList *freelist)	FullO3CPU< Impl >
syscall(ThreadID tid)	FullO3CPU< Impl >
syscallRetryLatency	BaseCPU
system	FullO3CPU< Impl >
takeOverFrom(BaseCPU *oldCPU) override	FullO3CPU< Impl >	virtual
taskId() const	BaseCPU	inline
taskId(uint32_t id)	BaseCPU	inline
tcBase(ThreadID tid)	FullO3CPU< Impl >	inline
Thread typedef	FullO3CPU< Impl >
thread	FullO3CPU< Impl >
threadContexts	BaseCPU	protected
threadExitEvent	FullO3CPU< Impl >	private
threadMap	FullO3CPU< Impl >
tick()	FullO3CPU< Impl >
tickEvent	FullO3CPU< Impl >	private
tids	FullO3CPU< Impl >
timeBuffer	FullO3CPU< Impl >
timesIdled	FullO3CPU< Impl >
TimeStruct typedef	FullO3CPU< Impl >
totalCpi	FullO3CPU< Impl >
totalInsts() const override	FullO3CPU< Impl >	virtual
totalIpc	FullO3CPU< Impl >
totalOps() const override	FullO3CPU< Impl >	virtual
traceFunctions(Addr pc)	BaseCPU	inline
traceFunctionsInternal(Addr pc)	BaseCPU	private
tracer	BaseCPU	protected
trap(const Fault &fault, ThreadID tid, const StaticInstPtr &inst)	FullO3CPU< Impl >
tryDrain()	FullO3CPU< Impl >	private
unscheduleTickEvent()	FullO3CPU< Impl >	inlineprivate
unserialize(CheckpointIn &cp) override	BaseCPU
unserializeThread(CheckpointIn &cp, ThreadID tid) override	FullO3CPU< Impl >	virtual
updateCycleCounters(CPUState state)	BaseCPU	inlineprotected
updateThreadPriority()	FullO3CPU< Impl >
VecElem typedef	FullO3CPU< Impl >
vecMode	FullO3CPU< Impl >	protected
VecPredRegContainer typedef	FullO3CPU< Impl >
vecPredRegfileReads	FullO3CPU< Impl >	mutable
vecPredRegfileWrites	FullO3CPU< Impl >
VecRegContainer typedef	FullO3CPU< Impl >
vecRegfileReads	FullO3CPU< Impl >	mutable
vecRegfileWrites	FullO3CPU< Impl >
vecRenameMode() const	FullO3CPU< Impl >	inline
vecRenameMode(Enums::VecRegRenameMode vec_mode)	FullO3CPU< Impl >	inline
verifyMemoryMode() const override	FullO3CPU< Impl >	virtual
waitForRemoteGDB() const	BaseCPU
wakeCPU()	FullO3CPU< Impl >
wakeup(ThreadID tid) override	FullO3CPU< Impl >	virtual
workItemBegin()	BaseCPU	inline
workItemEnd()	BaseCPU	inline
write(LSQRequest *req, uint8_t *data, int store_idx)	FullO3CPU< Impl >	inline
~BaseCPU()	BaseCPU	virtual
~FullO3CPU()	FullO3CPU< Impl >