#include <cpu_dummy.hh>

Inheritance diagram for BaseCPU:

Public Types
typedef BaseCPUParams	Params

Public Member Functions
virtual Port &	getDataPort ()=0
	Purely virtual method that returns a reference to the data port. More...

virtual PortProxy::SendFunctionalFunc	getSendFunctional ()
	Returns a sendFunctional delegate for use with port proxies. More...

virtual Port &	getInstPort ()=0
	Purely virtual method that returns a reference to the instruction port. More...

int	cpuId () const
	Reads this CPU's ID. More...

uint32_t	socketId () const
	Reads this CPU's Socket ID. More...

RequestorID	dataRequestorId () const
	Reads this CPU's unique data requestor ID. More...

RequestorID	instRequestorId () const
	Reads this CPU's unique instruction requestor ID. More...

Port &	getPort (const std::string &if_name, PortID idx=InvalidPortID) override
	Get a port on this CPU. More...

uint32_t	taskId () const
	Get cpu task id. More...

void	taskId (uint32_t id)
	Set cpu task id. More...

uint32_t	getPid () const

void	setPid (uint32_t pid)

void	workItemBegin ()

void	workItemEnd ()

Tick	instCount ()

BaseInterrupts *	getInterruptController (ThreadID tid)

virtual void	wakeup (ThreadID tid)=0

void	postInterrupt (ThreadID tid, int int_num, int index)

void	clearInterrupt (ThreadID tid, int int_num, int index)

void	clearInterrupts (ThreadID tid)

bool	checkInterrupts (ThreadID tid) const

Trace::InstTracer *	getTracer ()
	Provide access to the tracer pointer. More...

virtual void	activateContext (ThreadID thread_num)
	Notify the CPU that the indicated context is now active. More...

virtual void	suspendContext (ThreadID thread_num)
	Notify the CPU that the indicated context is now suspended. More...

virtual void	haltContext (ThreadID thread_num)
	Notify the CPU that the indicated context is now halted. More...

int	findContext (ThreadContext *tc)
	Given a Thread Context pointer return the thread num. More...

virtual ThreadContext *	getContext (int tn)
	Given a thread num get tho thread context for it. More...

unsigned	numContexts ()
	Get the number of thread contexts available. More...

ThreadID	contextToThread (ContextID cid)
	Convert ContextID to threadID. More...

const Params *	params () const

	BaseCPU (Params *params, bool is_checker=false)

virtual	~BaseCPU ()

void	init () override

void	startup () override

void	regStats () override

void	regProbePoints () override

void	registerThreadContexts ()

void	deschedulePowerGatingEvent ()

void	schedulePowerGatingEvent ()

virtual void	switchOut ()
	Prepare for another CPU to take over execution. More...

virtual void	takeOverFrom (BaseCPU *cpu)
	Load the state of a CPU from the previous CPU object, invoked on all new CPUs that are about to be switched in. More...

void	flushTLBs ()
	Flush all TLBs in the CPU. More...

bool	switchedOut () const
	Determine if the CPU is switched out. More...

virtual void	verifyMemoryMode () const
	Verify that the system is in a memory mode supported by the CPU. More...

unsigned int	cacheLineSize () const
	Get the cache line size of the system. More...

void	serialize (CheckpointOut &cp) const override
	Serialize this object to the given output stream. More...

void	unserialize (CheckpointIn &cp) override
	Reconstruct the state of this object from a checkpoint. More...

virtual void	serializeThread (CheckpointOut &cp, ThreadID tid) const
	Serialize a single thread. More...

virtual void	unserializeThread (CheckpointIn &cp, ThreadID tid)
	Unserialize one thread. More...

virtual Counter	totalInsts () const =0

virtual Counter	totalOps () const =0

void	scheduleInstStop (ThreadID tid, Counter insts, const char *cause)
	Schedule an event that exits the simulation loops after a predefined number of instructions. More...

uint64_t	getCurrentInstCount (ThreadID tid)
	Get the number of instructions executed by the specified thread on this CPU. More...

void	traceFunctions (Addr pc)

void	armMonitor (ThreadID tid, Addr address)

bool	mwait (ThreadID tid, PacketPtr pkt)

void	mwaitAtomic (ThreadID tid, ThreadContext tc, BaseTLB dtb)

AddressMonitor *	getCpuAddrMonitor (ThreadID tid)

bool	waitForRemoteGDB () const

Static Public Member Functions
static int	numSimulatedInsts ()

static int	numSimulatedOps ()

static void	wakeup (ThreadID tid)

static int	numSimulatedCPUs ()

static Counter	numSimulatedInsts ()

static Counter	numSimulatedOps ()

Public Attributes
ThreadID	numThreads
	Number of threads we're actually simulating (<= SMT_MAX_THREADS). More...

System *	system

Stats::Scalar	numCycles

Stats::Scalar	numWorkItemsStarted

Stats::Scalar	numWorkItemsCompleted

Cycles	syscallRetryLatency

Static Public Attributes
static const uint32_t	invldPid = std::numeric_limits<uint32_t>::max()
	Invalid or unknown Pid. More...

static const Addr	PCMask = ~((Addr)sizeof(TheISA::MachInst) - 1)

Protected Types
enum	CPUState { CPU_STATE_ON, CPU_STATE_SLEEP, CPU_STATE_WAKEUP }

Protected Member Functions
void	updateCycleCounters (CPUState state)
	base method keeping track of cycle progression More...

void	enterPwrGating ()

Protected Attributes
Tick	instCnt
	Instruction count used for SPARC misc register. More...

int	_cpuId

const uint32_t	_socketId
	Each cpu will have a socket ID that corresponds to its physical location in the system. More...

RequestorID	_instRequestorId
	instruction side request id that must be placed in all requests More...

RequestorID	_dataRequestorId
	data side request id that must be placed in all requests More...

uint32_t	_taskId
	An intrenal representation of a task identifier within gem5. More...

uint32_t	_pid
	The current OS process ID that is executing on this processor. More...

bool	_switchedOut
	Is the CPU switched out or active? More...

const unsigned int	_cacheLineSize
	Cache the cache line size that we get from the system. More...

std::vector< BaseInterrupts * >	interrupts

std::vector< ThreadContext * >	threadContexts

Trace::InstTracer *	tracer

Cycles	previousCycle

CPUState	previousState

const Cycles	pwrGatingLatency

const bool	powerGatingOnIdle

EventFunctionWrapper	enterPwrGatingEvent

Private Member Functions
void	enableFunctionTrace ()

void	traceFunctionsInternal (Addr pc)

Private Attributes
bool	functionTracingEnabled

std::ostream *	functionTraceStream

Addr	currentFunctionStart

Addr	currentFunctionEnd

Tick	functionEntryTick

std::vector< AddressMonitor >	addressMonitor

Static Private Attributes
static std::vector< BaseCPU * >	cpuList
	Static global cpu list. More...

PMU Probe points.
ProbePoints::PMUUPtr	ppRetiredInsts
	Instruction commit probe point. More...

ProbePoints::PMUUPtr	ppRetiredInstsPC

ProbePoints::PMUUPtr	ppRetiredLoads
	Retired load instructions. More...

ProbePoints::PMUUPtr	ppRetiredStores
	Retired store instructions. More...

ProbePoints::PMUUPtr	ppRetiredBranches
	Retired branches (any type) More...

ProbePoints::PMUUPtr	ppAllCycles
	CPU cycle counter even if any thread Context is suspended. More...

ProbePoints::PMUUPtr	ppActiveCycles
	CPU cycle counter, only counts if any thread contexts is active. More...

ProbePointArg< bool > *	ppSleeping
	ProbePoint that signals transitions of threadContexts sets. More...

virtual void	probeInstCommit (const StaticInstPtr &inst, Addr pc)
	Helper method to trigger PMU probes for a committed instruction. More...

ProbePoints::PMUUPtr	pmuProbePoint (const char *name)
	Helper method to instantiate probe points belonging to this object. More...

Detailed Description

Definition at line 43 of file cpu_dummy.hh.

Member Typedef Documentation

◆ Params

typedef BaseCPUParams BaseCPU::Params

Definition at line 295 of file base.hh.

Member Enumeration Documentation

◆ CPUState

enum BaseCPU::CPUState

protected

Enumerator
CPU_STATE_ON
CPU_STATE_SLEEP
CPU_STATE_WAKEUP

Definition at line 507 of file base.hh.

Constructor & Destructor Documentation

◆ BaseCPU()

BaseCPU::BaseCPU	(	Params *	params,
		bool	is_checker = `false`
	)

Definition at line 123 of file base.cc.

References enterPwrGating().

◆ ~BaseCPU()

BaseCPU::~BaseCPU ( )

virtual

Reimplemented in Iris::BaseCPU.

Definition at line 184 of file base.cc.

Member Function Documentation

◆ activateContext()

void BaseCPU::activateContext ( ThreadID thread_num )

virtual

Notify the CPU that the indicated context is now active.

Reimplemented in FullO3CPU< Impl >, FullO3CPU< O3CPUImpl >, TimingSimpleCPU, AtomicSimpleCPU, BaseKvmCPU, and MinorCPU.

Definition at line 480 of file base.cc.

References CPU_STATE_WAKEUP, DPRINTF, enterPwrGatingEvent, Event::scheduled(), threadContexts, and updateCycleCounters().

Referenced by SimpleThread::activate(), MinorCPU::activateContext(), AtomicSimpleCPU::activateContext(), FullO3CPU< O3CPUImpl >::activateContext(), and TimingSimpleCPU::activateContext().

◆ armMonitor()

void BaseCPU::armMonitor	(	ThreadID	tid,
		Addr	address
	)

Definition at line 200 of file base.cc.

References addressMonitor, AddressMonitor::armed, DPRINTF, numThreads, AddressMonitor::pAddr, and AddressMonitor::vAddr.

Referenced by Minor::ExecContext::armMonitor(), CheckerCPU::armMonitor(), and SimpleExecContext::armMonitor().

◆ cacheLineSize()

unsigned int BaseCPU::cacheLineSize ( ) const

inline

Get the cache line size of the system.

Definition at line 376 of file base.hh.

References _cacheLineSize.

Referenced by AtomicSimpleCPU::amoMem(), AtomicSimpleCPU::AtomicCPUDPort::AtomicCPUDPort(), TimingSimpleCPU::DcachePort::DcachePort(), TraceCPU::ElasticDataGen::executeMemReq(), Minor::Fetch1::Fetch1(), AtomicSimpleCPU::genMemFragmentRequest(), CheckerCPU::genMemFragmentRequest(), TimingSimpleCPU::initiateMemAMO(), TimingSimpleCPU::initiateMemRead(), ThreadState::initMemProxies(), Iris::ThreadContext::initMemProxies(), mwait(), mwaitAtomic(), and TimingSimpleCPU::writeMem().

◆ checkInterrupts()

bool BaseCPU::checkInterrupts ( ThreadID tid ) const

inline

Definition at line 246 of file base.hh.

References FullSystem, and interrupts.

Referenced by BaseSimpleCPU::checkForInterrupts(), and Minor::Execute::isInterrupted().

◆ clearInterrupt()

void BaseCPU::clearInterrupt	(	ThreadID	tid,
		int	int_num,
		int	index
	)

inline

Definition at line 234 of file base.hh.

References MipsISA::index, and interrupts.

Referenced by SparcISA::ISA::checkSoftInt(), SparcISA::TLB::doMmuRegRead(), SparcISA::TLB::doMmuRegWrite(), ArmISA::AbortFault< DataAbort >::invoke(), ArmISA::SystemError::invoke(), ArmISA::ArmSev::invoke(), SparcISA::ISA::setFSReg(), and SparcISA::ISA::setMiscReg().

◆ clearInterrupts()

void BaseCPU::clearInterrupts ( ThreadID tid )

inline

Definition at line 240 of file base.hh.

References interrupts.

Referenced by ArmISA::Reset::invoke().

◆ contextToThread()

ThreadID BaseCPU::contextToThread ( ContextID cid )

inline

Convert ContextID to threadID.

Definition at line 291 of file base.hh.

References threadContexts.

Referenced by Minor::LSQ::tryToSend().

◆ cpuId()

int BaseCPU::cpuId ( ) const

inline

Reads this CPU's ID.

Definition at line 178 of file base.hh.

References _cpuId.

Referenced by ThreadState::cpuId(), Iris::ThreadContext::cpuId(), takeOverFrom(), Trace::TarmacContext::tarmacCpuName(), PseudoInst::workbegin(), and PseudoInst::workend().

◆ dataRequestorId()

RequestorID BaseCPU::dataRequestorId ( ) const

inline

Reads this CPU's unique data requestor ID.

Definition at line 184 of file base.hh.

References _dataRequestorId.

Referenced by AtomicSimpleCPU::amoMem(), BaseKvmCPU::doMMIOAccess(), AtomicSimpleCPU::genMemFragmentRequest(), X86KvmCPU::handleKvmExitIO(), TimingSimpleCPU::htmSendAbortSignal(), TimingSimpleCPU::initiateHtmCmd(), TimingSimpleCPU::initiateMemAMO(), TimingSimpleCPU::initiateMemRead(), mwaitAtomic(), Minor::LSQ::pushRequest(), and TimingSimpleCPU::writeMem().

◆ deschedulePowerGatingEvent()

void BaseCPU::deschedulePowerGatingEvent ( )

Definition at line 444 of file base.cc.

References enterPwrGatingEvent, and Event::scheduled().

Referenced by MinorCPU::drain(), AtomicSimpleCPU::drain(), and TimingSimpleCPU::drain().

◆ enableFunctionTrace()

void BaseCPU::enableFunctionTrace ( )

private

Definition at line 179 of file base.cc.

References functionTracingEnabled.

◆ enterPwrGating()

void BaseCPU::enterPwrGating ( )

protected

Definition at line 526 of file base.cc.

References RiscvISA::OFF.

Referenced by BaseCPU().

◆ findContext()

int BaseCPU::findContext ( ThreadContext * tc )

Given a Thread Context pointer return the thread num.

Definition at line 469 of file base.cc.

References threadContexts.

◆ flushTLBs()

void BaseCPU::flushTLBs ( )

Flush all TLBs in the CPU.

This method is mainly used to flush stale translations when switching CPUs. It is also exported to the Python world to allow it to request a TLB flush after draining the CPU to make it easier to compare traces when debugging handover/checkpointing.

Definition at line 635 of file base.cc.

References BaseTLB::flushAll(), ThreadContext::getCheckerCpuPtr(), ThreadContext::getDTBPtr(), CheckerCPU::getDTBPtr(), ThreadContext::getITBPtr(), CheckerCPU::getITBPtr(), ArmISA::i, and threadContexts.

Referenced by switchOut().

◆ getContext()

virtual ThreadContext* BaseCPU::getContext ( int tn )

inlinevirtual

Given a thread num get tho thread context for it.

Reimplemented in BaseKvmCPU.

Definition at line 283 of file base.hh.

References threadContexts.

Referenced by Minor::Execute::commit(), Minor::Execute::commitInst(), Minor::Fetch2::evaluate(), Minor::Execute::evaluate(), Minor::Execute::executeMemRefInst(), Minor::Fetch1::fetchLine(), Minor::Fetch1::getScheduledThread(), Minor::Execute::handleMemResponse(), MinorCPU::init(), Shader::init(), Minor::Execute::issue(), MipsISA::readRegOtherThread(), Minor::LSQ::recvTimingSnoopReq(), ElasticTrace::regProbeListeners(), MipsISA::setRegOtherThread(), Minor::Execute::takeInterrupt(), Minor::LSQ::threadSnoop(), Minor::Execute::tryPCEvents(), Minor::Execute::tryToBranch(), Minor::LSQ::tryToSend(), Shader::updateContext(), MipsISA::ISA::updateCPU(), and Minor::Fetch1::wakeupFetch().

◆ getCpuAddrMonitor()

AddressMonitor* BaseCPU::getCpuAddrMonitor ( ThreadID tid )

inline

Definition at line 599 of file base.hh.

References addressMonitor, and numThreads.

Referenced by Minor::ExecContext::getAddrMonitor(), CheckerCPU::getAddrMonitor(), SimpleExecContext::getAddrMonitor(), AtomicSimpleCPU::AtomicCPUDPort::recvAtomicSnoop(), AtomicSimpleCPU::AtomicCPUDPort::recvFunctionalSnoop(), TimingSimpleCPU::DcachePort::recvFunctionalSnoop(), TimingSimpleCPU::DcachePort::recvTimingSnoopReq(), Minor::LSQ::recvTimingSnoopReq(), TimingSimpleCPU::threadSnoop(), AtomicSimpleCPU::threadSnoop(), Minor::LSQ::threadSnoop(), and BaseSimpleCPU::wakeup().

◆ getCurrentInstCount()

Tick BaseCPU::getCurrentInstCount ( ThreadID tid )

Get the number of instructions executed by the specified thread on this CPU.

Used by Python to control simulation.

Parameters

tid	Thread monitor

Returns: Number of instructions executed

Definition at line 698 of file base.cc.

References threadContexts.

Referenced by scheduleInstStop().

◆ getDataPort()

virtual Port& BaseCPU::getDataPort ( )

pure virtual

Purely virtual method that returns a reference to the data port.

All subclasses must implement this method.

Returns: a reference to the data port

Implemented in FullO3CPU< Impl >, FullO3CPU< O3CPUImpl >, TimingSimpleCPU, AtomicSimpleCPU, MinorCPU, CheckerCPU, BaseKvmCPU, Iris::BaseCPU, and TraceCPU.

Referenced by getPort(), getSendFunctional(), TraceCPU::takeOverFrom(), and takeOverFrom().

◆ getInstPort()

virtual Port& BaseCPU::getInstPort ( )

pure virtual

Purely virtual method that returns a reference to the instruction port.

All subclasses must implement this method.

Returns: a reference to the instruction port

Implemented in FullO3CPU< Impl >, FullO3CPU< O3CPUImpl >, TimingSimpleCPU, AtomicSimpleCPU, MinorCPU, CheckerCPU, BaseKvmCPU, Iris::BaseCPU, and TraceCPU.

Referenced by getPort(), TraceCPU::takeOverFrom(), and takeOverFrom().

◆ getInterruptController()

BaseInterrupts* BaseCPU::getInterruptController ( ThreadID tid )

inline

Definition at line 219 of file base.hh.

References interrupts.

Referenced by Minor::Execute::checkInterrupts(), SparcISA::TLB::doMmuRegRead(), SparcISA::TLB::doMmuRegWrite(), Minor::Execute::hasInterrupt(), RiscvISA::ISA::readMiscReg(), ArmISA::ISA::readMiscReg(), RiscvISA::ISA::setMiscReg(), and Minor::Execute::takeInterrupt().

◆ getPid()

uint32_t BaseCPU::getPid ( ) const

inline

Definition at line 206 of file base.hh.

References _pid.

Referenced by takeOverFrom().

◆ getPort()

Port & BaseCPU::getPort	(	const std::string &	if_name,
		PortID	idx = `InvalidPortID`
	)

override

Get a port on this CPU.

All CPUs have a data and instruction port, and this method uses getDataPort and getInstPort of the subclasses to resolve the two ports.

Parameters

if_name	the port name
idx	ignored index

Returns: a reference to the port with the given name

Definition at line 402 of file base.cc.

References getDataPort(), getInstPort(), and SimObject::getPort().

Referenced by FastModel::CortexA76::getPort().

◆ getSendFunctional()

virtual PortProxy::SendFunctionalFunc BaseCPU::getSendFunctional ( )

inlinevirtual

Returns a sendFunctional delegate for use with port proxies.

Reimplemented in Iris::BaseCPU.

Definition at line 162 of file base.hh.

References getDataPort().

Referenced by ThreadState::initMemProxies().

◆ getTracer()

Trace::InstTracer* BaseCPU::getTracer ( )

inline

Provide access to the tracer pointer.

Definition at line 267 of file base.hh.

References tracer.

◆ haltContext()

void BaseCPU::haltContext ( ThreadID thread_num )

virtual

Notify the CPU that the indicated context is now halted.

Reimplemented in FullO3CPU< Impl >, FullO3CPU< O3CPUImpl >, BaseSimpleCPU, and BaseKvmCPU.

Definition at line 520 of file base.cc.

References CPU_STATE_SLEEP, and updateCycleCounters().

Referenced by SimpleThread::halt().

◆ init()

void BaseCPU::init ( )

override

Definition at line 267 of file base.cc.

References MipsISA::event, ArmISA::i, numThreads, params(), registerThreadContexts(), scheduleInstStop(), threadContexts, and verifyMemoryMode().

Referenced by BaseKvmCPU::init(), BaseSimpleCPU::init(), Iris::BaseCPU::init(), MinorCPU::init(), TraceCPU::init(), and FullO3CPU< O3CPUImpl >::init().

◆ instCount()

Tick BaseCPU::instCount ( )

inline

Definition at line 212 of file base.hh.

References instCnt.

Referenced by SparcISA::ISA::processHSTickCompare(), SparcISA::ISA::processSTickCompare(), SparcISA::ISA::readMiscReg(), SparcISA::ISA::setFSReg(), and SparcISA::ISA::setMiscReg().

◆ instRequestorId()

RequestorID BaseCPU::instRequestorId ( ) const

inline

Reads this CPU's unique instruction requestor ID.

Definition at line 186 of file base.hh.

References _instRequestorId.

Referenced by Minor::Fetch1::fetchLine(), and BaseSimpleCPU::setupFetchRequest().

◆ mwait()

bool BaseCPU::mwait	(	ThreadID	tid,
		PacketPtr	pkt
	)

Definition at line 212 of file base.cc.

References addressMonitor, cacheLineSize(), DPRINTF, Packet::getAddr(), AddressMonitor::gotWakeup, ArmISA::mask, numThreads, AddressMonitor::pAddr, Packet::req, AddressMonitor::vAddr, and AddressMonitor::waiting.

Referenced by Minor::ExecContext::mwait(), CheckerCPU::mwait(), and SimpleExecContext::mwait().

◆ mwaitAtomic()

void BaseCPU::mwaitAtomic	(	ThreadID	tid,
		ThreadContext *	tc,
		BaseTLB *	dtb
	)

Definition at line 235 of file base.cc.

References addr, addressMonitor, cacheLineSize(), dataRequestorId(), DPRINTF, ThreadContext::instAddr(), ArmISA::mask, NoFault, numThreads, AddressMonitor::pAddr, BaseTLB::Read, roundDown(), BaseTLB::translateAtomic(), AddressMonitor::vAddr, and AddressMonitor::waiting.

Referenced by Minor::ExecContext::mwaitAtomic(), CheckerCPU::mwaitAtomic(), and SimpleExecContext::mwaitAtomic().

◆ numContexts()

unsigned BaseCPU::numContexts ( )

inline

Get the number of thread contexts available.

Definition at line 286 of file base.hh.

References threadContexts.

◆ numSimulatedCPUs()

static int BaseCPU::numSimulatedCPUs ( )

inlinestatic

Definition at line 563 of file base.hh.

References cpuList.

◆ numSimulatedInsts() [1/2]

static int BaseCPU::numSimulatedInsts ( )

inlinestatic

Definition at line 46 of file cpu_dummy.hh.

Referenced by Stats::Global::Global(), and ElasticTrace::regEtraceListeners().

◆ numSimulatedInsts() [2/2]

static Counter BaseCPU::numSimulatedInsts ( )

inlinestatic

Definition at line 564 of file base.hh.

References cpuList, ArmISA::i, Stats::total, and totalInsts().

◆ numSimulatedOps() [1/2]

static int BaseCPU::numSimulatedOps ( )

inlinestatic

Definition at line 47 of file cpu_dummy.hh.

Referenced by Stats::Global::Global().

◆ numSimulatedOps() [2/2]

static Counter BaseCPU::numSimulatedOps ( )

inlinestatic

Definition at line 575 of file base.hh.

References cpuList, ArmISA::i, Stats::total, and totalOps().

◆ params()

const Params* BaseCPU::params ( ) const

inline

Definition at line 296 of file base.hh.

Referenced by Iris::CPU< CortexA76TC >::CPU(), PseudoInst::dumpresetstats(), PseudoInst::dumpstats(), MinorCPU::init(), init(), PseudoInst::m5checkpoint(), MinorCPU::MinorCPU(), PseudoInst::resetstats(), BaseKvmCPU::startup(), startup(), BaseKvmCPU::startupThread(), and waitForRemoteGDB().

◆ pmuProbePoint()

ProbePoints::PMUUPtr BaseCPU::pmuProbePoint ( const char * name )

protected

Helper method to instantiate probe points belonging to this object.

Parameters

name	Name of the probe point.

Returns: A unique_ptr to the new probe point.

Definition at line 326 of file base.cc.

References name().

Referenced by regProbePoints().

◆ postInterrupt()

void BaseCPU::postInterrupt	(	ThreadID	tid,
		int	int_num,
		int	index
	)

Definition at line 189 of file base.cc.

References FullSystem, System::futexMap, MipsISA::index, interrupts, FutexMap::is_waiting(), system, threadContexts, and wakeup().

Referenced by SparcISA::ISA::checkSoftInt(), ArmISA::sendEvent(), SparcISA::ISA::setFSReg(), and SparcISA::ISA::setMiscReg().

◆ probeInstCommit()

void BaseCPU::probeInstCommit	(	const StaticInstPtr &	inst,
		Addr	pc
	)

virtual

Helper method to trigger PMU probes for a committed instruction.

Parameters

inst	Instruction that just committed
pc	PC of the instruction that just committed

Definition at line 351 of file base.cc.

References StaticInst::isAtomic(), StaticInst::isControl(), StaticInst::isLastMicroop(), StaticInst::isLoad(), StaticInst::isMicroop(), StaticInst::isStore(), MipsISA::pc, ppRetiredBranches, ppRetiredInsts, ppRetiredInstsPC, ppRetiredLoads, and ppRetiredStores.

Referenced by Minor::Execute::doInstCommitAccounting(), and BaseSimpleCPU::postExecute().

◆ registerThreadContexts()

void BaseCPU::registerThreadContexts ( )

Definition at line 416 of file base.cc.

References _cpuId, Process::assignThreadContext(), ThreadContext::contextId(), fatal_if, FullSystem, ThreadContext::getIsaPtr(), ThreadContext::getProcessPtr(), interrupts, System::multiThread, name(), numThreads, System::registerThreadContext(), ThreadContext::setContextId(), BaseISA::setThreadContext(), system, and threadContexts.

Referenced by init().

◆ regProbePoints()

void BaseCPU::regProbePoints ( )

override

Definition at line 335 of file base.cc.

References pmuProbePoint(), ppActiveCycles, ppAllCycles, ppRetiredBranches, ppRetiredInsts, ppRetiredInstsPC, ppRetiredLoads, ppRetiredStores, and ppSleeping.

Referenced by FullO3CPU< O3CPUImpl >::regProbePoints(), and AtomicSimpleCPU::regProbePoints().

◆ regStats()

void BaseCPU::regStats ( )

override

Definition at line 369 of file base.cc.

References ccprintf(), Stats::DataWrap< Derived, InfoProxyType >::desc(), ArmISA::i, name(), Stats::DataWrap< Derived, InfoProxyType >::name(), numCycles, numWorkItemsCompleted, numWorkItemsStarted, Stats::Group::regStats(), and threadContexts.

Referenced by BaseO3CPU::regStats(), MinorCPU::regStats(), and BaseSimpleCPU::regStats().

◆ scheduleInstStop()

void BaseCPU::scheduleInstStop	(	ThreadID	tid,
		Counter	insts,
		const char *	cause
	)

Schedule an event that exits the simulation loops after a predefined number of instructions.

This method is usually called from the configuration script to get an exit event some time in the future. It is typically used when the script wants to simulate for a specific number of instructions rather than ticks.

Parameters

tid	Thread monitor.
insts	Number of instructions into the future.
cause	Cause to signal in the exit event.

Definition at line 689 of file base.cc.

References MipsISA::event, getCurrentInstCount(), and threadContexts.

Referenced by init().

◆ schedulePowerGatingEvent()

void BaseCPU::schedulePowerGatingEvent ( )

Definition at line 452 of file base.cc.

References ThreadContext::Active, enterPwrGatingEvent, powerGatingOnIdle, pwrGatingLatency, Event::scheduled(), and threadContexts.

Referenced by MinorCPU::drainResume(), AtomicSimpleCPU::drainResume(), and TimingSimpleCPU::drainResume().

◆ serialize()

void BaseCPU::serialize ( CheckpointOut & cp ) const

override

Serialize this object to the given output stream.

Note: CPU models should normally overload the serializeThread() method instead of the serialize() method as this provides a uniform data format for all CPU models and promotes better code reuse.

Parameters

cp	The stream to serialize to.

Definition at line 651 of file base.cc.

References _pid, _switchedOut, csprintf(), ArmISA::i, instCnt, interrupts, numThreads, SERIALIZE_SCALAR, and serializeThread().

Referenced by MinorCPU::serialize(), and Iris::BaseCPU::serializeThread().

◆ serializeThread()

virtual void BaseCPU::serializeThread	(	CheckpointOut &	cp,
		ThreadID	tid
	)		const

inlinevirtual

Serialize a single thread.

Parameters

cp	The stream to serialize to.
tid	ID of the current thread.

Reimplemented in FullO3CPU< Impl >, FullO3CPU< O3CPUImpl >, BaseSimpleCPU, MinorCPU, Iris::BaseCPU, and BaseKvmCPU.

Definition at line 408 of file base.hh.

Referenced by serialize().

◆ setPid()

void BaseCPU::setPid ( uint32_t pid )

inline

Definition at line 207 of file base.hh.

References _pid.

Referenced by ArmISA::DumpStats::process().

◆ socketId()

uint32_t BaseCPU::socketId ( ) const

inline

Reads this CPU's Socket ID.

Definition at line 181 of file base.hh.

References _socketId.

Referenced by ThreadState::socketId(), and Iris::ThreadContext::socketId().

◆ startup()

void BaseCPU::startup ( )

override

Definition at line 310 of file base.cc.

References _switchedOut, RiscvISA::OFF, and params().

Referenced by BaseKvmCPU::startup(), MinorCPU::startup(), and FullO3CPU< O3CPUImpl >::startup().

◆ suspendContext()

void BaseCPU::suspendContext ( ThreadID thread_num )

virtual

Notify the CPU that the indicated context is now suspended.

Check if possible to enter a lower power state

Reimplemented in FullO3CPU< Impl >, FullO3CPU< O3CPUImpl >, TimingSimpleCPU, AtomicSimpleCPU, BaseKvmCPU, and MinorCPU.

Definition at line 494 of file base.cc.

References CPU_STATE_SLEEP, DPRINTF, enterPwrGatingEvent, powerGatingOnIdle, pwrGatingLatency, ThreadContext::Suspended, ArmISA::t, threadContexts, and updateCycleCounters().

Referenced by BaseSimpleCPU::haltContext(), SimpleThread::suspend(), MinorCPU::suspendContext(), AtomicSimpleCPU::suspendContext(), FullO3CPU< O3CPUImpl >::suspendContext(), and TimingSimpleCPU::suspendContext().

◆ switchedOut()

bool BaseCPU::switchedOut ( ) const

inline

Determine if the CPU is switched out.

Returns: True if the CPU is switched out, false otherwise.

Definition at line 352 of file base.hh.

References _switchedOut.

Referenced by BaseKvmCPU::drain(), MinorCPU::drain(), AtomicSimpleCPU::drain(), TimingSimpleCPU::drain(), BaseKvmCPU::drainResume(), MinorCPU::drainResume(), AtomicSimpleCPU::drainResume(), TimingSimpleCPU::drainResume(), CPUProgressEvent::process(), and MinorCPU::switchOut().

◆ switchOut()

void BaseCPU::switchOut ( )

virtual

Prepare for another CPU to take over execution.

When this method exits, all internal state should have been flushed. After the method returns, the simulator calls takeOverFrom() on the new CPU with this CPU as its parameter.

Reimplemented in FullO3CPU< Impl >, FullO3CPU< O3CPUImpl >, TimingSimpleCPU, AtomicSimpleCPU, MinorCPU, BaseKvmCPU, Checker< Impl >, and Checker< O3CPUImpl >.

Definition at line 532 of file base.cc.

References _switchedOut, flushTLBs(), and RiscvISA::OFF.

Referenced by BaseKvmCPU::switchOut(), MinorCPU::switchOut(), AtomicSimpleCPU::switchOut(), TimingSimpleCPU::switchOut(), and FullO3CPU< O3CPUImpl >::switchOut().

◆ takeOverFrom()

void BaseCPU::takeOverFrom ( BaseCPU * cpu )

virtual

Load the state of a CPU from the previous CPU object, invoked on all new CPUs that are about to be switched in.

A CPU model implementing this method is expected to initialize its state from the old CPU and connect its memory (unless they are already connected) to the memories connected to the old CPU.

Parameters

cpu	CPU to initialize read state from.

Reimplemented in FullO3CPU< Impl >, FullO3CPU< O3CPUImpl >, TimingSimpleCPU, AtomicSimpleCPU, Checker< Impl >, Checker< O3CPUImpl >, TraceCPU, MinorCPU, and BaseKvmCPU.

Definition at line 546 of file base.cc.

References _cpuId, _pid, _switchedOut, _taskId, ThreadContext::contextId(), cpuId(), ThreadContext::getCheckerCpuPtr(), getDataPort(), ThreadContext::getDTBPtr(), CheckerCPU::getDTBPtr(), getInstPort(), ThreadContext::getIsaPtr(), ThreadContext::getITBPtr(), CheckerCPU::getITBPtr(), getPid(), BaseTLB::getTableWalkerPort(), ArmISA::i, interrupts, numThreads, previousCycle, previousState, System::replaceThreadContext(), BaseISA::setThreadContext(), system, BaseTLB::takeOverFrom(), Port::takeOverFrom(), ThreadContext::takeOverFrom(), taskId(), threadContexts, and ThreadContext::threadId().

Referenced by BaseKvmCPU::takeOverFrom(), MinorCPU::takeOverFrom(), AtomicSimpleCPU::takeOverFrom(), TimingSimpleCPU::takeOverFrom(), and FullO3CPU< O3CPUImpl >::takeOverFrom().

◆ taskId() [1/2]

uint32_t BaseCPU::taskId ( ) const

inline

Get cpu task id.

Definition at line 202 of file base.hh.

References _taskId.

Referenced by AtomicSimpleCPU::amoMem(), TimingSimpleCPU::fetch(), TimingSimpleCPU::htmSendAbortSignal(), TimingSimpleCPU::initiateHtmCmd(), TimingSimpleCPU::initiateMemAMO(), TimingSimpleCPU::initiateMemRead(), ArmISA::DumpStats::process(), AtomicSimpleCPU::readMem(), takeOverFrom(), AtomicSimpleCPU::tick(), AtomicSimpleCPU::writeMem(), and TimingSimpleCPU::writeMem().

◆ taskId() [2/2]

void BaseCPU::taskId ( uint32_t id )

inline

Set cpu task id.

Definition at line 204 of file base.hh.

References _taskId, and ArmISA::id.

◆ totalInsts()

virtual Counter BaseCPU::totalInsts ( ) const

pure virtual

Implemented in FullO3CPU< Impl >, BaseSimpleCPU, CheckerCPU, MinorCPU, BaseKvmCPU, Iris::BaseCPU, and TraceCPU.

Referenced by numSimulatedInsts(), and RiscvISA::ISA::readMiscReg().

◆ totalOps()

virtual Counter BaseCPU::totalOps ( ) const

pure virtual

Implemented in FullO3CPU< Impl >, BaseSimpleCPU, CheckerCPU, MinorCPU, BaseKvmCPU, Iris::BaseCPU, and TraceCPU.

Referenced by numSimulatedOps(), and CPUProgressEvent::process().

◆ traceFunctions()

void BaseCPU::traceFunctions ( Addr pc )

inline

Definition at line 557 of file base.hh.

References functionTracingEnabled, MipsISA::pc, and traceFunctionsInternal().

Referenced by BaseSimpleCPU::postExecute().

◆ traceFunctionsInternal()

void BaseCPU::traceFunctionsInternal ( Addr pc )

private

Definition at line 724 of file base.cc.

References ccprintf(), csprintf(), currentFunctionEnd, currentFunctionStart, curTick(), Loader::debugSymbolTable, Loader::SymbolTable::findNearest(), functionEntryTick, functionTraceStream, and MipsISA::pc.

Referenced by traceFunctions().

◆ unserialize()

void BaseCPU::unserialize ( CheckpointIn & cp )

override

Reconstruct the state of this object from a checkpoint.

Note: CPU models should normally overload the unserializeThread() method instead of the unserialize() method as this provides a uniform data format for all CPU models and promotes better code reuse.

Parameters

cp	The checkpoint use.

Definition at line 672 of file base.cc.

References _pid, _switchedOut, csprintf(), ArmISA::i, instCnt, interrupts, numThreads, UNSERIALIZE_SCALAR, and unserializeThread().

Referenced by MinorCPU::unserialize().

◆ unserializeThread()

virtual void BaseCPU::unserializeThread	(	CheckpointIn &	cp,
		ThreadID	tid
	)

inlinevirtual

Unserialize one thread.

Parameters

cp	The checkpoint use.
tid	ID of the current thread.

Reimplemented in FullO3CPU< Impl >, FullO3CPU< O3CPUImpl >, BaseSimpleCPU, MinorCPU, and BaseKvmCPU.

Definition at line 416 of file base.hh.

Referenced by unserialize().

◆ updateCycleCounters()

void BaseCPU::updateCycleCounters ( CPUState state )

inlineprotected

base method keeping track of cycle progression

Definition at line 517 of file base.hh.

References CPU_STATE_ON, CPU_STATE_SLEEP, CPU_STATE_WAKEUP, ProbePointArg< Arg >::notify(), ppActiveCycles, ppAllCycles, ppSleeping, previousCycle, and previousState.

Referenced by activateContext(), TimingSimpleCPU::completeDataAccess(), TimingSimpleCPU::completeIfetch(), TimingSimpleCPU::fetch(), BaseKvmCPU::haltContext(), BaseSimpleCPU::haltContext(), haltContext(), TimingSimpleCPU::sendFetch(), suspendContext(), TimingSimpleCPU::switchOut(), AtomicSimpleCPU::tick(), and TimingSimpleCPU::translationFault().

◆ verifyMemoryMode()

virtual void BaseCPU::verifyMemoryMode ( ) const

inlinevirtual

Verify that the system is in a memory mode supported by the CPU.

Implementations are expected to query the system for the current memory mode and ensure that it is what the CPU model expects. If the check fails, the implementation should terminate the simulation using fatal().

Reimplemented in FullO3CPU< Impl >, TimingSimpleCPU, AtomicSimpleCPU, BaseKvmCPU, and NonCachingSimpleCPU.

Definition at line 363 of file base.hh.

Referenced by init().

◆ waitForRemoteGDB()

bool BaseCPU::waitForRemoteGDB ( ) const

Definition at line 753 of file base.cc.

References params().

◆ wakeup() [1/2]

static void BaseCPU::wakeup ( ThreadID tid )

inlinestatic

Definition at line 48 of file cpu_dummy.hh.

Referenced by postInterrupt().

◆ wakeup() [2/2]

virtual void BaseCPU::wakeup ( ThreadID tid )

pure virtual

Implemented in BaseKvmCPU, TraceCPU, FullO3CPU< Impl >, FullO3CPU< O3CPUImpl >, CheckerCPU, MinorCPU, BaseSimpleCPU, and Iris::BaseCPU.

◆ workItemBegin()

void BaseCPU::workItemBegin ( )

inline

Definition at line 209 of file base.hh.

References numWorkItemsStarted.

Referenced by PseudoInst::workbegin().

◆ workItemEnd()

void BaseCPU::workItemEnd ( )

inline

Definition at line 210 of file base.hh.

References numWorkItemsCompleted.

Referenced by PseudoInst::workend().

Member Data Documentation

◆ _cacheLineSize

const unsigned int BaseCPU::_cacheLineSize

protected

Cache the cache line size that we get from the system.

Definition at line 146 of file base.hh.

Referenced by cacheLineSize().

◆ _cpuId

int BaseCPU::_cpuId

protected

Definition at line 116 of file base.hh.

Referenced by cpuId(), registerThreadContexts(), and takeOverFrom().

◆ _dataRequestorId

RequestorID BaseCPU::_dataRequestorId

protected

data side request id that must be placed in all requests

Definition at line 129 of file base.hh.

Referenced by dataRequestorId().

◆ _instRequestorId

RequestorID BaseCPU::_instRequestorId

protected

instruction side request id that must be placed in all requests

Definition at line 126 of file base.hh.

Referenced by instRequestorId().

◆ _pid

uint32_t BaseCPU::_pid

protected

The current OS process ID that is executing on this processor.

This is used to generate a taskId

Definition at line 140 of file base.hh.

Referenced by getPid(), serialize(), setPid(), takeOverFrom(), and unserialize().

◆ _socketId

const uint32_t BaseCPU::_socketId

protected

Each cpu will have a socket ID that corresponds to its physical location in the system.

This is usually used to bucket cpu cores under single DVFS domain. This information may also be required by the OS to identify the cpu core grouping (as in the case of ARM via MPIDR register)

Definition at line 123 of file base.hh.

Referenced by socketId().

◆ _switchedOut

bool BaseCPU::_switchedOut

protected

Is the CPU switched out or active?

Definition at line 143 of file base.hh.

Referenced by serialize(), startup(), switchedOut(), switchOut(), takeOverFrom(), and unserialize().

◆ _taskId

uint32_t BaseCPU::_taskId

protected

An intrenal representation of a task identifier within gem5.

This is used so the CPU can add which taskId (which is an internal representation of the OS process ID) to each request so components in the memory system can track which process IDs are ultimately interacting with them

Definition at line 136 of file base.hh.

Referenced by takeOverFrom(), and taskId().

◆ addressMonitor

std::vector<AddressMonitor> BaseCPU::addressMonitor

private

Definition at line 593 of file base.hh.

Referenced by armMonitor(), getCpuAddrMonitor(), mwait(), and mwaitAtomic().

◆ cpuList

vector< BaseCPU * > BaseCPU::cpuList

staticprivate

Static global cpu list.

Definition at line 554 of file base.hh.

Referenced by numSimulatedCPUs(), numSimulatedInsts(), and numSimulatedOps().

◆ currentFunctionEnd

Addr BaseCPU::currentFunctionEnd

private

Definition at line 548 of file base.hh.

Referenced by traceFunctionsInternal().

◆ currentFunctionStart

Addr BaseCPU::currentFunctionStart

private

Definition at line 547 of file base.hh.

Referenced by traceFunctionsInternal().

◆ enterPwrGatingEvent

EventFunctionWrapper BaseCPU::enterPwrGatingEvent

protected

Definition at line 615 of file base.hh.

Referenced by activateContext(), deschedulePowerGatingEvent(), schedulePowerGatingEvent(), and suspendContext().

◆ functionEntryTick

Tick BaseCPU::functionEntryTick

private

Definition at line 549 of file base.hh.

Referenced by traceFunctionsInternal().

◆ functionTraceStream

std::ostream* BaseCPU::functionTraceStream

private

Definition at line 546 of file base.hh.

Referenced by traceFunctionsInternal().

◆ functionTracingEnabled

bool BaseCPU::functionTracingEnabled

private

Definition at line 545 of file base.hh.

Referenced by enableFunctionTrace(), and traceFunctions().

◆ instCnt

Tick BaseCPU::instCnt

protected

Instruction count used for SPARC misc register.

Todo:: unify this with the counters that cpus individually keep

Definition at line 110 of file base.hh.

Referenced by TimingSimpleCPU::completeIfetch(), instCount(), serialize(), AtomicSimpleCPU::tick(), and unserialize().

◆ interrupts

std::vector<BaseInterrupts*> BaseCPU::interrupts

protected

Definition at line 215 of file base.hh.

Referenced by BaseSimpleCPU::checkForInterrupts(), checkInterrupts(), clearInterrupt(), clearInterrupts(), X86KvmCPU::deliverInterrupts(), getInterruptController(), BaseArmKvmCPU::kvmRun(), X86KvmCPU::kvmRun(), ArmKvmCPU::kvmRun(), postInterrupt(), registerThreadContexts(), serialize(), takeOverFrom(), and unserialize().

◆ invldPid

const uint32_t BaseCPU::invldPid = std::numeric_limits<uint32_t>::max()

static

Invalid or unknown Pid.

Possible when operating system is not present or has not assigned a pid yet

Definition at line 261 of file base.hh.

Referenced by ArmISA::FsLinux::startup().

◆ numCycles

Stats::Scalar BaseCPU::numCycles

Definition at line 588 of file base.hh.

Referenced by BaseKvmCPU::activateContext(), AtomicSimpleCPU::activateContext(), BaseKvmCPU::kvmRun(), Minor::MinorStats::regStats(), BaseSimpleCPU::regStats(), regStats(), TraceCPU::schedDcacheNext(), AtomicSimpleCPU::tick(), and TimingSimpleCPU::updateCycleCounts().

◆ numThreads

ThreadID BaseCPU::numThreads

Number of threads we're actually simulating (<= SMT_MAX_THREADS).

This is a constant for the duration of the simulation.

Definition at line 363 of file base.hh.

Referenced by AtomicSimpleCPU::activateContext(), TimingSimpleCPU::activateContext(), armMonitor(), BaseSimpleCPU::BaseSimpleCPU(), Minor::Execute::checkInterrupts(), Minor::Execute::drain(), Minor::Pipeline::drainResume(), MinorCPU::drainResume(), AtomicSimpleCPU::drainResume(), TimingSimpleCPU::drainResume(), Minor::Execute::drainResume(), Minor::Decode::evaluate(), Minor::Fetch2::evaluate(), Minor::Execute::evaluate(), Minor::Fetch1::evaluate(), getCpuAddrMonitor(), BaseKvmCPU::init(), init(), Minor::Execute::isDrained(), Minor::Fetch1::isDrained(), MinorCPU::MinorCPU(), mwait(), mwaitAtomic(), MinorCPU::randomPriority(), AtomicSimpleCPU::AtomicCPUDPort::recvAtomicSnoop(), AtomicSimpleCPU::AtomicCPUDPort::recvFunctionalSnoop(), TimingSimpleCPU::DcachePort::recvFunctionalSnoop(), TimingSimpleCPU::DcachePort::recvTimingSnoopReq(), Minor::LSQ::recvTimingSnoopReq(), registerThreadContexts(), Minor::MinorStats::regStats(), BaseSimpleCPU::regStats(), MinorCPU::roundRobinPriority(), serialize(), MinorCPU::startup(), AtomicSimpleCPU::suspendContext(), TimingSimpleCPU::suspendContext(), BaseSimpleCPU::swapActiveThread(), takeOverFrom(), TimingSimpleCPU::threadSnoop(), AtomicSimpleCPU::threadSnoop(), Minor::LSQ::threadSnoop(), AtomicSimpleCPU::tick(), unserialize(), MinorCPU::wakeup(), and Minor::Execute::~Execute().

◆ numWorkItemsCompleted

Stats::Scalar BaseCPU::numWorkItemsCompleted

Definition at line 590 of file base.hh.

Referenced by regStats(), and workItemEnd().

◆ numWorkItemsStarted

Stats::Scalar BaseCPU::numWorkItemsStarted

Definition at line 589 of file base.hh.

Referenced by regStats(), and workItemBegin().

◆ PCMask

const Addr BaseCPU::PCMask = ~((Addr)sizeof(TheISA::MachInst) - 1)

static

Definition at line 264 of file base.hh.

Referenced by Minor::Fetch2::evaluate(), DefaultFetch< Impl >::fetch(), DefaultFetch< Impl >::pipelineIcacheAccesses(), BaseSimpleCPU::preExecute(), and BaseSimpleCPU::setupFetchRequest().

◆ powerGatingOnIdle

const bool BaseCPU::powerGatingOnIdle

protected

Definition at line 614 of file base.hh.

Referenced by schedulePowerGatingEvent(), and suspendContext().

◆ ppActiveCycles

ProbePoints::PMUUPtr BaseCPU::ppActiveCycles

protected

CPU cycle counter, only counts if any thread contexts is active.

Definition at line 494 of file base.hh.

Referenced by regProbePoints(), and updateCycleCounters().

◆ ppAllCycles

ProbePoints::PMUUPtr BaseCPU::ppAllCycles

protected

CPU cycle counter even if any thread Context is suspended.

Definition at line 491 of file base.hh.

Referenced by regProbePoints(), and updateCycleCounters().

◆ ppRetiredBranches

ProbePoints::PMUUPtr BaseCPU::ppRetiredBranches

protected

Retired branches (any type)

Definition at line 488 of file base.hh.

Referenced by probeInstCommit(), and regProbePoints().

◆ ppRetiredInsts

ProbePoints::PMUUPtr BaseCPU::ppRetiredInsts

protected

Instruction commit probe point.

This probe point is triggered whenever one or more instructions are committed. It is normally triggered once for every instruction. However, CPU models committing bundles of instructions may call notify once for the entire bundle.

Definition at line 479 of file base.hh.

Referenced by probeInstCommit(), and regProbePoints().

◆ ppRetiredInstsPC

ProbePoints::PMUUPtr BaseCPU::ppRetiredInstsPC

protected

Definition at line 480 of file base.hh.

Referenced by probeInstCommit(), and regProbePoints().

◆ ppRetiredLoads

ProbePoints::PMUUPtr BaseCPU::ppRetiredLoads

protected

Retired load instructions.

Definition at line 483 of file base.hh.

Referenced by probeInstCommit(), and regProbePoints().

◆ ppRetiredStores

ProbePoints::PMUUPtr BaseCPU::ppRetiredStores

protected

Retired store instructions.

Definition at line 485 of file base.hh.

Referenced by probeInstCommit(), and regProbePoints().

◆ ppSleeping

ProbePointArg<bool>* BaseCPU::ppSleeping

protected

ProbePoint that signals transitions of threadContexts sets.

The ProbePoint reports information through it bool parameter.

If the parameter is true then the last enabled threadContext of the CPU object was disabled.
If the parameter is false then a threadContext was enabled, all the remaining threadContexts are disabled.

Definition at line 504 of file base.hh.

Referenced by regProbePoints(), and updateCycleCounters().

◆ previousCycle

Cycles BaseCPU::previousCycle

protected

Definition at line 513 of file base.hh.

Referenced by takeOverFrom(), and updateCycleCounters().

◆ previousState

CPUState BaseCPU::previousState

protected

Definition at line 514 of file base.hh.

Referenced by takeOverFrom(), and updateCycleCounters().

◆ pwrGatingLatency

const Cycles BaseCPU::pwrGatingLatency

protected

Definition at line 613 of file base.hh.

Referenced by schedulePowerGatingEvent(), and suspendContext().

◆ syscallRetryLatency

Cycles BaseCPU::syscallRetryLatency

Definition at line 607 of file base.hh.

Referenced by TimingSimpleCPU::advanceInst(), and AtomicSimpleCPU::tick().

◆ system

◆ threadContexts

std::vector<ThreadContext *> BaseCPU::threadContexts

protected

Definition at line 252 of file base.hh.

Referenced by activateContext(), BaseSimpleCPU::advancePC(), BaseSimpleCPU::BaseSimpleCPU(), BaseSimpleCPU::checkPcEventQueue(), FastModel::CortexA76::clockPeriodUpdated(), contextToThread(), Iris::CPU< CortexA76TC >::CPU(), AtomicSimpleCPU::drainResume(), TimingSimpleCPU::drainResume(), findContext(), flushTLBs(), getContext(), getCurrentInstCount(), BaseSimpleCPU::init(), Iris::BaseCPU::init(), init(), FastModel::CortexA76::initState(), MinorCPU::MinorCPU(), numContexts(), BaseSimpleCPU::postExecute(), postInterrupt(), registerThreadContexts(), regStats(), scheduleInstStop(), schedulePowerGatingEvent(), Iris::BaseCPU::serializeThread(), CheckerCPU::setSystem(), suspendContext(), BaseKvmCPU::takeOverFrom(), takeOverFrom(), AtomicSimpleCPU::tick(), Iris::BaseCPU::totalInsts(), Iris::BaseCPU::wakeup(), and Iris::BaseCPU::~BaseCPU().

◆ tracer

Trace::InstTracer* BaseCPU::tracer

protected

Definition at line 254 of file base.hh.

Referenced by getTracer(), and BaseSimpleCPU::preExecute().

The documentation for this class was generated from the following files:

arch/null/cpu_dummy.hh
cpu/base.hh
cpu/base.cc

Public Types

Public Member Functions

Static Public Member Functions

Public Attributes

Static Public Attributes

Protected Types

Protected Member Functions

Protected Attributes

Private Member Functions

Private Attributes

Static Private Attributes

PMU Probe points.

Detailed Description

Member Typedef Documentation

◆ Params

Member Enumeration Documentation

◆ CPUState

Constructor & Destructor Documentation

◆ BaseCPU()

◆ ~BaseCPU()

Member Function Documentation

◆ activateContext()

◆ armMonitor()

◆ cacheLineSize()

◆ checkInterrupts()

◆ clearInterrupt()

◆ clearInterrupts()

◆ contextToThread()

◆ cpuId()

◆ dataRequestorId()

◆ deschedulePowerGatingEvent()

◆ enableFunctionTrace()

◆ enterPwrGating()

◆ findContext()

◆ flushTLBs()

◆ getContext()

◆ getCpuAddrMonitor()

◆ getCurrentInstCount()

◆ getDataPort()

◆ getInstPort()

◆ getInterruptController()

◆ getPid()

◆ getPort()

◆ getSendFunctional()

◆ getTracer()

◆ haltContext()

◆ init()

◆ instCount()

◆ instRequestorId()

◆ mwait()

◆ mwaitAtomic()

◆ numContexts()

◆ numSimulatedCPUs()

◆ numSimulatedInsts() [1/2]

◆ numSimulatedInsts() [2/2]

◆ numSimulatedOps() [1/2]

◆ numSimulatedOps() [2/2]

◆ params()

◆ pmuProbePoint()

◆ postInterrupt()

◆ probeInstCommit()

◆ registerThreadContexts()

◆ regProbePoints()

◆ regStats()

◆ scheduleInstStop()

◆ schedulePowerGatingEvent()

◆ serialize()

◆ serializeThread()

◆ setPid()

◆ socketId()

◆ startup()

◆ suspendContext()

◆ switchedOut()

◆ switchOut()

◆ takeOverFrom()

◆ taskId() [1/2]

◆ taskId() [2/2]

◆ totalInsts()

◆ totalOps()

◆ traceFunctions()