FullO3CPU class, has each of the stages (fetch through commit) within it, as well as all of the time buffers between stages. More...

#include <cpu.hh>

Inheritance diagram for FullO3CPU< Impl >:

Public Types
enum	Status { Running, Idle, Halted, Blocked, SwitchedOut }

enum	StageIdx { FetchIdx, DecodeIdx, RenameIdx, IEWIdx, CommitIdx, NumStages }
	Enum to give each stage a specific index, so when calling activateStage() or deactivateStage(), they can specify which stage is being activated/deactivated. More...

typedef Impl::CPUPol	CPUPolicy

typedef Impl::DynInstPtr	DynInstPtr

typedef Impl::O3CPU	O3CPU

using	VecElem = TheISA::VecElem

using	VecRegContainer = TheISA::VecRegContainer

using	VecPredRegContainer = TheISA::VecPredRegContainer

typedef O3ThreadState< Impl >	ImplState

typedef O3ThreadState< Impl >	Thread

typedef std::list< DynInstPtr >::iterator	ListIt

using	LSQRequest = typename LSQ< Impl >::LSQRequest

typedef CPUPolicy::TimeStruct	TimeStruct
	Typedefs from the Impl to get the structs that each of the time buffers should use. More...

typedef CPUPolicy::FetchStruct	FetchStruct

typedef CPUPolicy::DecodeStruct	DecodeStruct

typedef CPUPolicy::RenameStruct	RenameStruct

typedef CPUPolicy::IEWStruct	IEWStruct

Public Types inherited from BaseCPU
typedef BaseCPUParams	Params

Public Member Functions
	FullO3CPU (DerivO3CPUParams *params)
	Constructs a CPU with the given parameters. More...

	~FullO3CPU ()
	Destructor. More...

void	regStats () override
	Registers statistics. More...

void	regProbePoints () override
	Register probe points. More...

void	demapPage (Addr vaddr, uint64_t asn)

void	demapInstPage (Addr vaddr, uint64_t asn)

void	demapDataPage (Addr vaddr, uint64_t asn)

void	tick ()
	Ticks CPU, calling tick() on each stage, and checking the overall activity to see if the CPU should deschedule itself. More...

void	init () override
	Initialize the CPU. More...

void	startup () override

int	numActiveThreads ()
	Returns the Number of Active Threads in the CPU. More...

void	activateThread (ThreadID tid)
	Add Thread to Active Threads List. More...

void	deactivateThread (ThreadID tid)
	Remove Thread from Active Threads List. More...

void	insertThread (ThreadID tid)
	Setup CPU to insert a thread's context. More...

void	removeThread (ThreadID tid)
	Remove all of a thread's context from CPU. More...

Counter	totalInsts () const override
	Count the Total Instructions Committed in the CPU. More...

Counter	totalOps () const override
	Count the Total Ops (including micro ops) committed in the CPU. More...

void	activateContext (ThreadID tid) override
	Add Thread to Active Threads List. More...

void	suspendContext (ThreadID tid) override
	Remove Thread from Active Threads List. More...

void	haltContext (ThreadID tid) override
	Remove Thread from Active Threads List && Remove Thread Context from CPU. More...

void	updateThreadPriority ()
	Update The Order In Which We Process Threads. More...

bool	isDraining () const
	Is the CPU draining? More...

void	serializeThread (CheckpointOut &cp, ThreadID tid) const override
	Serialize a single thread. More...

void	unserializeThread (CheckpointIn &cp, ThreadID tid) override
	Unserialize one thread. More...

void	addThreadToExitingList (ThreadID tid)
	Insert tid to the list of threads trying to exit. More...

bool	isThreadExiting (ThreadID tid) const
	Is the thread trying to exit? More...

void	scheduleThreadExitEvent (ThreadID tid)
	If a thread is trying to exit and its corresponding trap event has been completed, schedule an event to terminate the thread. More...

void	exitThreads ()
	Terminate all threads that are ready to exit. More...

void	syscall (ThreadID tid)
	Executes a syscall. More...

DrainState	drain () override
	Starts draining the CPU's pipeline of all instructions in order to stop all memory accesses. More...

void	drainResume () override
	Resumes execution after a drain. More...

void	commitDrained (ThreadID tid)
	Commit has reached a safe point to drain a thread. More...

void	switchOut () override
	Switches out this CPU. More...

void	takeOverFrom (BaseCPU *oldCPU) override
	Takes over from another CPU. More...

void	verifyMemoryMode () const override
	Verify that the system is in a memory mode supported by the CPU. More...

InstSeqNum	getAndIncrementInstSeq ()
	Get the current instruction sequence number, and increment it. More...

void	trap (const Fault &fault, ThreadID tid, const StaticInstPtr &inst)
	Traps to handle given fault. More...

void	setVectorsAsReady (ThreadID tid)
	Mark vector fields in scoreboard as ready right after switching vector mode, since software may read vectors at this time. More...

void	switchRenameMode (ThreadID tid, UnifiedFreeList *freelist)
	Check if a change in renaming is needed for vector registers. More...

Fault	getInterrupts ()
	Returns the Fault for any valid interrupt. More...

void	processInterrupts (const Fault &interrupt)
	Processes any an interrupt fault. More...

void	halt ()
	Halts the CPU. More...

RegVal	readMiscRegNoEffect (int misc_reg, ThreadID tid) const
	Register accessors. More...

RegVal	readMiscReg (int misc_reg, ThreadID tid)
	Reads a misc. More...

void	setMiscRegNoEffect (int misc_reg, RegVal val, ThreadID tid)
	Sets a miscellaneous register. More...

void	setMiscReg (int misc_reg, RegVal val, ThreadID tid)
	Sets a misc. More...

RegVal	readIntReg (PhysRegIdPtr phys_reg)

RegVal	readFloatReg (PhysRegIdPtr phys_reg)

const VecRegContainer &	readVecReg (PhysRegIdPtr reg_idx) const

VecRegContainer &	getWritableVecReg (PhysRegIdPtr reg_idx)
	Read physical vector register for modification. More...

Enums::VecRegRenameMode	vecRenameMode () const
	Returns current vector renaming mode. More...

void	vecRenameMode (Enums::VecRegRenameMode vec_mode)
	Sets the current vector renaming mode. More...

template<typename VecElem , int LaneIdx>
VecLaneT< VecElem, true >	readVecLane (PhysRegIdPtr phys_reg) const
	Read physical vector register lane. More...

template<typename VecElem >
VecLaneT< VecElem, true >	readVecLane (PhysRegIdPtr phys_reg) const
	Read physical vector register lane. More...

template<typename LD >
void	setVecLane (PhysRegIdPtr phys_reg, const LD &val)
	Write a lane of the destination vector register. More...

const VecElem &	readVecElem (PhysRegIdPtr reg_idx) const

const VecPredRegContainer &	readVecPredReg (PhysRegIdPtr reg_idx) const

VecPredRegContainer &	getWritableVecPredReg (PhysRegIdPtr reg_idx)

RegVal	readCCReg (PhysRegIdPtr phys_reg)

void	setIntReg (PhysRegIdPtr phys_reg, RegVal val)

void	setFloatReg (PhysRegIdPtr phys_reg, RegVal val)

void	setVecReg (PhysRegIdPtr reg_idx, const VecRegContainer &val)

void	setVecElem (PhysRegIdPtr reg_idx, const VecElem &val)

void	setVecPredReg (PhysRegIdPtr reg_idx, const VecPredRegContainer &val)

void	setCCReg (PhysRegIdPtr phys_reg, RegVal val)

RegVal	readArchIntReg (int reg_idx, ThreadID tid)

RegVal	readArchFloatReg (int reg_idx, ThreadID tid)

const VecRegContainer &	readArchVecReg (int reg_idx, ThreadID tid) const

VecRegContainer &	getWritableArchVecReg (int reg_idx, ThreadID tid)
	Read architectural vector register for modification. More...

template<typename VecElem >
VecLaneT< VecElem, true >	readArchVecLane (int reg_idx, int lId, ThreadID tid) const
	Read architectural vector register lane. More...

template<typename LD >
void	setArchVecLane (int reg_idx, int lId, ThreadID tid, const LD &val)
	Write a lane of the destination vector register. More...

const VecElem &	readArchVecElem (const RegIndex &reg_idx, const ElemIndex &ldx, ThreadID tid) const

const VecPredRegContainer &	readArchVecPredReg (int reg_idx, ThreadID tid) const

VecPredRegContainer &	getWritableArchVecPredReg (int reg_idx, ThreadID tid)

RegVal	readArchCCReg (int reg_idx, ThreadID tid)

void	setArchIntReg (int reg_idx, RegVal val, ThreadID tid)
	Architectural register accessors. More...

void	setArchFloatReg (int reg_idx, RegVal val, ThreadID tid)

void	setArchVecPredReg (int reg_idx, const VecPredRegContainer &val, ThreadID tid)

void	setArchVecReg (int reg_idx, const VecRegContainer &val, ThreadID tid)

void	setArchVecElem (const RegIndex &reg_idx, const ElemIndex &ldx, const VecElem &val, ThreadID tid)

void	setArchCCReg (int reg_idx, RegVal val, ThreadID tid)

void	pcState (const TheISA::PCState &newPCState, ThreadID tid)
	Sets the commit PC state of a specific thread. More...

TheISA::PCState	pcState (ThreadID tid)
	Reads the commit PC state of a specific thread. More...

Addr	instAddr (ThreadID tid)
	Reads the commit PC of a specific thread. More...

MicroPC	microPC (ThreadID tid)
	Reads the commit micro PC of a specific thread. More...

Addr	nextInstAddr (ThreadID tid)
	Reads the next PC of a specific thread. More...

void	squashFromTC (ThreadID tid)
	Initiates a squash of all in-flight instructions for a given thread. More...

ListIt	addInst (const DynInstPtr &inst)
	Function to add instruction onto the head of the list of the instructions. More...

void	instDone (ThreadID tid, const DynInstPtr &inst)
	Function to tell the CPU that an instruction has completed. More...

void	removeFrontInst (const DynInstPtr &inst)
	Remove an instruction from the front end of the list. More...

void	removeInstsNotInROB (ThreadID tid)
	Remove all instructions that are not currently in the ROB. More...

void	removeInstsUntil (const InstSeqNum &seq_num, ThreadID tid)
	Remove all instructions younger than the given sequence number. More...

void	squashInstIt (const ListIt &instIt, ThreadID tid)
	Removes the instruction pointed to by the iterator. More...

void	cleanUpRemovedInsts ()
	Cleans up all instructions on the remove list. More...

void	dumpInsts ()
	Debug function to print all instructions on the list. More...

void	activityThisCycle ()
	Records that there was time buffer activity this cycle. More...

void	activateStage (const StageIdx idx)
	Changes a stage's status to active within the activity recorder. More...

void	deactivateStage (const StageIdx idx)
	Changes a stage's status to inactive within the activity recorder. More...

void	wakeCPU ()
	Wakes the CPU, rescheduling the CPU if it's not already active. More...

virtual void	wakeup (ThreadID tid) override

ThreadID	getFreeTid ()
	Gets a free thread id. More...

ThreadContext *	tcBase (ThreadID tid)
	Returns a pointer to a thread context. More...

Fault	pushRequest (const DynInstPtr &inst, bool isLoad, uint8_t data, unsigned int size, Addr addr, Request::Flags flags, uint64_t res, AtomicOpFunctorPtr amo_op=nullptr, const std::vector< bool > &byte_enable=std::vector< bool >())
	CPU pushRequest function, forwards request to LSQ. More...

Fault	read (LSQRequest *req, int load_idx)
	CPU read function, forwards read to LSQ. More...

Fault	write (LSQRequest req, uint8_t data, int store_idx)
	CPU write function, forwards write to LSQ. More...

Port &	getInstPort () override
	Used by the fetch unit to get a hold of the instruction port. More...

Port &	getDataPort () override
	Get the dcache port (used to find block size for translations). More...

void	htmSendAbortSignal (ThreadID tid, uint64_t htm_uid, HtmFailureFaultCause cause)

Public Member Functions inherited from BaseO3CPU
	BaseO3CPU (BaseCPUParams *params)

void	regStats ()

Public Member Functions inherited from BaseCPU
virtual PortProxy::SendFunctionalFunc	getSendFunctional ()
	Returns a sendFunctional delegate for use with port proxies. More...

int	cpuId () const
	Reads this CPU's ID. More...

uint32_t	socketId () const
	Reads this CPU's Socket ID. More...

RequestorID	dataRequestorId () const
	Reads this CPU's unique data requestor ID. More...

RequestorID	instRequestorId () const
	Reads this CPU's unique instruction requestor ID. More...

Port &	getPort (const std::string &if_name, PortID idx=InvalidPortID) override
	Get a port on this CPU. More...

uint32_t	taskId () const
	Get cpu task id. More...

void	taskId (uint32_t id)
	Set cpu task id. More...

uint32_t	getPid () const

void	setPid (uint32_t pid)

void	workItemBegin ()

void	workItemEnd ()

Tick	instCount ()

BaseInterrupts *	getInterruptController (ThreadID tid)

void	postInterrupt (ThreadID tid, int int_num, int index)

void	clearInterrupt (ThreadID tid, int int_num, int index)

void	clearInterrupts (ThreadID tid)

bool	checkInterrupts (ThreadID tid) const

Trace::InstTracer *	getTracer ()
	Provide access to the tracer pointer. More...

int	findContext (ThreadContext *tc)
	Given a Thread Context pointer return the thread num. More...

virtual ThreadContext *	getContext (int tn)
	Given a thread num get tho thread context for it. More...

unsigned	numContexts ()
	Get the number of thread contexts available. More...

ThreadID	contextToThread (ContextID cid)
	Convert ContextID to threadID. More...

const Params *	params () const

	BaseCPU (Params *params, bool is_checker=false)

virtual	~BaseCPU ()

void	init () override

void	startup () override

void	regStats () override

void	regProbePoints () override

void	registerThreadContexts ()

void	deschedulePowerGatingEvent ()

void	schedulePowerGatingEvent ()

void	flushTLBs ()
	Flush all TLBs in the CPU. More...

bool	switchedOut () const
	Determine if the CPU is switched out. More...

unsigned int	cacheLineSize () const
	Get the cache line size of the system. More...

void	serialize (CheckpointOut &cp) const override
	Serialize this object to the given output stream. More...

void	unserialize (CheckpointIn &cp) override
	Reconstruct the state of this object from a checkpoint. More...

void	scheduleInstStop (ThreadID tid, Counter insts, const char *cause)
	Schedule an event that exits the simulation loops after a predefined number of instructions. More...

uint64_t	getCurrentInstCount (ThreadID tid)
	Get the number of instructions executed by the specified thread on this CPU. More...

void	traceFunctions (Addr pc)

void	armMonitor (ThreadID tid, Addr address)

bool	mwait (ThreadID tid, PacketPtr pkt)

void	mwaitAtomic (ThreadID tid, ThreadContext tc, BaseTLB dtb)

AddressMonitor *	getCpuAddrMonitor (ThreadID tid)

bool	waitForRemoteGDB () const

virtual void	probeInstCommit (const StaticInstPtr &inst, Addr pc)
	Helper method to trigger PMU probes for a committed instruction. More...

Public Attributes
BaseTLB *	itb

BaseTLB *	dtb

Status	_status
	Overall CPU status. More...

ProbePointArg< PacketPtr > *	ppInstAccessComplete

ProbePointArg< std::pair< DynInstPtr, PacketPtr > > *	ppDataAccessComplete

int	instcount
	Count of total number of dynamic instructions in flight. More...

std::list< DynInstPtr >	instList
	List of all the instructions in flight. More...

std::queue< ListIt >	removeList
	List of all the instructions that will be removed at the end of this cycle. More...

bool	removeInstsThisCycle
	Records if instructions need to be removed this cycle due to being retired or squashed. More...

TimeBuffer< TimeStruct >	timeBuffer
	The main time buffer to do backwards communication. More...

TimeBuffer< FetchStruct >	fetchQueue
	The fetch stage's instruction queue. More...

TimeBuffer< DecodeStruct >	decodeQueue
	The decode stage's instruction queue. More...

TimeBuffer< RenameStruct >	renameQueue
	The rename stage's instruction queue. More...

TimeBuffer< IEWStruct >	iewQueue
	The IEW stage's instruction queue. More...

InstSeqNum	globalSeqNum
	The global sequence number counter. More...

Checker< Impl > *	checker
	Pointer to the checker, which can dynamically verify instruction results at run time. More...

System *	system
	Pointer to the system. More...

std::vector< Thread * >	thread
	Pointers to all of the threads in the CPU. More...

std::list< int >	cpuWaitList
	Threads Scheduled to Enter CPU. More...

Cycles	lastRunningCycle
	The cycle that the CPU was last running, used for statistics. More...

Tick	lastActivatedCycle
	The cycle that the CPU was last activated by a new thread. More...

std::map< ThreadID, unsigned >	threadMap
	Mapping for system thread id to cpu id. More...

std::vector< ThreadID >	tids
	Available thread ids in the cpu. More...

Stats::Scalar	timesIdled
	Stat for total number of times the CPU is descheduled. More...

Stats::Scalar	idleCycles
	Stat for total number of cycles the CPU spends descheduled. More...

Stats::Scalar	quiesceCycles
	Stat for total number of cycles the CPU spends descheduled due to a quiesce operation or waiting for an interrupt. More...

Stats::Vector	committedInsts
	Stat for the number of committed instructions per thread. More...

Stats::Vector	committedOps
	Stat for the number of committed ops (including micro ops) per thread. More...

Stats::Formula	cpi
	Stat for the CPI per thread. More...

Stats::Formula	totalCpi
	Stat for the total CPI. More...

Stats::Formula	ipc
	Stat for the IPC per thread. More...

Stats::Formula	totalIpc
	Stat for the total IPC. More...

Stats::Scalar	intRegfileReads

Stats::Scalar	intRegfileWrites

Stats::Scalar	fpRegfileReads

Stats::Scalar	fpRegfileWrites

Stats::Scalar	vecRegfileReads

Stats::Scalar	vecRegfileWrites

Stats::Scalar	vecPredRegfileReads

Stats::Scalar	vecPredRegfileWrites

Stats::Scalar	ccRegfileReads

Stats::Scalar	ccRegfileWrites

Stats::Scalar	miscRegfileReads

Stats::Scalar	miscRegfileWrites

Public Attributes inherited from BaseCPU
ThreadID	numThreads
	Number of threads we're actually simulating (<= SMT_MAX_THREADS). More...

System *	system

Stats::Scalar	numCycles

Stats::Scalar	numWorkItemsStarted

Stats::Scalar	numWorkItemsCompleted

Cycles	syscallRetryLatency

Protected Attributes
CPUPolicy::Fetch	fetch
	The fetch stage. More...

CPUPolicy::Decode	decode
	The decode stage. More...

CPUPolicy::Rename	rename
	The dispatch stage. More...

CPUPolicy::IEW	iew
	The issue/execute/writeback stages. More...

CPUPolicy::Commit	commit
	The commit stage. More...

Enums::VecRegRenameMode	vecMode
	The rename mode of the vector registers. More...

PhysRegFile	regFile
	The register file. More...

CPUPolicy::FreeList	freeList
	The free list. More...

CPUPolicy::RenameMap	renameMap [Impl::MaxThreads]
	The rename map. More...

CPUPolicy::RenameMap	commitRenameMap [Impl::MaxThreads]
	The commit rename map. More...

CPUPolicy::ROB	rob
	The re-order buffer. More...

std::list< ThreadID >	activeThreads
	Active Threads List. More...

std::unordered_map< ThreadID, bool >	exitingThreads
	This is a list of threads that are trying to exit. More...

Scoreboard	scoreboard
	Integer Register Scoreboard. More...

std::vector< TheISA::ISA * >	isa

Protected Attributes inherited from BaseCPU
Tick	instCnt
	Instruction count used for SPARC misc register. More...

int	_cpuId

const uint32_t	_socketId
	Each cpu will have a socket ID that corresponds to its physical location in the system. More...

RequestorID	_instRequestorId
	instruction side request id that must be placed in all requests More...

RequestorID	_dataRequestorId
	data side request id that must be placed in all requests More...

uint32_t	_taskId
	An intrenal representation of a task identifier within gem5. More...

uint32_t	_pid
	The current OS process ID that is executing on this processor. More...

bool	_switchedOut
	Is the CPU switched out or active? More...

const unsigned int	_cacheLineSize
	Cache the cache line size that we get from the system. More...

std::vector< BaseInterrupts * >	interrupts

std::vector< ThreadContext * >	threadContexts

Trace::InstTracer *	tracer

Cycles	previousCycle

CPUState	previousState

const Cycles	pwrGatingLatency

const bool	powerGatingOnIdle

EventFunctionWrapper	enterPwrGatingEvent

ProbePoints::PMUUPtr	ppRetiredInsts
	Instruction commit probe point. More...

ProbePoints::PMUUPtr	ppRetiredInstsPC

ProbePoints::PMUUPtr	ppRetiredLoads
	Retired load instructions. More...

ProbePoints::PMUUPtr	ppRetiredStores
	Retired store instructions. More...

ProbePoints::PMUUPtr	ppRetiredBranches
	Retired branches (any type) More...

ProbePoints::PMUUPtr	ppAllCycles
	CPU cycle counter even if any thread Context is suspended. More...

ProbePoints::PMUUPtr	ppActiveCycles
	CPU cycle counter, only counts if any thread contexts is active. More...

ProbePointArg< bool > *	ppSleeping
	ProbePoint that signals transitions of threadContexts sets. More...

Private Member Functions
void	scheduleTickEvent (Cycles delay)
	Schedule tick event, regardless of its current state. More...

void	unscheduleTickEvent ()
	Unschedule tick event, regardless of its current state. More...

bool	tryDrain ()
	Check if the pipeline has drained and signal drain done. More...

void	drainSanityCheck () const
	Perform sanity checks after a drain. More...

bool	isCpuDrained () const
	Check if a system is in a drained state. More...

Private Attributes
EventFunctionWrapper	tickEvent
	The tick event used for scheduling CPU ticks. More...

EventFunctionWrapper	threadExitEvent
	The exit event used for terminating all ready-to-exit threads. More...

ActivityRecorder	activityRec
	The activity recorder; used to tell if the CPU has any activity remaining or if it can go to idle and deschedule itself. More...

Friends
class	O3ThreadContext< Impl >

Additional Inherited Members
Static Public Member Functions inherited from BaseCPU
static int	numSimulatedInsts ()

static int	numSimulatedOps ()

static void	wakeup (ThreadID tid)

static int	numSimulatedCPUs ()

static Counter	numSimulatedInsts ()

static Counter	numSimulatedOps ()

Static Public Attributes inherited from BaseCPU
static const uint32_t	invldPid = std::numeric_limits<uint32_t>::max()
	Invalid or unknown Pid. More...

static const Addr	PCMask = ~((Addr)sizeof(TheISA::MachInst) - 1)

Protected Types inherited from BaseCPU
enum	CPUState { CPU_STATE_ON, CPU_STATE_SLEEP, CPU_STATE_WAKEUP }

Protected Member Functions inherited from BaseCPU
void	updateCycleCounters (CPUState state)
	base method keeping track of cycle progression More...

void	enterPwrGating ()

ProbePoints::PMUUPtr	pmuProbePoint (const char *name)
	Helper method to instantiate probe points belonging to this object. More...

Detailed Description

template<class Impl>
class FullO3CPU< Impl >

FullO3CPU class, has each of the stages (fetch through commit) within it, as well as all of the time buffers between stages.

The tick() function for the CPU is defined here.

Definition at line 93 of file cpu.hh.

Member Typedef Documentation

◆ CPUPolicy

template<class Impl >

typedef Impl::CPUPol FullO3CPU< Impl >::CPUPolicy

Definition at line 97 of file cpu.hh.

◆ DecodeStruct

template<class Impl >

typedef CPUPolicy::DecodeStruct FullO3CPU< Impl >::DecodeStruct

Definition at line 628 of file cpu.hh.

◆ DynInstPtr

template<class Impl >

typedef Impl::DynInstPtr FullO3CPU< Impl >::DynInstPtr

Definition at line 98 of file cpu.hh.

◆ FetchStruct

template<class Impl >

typedef CPUPolicy::FetchStruct FullO3CPU< Impl >::FetchStruct

Definition at line 626 of file cpu.hh.

◆ IEWStruct

template<class Impl >

typedef CPUPolicy::IEWStruct FullO3CPU< Impl >::IEWStruct

Definition at line 632 of file cpu.hh.

◆ ImplState

template<class Impl >

typedef O3ThreadState<Impl> FullO3CPU< Impl >::ImplState

Definition at line 106 of file cpu.hh.

◆ ListIt

template<class Impl >

typedef std::list<DynInstPtr>::iterator FullO3CPU< Impl >::ListIt

Definition at line 109 of file cpu.hh.

◆ LSQRequest

template<class Impl >

using FullO3CPU< Impl >::LSQRequest = typename LSQ<Impl>::LSQRequest

Definition at line 124 of file cpu.hh.

◆ O3CPU

template<class Impl >

typedef Impl::O3CPU FullO3CPU< Impl >::O3CPU

Definition at line 99 of file cpu.hh.

◆ RenameStruct

template<class Impl >

typedef CPUPolicy::RenameStruct FullO3CPU< Impl >::RenameStruct

Definition at line 630 of file cpu.hh.

◆ Thread

template<class Impl >

typedef O3ThreadState<Impl> FullO3CPU< Impl >::Thread

Definition at line 107 of file cpu.hh.

◆ TimeStruct

template<class Impl >

typedef CPUPolicy::TimeStruct FullO3CPU< Impl >::TimeStruct

Typedefs from the Impl to get the structs that each of the time buffers should use.

Definition at line 624 of file cpu.hh.

◆ VecElem

template<class Impl >

using FullO3CPU< Impl >::VecElem = TheISA::VecElem

Definition at line 101 of file cpu.hh.

◆ VecPredRegContainer

template<class Impl >

using FullO3CPU< Impl >::VecPredRegContainer = TheISA::VecPredRegContainer

Definition at line 104 of file cpu.hh.

◆ VecRegContainer

template<class Impl >

using FullO3CPU< Impl >::VecRegContainer = TheISA::VecRegContainer

Definition at line 102 of file cpu.hh.

Member Enumeration Documentation

◆ StageIdx

template<class Impl >

enum FullO3CPU::StageIdx

Enum to give each stage a specific index, so when calling activateStage() or deactivateStage(), they can specify which stage is being activated/deactivated.

Enumerator
FetchIdx
DecodeIdx
RenameIdx
IEWIdx
CommitIdx
NumStages

Definition at line 613 of file cpu.hh.

◆ Status

template<class Impl >

enum FullO3CPU::Status

Enumerator
Running
Idle
Halted
Blocked
SwitchedOut

Definition at line 114 of file cpu.hh.

Constructor & Destructor Documentation

◆ FullO3CPU()

template<class Impl >

FullO3CPU< Impl >::FullO3CPU ( DerivO3CPUParams * params )

Constructs a CPU with the given parameters.

Definition at line 82 of file cpu.cc.

◆ ~FullO3CPU()

template<class Impl >

FullO3CPU< Impl >::~FullO3CPU

Destructor.

Definition at line 360 of file cpu.cc.

Member Function Documentation

◆ activateContext()

template<class Impl >

void FullO3CPU< Impl >::activateContext ( ThreadID tid )

overridevirtual

Add Thread to Active Threads List.

Reimplemented from BaseCPU.

Definition at line 671 of file cpu.cc.

◆ activateStage()

template<class Impl >

void FullO3CPU< Impl >::activateStage ( const StageIdx idx )

inline

Changes a stage's status to active within the activity recorder.

Definition at line 661 of file cpu.hh.

◆ activateThread()

template<class Impl >

void FullO3CPU< Impl >::activateThread ( ThreadID tid )

Add Thread to Active Threads List.

Definition at line 602 of file cpu.cc.

◆ activityThisCycle()

template<class Impl >

void FullO3CPU< Impl >::activityThisCycle ( )

inline

Records that there was time buffer activity this cycle.

Definition at line 658 of file cpu.hh.

◆ addInst()

template<class Impl >

FullO3CPU< Impl >::ListIt FullO3CPU< Impl >::addInst ( const DynInstPtr & inst )

Function to add instruction onto the head of the list of the instructions.

Used when new instructions are fetched.

Definition at line 1501 of file cpu.cc.

◆ addThreadToExitingList()

template<class Impl >

void FullO3CPU< Impl >::addThreadToExitingList ( ThreadID tid )

Insert tid to the list of threads trying to exit.

Definition at line 1760 of file cpu.cc.

◆ cleanUpRemovedInsts()

template<class Impl >

void FullO3CPU< Impl >::cleanUpRemovedInsts

Cleans up all instructions on the remove list.

Definition at line 1640 of file cpu.cc.

◆ commitDrained()

template<class Impl >

void FullO3CPU< Impl >::commitDrained ( ThreadID tid )

Commit has reached a safe point to drain a thread.

Commit calls this method to inform the pipeline that it has reached a point where it is not executed microcode and is about to squash uncommitted instructions to fully drain the pipeline.

Definition at line 1081 of file cpu.cc.

◆ deactivateStage()

template<class Impl >

void FullO3CPU< Impl >::deactivateStage ( const StageIdx idx )

inline

Changes a stage's status to inactive within the activity recorder.

Definition at line 665 of file cpu.hh.

◆ deactivateThread()

template<class Impl >

void FullO3CPU< Impl >::deactivateThread ( ThreadID tid )

Remove Thread from Active Threads List.

Definition at line 620 of file cpu.cc.

◆ demapDataPage()

template<class Impl >

void FullO3CPU< Impl >::demapDataPage	(	Addr	vaddr,
		uint64_t	asn
	)

inline

Definition at line 206 of file cpu.hh.

◆ demapInstPage()

template<class Impl >

void FullO3CPU< Impl >::demapInstPage	(	Addr	vaddr,
		uint64_t	asn
	)

inline

Definition at line 201 of file cpu.hh.

◆ demapPage()

template<class Impl >

void FullO3CPU< Impl >::demapPage	(	Addr	vaddr,
		uint64_t	asn
	)

inline

Definition at line 195 of file cpu.hh.

◆ drain()

template<class Impl >

DrainState FullO3CPU< Impl >::drain

override

Starts draining the CPU's pipeline of all instructions in order to stop all memory accesses.

Definition at line 951 of file cpu.cc.

◆ drainResume()

template<class Impl >

void FullO3CPU< Impl >::drainResume

override

Resumes execution after a drain.

Definition at line 1088 of file cpu.cc.

◆ drainSanityCheck()

template<class Impl >

void FullO3CPU< Impl >::drainSanityCheck

private

Perform sanity checks after a drain.

This method is called from drain() when it has determined that the CPU is fully drained when gem5 is compiled with the NDEBUG macro undefined. The intention of this method is to do more extensive tests than the isDrained() method to weed out any draining bugs.

Definition at line 1030 of file cpu.cc.

◆ dumpInsts()

template<class Impl >

void FullO3CPU< Impl >::dumpInsts

Debug function to print all instructions on the list.

Definition at line 1666 of file cpu.cc.

◆ exitThreads()

template<class Impl >

void FullO3CPU< Impl >::exitThreads

Terminate all threads that are ready to exit.

Definition at line 1808 of file cpu.cc.

◆ getAndIncrementInstSeq()

template<class Impl >

InstSeqNum FullO3CPU< Impl >::getAndIncrementInstSeq ( )

inline

Get the current instruction sequence number, and increment it.

Definition at line 309 of file cpu.hh.

◆ getDataPort()

template<class Impl >

Port& FullO3CPU< Impl >::getDataPort ( )

inlineoverridevirtual

Get the dcache port (used to find block size for translations).

Implements BaseCPU.

Definition at line 747 of file cpu.hh.

◆ getFreeTid()

template<class Impl >

ThreadID FullO3CPU< Impl >::getFreeTid

Gets a free thread id.

Use if thread ids change across system.

Definition at line 1729 of file cpu.cc.

◆ getInstPort()

template<class Impl >

Port& FullO3CPU< Impl >::getInstPort ( )

inlineoverridevirtual

Used by the fetch unit to get a hold of the instruction port.

Implements BaseCPU.

Definition at line 740 of file cpu.hh.

◆ getInterrupts()

template<class Impl >

Fault FullO3CPU< Impl >::getInterrupts

Returns the Fault for any valid interrupt.

Definition at line 883 of file cpu.cc.

◆ getWritableArchVecPredReg()

template<class Impl >

auto FullO3CPU< Impl >::getWritableArchVecPredReg	(	int	reg_idx,
		ThreadID	tid
	)

Definition at line 1374 of file cpu.cc.

◆ getWritableArchVecReg()

template<class Impl >

auto FullO3CPU< Impl >::getWritableArchVecReg	(	int	reg_idx,
		ThreadID	tid
	)

Read architectural vector register for modification.

Definition at line 1344 of file cpu.cc.

◆ getWritableVecPredReg()

template<class Impl >

auto FullO3CPU< Impl >::getWritableVecPredReg ( PhysRegIdPtr reg_idx )

Definition at line 1246 of file cpu.cc.

◆ getWritableVecReg()

template<class Impl >

auto FullO3CPU< Impl >::getWritableVecReg ( PhysRegIdPtr reg_idx )

Read physical vector register for modification.

Definition at line 1220 of file cpu.cc.

◆ halt()

template<class Impl >

void FullO3CPU< Impl >::halt ( )

inline

Halts the CPU.

Definition at line 336 of file cpu.hh.

◆ haltContext()

template<class Impl >

void FullO3CPU< Impl >::haltContext ( ThreadID tid )

overridevirtual

Remove Thread from Active Threads List && Remove Thread Context from CPU.

Reimplemented from BaseCPU.

Definition at line 731 of file cpu.cc.

◆ htmSendAbortSignal()

template<class Impl >

void FullO3CPU< Impl >::htmSendAbortSignal	(	ThreadID	tid,
		uint64_t	htm_uid,
		HtmFailureFaultCause	cause
	)

Definition at line 1832 of file cpu.cc.

◆ init()

template<class Impl >

void FullO3CPU< Impl >::init

override

Initialize the CPU.

Definition at line 568 of file cpu.cc.

◆ insertThread()

template<class Impl >

void FullO3CPU< Impl >::insertThread ( ThreadID tid )

Setup CPU to insert a thread's context.

Definition at line 745 of file cpu.cc.

◆ instAddr()

template<class Impl >

Addr FullO3CPU< Impl >::instAddr ( ThreadID tid )

Reads the commit PC of a specific thread.

Definition at line 1472 of file cpu.cc.

◆ instDone()

template<class Impl >

void FullO3CPU< Impl >::instDone	(	ThreadID	tid,
		const DynInstPtr &	inst
	)

Function to tell the CPU that an instruction has completed.

Definition at line 1510 of file cpu.cc.

◆ isCpuDrained()

template<class Impl >

bool FullO3CPU< Impl >::isCpuDrained

private

Check if a system is in a drained state.

Definition at line 1042 of file cpu.cc.

◆ isDraining()

template<class Impl >

bool FullO3CPU< Impl >::isDraining ( ) const

inline

Is the CPU draining?

Definition at line 258 of file cpu.hh.

◆ isThreadExiting()

template<class Impl >

bool FullO3CPU< Impl >::isThreadExiting ( ThreadID tid ) const

Is the thread trying to exit?

Definition at line 1780 of file cpu.cc.

◆ microPC()

template<class Impl >

MicroPC FullO3CPU< Impl >::microPC ( ThreadID tid )

Reads the commit micro PC of a specific thread.

Definition at line 1486 of file cpu.cc.

◆ nextInstAddr()

template<class Impl >

Addr FullO3CPU< Impl >::nextInstAddr ( ThreadID tid )

Reads the next PC of a specific thread.

Definition at line 1479 of file cpu.cc.

◆ numActiveThreads()

template<class Impl >

int FullO3CPU< Impl >::numActiveThreads ( )

inline

Returns the Number of Active Threads in the CPU.

Definition at line 222 of file cpu.hh.

◆ pcState() [1/2]

template<class Impl >

void FullO3CPU< Impl >::pcState	(	const TheISA::PCState &	newPCState,
		ThreadID	tid
	)

Sets the commit PC state of a specific thread.

Definition at line 1465 of file cpu.cc.

◆ pcState() [2/2]

template<class Impl >

TheISA::PCState FullO3CPU< Impl >::pcState ( ThreadID tid )

Reads the commit PC state of a specific thread.

Definition at line 1458 of file cpu.cc.

◆ processInterrupts()

template<class Impl >

void FullO3CPU< Impl >::processInterrupts ( const Fault & interrupt )

Processes any an interrupt fault.

Definition at line 891 of file cpu.cc.

◆ pushRequest()

template<class Impl >

Fault FullO3CPU< Impl >::pushRequest	(	const DynInstPtr &	inst,
		bool	isLoad,
		uint8_t *	data,
		unsigned int	size,
		Addr	addr,
		Request::Flags	flags,
		uint64_t *	res,
		AtomicOpFunctorPtr	amo_op = `nullptr`,
		const std::vector< bool > &	byte_enable = `std::vector<bool>()`
	)

inline

CPU pushRequest function, forwards request to LSQ.

Definition at line 715 of file cpu.hh.

◆ read()

template<class Impl >

Fault FullO3CPU< Impl >::read	(	LSQRequest *	req,
		int	load_idx
	)

inline

CPU read function, forwards read to LSQ.

Definition at line 727 of file cpu.hh.

◆ readArchCCReg()

template<class Impl >

RegVal FullO3CPU< Impl >::readArchCCReg	(	int	reg_idx,
		ThreadID	tid
	)

Definition at line 1384 of file cpu.cc.

◆ readArchFloatReg()

template<class Impl >

RegVal FullO3CPU< Impl >::readArchFloatReg	(	int	reg_idx,
		ThreadID	tid
	)

Definition at line 1323 of file cpu.cc.

◆ readArchIntReg()

template<class Impl >

RegVal FullO3CPU< Impl >::readArchIntReg	(	int	reg_idx,
		ThreadID	tid
	)

Definition at line 1312 of file cpu.cc.

◆ readArchVecElem()

template<class Impl >

auto FullO3CPU< Impl >::readArchVecElem	(	const RegIndex &	reg_idx,
		const ElemIndex &	ldx,
		ThreadID	tid
	)		const

Definition at line 1354 of file cpu.cc.

◆ readArchVecLane()

template<class Impl >

template<typename VecElem >

VecLaneT<VecElem, true> FullO3CPU< Impl >::readArchVecLane	(	int	reg_idx,
		int	lId,
		ThreadID	tid
	)		const

inline

Read architectural vector register lane.

Definition at line 436 of file cpu.hh.

◆ readArchVecPredReg()

template<class Impl >

auto FullO3CPU< Impl >::readArchVecPredReg	(	int	reg_idx,
		ThreadID	tid
	)		const

Definition at line 1364 of file cpu.cc.

◆ readArchVecReg()

template<class Impl >

auto FullO3CPU< Impl >::readArchVecReg	(	int	reg_idx,
		ThreadID	tid
	)		const

Definition at line 1334 of file cpu.cc.

◆ readCCReg()

template<class Impl >

RegVal FullO3CPU< Impl >::readCCReg ( PhysRegIdPtr phys_reg )

Definition at line 1255 of file cpu.cc.

◆ readFloatReg()

template<class Impl >

RegVal FullO3CPU< Impl >::readFloatReg ( PhysRegIdPtr phys_reg )

Definition at line 1203 of file cpu.cc.

◆ readIntReg()

template<class Impl >

RegVal FullO3CPU< Impl >::readIntReg ( PhysRegIdPtr phys_reg )

Definition at line 1195 of file cpu.cc.

◆ readMiscReg()

template<class Impl >

RegVal FullO3CPU< Impl >::readMiscReg	(	int	misc_reg,
		ThreadID	tid
	)

Reads a misc.

register, including any side effects the read might have as defined by the architecture.

Definition at line 1172 of file cpu.cc.

◆ readMiscRegNoEffect()

template<class Impl >

RegVal FullO3CPU< Impl >::readMiscRegNoEffect	(	int	misc_reg,
		ThreadID	tid
	)		const

Register accessors.

Index refers to the physical register index. Reads a miscellaneous register.

Definition at line 1165 of file cpu.cc.

◆ readVecElem()

template<class Impl >

auto FullO3CPU< Impl >::readVecElem ( PhysRegIdPtr reg_idx ) const

Definition at line 1229 of file cpu.cc.

◆ readVecLane() [1/2]

template<class Impl >

template<typename VecElem , int LaneIdx>

VecLaneT<VecElem, true> FullO3CPU< Impl >::readVecLane ( PhysRegIdPtr phys_reg ) const

inline

Read physical vector register lane.

Definition at line 379 of file cpu.hh.

◆ readVecLane() [2/2]

template<class Impl >

template<typename VecElem >

VecLaneT<VecElem, true> FullO3CPU< Impl >::readVecLane ( PhysRegIdPtr phys_reg ) const

inline

Read physical vector register lane.

Definition at line 390 of file cpu.hh.

◆ readVecPredReg()

template<class Impl >

auto FullO3CPU< Impl >::readVecPredReg ( PhysRegIdPtr reg_idx ) const

Definition at line 1237 of file cpu.cc.

◆ readVecReg()

template<class Impl >

auto FullO3CPU< Impl >::readVecReg ( PhysRegIdPtr reg_idx ) const

Definition at line 1211 of file cpu.cc.

◆ regProbePoints()

template<class Impl >

void FullO3CPU< Impl >::regProbePoints

override

Register probe points.

Definition at line 366 of file cpu.cc.

◆ regStats()

template<class Impl >

void FullO3CPU< Impl >::regStats

override

Registers statistics.

Definition at line 381 of file cpu.cc.

◆ removeFrontInst()

template<class Impl >

void FullO3CPU< Impl >::removeFrontInst ( const DynInstPtr & inst )

Remove an instruction from the front end of the list.

There's no restriction on location of the instruction.

Definition at line 1531 of file cpu.cc.

◆ removeInstsNotInROB()

template<class Impl >

void FullO3CPU< Impl >::removeInstsNotInROB ( ThreadID tid )

Remove all instructions that are not currently in the ROB.

There's also an option to not squash delay slot instructions.

Definition at line 1545 of file cpu.cc.

◆ removeInstsUntil()

template<class Impl >

void FullO3CPU< Impl >::removeInstsUntil	(	const InstSeqNum &	seq_num,
		ThreadID	tid
	)

Remove all instructions younger than the given sequence number.

Definition at line 1590 of file cpu.cc.

◆ removeThread()

template<class Impl >

void FullO3CPU< Impl >::removeThread ( ThreadID tid )

Remove all of a thread's context from CPU.

Definition at line 797 of file cpu.cc.

◆ scheduleThreadExitEvent()

template<class Impl >

void FullO3CPU< Impl >::scheduleThreadExitEvent ( ThreadID tid )

If a thread is trying to exit and its corresponding trap event has been completed, schedule an event to terminate the thread.

Definition at line 1787 of file cpu.cc.

◆ scheduleTickEvent()

template<class Impl >

void FullO3CPU< Impl >::scheduleTickEvent ( Cycles delay )

inlineprivate

Schedule tick event, regardless of its current state.

Definition at line 138 of file cpu.hh.

◆ serializeThread()

template<class Impl >

void FullO3CPU< Impl >::serializeThread	(	CheckpointOut &	cp,
		ThreadID	tid
	)		const

overridevirtual

Serialize a single thread.

Parameters

cp	The stream to serialize to.
tid	ID of the current thread.

Reimplemented from BaseCPU.

Definition at line 937 of file cpu.cc.

◆ setArchCCReg()

template<class Impl >

void FullO3CPU< Impl >::setArchCCReg	(	int	reg_idx,
		RegVal	val,
		ThreadID	tid
	)

Definition at line 1447 of file cpu.cc.

◆ setArchFloatReg()

template<class Impl >

void FullO3CPU< Impl >::setArchFloatReg	(	int	reg_idx,
		RegVal	val,
		ThreadID	tid
	)

Definition at line 1406 of file cpu.cc.

◆ setArchIntReg()

template<class Impl >

void FullO3CPU< Impl >::setArchIntReg	(	int	reg_idx,
		RegVal	val,
		ThreadID	tid
	)

Architectural register accessors.

Looks up in the commit rename table to obtain the true physical index of the architected register first, then accesses that physical register.

Definition at line 1395 of file cpu.cc.

◆ setArchVecElem()

template<class Impl >

void FullO3CPU< Impl >::setArchVecElem	(	const RegIndex &	reg_idx,
		const ElemIndex &	ldx,
		const VecElem &	val,
		ThreadID	tid
	)

Definition at line 1427 of file cpu.cc.

◆ setArchVecLane()

template<class Impl >

template<typename LD >

void FullO3CPU< Impl >::setArchVecLane	(	int	reg_idx,
		int	lId,
		ThreadID	tid,
		const LD &	val
	)

inline

Write a lane of the destination vector register.

Definition at line 447 of file cpu.hh.

◆ setArchVecPredReg()

template<class Impl >

void FullO3CPU< Impl >::setArchVecPredReg	(	int	reg_idx,
		const VecPredRegContainer &	val,
		ThreadID	tid
	)

Definition at line 1437 of file cpu.cc.

◆ setArchVecReg()

template<class Impl >

void FullO3CPU< Impl >::setArchVecReg	(	int	reg_idx,
		const VecRegContainer &	val,
		ThreadID	tid
	)

Definition at line 1417 of file cpu.cc.

◆ setCCReg()

template<class Impl >

void FullO3CPU< Impl >::setCCReg	(	PhysRegIdPtr	phys_reg,
		RegVal	val
	)

Definition at line 1304 of file cpu.cc.

◆ setFloatReg()

template<class Impl >

void FullO3CPU< Impl >::setFloatReg	(	PhysRegIdPtr	phys_reg,
		RegVal	val
	)

Definition at line 1271 of file cpu.cc.

◆ setIntReg()

template<class Impl >

void FullO3CPU< Impl >::setIntReg	(	PhysRegIdPtr	phys_reg,
		RegVal	val
	)

Definition at line 1263 of file cpu.cc.

◆ setMiscReg()

template<class Impl >

void FullO3CPU< Impl >::setMiscReg	(	int	misc_reg,
		RegVal	val,
		ThreadID	tid
	)

Sets a misc.

register, including any side effects the write might have as defined by the architecture.

Definition at line 1187 of file cpu.cc.

◆ setMiscRegNoEffect()

template<class Impl >

void FullO3CPU< Impl >::setMiscRegNoEffect	(	int	misc_reg,
		RegVal	val,
		ThreadID	tid
	)

Sets a miscellaneous register.

Definition at line 1180 of file cpu.cc.

◆ setVecElem()

template<class Impl >

void FullO3CPU< Impl >::setVecElem	(	PhysRegIdPtr	reg_idx,
		const VecElem &	val
	)

Definition at line 1287 of file cpu.cc.

◆ setVecLane()

template<class Impl >

template<typename LD >

void FullO3CPU< Impl >::setVecLane	(	PhysRegIdPtr	phys_reg,
		const LD &	val
	)

inline

Write a lane of the destination vector register.

Definition at line 399 of file cpu.hh.

Referenced by FullO3CPU< O3CPUImpl >::setArchVecLane().

◆ setVecPredReg()

template<class Impl >

void FullO3CPU< Impl >::setVecPredReg	(	PhysRegIdPtr	reg_idx,
		const VecPredRegContainer &	val
	)

Definition at line 1295 of file cpu.cc.

◆ setVecReg()

template<class Impl >

void FullO3CPU< Impl >::setVecReg	(	PhysRegIdPtr	reg_idx,
		const VecRegContainer &	val
	)

Definition at line 1279 of file cpu.cc.

◆ setVectorsAsReady()

template<class Impl >

void FullO3CPU< Impl >::setVectorsAsReady ( ThreadID tid )

Mark vector fields in scoreboard as ready right after switching vector mode, since software may read vectors at this time.

Definition at line 841 of file cpu.cc.

◆ squashFromTC()

template<class Impl >

void FullO3CPU< Impl >::squashFromTC ( ThreadID tid )

Initiates a squash of all in-flight instructions for a given thread.

The source of the squash is an external update of state through the TC.

Definition at line 1493 of file cpu.cc.

◆ squashInstIt()

template<class Impl >

void FullO3CPU< Impl >::squashInstIt	(	const ListIt &	instIt,
		ThreadID	tid
	)

inline

Removes the instruction pointed to by the iterator.

Definition at line 1619 of file cpu.cc.

◆ startup()

template<class Impl >

void FullO3CPU< Impl >::startup

override

Definition at line 589 of file cpu.cc.

◆ suspendContext()

template<class Impl >

void FullO3CPU< Impl >::suspendContext ( ThreadID tid )

overridevirtual

Remove Thread from Active Threads List.

Reimplemented from BaseCPU.

Definition at line 710 of file cpu.cc.

◆ switchOut()

template<class Impl >

void FullO3CPU< Impl >::switchOut

overridevirtual

Switches out this CPU.

Reimplemented from BaseCPU.

Definition at line 1118 of file cpu.cc.

◆ switchRenameMode()

template<class Impl >

void FullO3CPU< Impl >::switchRenameMode	(	ThreadID	tid,
		UnifiedFreeList *	freelist
	)

Check if a change in renaming is needed for vector registers.

The vecMode variable is updated and propagated to rename maps.

Parameters

tid	ThreadID
freelist	list of free registers

Definition at line 863 of file cpu.cc.

◆ syscall()

template<class Impl >

void FullO3CPU< Impl >::syscall ( ThreadID tid )

Executes a syscall.

Todo:: : Determine if this needs to be virtual.

Definition at line 917 of file cpu.cc.

◆ takeOverFrom()

template<class Impl >

void FullO3CPU< Impl >::takeOverFrom ( BaseCPU * oldCPU )

overridevirtual

Takes over from another CPU.

Reimplemented from BaseCPU.

Definition at line 1133 of file cpu.cc.

◆ tcBase()

template<class Impl >

ThreadContext* FullO3CPU< Impl >::tcBase ( ThreadID tid )

inline

Returns a pointer to a thread context.

Definition at line 679 of file cpu.hh.

◆ tick()

template<class Impl >

void FullO3CPU< Impl >::tick

Ticks CPU, calling tick() on each stage, and checking the overall activity to see if the CPU should deschedule itself.

Definition at line 509 of file cpu.cc.

Referenced by FullO3CPU< O3CPUImpl >::FullO3CPU().

◆ totalInsts()

template<class Impl >

Counter FullO3CPU< Impl >::totalInsts

overridevirtual

Count the Total Instructions Committed in the CPU.

Implements BaseCPU.

Definition at line 645 of file cpu.cc.

◆ totalOps()

template<class Impl >

Counter FullO3CPU< Impl >::totalOps

overridevirtual

Count the Total Ops (including micro ops) committed in the CPU.

Implements BaseCPU.

Definition at line 658 of file cpu.cc.

◆ trap()

template<class Impl >

void FullO3CPU< Impl >::trap	(	const Fault &	fault,
		ThreadID	tid,
		const StaticInstPtr &	inst
	)

Traps to handle given fault.

Definition at line 908 of file cpu.cc.

◆ tryDrain()

template<class Impl >

bool FullO3CPU< Impl >::tryDrain

private

Check if the pipeline has drained and signal drain done.

This method checks if a drain has been requested and if the CPU has drained successfully (i.e., there are no instructions in the pipeline). If the CPU has drained, it deschedules the tick event and signals the drain manager.

Returns: False if a drain hasn't been requested or the CPU hasn't drained, true otherwise.

Definition at line 1014 of file cpu.cc.

◆ unscheduleTickEvent()

template<class Impl >

void FullO3CPU< Impl >::unscheduleTickEvent ( )

inlineprivate

Unschedule tick event, regardless of its current state.

Definition at line 147 of file cpu.hh.

◆ unserializeThread()

template<class Impl >

void FullO3CPU< Impl >::unserializeThread	(	CheckpointIn &	cp,
		ThreadID	tid
	)

overridevirtual

Unserialize one thread.

Parameters

cp	The checkpoint use.
tid	ID of the current thread.

Reimplemented from BaseCPU.

Definition at line 944 of file cpu.cc.

◆ updateThreadPriority()

template<class Impl >

void FullO3CPU< Impl >::updateThreadPriority

Update The Order In Which We Process Threads.

Definition at line 1743 of file cpu.cc.

◆ vecRenameMode() [1/2]

template<class Impl >

Enums::VecRegRenameMode FullO3CPU< Impl >::vecRenameMode ( ) const

inline

Returns current vector renaming mode.

Definition at line 368 of file cpu.hh.

◆ vecRenameMode() [2/2]

template<class Impl >

void FullO3CPU< Impl >::vecRenameMode ( Enums::VecRegRenameMode vec_mode )

inline

Sets the current vector renaming mode.

Definition at line 371 of file cpu.hh.

◆ verifyMemoryMode()

template<class Impl >

void FullO3CPU< Impl >::verifyMemoryMode

overridevirtual

Verify that the system is in a memory mode supported by the CPU.

Implementations are expected to query the system for the current memory mode and ensure that it is what the CPU model expects. If the check fails, the implementation should terminate the simulation using fatal().

Reimplemented from BaseCPU.

Definition at line 1155 of file cpu.cc.

◆ wakeCPU()

template<class Impl >

void FullO3CPU< Impl >::wakeCPU

Wakes the CPU, rescheduling the CPU if it's not already active.

Definition at line 1694 of file cpu.cc.

◆ wakeup()

template<class Impl >

void FullO3CPU< Impl >::wakeup ( ThreadID tid )

overridevirtual

Implements BaseCPU.

Definition at line 1716 of file cpu.cc.

◆ write()

template<class Impl >

Fault FullO3CPU< Impl >::write	(	LSQRequest *	req,
		uint8_t *	data,
		int	store_idx
	)

inline

CPU write function, forwards write to LSQ.

Definition at line 733 of file cpu.hh.

Friends And Related Function Documentation

◆ O3ThreadContext< Impl >

template<class Impl >

friend class O3ThreadContext< Impl >

friend

Definition at line 111 of file cpu.hh.

Member Data Documentation

◆ _status

template<class Impl >

Status FullO3CPU< Impl >::_status

Overall CPU status.

Definition at line 127 of file cpu.hh.

◆ activeThreads

template<class Impl >

std::list<ThreadID> FullO3CPU< Impl >::activeThreads

protected

Active Threads List.

Definition at line 594 of file cpu.hh.

Referenced by FullO3CPU< O3CPUImpl >::numActiveThreads().

◆ activityRec

template<class Impl >

ActivityRecorder FullO3CPU< Impl >::activityRec

private

The activity recorder; used to tell if the CPU has any activity remaining or if it can go to idle and deschedule itself.

Definition at line 654 of file cpu.hh.

Referenced by FullO3CPU< O3CPUImpl >::activateStage(), FullO3CPU< O3CPUImpl >::activityThisCycle(), and FullO3CPU< O3CPUImpl >::deactivateStage().

◆ ccRegfileReads

template<class Impl >

Stats::Scalar FullO3CPU< Impl >::ccRegfileReads

Definition at line 785 of file cpu.hh.

◆ ccRegfileWrites

template<class Impl >

Stats::Scalar FullO3CPU< Impl >::ccRegfileWrites

Definition at line 786 of file cpu.hh.

◆ checker

template<class Impl >

Checker<Impl>* FullO3CPU< Impl >::checker

Pointer to the checker, which can dynamically verify instruction results at run time.

This can be set to NULL if it is not being used.

Definition at line 691 of file cpu.hh.

◆ commit

template<class Impl >

CPUPolicy::Commit FullO3CPU< Impl >::commit

protected

The commit stage.

Definition at line 573 of file cpu.hh.

◆ commitRenameMap

template<class Impl >

CPUPolicy::RenameMap FullO3CPU< Impl >::commitRenameMap[Impl::MaxThreads]

protected

The commit rename map.

Definition at line 588 of file cpu.hh.

Referenced by FullO3CPU< O3CPUImpl >::readArchVecLane(), and FullO3CPU< O3CPUImpl >::setArchVecLane().

◆ committedInsts

template<class Impl >

Stats::Vector FullO3CPU< Impl >::committedInsts

Stat for the number of committed instructions per thread.

Definition at line 760 of file cpu.hh.

◆ committedOps

template<class Impl >

Stats::Vector FullO3CPU< Impl >::committedOps

Stat for the number of committed ops (including micro ops) per thread.

Definition at line 762 of file cpu.hh.

◆ cpi

template<class Impl >

Stats::Formula FullO3CPU< Impl >::cpi

Stat for the CPI per thread.

Definition at line 764 of file cpu.hh.

◆ cpuWaitList

template<class Impl >

std::list<int> FullO3CPU< Impl >::cpuWaitList

Threads Scheduled to Enter CPU.

Definition at line 700 of file cpu.hh.

◆ decode

template<class Impl >

CPUPolicy::Decode FullO3CPU< Impl >::decode

protected

The decode stage.

Definition at line 564 of file cpu.hh.

◆ decodeQueue

template<class Impl >

TimeBuffer<DecodeStruct> FullO3CPU< Impl >::decodeQueue

The decode stage's instruction queue.

Definition at line 641 of file cpu.hh.

◆ dtb

template<class Impl >

BaseTLB* FullO3CPU< Impl >::dtb

Definition at line 123 of file cpu.hh.

◆ exitingThreads

template<class Impl >

std::unordered_map<ThreadID, bool> FullO3CPU< Impl >::exitingThreads

protected

This is a list of threads that are trying to exit.

Each thread id is mapped to a boolean value denoting whether the thread is ready to exit.

Definition at line 601 of file cpu.hh.

◆ fetch

template<class Impl >

CPUPolicy::Fetch FullO3CPU< Impl >::fetch

protected

The fetch stage.

Definition at line 561 of file cpu.hh.

◆ fetchQueue

template<class Impl >

TimeBuffer<FetchStruct> FullO3CPU< Impl >::fetchQueue

The fetch stage's instruction queue.

Definition at line 638 of file cpu.hh.

◆ fpRegfileReads

template<class Impl >

Stats::Scalar FullO3CPU< Impl >::fpRegfileReads

Definition at line 776 of file cpu.hh.

◆ fpRegfileWrites

template<class Impl >

Stats::Scalar FullO3CPU< Impl >::fpRegfileWrites

Definition at line 777 of file cpu.hh.

◆ freeList

template<class Impl >

CPUPolicy::FreeList FullO3CPU< Impl >::freeList

protected

The free list.

Definition at line 582 of file cpu.hh.

◆ globalSeqNum

template<class Impl >

InstSeqNum FullO3CPU< Impl >::globalSeqNum

The global sequence number counter.

Definition at line 685 of file cpu.hh.

Referenced by FullO3CPU< O3CPUImpl >::getAndIncrementInstSeq(), and FullO3CPU< O3CPUImpl >::takeOverFrom().

◆ idleCycles

template<class Impl >

Stats::Scalar FullO3CPU< Impl >::idleCycles

Stat for total number of cycles the CPU spends descheduled.

Definition at line 755 of file cpu.hh.

◆ iew

template<class Impl >

CPUPolicy::IEW FullO3CPU< Impl >::iew

protected

The issue/execute/writeback stages.

Definition at line 570 of file cpu.hh.

Referenced by FullO3CPU< O3CPUImpl >::pushRequest().

◆ iewQueue

template<class Impl >

TimeBuffer<IEWStruct> FullO3CPU< Impl >::iewQueue

The IEW stage's instruction queue.

Definition at line 647 of file cpu.hh.

◆ instcount

template<class Impl >

int FullO3CPU< Impl >::instcount

Count of total number of dynamic instructions in flight.

Definition at line 536 of file cpu.hh.

◆ instList

template<class Impl >

std::list<DynInstPtr> FullO3CPU< Impl >::instList

List of all the instructions in flight.

Definition at line 540 of file cpu.hh.

◆ intRegfileReads

template<class Impl >

Stats::Scalar FullO3CPU< Impl >::intRegfileReads

Definition at line 773 of file cpu.hh.

◆ intRegfileWrites

template<class Impl >

Stats::Scalar FullO3CPU< Impl >::intRegfileWrites

Definition at line 774 of file cpu.hh.

◆ ipc

template<class Impl >

Stats::Formula FullO3CPU< Impl >::ipc

Stat for the IPC per thread.

Definition at line 768 of file cpu.hh.

◆ isa

template<class Impl >

std::vector<TheISA::ISA *> FullO3CPU< Impl >::isa

protected

Definition at line 606 of file cpu.hh.

◆ itb

template<class Impl >

BaseTLB* FullO3CPU< Impl >::itb

Definition at line 122 of file cpu.hh.

◆ lastActivatedCycle

template<class Impl >

Tick FullO3CPU< Impl >::lastActivatedCycle

The cycle that the CPU was last activated by a new thread.

Definition at line 706 of file cpu.hh.

◆ lastRunningCycle

template<class Impl >

Cycles FullO3CPU< Impl >::lastRunningCycle

The cycle that the CPU was last running, used for statistics.

Definition at line 703 of file cpu.hh.

◆ miscRegfileReads

template<class Impl >

Stats::Scalar FullO3CPU< Impl >::miscRegfileReads

Definition at line 788 of file cpu.hh.

◆ miscRegfileWrites

template<class Impl >

Stats::Scalar FullO3CPU< Impl >::miscRegfileWrites

Definition at line 789 of file cpu.hh.

◆ ppDataAccessComplete

template<class Impl >

ProbePointArg<std::pair<DynInstPtr, PacketPtr> >* FullO3CPU< Impl >::ppDataAccessComplete

Definition at line 190 of file cpu.hh.

◆ ppInstAccessComplete

template<class Impl >

ProbePointArg<PacketPtr>* FullO3CPU< Impl >::ppInstAccessComplete

Definition at line 189 of file cpu.hh.

◆ quiesceCycles

template<class Impl >

Stats::Scalar FullO3CPU< Impl >::quiesceCycles

Stat for total number of cycles the CPU spends descheduled due to a quiesce operation or waiting for an interrupt.

Definition at line 758 of file cpu.hh.

◆ regFile

template<class Impl >

PhysRegFile FullO3CPU< Impl >::regFile

protected

The register file.

Definition at line 579 of file cpu.hh.

Referenced by FullO3CPU< O3CPUImpl >::readVecLane(), and FullO3CPU< O3CPUImpl >::setVecLane().

◆ removeInstsThisCycle

template<class Impl >

bool FullO3CPU< Impl >::removeInstsThisCycle

Records if instructions need to be removed this cycle due to being retired or squashed.

Definition at line 557 of file cpu.hh.

◆ removeList

template<class Impl >

std::queue<ListIt> FullO3CPU< Impl >::removeList

List of all the instructions that will be removed at the end of this cycle.

Definition at line 545 of file cpu.hh.

◆ rename

template<class Impl >

CPUPolicy::Rename FullO3CPU< Impl >::rename

protected

The dispatch stage.

Definition at line 567 of file cpu.hh.

◆ renameMap

template<class Impl >

CPUPolicy::RenameMap FullO3CPU< Impl >::renameMap[Impl::MaxThreads]

protected

The rename map.

Definition at line 585 of file cpu.hh.

◆ renameQueue

template<class Impl >

TimeBuffer<RenameStruct> FullO3CPU< Impl >::renameQueue

The rename stage's instruction queue.

Definition at line 644 of file cpu.hh.

◆ rob

template<class Impl >

CPUPolicy::ROB FullO3CPU< Impl >::rob

protected

The re-order buffer.

Definition at line 591 of file cpu.hh.

◆ scoreboard

template<class Impl >

Scoreboard FullO3CPU< Impl >::scoreboard

protected

Integer Register Scoreboard.

Definition at line 604 of file cpu.hh.

◆ system

template<class Impl >

System* FullO3CPU< Impl >::system

Pointer to the system.

Definition at line 694 of file cpu.hh.

◆ thread

template<class Impl >

std::vector<Thread *> FullO3CPU< Impl >::thread

Pointers to all of the threads in the CPU.

Definition at line 697 of file cpu.hh.

Referenced by FullO3CPU< O3CPUImpl >::tcBase().

◆ threadExitEvent

template<class Impl >

EventFunctionWrapper FullO3CPU< Impl >::threadExitEvent

private

The exit event used for terminating all ready-to-exit threads.

Definition at line 135 of file cpu.hh.

◆ threadMap

template<class Impl >

std::map<ThreadID, unsigned> FullO3CPU< Impl >::threadMap

Mapping for system thread id to cpu id.

Definition at line 709 of file cpu.hh.

◆ tickEvent

template<class Impl >

EventFunctionWrapper FullO3CPU< Impl >::tickEvent

private

The tick event used for scheduling CPU ticks.

Definition at line 132 of file cpu.hh.

Referenced by FullO3CPU< O3CPUImpl >::scheduleTickEvent(), and FullO3CPU< O3CPUImpl >::unscheduleTickEvent().

◆ tids

template<class Impl >

std::vector<ThreadID> FullO3CPU< Impl >::tids

Available thread ids in the cpu.

Definition at line 712 of file cpu.hh.

◆ timeBuffer

template<class Impl >

TimeBuffer<TimeStruct> FullO3CPU< Impl >::timeBuffer

The main time buffer to do backwards communication.

Definition at line 635 of file cpu.hh.

◆ timesIdled

template<class Impl >

Stats::Scalar FullO3CPU< Impl >::timesIdled

Stat for total number of times the CPU is descheduled.

Definition at line 753 of file cpu.hh.

◆ totalCpi

template<class Impl >

Stats::Formula FullO3CPU< Impl >::totalCpi

Stat for the total CPI.

Definition at line 766 of file cpu.hh.

◆ totalIpc

template<class Impl >

Stats::Formula FullO3CPU< Impl >::totalIpc

Stat for the total IPC.

Definition at line 770 of file cpu.hh.

◆ vecMode

template<class Impl >

Enums::VecRegRenameMode FullO3CPU< Impl >::vecMode

protected

The rename mode of the vector registers.

Definition at line 576 of file cpu.hh.

Referenced by FullO3CPU< O3CPUImpl >::vecRenameMode().

◆ vecPredRegfileReads

template<class Impl >

Stats::Scalar FullO3CPU< Impl >::vecPredRegfileReads

mutable

Definition at line 782 of file cpu.hh.

◆ vecPredRegfileWrites

template<class Impl >

Stats::Scalar FullO3CPU< Impl >::vecPredRegfileWrites

Definition at line 783 of file cpu.hh.

◆ vecRegfileReads

template<class Impl >

Stats::Scalar FullO3CPU< Impl >::vecRegfileReads

mutable

Definition at line 779 of file cpu.hh.

Referenced by FullO3CPU< O3CPUImpl >::readVecLane().

◆ vecRegfileWrites

template<class Impl >

Stats::Scalar FullO3CPU< Impl >::vecRegfileWrites

Definition at line 780 of file cpu.hh.

Referenced by FullO3CPU< O3CPUImpl >::setVecLane().

The documentation for this class was generated from the following files:

cpu/o3/cpu.hh
cpu/o3/cpu.cc

Public Types

Public Member Functions

Public Attributes

Protected Attributes

Private Member Functions

Private Attributes

Friends

Additional Inherited Members

Detailed Description

template<class Impl> class FullO3CPU< Impl >

Member Typedef Documentation

◆ CPUPolicy

◆ DecodeStruct

◆ DynInstPtr

◆ FetchStruct

◆ IEWStruct

◆ ImplState

◆ ListIt

◆ LSQRequest

◆ O3CPU

◆ RenameStruct

◆ Thread

◆ TimeStruct

◆ VecElem

◆ VecPredRegContainer

◆ VecRegContainer

Member Enumeration Documentation

◆ StageIdx

◆ Status

Constructor & Destructor Documentation

◆ FullO3CPU()

◆ ~FullO3CPU()

Member Function Documentation

◆ activateContext()

◆ activateStage()

◆ activateThread()

◆ activityThisCycle()

◆ addInst()

◆ addThreadToExitingList()

◆ cleanUpRemovedInsts()

◆ commitDrained()

◆ deactivateStage()

◆ deactivateThread()

◆ demapDataPage()

◆ demapInstPage()

◆ demapPage()

◆ drain()

◆ drainResume()

◆ drainSanityCheck()

◆ dumpInsts()

◆ exitThreads()

◆ getAndIncrementInstSeq()

◆ getDataPort()

◆ getFreeTid()

◆ getInstPort()

◆ getInterrupts()

◆ getWritableArchVecPredReg()

◆ getWritableArchVecReg()

◆ getWritableVecPredReg()

◆ getWritableVecReg()

◆ halt()

◆ haltContext()

◆ htmSendAbortSignal()

◆ init()

◆ insertThread()

◆ instAddr()

◆ instDone()

◆ isCpuDrained()

◆ isDraining()

◆ isThreadExiting()

◆ microPC()

◆ nextInstAddr()

◆ numActiveThreads()

◆ pcState() [1/2]

◆ pcState() [2/2]

◆ processInterrupts()

◆ pushRequest()

◆ read()

◆ readArchCCReg()

◆ readArchFloatReg()

template<class Impl>
class FullO3CPU< Impl >