| _cacheLineSize | BaseCPU | protected |
| _cpuId | BaseCPU | protected |
| _dataRequestorId | BaseCPU | protected |
| _instRequestorId | BaseCPU | protected |
| _pid | BaseCPU | protected |
| _socketId | BaseCPU | protected |
| _switchedOut | BaseCPU | protected |
| _taskId | BaseCPU | protected |
| activateContext(ThreadID thread_num) | BaseCPU | virtual |
| addressMonitor | BaseCPU | private |
| armMonitor(ThreadID tid, Addr address) | BaseCPU | |
| BaseCPU(BaseCPUParams *params, sc_core::sc_module *_evs) | Iris::BaseCPU | |
| BaseCPU::BaseCPU(Params *params, bool is_checker=false) | BaseCPU | |
| cacheLineSize() const | BaseCPU | inline |
| checkInterrupts(ThreadID tid) const | BaseCPU | inline |
| clearInterrupt(ThreadID tid, int int_num, int index) | BaseCPU | inline |
| clearInterrupts(ThreadID tid) | BaseCPU | inline |
| clockEvent | Iris::BaseCPU | private |
| clockPeriodUpdated() override | Iris::BaseCPU | inlineprotected |
| contextToThread(ContextID cid) | BaseCPU | inline |
| CPU(IrisBaseCPUParams *params, iris::IrisConnectionInterface *iris_if) | Iris::CPU< TC > | inline |
| CPU_STATE_ON enum value | BaseCPU | protected |
| CPU_STATE_SLEEP enum value | BaseCPU | protected |
| CPU_STATE_WAKEUP enum value | BaseCPU | protected |
| cpuId() const | BaseCPU | inline |
| cpuList | BaseCPU | privatestatic |
| CPUState enum name | BaseCPU | protected |
| currentFunctionEnd | BaseCPU | private |
| currentFunctionStart | BaseCPU | private |
| dataRequestorId() const | BaseCPU | inline |
| deschedulePowerGatingEvent() | BaseCPU | |
| enableFunctionTrace() | BaseCPU | private |
| enterPwrGating() | BaseCPU | protected |
| enterPwrGatingEvent | BaseCPU | protected |
| evs | Iris::BaseCPU | protected |
| findContext(ThreadContext *tc) | BaseCPU | |
| flushTLBs() | BaseCPU | |
| functionEntryTick | BaseCPU | private |
| functionTraceStream | BaseCPU | private |
| functionTracingEnabled | BaseCPU | private |
| getContext(int tn) | BaseCPU | inlinevirtual |
| getCpuAddrMonitor(ThreadID tid) | BaseCPU | inline |
| getCurrentInstCount(ThreadID tid) | BaseCPU | |
| getDataPort() override | Iris::BaseCPU | inlinevirtual |
| getInstPort() override | Iris::BaseCPU | inlinevirtual |
| getInterruptController(ThreadID tid) | BaseCPU | inline |
| getPid() const | BaseCPU | inline |
| getPort(const std::string &if_name, PortID idx=InvalidPortID) override | BaseCPU | |
| getSendFunctional() override | Iris::BaseCPU | inlinevirtual |
| getTracer() | BaseCPU | inline |
| haltContext(ThreadID thread_num) | BaseCPU | virtual |
| init() override | Iris::BaseCPU | protected |
| instCnt | BaseCPU | protected |
| instCount() | BaseCPU | inline |
| instRequestorId() const | BaseCPU | inline |
| interrupts | BaseCPU | protected |
| invldPid | BaseCPU | static |
| mwait(ThreadID tid, PacketPtr pkt) | BaseCPU | |
| mwaitAtomic(ThreadID tid, ThreadContext *tc, BaseTLB *dtb) | BaseCPU | |
| numContexts() | BaseCPU | inline |
| numCycles | BaseCPU | |
| numSimulatedCPUs() | BaseCPU | inlinestatic |
| numSimulatedInsts() | BaseCPU | inlinestatic |
| numSimulatedInsts() | BaseCPU | inlinestatic |
| numSimulatedOps() | BaseCPU | inlinestatic |
| numSimulatedOps() | BaseCPU | inlinestatic |
| numThreads | BaseCPU | |
| numWorkItemsCompleted | BaseCPU | |
| numWorkItemsStarted | BaseCPU | |
| Params typedef | BaseCPU | |
| params() const | BaseCPU | inline |
| PCMask | BaseCPU | static |
| periodAttribute | Iris::BaseCPU | private |
| pmuProbePoint(const char *name) | BaseCPU | protected |
| postInterrupt(ThreadID tid, int int_num, int index) | BaseCPU | |
| powerGatingOnIdle | BaseCPU | protected |
| ppActiveCycles | BaseCPU | protected |
| ppAllCycles | BaseCPU | protected |
| ppRetiredBranches | BaseCPU | protected |
| ppRetiredInsts | BaseCPU | protected |
| ppRetiredInstsPC | BaseCPU | protected |
| ppRetiredLoads | BaseCPU | protected |
| ppRetiredStores | BaseCPU | protected |
| ppSleeping | BaseCPU | protected |
| previousCycle | BaseCPU | protected |
| previousState | BaseCPU | protected |
| probeInstCommit(const StaticInstPtr &inst, Addr pc) | BaseCPU | virtual |
| pwrGatingLatency | BaseCPU | protected |
| registerThreadContexts() | BaseCPU | |
| regProbePoints() override | BaseCPU | |
| regStats() override | BaseCPU | |
| scheduleInstStop(ThreadID tid, Counter insts, const char *cause) | BaseCPU | |
| schedulePowerGatingEvent() | BaseCPU | |
| sendFunctional | Iris::BaseCPU | private |
| serialize(CheckpointOut &cp) const override | BaseCPU | |
| serializeThread(CheckpointOut &cp, ThreadID tid) const override | Iris::BaseCPU | protectedvirtual |
| setPid(uint32_t pid) | BaseCPU | inline |
| socketId() const | BaseCPU | inline |
| startup() override | BaseCPU | |
| suspendContext(ThreadID thread_num) | BaseCPU | virtual |
| switchedOut() const | BaseCPU | inline |
| switchOut() | BaseCPU | virtual |
| syscallRetryLatency | BaseCPU | |
| system | BaseCPU | |
| takeOverFrom(BaseCPU *cpu) | BaseCPU | virtual |
| taskId() const | BaseCPU | inline |
| taskId(uint32_t id) | BaseCPU | inline |
| threadContexts | BaseCPU | protected |
| totalInsts() const override | Iris::BaseCPU | virtual |
| totalOps() const override | Iris::BaseCPU | inlinevirtual |
| traceFunctions(Addr pc) | BaseCPU | inline |
| traceFunctionsInternal(Addr pc) | BaseCPU | private |
| tracer | BaseCPU | protected |
| unserialize(CheckpointIn &cp) override | BaseCPU | |
| unserializeThread(CheckpointIn &cp, ThreadID tid) | BaseCPU | inlinevirtual |
| updateCycleCounters(CPUState state) | BaseCPU | inlineprotected |
| verifyMemoryMode() const | BaseCPU | inlinevirtual |
| waitForRemoteGDB() const | BaseCPU | |
| wakeup(ThreadID tid) override | Iris::BaseCPU | inlinevirtual |
| workItemBegin() | BaseCPU | inline |
| workItemEnd() | BaseCPU | inline |
| ~BaseCPU() | Iris::BaseCPU | virtual |